ALSA: hda: Prevent writing ICH6_PCIREG_TCSEL on AMD systems

azx_init_pci() always writes PCI config register ICH6_PCIREG_TCSEL
although this looks to be only defined on Intel systems and has a
different meaning on AMD systems. On AMD systems the PCI interrupt pin
control register is modified instead.

Since the meaning of offset 0x44 in device specific configuration space is
unknown for devices by other vendors, we only exclude AMD systems to
retain the current behaviour.

Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Signed-off-by: Takashi Iwai <tiwai@suse.de>

1 files changed, 5 insertions, 2 deletions

diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index fcedad9a5fef..70a9d32f0e96 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -1052,9 +1052,12 @@ static void azx_init_pci(struct azx *chip)
         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
          * Ensuring these bits are 0 clears playback static on some HD Audio
-         * codecs
+         * codecs.
+         * The PCI register TCSEL is defined in the Intel manuals.
          */
-        update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
+        if (chip->driver_type != AZX_DRIVER_ATI &&
+            chip->driver_type != AZX_DRIVER_ATIHDMI)
+                update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 
         switch (chip->driver_type) {
         case AZX_DRIVER_ATI: