aboutsummaryrefslogtreecommitdiffstats
path: root/sound/pci/hda/patch_ca0132.c
diff options
context:
space:
mode:
authorIan Minett <ian_minett@creativelabs.com>2012-09-20 23:29:16 -0400
committerTakashi Iwai <tiwai@suse.de>2012-11-28 02:47:12 -0500
commit01ef7dbffb411d9d78d1150b268d9c757f9f2f93 (patch)
tree0a0b57118163032d38775e6d3418c35fee22f32a /sound/pci/hda/patch_ca0132.c
parent4aa3bb0c52ac1d973eeced63b40ce22130e2eae4 (diff)
ALSA: hda - Update CA0132 codec to load DSP firmware binary
This patch adds the code needed to fetch the DSP binary image from the local firmware install location and transfer it over to the chip using the new DSP loader bus ops. Actual DSP effect controls, parameters and mixers are to be included later. - Add calls to new DSP loader system to transfer firmware to the hardware. - Add chip read/write routines, DSP I/O, SCP packet format helper functions and transfer DMA management. - Add guard around DSP download to ensure loader config switch is enabled. The general scheme for downloading the DSP is as follows: 1) If DSP firmware loader is enabled, ca0132_download_dsp() is called to start the process. 2) Driver requests DSP image using request_firmware(). 3) Driver sets up the streaming DMA for DSP image download with dspload_image() and dspxfr_image(), which in turn calls the DSP loader op snd_hda_codec_load_dsp_prepare() to ready the system. 4) DSP image will consist of 1 or more segments, each transferred in sequence by a call to dspxfr_one_seg() and snd_hda_codec_load_dsp_trigger(). 5) Once complete, the loader state is cleaned up with snd_hda_codec_load_dsp_cleanup(). Signed-off-by: Ian Minett <ian_minett@creativelabs.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/pci/hda/patch_ca0132.c')
-rw-r--r--sound/pci/hda/patch_ca0132.c1609
1 files changed, 1605 insertions, 4 deletions
diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c
index 846826d2b738..f5aea7865dbf 100644
--- a/sound/pci/hda/patch_ca0132.c
+++ b/sound/pci/hda/patch_ca0132.c
@@ -48,9 +48,6 @@
48#define WIDGET_CHIP_CTRL 0x15 48#define WIDGET_CHIP_CTRL 0x15
49#define WIDGET_DSP_CTRL 0x16 49#define WIDGET_DSP_CTRL 0x16
50 50
51#define WUH_MEM_CONNID 10
52#define DSP_MEM_CONNID 16
53
54#define MEM_CONNID_MICIN1 3 51#define MEM_CONNID_MICIN1 3
55#define MEM_CONNID_MICIN2 5 52#define MEM_CONNID_MICIN2 5
56#define MEM_CONNID_MICOUT1 12 53#define MEM_CONNID_MICOUT1 12
@@ -62,6 +59,10 @@
62#define SCP_SET 0 59#define SCP_SET 0
63#define SCP_GET 1 60#define SCP_GET 1
64 61
62#define EFX_FILE "ctefx.bin"
63
64MODULE_FIRMWARE(EFX_FILE);
65
65enum hda_cmd_vendor_io { 66enum hda_cmd_vendor_io {
66 /* for DspIO node */ 67 /* for DspIO node */
67 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 68 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
@@ -348,6 +349,25 @@ static int _add_volume(struct hda_codec *codec, hda_nid_t nid, const char *pfx,
348#define add_in_mono_volume(codec, nid, pfx, chan) \ 349#define add_in_mono_volume(codec, nid, pfx, chan) \
349 _add_volume(codec, nid, pfx, chan, 1) 350 _add_volume(codec, nid, pfx, chan, 1)
350 351
352enum dsp_download_state {
353 DSP_DOWNLOAD_FAILED = -1,
354 DSP_DOWNLOAD_INIT = 0,
355 DSP_DOWNLOADING = 1,
356 DSP_DOWNLOADED = 2
357};
358
359struct hda_stream_format {
360 unsigned int sample_rate;
361 unsigned short valid_bits_per_sample;
362 unsigned short container_size;
363 unsigned short number_channels;
364};
365
366/* retrieve parameters from hda format */
367#define get_hdafmt_chs(fmt) (fmt & 0xf)
368#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
369#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
370#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
351 371
352/* 372/*
353 * CA0132 specific 373 * CA0132 specific
@@ -367,11 +387,55 @@ struct ca0132_spec {
367 long curr_hp_switch; 387 long curr_hp_switch;
368 long curr_hp_volume[2]; 388 long curr_hp_volume[2];
369 long curr_speaker_switch; 389 long curr_speaker_switch;
370 struct mutex chipio_mutex;
371 const char *input_labels[AUTO_PIN_LAST]; 390 const char *input_labels[AUTO_PIN_LAST];
372 struct hda_pcm pcm_rec[2]; /* PCM information */ 391 struct hda_pcm pcm_rec[2]; /* PCM information */
392
393 /* chip access */
394 struct mutex chipio_mutex; /* chip access mutex */
395 u32 curr_chip_addx;
396
397 /* DSP download related */
398 enum dsp_download_state dsp_state;
399 unsigned int dsp_stream_id;
400 unsigned int wait_scp;
401 unsigned int wait_scp_header;
402 unsigned int wait_num_data;
403 unsigned int scp_resp_header;
404 unsigned int scp_resp_data[4];
405 unsigned int scp_resp_count;
373}; 406};
374 407
408/*
409 * CA0132 codec access
410 */
411unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
412 unsigned int verb, unsigned int parm, unsigned int *res)
413{
414 unsigned int response;
415 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
416 *res = response;
417
418 return ((response == -1) ? -1 : 0);
419}
420
421static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
422 unsigned short converter_format, unsigned int *res)
423{
424 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
425 converter_format & 0xffff, res);
426}
427
428static int codec_set_converter_stream_channel(struct hda_codec *codec,
429 hda_nid_t nid, unsigned char stream,
430 unsigned char channel, unsigned int *res)
431{
432 unsigned char converter_stream_channel = 0;
433
434 converter_stream_channel = (stream << 4) | (channel & 0x0f);
435 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
436 converter_stream_channel, res);
437}
438
375/* Chip access helper function */ 439/* Chip access helper function */
376static int chipio_send(struct hda_codec *codec, 440static int chipio_send(struct hda_codec *codec,
377 unsigned int reg, 441 unsigned int reg,
@@ -411,6 +475,30 @@ static int chipio_write_address(struct hda_codec *codec,
411 return res; 475 return res;
412} 476}
413 477
478static int chipio_write_addx(struct hda_codec *codec, u32 chip_addx)
479{
480 struct ca0132_spec *spec = codec->spec;
481 int status;
482
483 if (spec->curr_chip_addx == chip_addx)
484 return 0;
485
486 /* send low 16 bits of the address */
487 status = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
488 chip_addx & 0xffff);
489
490 if (status < 0)
491 return status;
492
493 /* send high 16 bits of the address */
494 status = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
495 chip_addx >> 16);
496
497 spec->curr_chip_addx = (status < 0) ? ~0UL : chip_addx;
498
499 return status;
500}
501
414/* 502/*
415 * Write data through the vendor widget -- NOT protected by the Mutex! 503 * Write data through the vendor widget -- NOT protected by the Mutex!
416 */ 504 */
@@ -431,6 +519,24 @@ static int chipio_write_data(struct hda_codec *codec, unsigned int data)
431 return res; 519 return res;
432} 520}
433 521
522static int chipio_write_data_multiple(struct hda_codec *codec,
523 const u32 *data,
524 unsigned int count)
525{
526 int status = 0;
527
528 if (data == NULL) {
529 snd_printdd(KERN_ERR "chipio_write_data null ptr");
530 return -EINVAL;
531 }
532
533 while ((count-- != 0) && (status == 0))
534 status = chipio_write_data(codec, *data++);
535
536 return status;
537}
538
539
434/* 540/*
435 * Read data through the vendor widget -- NOT protected by the Mutex! 541 * Read data through the vendor widget -- NOT protected by the Mutex!
436 */ 542 */
@@ -482,6 +588,26 @@ exit:
482 return err; 588 return err;
483} 589}
484 590
591static int chipio_write_multiple(struct hda_codec *codec,
592 u32 chip_addx,
593 const u32 *data,
594 unsigned int count)
595{
596 struct ca0132_spec *spec = codec->spec;
597 int status;
598
599 mutex_lock(&spec->chipio_mutex);
600 status = chipio_write_addx(codec, chip_addx);
601 if (status < 0)
602 goto error;
603
604 status = chipio_write_data_multiple(codec, data, count);
605error:
606 mutex_unlock(&spec->chipio_mutex);
607
608 return status;
609}
610
485/* 611/*
486 * Read the given address through the chip I/O widget 612 * Read the given address through the chip I/O widget
487 * protected by the Mutex 613 * protected by the Mutex
@@ -508,6 +634,1425 @@ exit:
508 return err; 634 return err;
509} 635}
510 636
637static void chipio_set_control_flag(struct hda_codec *codec,
638 enum control_flag_id flag_id,
639 bool flag_state)
640{
641 unsigned int val;
642 unsigned int flag_bit;
643
644 flag_bit = (flag_state ? 1 : 0);
645 val = (flag_bit << 7) | (flag_id);
646 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
647 VENDOR_CHIPIO_FLAG_SET, val);
648}
649
650static void chipio_set_control_param(struct hda_codec *codec,
651 enum control_param_id param_id, int param_val)
652{
653 struct ca0132_spec *spec = codec->spec;
654 int val;
655
656 if ((param_id < 32) && (param_val < 8)) {
657 val = (param_val << 5) | (param_id);
658 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
659 VENDOR_CHIPIO_PARAM_SET, val);
660 } else {
661 mutex_lock(&spec->chipio_mutex);
662 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
663 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
664 VENDOR_CHIPIO_PARAM_EX_ID_SET,
665 param_id);
666 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
667 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
668 param_val);
669 }
670 mutex_unlock(&spec->chipio_mutex);
671 }
672}
673
674static void chipio_set_conn_rate(struct hda_codec *codec,
675 int connid, enum ca0132_sample_rate rate)
676{
677 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
678 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
679 rate);
680}
681
682static void chipio_enable_clocks(struct hda_codec *codec)
683{
684 struct ca0132_spec *spec = codec->spec;
685
686 mutex_lock(&spec->chipio_mutex);
687 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
688 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
689 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
690 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
691 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
692 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
693 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
694 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
695 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
696 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
697 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
698 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
699 mutex_unlock(&spec->chipio_mutex);
700}
701
702/*
703 * CA0132 DSP IO stuffs
704 */
705static int dspio_send(struct hda_codec *codec, unsigned int reg,
706 unsigned int data)
707{
708 unsigned int res;
709 int retry = 50;
710
711 /* send bits of data specified by reg to dsp */
712 do {
713 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
714 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
715 return res;
716 } while (--retry);
717
718 return -EIO;
719}
720
721static void dspio_write_wait(struct hda_codec *codec)
722{
723 int cur_val, prv_val;
724 int retry = 50;
725
726 cur_val = 0;
727 do {
728 prv_val = cur_val;
729 msleep(20);
730 dspio_send(codec, VENDOR_DSPIO_SCP_POST_COUNT_QUERY, 1);
731 dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
732 cur_val = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
733 VENDOR_DSPIO_SCP_READ_COUNT, 0);
734 } while (cur_val && (cur_val == prv_val) && --retry);
735}
736
737static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
738{
739 struct ca0132_spec *spec = codec->spec;
740 int status;
741
742 dspio_write_wait(codec);
743
744 mutex_lock(&spec->chipio_mutex);
745 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
746 scp_data & 0xffff);
747 if (status < 0)
748 goto error;
749
750 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
751 scp_data >> 16);
752 if (status < 0)
753 goto error;
754
755 /* OK, now check if the write itself has executed*/
756 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
757 VENDOR_DSPIO_STATUS, 0);
758error:
759 mutex_unlock(&spec->chipio_mutex);
760
761 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
762 -EIO : 0;
763}
764
765static int dspio_write_multiple(struct hda_codec *codec,
766 unsigned int *buffer, unsigned int size)
767{
768 int status = 0;
769 unsigned int count;
770
771 if ((buffer == NULL))
772 return -EINVAL;
773
774 count = 0;
775 while (count < size) {
776 status = dspio_write(codec, *buffer++);
777 if (status != 0)
778 break;
779 count++;
780 }
781
782 return status;
783}
784
785static inline unsigned int
786make_scp_header(unsigned int target_id, unsigned int source_id,
787 unsigned int get_flag, unsigned int req,
788 unsigned int device_flag, unsigned int resp_flag,
789 unsigned int error_flag, unsigned int data_size)
790{
791 unsigned int header = 0;
792
793 header = (data_size & 0x1f) << 27;
794 header |= (error_flag & 0x01) << 26;
795 header |= (resp_flag & 0x01) << 25;
796 header |= (device_flag & 0x01) << 24;
797 header |= (req & 0x7f) << 17;
798 header |= (get_flag & 0x01) << 16;
799 header |= (source_id & 0xff) << 8;
800 header |= target_id & 0xff;
801
802 return header;
803}
804
805static inline void
806extract_scp_header(unsigned int header,
807 unsigned int *target_id, unsigned int *source_id,
808 unsigned int *get_flag, unsigned int *req,
809 unsigned int *device_flag, unsigned int *resp_flag,
810 unsigned int *error_flag, unsigned int *data_size)
811{
812 if (data_size)
813 *data_size = (header >> 27) & 0x1f;
814 if (error_flag)
815 *error_flag = (header >> 26) & 0x01;
816 if (resp_flag)
817 *resp_flag = (header >> 25) & 0x01;
818 if (device_flag)
819 *device_flag = (header >> 24) & 0x01;
820 if (req)
821 *req = (header >> 17) & 0x7f;
822 if (get_flag)
823 *get_flag = (header >> 16) & 0x01;
824 if (source_id)
825 *source_id = (header >> 8) & 0xff;
826 if (target_id)
827 *target_id = header & 0xff;
828}
829
830#define SCP_MAX_DATA_WORDS (16)
831
832/* Structure to contain any SCP message */
833struct scp_msg {
834 unsigned int hdr;
835 unsigned int data[SCP_MAX_DATA_WORDS];
836};
837
838static int dspio_send_scp_message(struct hda_codec *codec,
839 unsigned char *send_buf,
840 unsigned int send_buf_size,
841 unsigned char *return_buf,
842 unsigned int return_buf_size,
843 unsigned int *bytes_returned)
844{
845 struct ca0132_spec *spec = codec->spec;
846 int retry;
847 int status = -1;
848 unsigned int scp_send_size = 0;
849 unsigned int total_size;
850 bool waiting_for_resp = false;
851 unsigned int header;
852 struct scp_msg *ret_msg;
853 unsigned int resp_src_id, resp_target_id;
854 unsigned int data_size, src_id, target_id, get_flag, device_flag;
855
856 if (bytes_returned)
857 *bytes_returned = 0;
858
859 /* get scp header from buffer */
860 header = *((unsigned int *)send_buf);
861 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
862 &device_flag, NULL, NULL, &data_size);
863 scp_send_size = data_size + 1;
864 total_size = (scp_send_size * 4);
865
866 if (send_buf_size < total_size)
867 return -EINVAL;
868
869 if (get_flag || device_flag) {
870 if (!return_buf || return_buf_size < 4 || !bytes_returned)
871 return -EINVAL;
872
873 spec->wait_scp_header = *((unsigned int *)send_buf);
874
875 /* swap source id with target id */
876 resp_target_id = src_id;
877 resp_src_id = target_id;
878 spec->wait_scp_header &= 0xffff0000;
879 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
880 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
881 spec->wait_scp = 1;
882 waiting_for_resp = true;
883 }
884
885 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
886 scp_send_size);
887 if (status < 0) {
888 spec->wait_scp = 0;
889 return status;
890 }
891
892 if (waiting_for_resp) {
893 memset(return_buf, 0, return_buf_size);
894 retry = 50;
895 do {
896 msleep(20);
897 } while (spec->wait_scp && (--retry != 0));
898 waiting_for_resp = false;
899 if (retry != 0) {
900 ret_msg = (struct scp_msg *)return_buf;
901 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
902 memcpy(&ret_msg->data, spec->scp_resp_data,
903 spec->wait_num_data);
904 *bytes_returned = (spec->scp_resp_count + 1) * 4;
905 status = 0;
906 } else {
907 status = -EIO;
908 }
909 spec->wait_scp = 0;
910 }
911
912 return status;
913}
914
915static int dspio_scp(struct hda_codec *codec,
916 int mod_id, int req, int dir, void *data, unsigned int len,
917 void *reply, unsigned int *reply_len)
918{
919 int status = 0;
920 struct scp_msg scp_send, scp_reply;
921 unsigned int ret_bytes, send_size, ret_size;
922 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
923 unsigned int reply_data_size;
924
925 memset(&scp_send, 0, sizeof(scp_send));
926 memset(&scp_reply, 0, sizeof(scp_reply));
927
928 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
929 return -EINVAL;
930
931 if (dir == SCP_GET && reply == NULL) {
932 snd_printdd(KERN_ERR "dspio_scp get but has no buffer");
933 return -EINVAL;
934 }
935
936 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
937 snd_printdd(KERN_ERR "dspio_scp bad resp buf len parms");
938 return -EINVAL;
939 }
940
941 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
942 0, 0, 0, len/sizeof(unsigned int));
943 if (data != NULL && len > 0) {
944 len = min((unsigned int)(sizeof(scp_send.data)), len);
945 memcpy(scp_send.data, data, len);
946 }
947
948 ret_bytes = 0;
949 send_size = sizeof(unsigned int) + len;
950 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
951 send_size, (unsigned char *)&scp_reply,
952 sizeof(scp_reply), &ret_bytes);
953
954 if (status < 0) {
955 snd_printdd(KERN_ERR "dspio_scp: send scp msg failed");
956 return status;
957 }
958
959 /* extract send and reply headers members */
960 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
961 NULL, NULL, NULL, NULL, NULL);
962 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
963 &reply_resp_flag, &reply_error_flag,
964 &reply_data_size);
965
966 if (!send_get_flag)
967 return 0;
968
969 if (reply_resp_flag && !reply_error_flag) {
970 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
971 / sizeof(unsigned int);
972
973 if (*reply_len < ret_size*sizeof(unsigned int)) {
974 snd_printdd(KERN_ERR "reply too long for buf");
975 return -EINVAL;
976 } else if (ret_size != reply_data_size) {
977 snd_printdd(KERN_ERR "RetLen and HdrLen .NE.");
978 return -EINVAL;
979 } else {
980 *reply_len = ret_size*sizeof(unsigned int);
981 memcpy(reply, scp_reply.data, *reply_len);
982 }
983 } else {
984 snd_printdd(KERN_ERR "reply ill-formed or errflag set");
985 return -EIO;
986 }
987
988 return status;
989}
990
991static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
992{
993 int status = 0;
994 unsigned int size = sizeof(dma_chan);
995
996 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- begin");
997 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
998 SCP_GET, NULL, 0, dma_chan, &size);
999
1000 if (status < 0) {
1001 snd_printdd(KERN_INFO "dspio_alloc_dma_chan: SCP Failed");
1002 return status;
1003 }
1004
1005 if ((*dma_chan + 1) == 0) {
1006 snd_printdd(KERN_INFO "no free dma channels to allocate");
1007 return -EBUSY;
1008 }
1009
1010 snd_printdd("dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1011 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- complete");
1012
1013 return status;
1014}
1015
1016static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1017{
1018 int status = 0;
1019 unsigned int dummy = 0;
1020
1021 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- begin");
1022 snd_printdd("dspio_free_dma_chan: chan=%d\n", dma_chan);
1023
1024 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1025 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1026
1027 if (status < 0) {
1028 snd_printdd(KERN_INFO "dspio_free_dma_chan: SCP Failed");
1029 return status;
1030 }
1031
1032 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- complete");
1033
1034 return status;
1035}
1036
1037/*
1038 * CA0132 DSP access stuffs
1039 */
1040static int dsp_set_run_state(struct hda_codec *codec)
1041{
1042 unsigned int dbg_ctrl_reg;
1043 unsigned int halt_state;
1044 int err;
1045
1046 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1047 if (err < 0)
1048 return err;
1049
1050 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1051 DSP_DBGCNTL_STATE_LOBIT;
1052
1053 if (halt_state != 0) {
1054 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1055 DSP_DBGCNTL_SS_MASK);
1056 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1057 dbg_ctrl_reg);
1058 if (err < 0)
1059 return err;
1060
1061 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1062 DSP_DBGCNTL_EXEC_MASK;
1063 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1064 dbg_ctrl_reg);
1065 if (err < 0)
1066 return err;
1067 }
1068
1069 return 0;
1070}
1071
1072static int dsp_reset(struct hda_codec *codec)
1073{
1074 unsigned int res;
1075 int retry = 20;
1076
1077 snd_printdd("dsp_reset\n");
1078 do {
1079 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1080 retry--;
1081 } while (res == -EIO && retry);
1082
1083 if (!retry) {
1084 snd_printdd("dsp_reset timeout\n");
1085 return -EIO;
1086 }
1087
1088 return 0;
1089}
1090
1091static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1092 bool *code, bool *yram)
1093{
1094 *code = *yram = false;
1095
1096 if (UC_RANGE(chip_addx, 1)) {
1097 *code = true;
1098 return UC_OFF(chip_addx);
1099 } else if (X_RANGE_ALL(chip_addx, 1)) {
1100 return X_OFF(chip_addx);
1101 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1102 *yram = true;
1103 return Y_OFF(chip_addx);
1104 }
1105
1106 return (unsigned int)INVALID_CHIP_ADDRESS;
1107}
1108
1109static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1110{
1111 unsigned int dma_chnlstart_reg;
1112
1113 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1114
1115 return ((dma_chnlstart_reg & (1 <<
1116 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1117}
1118
1119static int dsp_dma_setup_common(struct hda_codec *codec,
1120 unsigned int chip_addx,
1121 unsigned int dma_chan,
1122 unsigned int port_map_mask,
1123 bool ovly)
1124{
1125 int status = 0;
1126 unsigned int chnl_prop;
1127 unsigned int dsp_addx;
1128 unsigned int active;
1129 bool code, yram;
1130
1131 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Begin ---------");
1132
1133 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
1134 snd_printdd(KERN_ERR "dma chan num invalid");
1135 return -EINVAL;
1136 }
1137
1138 if (dsp_is_dma_active(codec, dma_chan)) {
1139 snd_printdd(KERN_ERR "dma already active");
1140 return -EBUSY;
1141 }
1142
1143 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1144
1145 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1146 snd_printdd(KERN_ERR "invalid chip addr");
1147 return -ENXIO;
1148 }
1149
1150 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1151 active = 0;
1152
1153 snd_printdd(KERN_INFO " dsp_dma_setup_common() start reg pgm");
1154
1155 if (ovly) {
1156 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1157 &chnl_prop);
1158
1159 if (status < 0) {
1160 snd_printdd(KERN_ERR "read CHNLPROP Reg fail");
1161 return status;
1162 }
1163 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read CHNLPROP");
1164 }
1165
1166 if (!code)
1167 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1168 else
1169 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1170
1171 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1172
1173 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1174 if (status < 0) {
1175 snd_printdd(KERN_ERR "write CHNLPROP Reg fail");
1176 return status;
1177 }
1178 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write CHNLPROP");
1179
1180 if (ovly) {
1181 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1182 &active);
1183
1184 if (status < 0) {
1185 snd_printdd(KERN_ERR "read ACTIVE Reg fail");
1186 return status;
1187 }
1188 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read ACTIVE");
1189 }
1190
1191 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1192 DSPDMAC_ACTIVE_AAR_MASK;
1193
1194 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1195 if (status < 0) {
1196 snd_printdd(KERN_ERR "write ACTIVE Reg fail");
1197 return status;
1198 }
1199
1200 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write ACTIVE");
1201
1202 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1203 port_map_mask);
1204 if (status < 0) {
1205 snd_printdd(KERN_ERR "write AUDCHSEL Reg fail");
1206 return status;
1207 }
1208 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write AUDCHSEL");
1209
1210 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1211 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1212 if (status < 0) {
1213 snd_printdd(KERN_ERR "write IRQCNT Reg fail");
1214 return status;
1215 }
1216 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write IRQCNT");
1217
1218 snd_printdd(
1219 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1220 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1221 chip_addx, dsp_addx, dma_chan,
1222 port_map_mask, chnl_prop, active);
1223
1224 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Complete ------");
1225
1226 return 0;
1227}
1228
1229static int dsp_dma_setup(struct hda_codec *codec,
1230 unsigned int chip_addx,
1231 unsigned int count,
1232 unsigned int dma_chan)
1233{
1234 int status = 0;
1235 bool code, yram;
1236 unsigned int dsp_addx;
1237 unsigned int addr_field;
1238 unsigned int incr_field;
1239 unsigned int base_cnt;
1240 unsigned int cur_cnt;
1241 unsigned int dma_cfg = 0;
1242 unsigned int adr_ofs = 0;
1243 unsigned int xfr_cnt = 0;
1244 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1245 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1246
1247 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Begin ---------");
1248
1249 if (count > max_dma_count) {
1250 snd_printdd(KERN_ERR "count too big");
1251 return -EINVAL;
1252 }
1253
1254 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1255 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1256 snd_printdd(KERN_ERR "invalid chip addr");
1257 return -ENXIO;
1258 }
1259
1260 snd_printdd(KERN_INFO " dsp_dma_setup() start reg pgm");
1261
1262 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1263 incr_field = 0;
1264
1265 if (!code) {
1266 addr_field <<= 1;
1267 if (yram)
1268 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1269
1270 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1271 }
1272
1273 dma_cfg = addr_field + incr_field;
1274 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1275 dma_cfg);
1276 if (status < 0) {
1277 snd_printdd(KERN_ERR "write DMACFG Reg fail");
1278 return status;
1279 }
1280 snd_printdd(KERN_INFO " dsp_dma_setup() Write DMACFG");
1281
1282 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1283 (code ? 0 : 1));
1284
1285 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1286 adr_ofs);
1287 if (status < 0) {
1288 snd_printdd(KERN_ERR "write DSPADROFS Reg fail");
1289 return status;
1290 }
1291 snd_printdd(KERN_INFO " dsp_dma_setup() Write DSPADROFS");
1292
1293 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1294
1295 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1296
1297 xfr_cnt = base_cnt | cur_cnt;
1298
1299 status = chipio_write(codec,
1300 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1301 if (status < 0) {
1302 snd_printdd(KERN_ERR "write XFRCNT Reg fail");
1303 return status;
1304 }
1305 snd_printdd(KERN_INFO " dsp_dma_setup() Write XFRCNT");
1306
1307 snd_printdd(
1308 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1309 "ADROFS=0x%x, XFRCNT=0x%x\n",
1310 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1311
1312 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Complete ---------");
1313
1314 return 0;
1315}
1316
1317static int dsp_dma_start(struct hda_codec *codec,
1318 unsigned int dma_chan, bool ovly)
1319{
1320 unsigned int reg = 0;
1321 int status = 0;
1322
1323 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Begin ---------");
1324
1325 if (ovly) {
1326 status = chipio_read(codec,
1327 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1328
1329 if (status < 0) {
1330 snd_printdd(KERN_ERR "read CHNLSTART reg fail");
1331 return status;
1332 }
1333 snd_printdd(KERN_INFO "-- dsp_dma_start() Read CHNLSTART");
1334
1335 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1336 DSPDMAC_CHNLSTART_DIS_MASK);
1337 }
1338
1339 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1340 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1341 if (status < 0) {
1342 snd_printdd(KERN_ERR "write CHNLSTART reg fail");
1343 return status;
1344 }
1345 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Complete ---------");
1346
1347 return status;
1348}
1349
1350static int dsp_dma_stop(struct hda_codec *codec,
1351 unsigned int dma_chan, bool ovly)
1352{
1353 unsigned int reg = 0;
1354 int status = 0;
1355
1356 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Begin ---------");
1357
1358 if (ovly) {
1359 status = chipio_read(codec,
1360 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1361
1362 if (status < 0) {
1363 snd_printdd(KERN_ERR "read CHNLSTART reg fail");
1364 return status;
1365 }
1366 snd_printdd(KERN_INFO "-- dsp_dma_stop() Read CHNLSTART");
1367 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1368 DSPDMAC_CHNLSTART_DIS_MASK);
1369 }
1370
1371 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1372 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1373 if (status < 0) {
1374 snd_printdd(KERN_ERR "write CHNLSTART reg fail");
1375 return status;
1376 }
1377 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Complete ---------");
1378
1379 return status;
1380}
1381
1382static int dsp_allocate_router_ports(struct hda_codec *codec,
1383 unsigned int num_chans,
1384 unsigned int ports_per_channel,
1385 unsigned int start_device,
1386 unsigned int *port_map)
1387{
1388 int status = 0;
1389 int res;
1390 u8 val;
1391
1392 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1393 if (status < 0)
1394 return status;
1395
1396 val = start_device << 6;
1397 val |= (ports_per_channel - 1) << 4;
1398 val |= num_chans - 1;
1399
1400 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1401 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1402 val);
1403
1404 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1405 VENDOR_CHIPIO_PORT_ALLOC_SET,
1406 MEM_CONNID_DSP);
1407
1408 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1409 if (status < 0)
1410 return status;
1411
1412 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1413 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1414
1415 *port_map = res;
1416
1417 return (res < 0) ? res : 0;
1418}
1419
1420static int dsp_free_router_ports(struct hda_codec *codec)
1421{
1422 int status = 0;
1423
1424 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1425 if (status < 0)
1426 return status;
1427
1428 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1429 VENDOR_CHIPIO_PORT_FREE_SET,
1430 MEM_CONNID_DSP);
1431
1432 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1433
1434 return status;
1435}
1436
1437static int dsp_allocate_ports(struct hda_codec *codec,
1438 unsigned int num_chans,
1439 unsigned int rate_multi, unsigned int *port_map)
1440{
1441 int status;
1442
1443 snd_printdd(KERN_INFO " dsp_allocate_ports() -- begin");
1444
1445 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1446 snd_printdd(KERN_ERR "bad rate multiple");
1447 return -EINVAL;
1448 }
1449
1450 status = dsp_allocate_router_ports(codec, num_chans,
1451 rate_multi, 0, port_map);
1452
1453 snd_printdd(KERN_INFO " dsp_allocate_ports() -- complete");
1454
1455 return status;
1456}
1457
1458static int dsp_free_ports(struct hda_codec *codec)
1459{
1460 int status;
1461
1462 snd_printdd(KERN_INFO " dsp_free_ports() -- begin");
1463
1464 status = dsp_free_router_ports(codec);
1465 if (status < 0) {
1466 snd_printdd(KERN_ERR "free router ports fail");
1467 return status;
1468 }
1469 snd_printdd(KERN_INFO " dsp_free_ports() -- complete");
1470
1471 return status;
1472}
1473
1474static int dsp_allocate_ports_format(struct hda_codec *codec,
1475 const unsigned short fmt,
1476 unsigned int *port_map)
1477{
1478 int status;
1479 unsigned int num_chans;
1480
1481 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
1482 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
1483 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
1484
1485 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1486 snd_printdd(KERN_ERR "bad rate multiple");
1487 return -EINVAL;
1488 }
1489
1490 num_chans = get_hdafmt_chs(fmt) + 1;
1491
1492 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
1493
1494 return status;
1495}
1496
1497/*
1498 * HDA DMA engine stuffs for DSP code download
1499 */
1500struct dma_engine {
1501 struct hda_codec *codec;
1502 unsigned short m_converter_format;
1503 struct snd_dma_buffer *dmab;
1504 unsigned int buf_size;
1505};
1506
1507
1508enum dma_state {
1509 DMA_STATE_STOP = 0,
1510 DMA_STATE_RUN = 1
1511};
1512
1513static int dma_convert_to_hda_format(
1514 struct hda_stream_format *stream_format,
1515 unsigned short *hda_format)
1516{
1517 unsigned int format_val;
1518
1519 format_val = snd_hda_calc_stream_format(
1520 stream_format->sample_rate,
1521 stream_format->number_channels,
1522 SNDRV_PCM_FORMAT_S32_LE,
1523 stream_format->container_size, 0);
1524
1525 if (hda_format)
1526 *hda_format = (unsigned short)format_val;
1527
1528 return 0;
1529}
1530
1531static int dma_reset(struct dma_engine *dma)
1532{
1533 struct hda_codec *codec = dma->codec;
1534 struct ca0132_spec *spec = codec->spec;
1535 int status;
1536
1537 if (dma->dmab)
1538 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
1539
1540 status = snd_hda_codec_load_dsp_prepare(codec,
1541 dma->m_converter_format,
1542 dma->buf_size,
1543 dma->dmab);
1544 if (status < 0)
1545 return status;
1546 spec->dsp_stream_id = status;
1547 return 0;
1548}
1549
1550static int dma_set_state(struct dma_engine *dma, enum dma_state state)
1551{
1552 bool cmd;
1553
1554 snd_printdd("dma_set_state state=%d\n", state);
1555
1556 switch (state) {
1557 case DMA_STATE_STOP:
1558 cmd = false;
1559 break;
1560 case DMA_STATE_RUN:
1561 cmd = true;
1562 break;
1563 default:
1564 return 0;
1565 }
1566
1567 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
1568 return 0;
1569}
1570
1571static unsigned int dma_get_buffer_size(struct dma_engine *dma)
1572{
1573 return dma->dmab->bytes;
1574}
1575
1576static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
1577{
1578 return dma->dmab->area;
1579}
1580
1581static int dma_xfer(struct dma_engine *dma,
1582 const unsigned int *data,
1583 unsigned int count)
1584{
1585 memcpy(dma->dmab->area, data, count);
1586 return 0;
1587}
1588
1589static void dma_get_converter_format(
1590 struct dma_engine *dma,
1591 unsigned short *format)
1592{
1593 if (format)
1594 *format = dma->m_converter_format;
1595}
1596
1597static unsigned int dma_get_stream_id(struct dma_engine *dma)
1598{
1599 struct ca0132_spec *spec = dma->codec->spec;
1600
1601 return spec->dsp_stream_id;
1602}
1603
1604struct dsp_image_seg {
1605 u32 magic;
1606 u32 chip_addr;
1607 u32 count;
1608 u32 data[0];
1609};
1610
1611static const u32 g_magic_value = 0x4c46584d;
1612static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
1613
1614static bool is_valid(const struct dsp_image_seg *p)
1615{
1616 return p->magic == g_magic_value;
1617}
1618
1619static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
1620{
1621 return g_chip_addr_magic_value == p->chip_addr;
1622}
1623
1624static bool is_last(const struct dsp_image_seg *p)
1625{
1626 return p->count == 0;
1627}
1628
1629static size_t dsp_sizeof(const struct dsp_image_seg *p)
1630{
1631 return sizeof(*p) + p->count*sizeof(u32);
1632}
1633
1634static const struct dsp_image_seg *get_next_seg_ptr(
1635 const struct dsp_image_seg *p)
1636{
1637 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
1638}
1639
1640/*
1641 * CA0132 chip DSP transfer stuffs. For DSP download.
1642 */
1643#define INVALID_DMA_CHANNEL (~0UL)
1644
1645static int dspxfr_hci_write(struct hda_codec *codec,
1646 const struct dsp_image_seg *fls)
1647{
1648 int status;
1649 const u32 *data;
1650 unsigned int count;
1651
1652 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
1653 snd_printdd(KERN_ERR "hci_write invalid params");
1654 return -EINVAL;
1655 }
1656
1657 count = fls->count;
1658 data = (u32 *)(fls->data);
1659 while (count >= 2) {
1660 status = chipio_write(codec, data[0], data[1]);
1661 if (status < 0) {
1662 snd_printdd(KERN_ERR "hci_write chipio failed");
1663 return status;
1664 }
1665 count -= 2;
1666 data += 2;
1667 }
1668 return 0;
1669}
1670
1671static int dspxfr_one_seg(struct hda_codec *codec,
1672 const struct dsp_image_seg *fls,
1673 unsigned int reloc,
1674 struct dma_engine *dma_engine,
1675 unsigned int dma_chan,
1676 unsigned int port_map_mask,
1677 bool ovly)
1678{
1679 int status;
1680 bool comm_dma_setup_done = false;
1681 const unsigned int *data;
1682 unsigned int chip_addx;
1683 unsigned int words_to_write;
1684 unsigned int buffer_size_words;
1685 unsigned char *buffer_addx;
1686 unsigned short hda_format;
1687 unsigned int sample_rate_div;
1688 unsigned int sample_rate_mul;
1689 unsigned int num_chans;
1690 unsigned int hda_frame_size_words;
1691 unsigned int remainder_words;
1692 const u32 *data_remainder;
1693 u32 chip_addx_remainder;
1694 unsigned int run_size_words;
1695 const struct dsp_image_seg *hci_write = NULL;
1696 int retry;
1697
1698 if (fls == NULL)
1699 return -EINVAL;
1700 if (is_hci_prog_list_seg(fls)) {
1701 hci_write = fls;
1702 fls = get_next_seg_ptr(fls);
1703 }
1704
1705 if (hci_write && (!fls || is_last(fls))) {
1706 snd_printdd("hci_write\n");
1707 return dspxfr_hci_write(codec, hci_write);
1708 }
1709
1710 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
1711 snd_printdd("Invalid Params\n");
1712 return -EINVAL;
1713 }
1714
1715 data = fls->data;
1716 chip_addx = fls->chip_addr,
1717 words_to_write = fls->count;
1718
1719 if (!words_to_write)
1720 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
1721 if (reloc)
1722 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
1723
1724 if (!UC_RANGE(chip_addx, words_to_write) &&
1725 !X_RANGE_ALL(chip_addx, words_to_write) &&
1726 !Y_RANGE_ALL(chip_addx, words_to_write)) {
1727 snd_printdd("Invalid chip_addx Params\n");
1728 return -EINVAL;
1729 }
1730
1731 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
1732 sizeof(u32);
1733
1734 buffer_addx = dma_get_buffer_addr(dma_engine);
1735
1736 if (buffer_addx == NULL) {
1737 snd_printdd(KERN_ERR "dma_engine buffer NULL\n");
1738 return -EINVAL;
1739 }
1740
1741 dma_get_converter_format(dma_engine, &hda_format);
1742 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
1743 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
1744 num_chans = get_hdafmt_chs(hda_format) + 1;
1745
1746 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
1747 (num_chans * sample_rate_mul / sample_rate_div));
1748
1749 buffer_size_words = min(buffer_size_words,
1750 (unsigned int)(UC_RANGE(chip_addx, 1) ?
1751 65536 : 32768));
1752 buffer_size_words -= buffer_size_words % hda_frame_size_words;
1753 snd_printdd(
1754 "chpadr=0x%08x frmsz=%u nchan=%u "
1755 "rate_mul=%u div=%u bufsz=%u\n",
1756 chip_addx, hda_frame_size_words, num_chans,
1757 sample_rate_mul, sample_rate_div, buffer_size_words);
1758
1759 if ((buffer_addx == NULL) || (hda_frame_size_words == 0) ||
1760 (buffer_size_words < hda_frame_size_words)) {
1761 snd_printdd(KERN_ERR "dspxfr_one_seg:failed\n");
1762 return -EINVAL;
1763 }
1764
1765 remainder_words = words_to_write % hda_frame_size_words;
1766 data_remainder = data;
1767 chip_addx_remainder = chip_addx;
1768
1769 data += remainder_words;
1770 chip_addx += remainder_words*sizeof(u32);
1771 words_to_write -= remainder_words;
1772
1773 while (words_to_write != 0) {
1774 run_size_words = min(buffer_size_words, words_to_write);
1775 snd_printdd("dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
1776 words_to_write, run_size_words, remainder_words);
1777 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
1778 if (!comm_dma_setup_done) {
1779 status = dsp_dma_stop(codec, dma_chan, ovly);
1780 if (status < 0)
1781 return -EIO;
1782 status = dsp_dma_setup_common(codec, chip_addx,
1783 dma_chan, port_map_mask, ovly);
1784 if (status < 0)
1785 return status;
1786 comm_dma_setup_done = true;
1787 }
1788
1789 status = dsp_dma_setup(codec, chip_addx,
1790 run_size_words, dma_chan);
1791 if (status < 0)
1792 return status;
1793 status = dsp_dma_start(codec, dma_chan, ovly);
1794 if (status < 0)
1795 return status;
1796 if (!dsp_is_dma_active(codec, dma_chan)) {
1797 snd_printdd(KERN_ERR "dspxfr:DMA did not start");
1798 return -EIO;
1799 }
1800 status = dma_set_state(dma_engine, DMA_STATE_RUN);
1801 if (status < 0)
1802 return status;
1803 if (remainder_words != 0) {
1804 status = chipio_write_multiple(codec,
1805 chip_addx_remainder,
1806 data_remainder,
1807 remainder_words);
1808 remainder_words = 0;
1809 }
1810 if (hci_write) {
1811 status = dspxfr_hci_write(codec, hci_write);
1812 hci_write = NULL;
1813 }
1814 retry = 5000;
1815 while (dsp_is_dma_active(codec, dma_chan)) {
1816 if (--retry <= 0)
1817 break;
1818 }
1819 snd_printdd(KERN_INFO "+++++ DMA complete");
1820 dma_set_state(dma_engine, DMA_STATE_STOP);
1821 dma_reset(dma_engine);
1822
1823 if (status < 0)
1824 return status;
1825
1826 data += run_size_words;
1827 chip_addx += run_size_words*sizeof(u32);
1828 words_to_write -= run_size_words;
1829 }
1830
1831 if (remainder_words != 0) {
1832 status = chipio_write_multiple(codec, chip_addx_remainder,
1833 data_remainder, remainder_words);
1834 }
1835
1836 return status;
1837}
1838
1839static int dspxfr_image(struct hda_codec *codec,
1840 const struct dsp_image_seg *fls_data,
1841 unsigned int reloc, struct hda_stream_format *format,
1842 bool ovly)
1843{
1844 struct ca0132_spec *spec = codec->spec;
1845 int status;
1846 unsigned short hda_format = 0;
1847 unsigned int response;
1848 unsigned char stream_id = 0;
1849 struct dma_engine *dma_engine;
1850 unsigned int dma_chan;
1851 unsigned int port_map_mask;
1852
1853 if (fls_data == NULL)
1854 return -EINVAL;
1855
1856 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
1857 if (!dma_engine) {
1858 status = -ENOMEM;
1859 goto exit;
1860 }
1861 memset((void *)dma_engine, 0, sizeof(*dma_engine));
1862
1863 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
1864 if (!dma_engine->dmab) {
1865 status = -ENOMEM;
1866 goto exit;
1867 }
1868
1869 dma_engine->codec = codec;
1870 dma_convert_to_hda_format(format, &hda_format);
1871 dma_engine->m_converter_format = hda_format;
1872 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
1873 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
1874
1875 dma_chan = 0;
1876
1877 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
1878 hda_format, &response);
1879
1880 if (status < 0) {
1881 snd_printdd(KERN_ERR "set converter format fail");
1882 goto exit;
1883 }
1884
1885 status = snd_hda_codec_load_dsp_prepare(codec,
1886 dma_engine->m_converter_format,
1887 dma_engine->buf_size,
1888 dma_engine->dmab);
1889 if (status < 0)
1890 goto exit;
1891 spec->dsp_stream_id = status;
1892
1893 if (ovly) {
1894 status = dspio_alloc_dma_chan(codec, &dma_chan);
1895 if (status < 0) {
1896 snd_printdd(KERN_ERR "alloc dmachan fail");
1897 dma_chan = (unsigned int)INVALID_DMA_CHANNEL;
1898 goto exit;
1899 }
1900 }
1901
1902 port_map_mask = 0;
1903 status = dsp_allocate_ports_format(codec, hda_format,
1904 &port_map_mask);
1905 if (status < 0) {
1906 snd_printdd(KERN_ERR "alloc ports fail");
1907 goto exit;
1908 }
1909
1910 stream_id = dma_get_stream_id(dma_engine);
1911 status = codec_set_converter_stream_channel(codec,
1912 WIDGET_CHIP_CTRL, stream_id, 0, &response);
1913 if (status < 0) {
1914 snd_printdd(KERN_ERR "set stream chan fail");
1915 goto exit;
1916 }
1917
1918 while ((fls_data != NULL) && !is_last(fls_data)) {
1919 if (!is_valid(fls_data)) {
1920 snd_printdd(KERN_ERR "FLS check fail");
1921 status = -EINVAL;
1922 goto exit;
1923 }
1924 status = dspxfr_one_seg(codec, fls_data, reloc,
1925 dma_engine, dma_chan,
1926 port_map_mask, ovly);
1927 if (status < 0)
1928 break;
1929
1930 if (is_hci_prog_list_seg(fls_data))
1931 fls_data = get_next_seg_ptr(fls_data);
1932
1933 if ((fls_data != NULL) && !is_last(fls_data))
1934 fls_data = get_next_seg_ptr(fls_data);
1935 }
1936
1937 if (port_map_mask != 0)
1938 status = dsp_free_ports(codec);
1939
1940 if (status < 0)
1941 goto exit;
1942
1943 status = codec_set_converter_stream_channel(codec,
1944 WIDGET_CHIP_CTRL, 0, 0, &response);
1945
1946exit:
1947 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
1948 dspio_free_dma_chan(codec, dma_chan);
1949
1950 if (dma_engine->dmab)
1951 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
1952 kfree(dma_engine->dmab);
1953 kfree(dma_engine);
1954
1955 return status;
1956}
1957
1958/*
1959 * CA0132 DSP download stuffs.
1960 */
1961static void dspload_post_setup(struct hda_codec *codec)
1962{
1963 snd_printdd(KERN_INFO "---- dspload_post_setup ------");
1964
1965 /*set DSP speaker to 2.0 configuration*/
1966 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
1967 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
1968
1969 /*update write pointer*/
1970 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
1971}
1972
1973static int dspload_image(struct hda_codec *codec,
1974 const struct dsp_image_seg *fls,
1975 bool ovly,
1976 unsigned int reloc,
1977 bool autostart,
1978 int router_chans)
1979{
1980 int status = 0;
1981 struct hda_stream_format stream_format;
1982
1983 snd_printdd(KERN_INFO "---- dspload_image begin ------");
1984 if (router_chans == 0) {
1985 if (!ovly)
1986 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
1987 else
1988 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
1989 }
1990
1991 stream_format.sample_rate = 48000;
1992 stream_format.number_channels = (unsigned short)router_chans;
1993
1994 while (stream_format.number_channels > 16) {
1995 stream_format.sample_rate *= 2;
1996 stream_format.number_channels /= 2;
1997 }
1998
1999 stream_format.container_size = 32;
2000 stream_format.valid_bits_per_sample = 32;
2001
2002 do {
2003 snd_printdd(KERN_INFO "Ready to program DMA");
2004 if (!ovly)
2005 status = dsp_reset(codec);
2006
2007 if (status < 0)
2008 break;
2009
2010 snd_printdd(KERN_INFO "dsp_reset() complete");
2011 status = dspxfr_image(codec, fls, reloc, &stream_format, ovly);
2012
2013 if (status < 0)
2014 break;
2015
2016 snd_printdd(KERN_INFO "dspxfr_image() complete");
2017 if (autostart && !ovly) {
2018 dspload_post_setup(codec);
2019 status = dsp_set_run_state(codec);
2020 }
2021
2022 snd_printdd(KERN_INFO "LOAD FINISHED");
2023 } while (0);
2024
2025 return status;
2026}
2027
2028static bool dspload_is_loaded(struct hda_codec *codec)
2029{
2030 unsigned int data = 0;
2031 int status = 0;
2032
2033 status = chipio_read(codec, 0x40004, &data);
2034 if ((status < 0) || (data != 1))
2035 return false;
2036
2037 return true;
2038}
2039
2040static bool dspload_wait_loaded(struct hda_codec *codec)
2041{
2042 int retry = 100;
2043
2044 do {
2045 msleep(20);
2046 if (dspload_is_loaded(codec)) {
2047 pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n");
2048 return true;
2049 }
2050 } while (--retry);
2051
2052 pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n");
2053 return false;
2054}
2055
511/* 2056/*
512 * PCM callbacks 2057 * PCM callbacks
513 */ 2058 */
@@ -979,12 +2524,68 @@ static void ca0132_exit_chip(struct hda_codec *codec)
979 /* put any chip cleanup stuffs here. */ 2524 /* put any chip cleanup stuffs here. */
980} 2525}
981 2526
2527static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
2528{
2529 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
2530 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
2531 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
2532 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
2533 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
2534 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
2535
2536 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
2537 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
2538 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
2539}
2540
2541static bool ca0132_download_dsp_images(struct hda_codec *codec)
2542{
2543 bool dsp_loaded = false;
2544 const struct dsp_image_seg *dsp_os_image;
2545 const struct firmware *fw_entry;
2546
2547 if (request_firmware(&fw_entry, EFX_FILE, codec->bus->card->dev) != 0)
2548 return false;
2549
2550 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
2551 dspload_image(codec, dsp_os_image, 0, 0, true, 0);
2552 dsp_loaded = dspload_wait_loaded(codec);
2553
2554 release_firmware(fw_entry);
2555
2556
2557 return dsp_loaded;
2558}
2559
2560static void ca0132_download_dsp(struct hda_codec *codec)
2561{
2562 struct ca0132_spec *spec = codec->spec;
2563
2564 spec->dsp_state = DSP_DOWNLOAD_INIT;
2565
2566 if (spec->dsp_state == DSP_DOWNLOAD_INIT) {
2567 chipio_enable_clocks(codec);
2568 spec->dsp_state = DSP_DOWNLOADING;
2569 if (!ca0132_download_dsp_images(codec))
2570 spec->dsp_state = DSP_DOWNLOAD_FAILED;
2571 else
2572 spec->dsp_state = DSP_DOWNLOADED;
2573 }
2574
2575 if (spec->dsp_state == DSP_DOWNLOADED)
2576 ca0132_set_dsp_msr(codec, true);
2577}
2578
982static int ca0132_init(struct hda_codec *codec) 2579static int ca0132_init(struct hda_codec *codec)
983{ 2580{
984 struct ca0132_spec *spec = codec->spec; 2581 struct ca0132_spec *spec = codec->spec;
985 struct auto_pin_cfg *cfg = &spec->autocfg; 2582 struct auto_pin_cfg *cfg = &spec->autocfg;
986 int i; 2583 int i;
987 2584
2585#ifdef CONFIG_SND_HDA_DSP_LOADER
2586 ca0132_download_dsp(codec);
2587#endif
2588
988 for (i = 0; i < spec->multiout.num_dacs; i++) { 2589 for (i = 0; i < spec->multiout.num_dacs; i++) {
989 init_output(codec, spec->out_pins[i], 2590 init_output(codec, spec->out_pins[i],
990 spec->multiout.dac_nids[i]); 2591 spec->multiout.dac_nids[i]);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 04:20:15 -0500