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authorTakashi Iwai <tiwai@suse.de>2009-06-08 09:31:22 -0400
committerTakashi Iwai <tiwai@suse.de>2009-06-08 09:31:22 -0400
commitd362af62ed98f58c64a2b3dd58c79d25ad181b0b (patch)
treee18d1e960dd3bac08065ce13705efc2cb218d1f2 /sound/pci/ctxfi
parentaf8500bbbd18438495d2f91ad07bda49fff3b770 (diff)
ALSA: ctxfi - Fix / clean up hw20k2 chip code
- Clean up Hungarian coding style - Don't use static variables for I2C information; this unables to use multiple instances. Now they are stored in struct hw20k2 fields. Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/pci/ctxfi')
-rw-r--r--sound/pci/ctxfi/cthw20k2.c346
1 files changed, 177 insertions, 169 deletions
diff --git a/sound/pci/ctxfi/cthw20k2.c b/sound/pci/ctxfi/cthw20k2.c
index 7d6dcbaf5244..4493a51c6b01 100644
--- a/sound/pci/ctxfi/cthw20k2.c
+++ b/sound/pci/ctxfi/cthw20k2.c
@@ -15,8 +15,6 @@
15 * 15 *
16 */ 16 */
17 17
18#include "cthw20k2.h"
19#include "ct20k2reg.h"
20#include <linux/types.h> 18#include <linux/types.h>
21#include <linux/slab.h> 19#include <linux/slab.h>
22#include <linux/pci.h> 20#include <linux/pci.h>
@@ -25,6 +23,8 @@
25#include <linux/kernel.h> 23#include <linux/kernel.h>
26#include <linux/interrupt.h> 24#include <linux/interrupt.h>
27#include <linux/delay.h> 25#include <linux/delay.h>
26#include "cthw20k2.h"
27#include "ct20k2reg.h"
28 28
29#if BITS_PER_LONG == 32 29#if BITS_PER_LONG == 32
30#define CT_XFI_DMA_MASK DMA_BIT_MASK(32) /* 32 bit PTE */ 30#define CT_XFI_DMA_MASK DMA_BIT_MASK(32) /* 32 bit PTE */
@@ -32,6 +32,14 @@
32#define CT_XFI_DMA_MASK DMA_BIT_MASK(64) /* 64 bit PTE */ 32#define CT_XFI_DMA_MASK DMA_BIT_MASK(64) /* 64 bit PTE */
33#endif 33#endif
34 34
35struct hw20k2 {
36 struct hw hw;
37 /* for i2c */
38 unsigned char dev_id;
39 unsigned char addr_size;
40 unsigned char data_size;
41};
42
35static u32 hw_read_20kx(struct hw *hw, u32 reg); 43static u32 hw_read_20kx(struct hw *hw, u32 reg);
36static void hw_write_20kx(struct hw *hw, u32 reg, u32 data); 44static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
37 45
@@ -1125,7 +1133,7 @@ struct trn_conf {
1125 1133
1126static int hw_daio_init(struct hw *hw, const struct daio_conf *info) 1134static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1127{ 1135{
1128 u32 dwData; 1136 u32 data;
1129 int i; 1137 int i;
1130 1138
1131 /* Program I2S with proper sample rate and enable the correct I2S 1139 /* Program I2S with proper sample rate and enable the correct I2S
@@ -1156,12 +1164,12 @@ static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1156 if (i <= 3) { 1164 if (i <= 3) {
1157 /* 1st 3 channels are SPDIFs (SB0960) */ 1165 /* 1st 3 channels are SPDIFs (SB0960) */
1158 if (i == 3) 1166 if (i == 3)
1159 dwData = 0x1001001; 1167 data = 0x1001001;
1160 else 1168 else
1161 dwData = 0x1000001; 1169 data = 0x1000001;
1162 1170
1163 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), dwData); 1171 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1164 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), dwData); 1172 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1165 1173
1166 /* Initialize the SPDIF Out Channel status registers. 1174 /* Initialize the SPDIF Out Channel status registers.
1167 * The value specified here is based on the typical 1175 * The value specified here is based on the typical
@@ -1179,13 +1187,13 @@ static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1179 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B); 1187 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B);
1180 } else { 1188 } else {
1181 /* Next 5 channels are I2S (SB0960) */ 1189 /* Next 5 channels are I2S (SB0960) */
1182 dwData = 0x11; 1190 data = 0x11;
1183 hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), dwData); 1191 hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), data);
1184 if (2 == info->msr) { 1192 if (2 == info->msr) {
1185 /* Four channels per sample period */ 1193 /* Four channels per sample period */
1186 dwData |= 0x1000; 1194 data |= 0x1000;
1187 } 1195 }
1188 hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), dwData); 1196 hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), data);
1189 } 1197 }
1190 } 1198 }
1191 1199
@@ -1377,34 +1385,32 @@ static int hw_auto_init(struct hw *hw)
1377#define I2C_ADDRESS_PTAD 0x0000FFFF 1385#define I2C_ADDRESS_PTAD 0x0000FFFF
1378#define I2C_ADDRESS_SLAD 0x007F0000 1386#define I2C_ADDRESS_SLAD 0x007F0000
1379 1387
1380struct REGS_CS4382 { 1388struct regs_cs4382 {
1381 u32 dwModeControl_1; 1389 u32 mode_control_1;
1382 u32 dwModeControl_2; 1390 u32 mode_control_2;
1383 u32 dwModeControl_3; 1391 u32 mode_control_3;
1384 1392
1385 u32 dwFilterControl; 1393 u32 filter_control;
1386 u32 dwInvertControl; 1394 u32 invert_control;
1387 1395
1388 u32 dwMixControl_P1; 1396 u32 mix_control_P1;
1389 u32 dwVolControl_A1; 1397 u32 vol_control_A1;
1390 u32 dwVolControl_B1; 1398 u32 vol_control_B1;
1391 1399
1392 u32 dwMixControl_P2; 1400 u32 mix_control_P2;
1393 u32 dwVolControl_A2; 1401 u32 vol_control_A2;
1394 u32 dwVolControl_B2; 1402 u32 vol_control_B2;
1395 1403
1396 u32 dwMixControl_P3; 1404 u32 mix_control_P3;
1397 u32 dwVolControl_A3; 1405 u32 vol_control_A3;
1398 u32 dwVolControl_B3; 1406 u32 vol_control_B3;
1399 1407
1400 u32 dwMixControl_P4; 1408 u32 mix_control_P4;
1401 u32 dwVolControl_A4; 1409 u32 vol_control_A4;
1402 u32 dwVolControl_B4; 1410 u32 vol_control_B4;
1403}; 1411};
1404 1412
1405static u8 m_bAddressSize, m_bDataSize, m_bDeviceID; 1413static int hw20k2_i2c_unlock_full_access(struct hw *hw)
1406
1407static int I2CUnlockFullAccess(struct hw *hw)
1408{ 1414{
1409 u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] = {0xB3, 0xD4}; 1415 u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] = {0xB3, 0xD4};
1410 1416
@@ -1420,7 +1426,7 @@ static int I2CUnlockFullAccess(struct hw *hw)
1420 return -1; 1426 return -1;
1421} 1427}
1422 1428
1423static int I2CLockChip(struct hw *hw) 1429static int hw20k2_i2c_lock_chip(struct hw *hw)
1424{ 1430{
1425 /* Write twice */ 1431 /* Write twice */
1426 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED); 1432 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
@@ -1431,54 +1437,55 @@ static int I2CLockChip(struct hw *hw)
1431 return -1; 1437 return -1;
1432} 1438}
1433 1439
1434static int I2CInit(struct hw *hw, u8 bDeviceID, u8 bAddressSize, u8 bDataSize) 1440static int hw20k2_i2c_init(struct hw *hw, u8 dev_id, u8 addr_size, u8 data_size)
1435{ 1441{
1442 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1436 int err; 1443 int err;
1437 unsigned int RegI2CStatus; 1444 unsigned int i2c_status;
1438 unsigned int RegI2CAddress; 1445 unsigned int i2c_addr;
1439 1446
1440 err = I2CUnlockFullAccess(hw); 1447 err = hw20k2_i2c_unlock_full_access(hw);
1441 if (err < 0) 1448 if (err < 0)
1442 return err; 1449 return err;
1443 1450
1444 m_bAddressSize = bAddressSize; 1451 hw20k2->addr_size = addr_size;
1445 m_bDataSize = bDataSize; 1452 hw20k2->data_size = data_size;
1446 m_bDeviceID = bDeviceID; 1453 hw20k2->dev_id = dev_id;
1447 1454
1448 RegI2CAddress = 0; 1455 i2c_addr = 0;
1449 set_field(&RegI2CAddress, I2C_ADDRESS_SLAD, bDeviceID); 1456 set_field(&i2c_addr, I2C_ADDRESS_SLAD, dev_id);
1450 1457
1451 hw_write_20kx(hw, I2C_IF_ADDRESS, RegI2CAddress); 1458 hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
1452 1459
1453 RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS); 1460 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1454 1461
1455 set_field(&RegI2CStatus, I2C_STATUS_DCM, 1); /* Direct control mode */ 1462 set_field(&i2c_status, I2C_STATUS_DCM, 1); /* Direct control mode */
1456 1463
1457 hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus); 1464 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1458 1465
1459 return 0; 1466 return 0;
1460} 1467}
1461 1468
1462static int I2CUninit(struct hw *hw) 1469static int hw20k2_i2c_uninit(struct hw *hw)
1463{ 1470{
1464 unsigned int RegI2CStatus; 1471 unsigned int i2c_status;
1465 unsigned int RegI2CAddress; 1472 unsigned int i2c_addr;
1466 1473
1467 RegI2CAddress = 0; 1474 i2c_addr = 0;
1468 set_field(&RegI2CAddress, I2C_ADDRESS_SLAD, 0x57); /* I2C id */ 1475 set_field(&i2c_addr, I2C_ADDRESS_SLAD, 0x57); /* I2C id */
1469 1476
1470 hw_write_20kx(hw, I2C_IF_ADDRESS, RegI2CAddress); 1477 hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
1471 1478
1472 RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS); 1479 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1473 1480
1474 set_field(&RegI2CStatus, I2C_STATUS_DCM, 0); /* I2C mode */ 1481 set_field(&i2c_status, I2C_STATUS_DCM, 0); /* I2C mode */
1475 1482
1476 hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus); 1483 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1477 1484
1478 return I2CLockChip(hw); 1485 return hw20k2_i2c_lock_chip(hw);
1479} 1486}
1480 1487
1481static int I2CWaitDataReady(struct hw *hw) 1488static int hw20k2_i2c_wait_data_ready(struct hw *hw)
1482{ 1489{
1483 int i = 0x400000; 1490 int i = 0x400000;
1484 unsigned int ret; 1491 unsigned int ret;
@@ -1490,51 +1497,53 @@ static int I2CWaitDataReady(struct hw *hw)
1490 return i; 1497 return i;
1491} 1498}
1492 1499
1493static int I2CRead(struct hw *hw, u16 wAddress, u32 *pdwData) 1500static int hw20k2_i2c_read(struct hw *hw, u16 addr, u32 *datap)
1494{ 1501{
1495 unsigned int RegI2CStatus; 1502 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1503 unsigned int i2c_status;
1496 1504
1497 RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS); 1505 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1498 set_field(&RegI2CStatus, I2C_STATUS_BC, 1506 set_field(&i2c_status, I2C_STATUS_BC,
1499 (4 == m_bAddressSize) ? 0 : m_bAddressSize); 1507 (4 == hw20k2->addr_size) ? 0 : hw20k2->addr_size);
1500 hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus); 1508 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1501 if (!I2CWaitDataReady(hw)) 1509 if (!hw20k2_i2c_wait_data_ready(hw))
1502 return -1; 1510 return -1;
1503 1511
1504 hw_write_20kx(hw, I2C_IF_WDATA, (u32)wAddress); 1512 hw_write_20kx(hw, I2C_IF_WDATA, addr);
1505 if (!I2CWaitDataReady(hw)) 1513 if (!hw20k2_i2c_wait_data_ready(hw))
1506 return -1; 1514 return -1;
1507 1515
1508 /* Force a read operation */ 1516 /* Force a read operation */
1509 hw_write_20kx(hw, I2C_IF_RDATA, 0); 1517 hw_write_20kx(hw, I2C_IF_RDATA, 0);
1510 if (!I2CWaitDataReady(hw)) 1518 if (!hw20k2_i2c_wait_data_ready(hw))
1511 return -1; 1519 return -1;
1512 1520
1513 *pdwData = hw_read_20kx(hw, I2C_IF_RDATA); 1521 *datap = hw_read_20kx(hw, I2C_IF_RDATA);
1514 1522
1515 return 0; 1523 return 0;
1516} 1524}
1517 1525
1518static int I2CWrite(struct hw *hw, u16 wAddress, u32 dwData) 1526static int hw20k2_i2c_write(struct hw *hw, u16 addr, u32 data)
1519{ 1527{
1520 unsigned int dwI2CData = (dwData << (m_bAddressSize * 8)) | wAddress; 1528 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1521 unsigned int RegI2CStatus; 1529 unsigned int i2c_data = (data << (hw20k2->addr_size * 8)) | addr;
1530 unsigned int i2c_status;
1522 1531
1523 RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS); 1532 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1524 1533
1525 set_field(&RegI2CStatus, I2C_STATUS_BC, 1534 set_field(&i2c_status, I2C_STATUS_BC,
1526 (4 == (m_bAddressSize + m_bDataSize)) ? 1535 (4 == (hw20k2->addr_size + hw20k2->data_size)) ?
1527 0 : (m_bAddressSize + m_bDataSize)); 1536 0 : (hw20k2->addr_size + hw20k2->data_size));
1528 1537
1529 hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus); 1538 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1530 I2CWaitDataReady(hw); 1539 hw20k2_i2c_wait_data_ready(hw);
1531 /* Dummy write to trigger the write oprtation */ 1540 /* Dummy write to trigger the write oprtation */
1532 hw_write_20kx(hw, I2C_IF_WDATA, 0); 1541 hw_write_20kx(hw, I2C_IF_WDATA, 0);
1533 I2CWaitDataReady(hw); 1542 hw20k2_i2c_wait_data_ready(hw);
1534 1543
1535 /* This is the real data */ 1544 /* This is the real data */
1536 hw_write_20kx(hw, I2C_IF_WDATA, dwI2CData); 1545 hw_write_20kx(hw, I2C_IF_WDATA, i2c_data);
1537 I2CWaitDataReady(hw); 1546 hw20k2_i2c_wait_data_ready(hw);
1538 1547
1539 return 0; 1548 return 0;
1540} 1549}
@@ -1542,10 +1551,10 @@ static int I2CWrite(struct hw *hw, u16 wAddress, u32 dwData)
1542static int hw_dac_init(struct hw *hw, const struct dac_conf *info) 1551static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1543{ 1552{
1544 int err; 1553 int err;
1545 u32 dwData; 1554 u32 data;
1546 int i; 1555 int i;
1547 struct REGS_CS4382 cs4382_Read = {0}; 1556 struct regs_cs4382 cs_read = {0};
1548 struct REGS_CS4382 cs4382_Def = { 1557 struct regs_cs4382 cs_def = {
1549 0x00000001, /* Mode Control 1 */ 1558 0x00000001, /* Mode Control 1 */
1550 0x00000000, /* Mode Control 2 */ 1559 0x00000000, /* Mode Control 2 */
1551 0x00000084, /* Mode Control 3 */ 1560 0x00000084, /* Mode Control 3 */
@@ -1566,87 +1575,86 @@ static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1566 }; 1575 };
1567 1576
1568 /* Set DAC reset bit as output */ 1577 /* Set DAC reset bit as output */
1569 dwData = hw_read_20kx(hw, GPIO_CTRL); 1578 data = hw_read_20kx(hw, GPIO_CTRL);
1570 dwData |= 0x02; 1579 data |= 0x02;
1571 hw_write_20kx(hw, GPIO_CTRL, dwData); 1580 hw_write_20kx(hw, GPIO_CTRL, data);
1572 1581
1573 err = I2CInit(hw, 0x18, 1, 1); 1582 err = hw20k2_i2c_init(hw, 0x18, 1, 1);
1574 if (err < 0) 1583 if (err < 0)
1575 goto End; 1584 goto End;
1576 1585
1577 for (i = 0; i < 2; i++) { 1586 for (i = 0; i < 2; i++) {
1578 /* Reset DAC twice just in-case the chip 1587 /* Reset DAC twice just in-case the chip
1579 * didn't initialized properly */ 1588 * didn't initialized properly */
1580 dwData = hw_read_20kx(hw, GPIO_DATA); 1589 data = hw_read_20kx(hw, GPIO_DATA);
1581 /* GPIO data bit 1 */ 1590 /* GPIO data bit 1 */
1582 dwData &= 0xFFFFFFFD; 1591 data &= 0xFFFFFFFD;
1583 hw_write_20kx(hw, GPIO_DATA, dwData); 1592 hw_write_20kx(hw, GPIO_DATA, data);
1584 mdelay(10); 1593 mdelay(10);
1585 dwData |= 0x2; 1594 data |= 0x2;
1586 hw_write_20kx(hw, GPIO_DATA, dwData); 1595 hw_write_20kx(hw, GPIO_DATA, data);
1587 mdelay(50); 1596 mdelay(50);
1588 1597
1589 /* Reset the 2nd time */ 1598 /* Reset the 2nd time */
1590 dwData &= 0xFFFFFFFD; 1599 data &= 0xFFFFFFFD;
1591 hw_write_20kx(hw, GPIO_DATA, dwData); 1600 hw_write_20kx(hw, GPIO_DATA, data);
1592 mdelay(10); 1601 mdelay(10);
1593 dwData |= 0x2; 1602 data |= 0x2;
1594 hw_write_20kx(hw, GPIO_DATA, dwData); 1603 hw_write_20kx(hw, GPIO_DATA, data);
1595 mdelay(50); 1604 mdelay(50);
1596 1605
1597 if (I2CRead(hw, CS4382_MC1, &cs4382_Read.dwModeControl_1)) 1606 if (hw20k2_i2c_read(hw, CS4382_MC1, &cs_read.mode_control_1))
1598 continue; 1607 continue;
1599 1608
1600 if (I2CRead(hw, CS4382_MC2, &cs4382_Read.dwModeControl_2)) 1609 if (hw20k2_i2c_read(hw, CS4382_MC2, &cs_read.mode_control_2))
1601 continue; 1610 continue;
1602 1611
1603 if (I2CRead(hw, CS4382_MC3, &cs4382_Read.dwModeControl_3)) 1612 if (hw20k2_i2c_read(hw, CS4382_MC3, &cs_read.mode_control_3))
1604 continue; 1613 continue;
1605 1614
1606 if (I2CRead(hw, CS4382_FC, &cs4382_Read.dwFilterControl)) 1615 if (hw20k2_i2c_read(hw, CS4382_FC, &cs_read.filter_control))
1607 continue; 1616 continue;
1608 1617
1609 if (I2CRead(hw, CS4382_IC, &cs4382_Read.dwInvertControl)) 1618 if (hw20k2_i2c_read(hw, CS4382_IC, &cs_read.invert_control))
1610 continue; 1619 continue;
1611 1620
1612 if (I2CRead(hw, CS4382_XC1, &cs4382_Read.dwMixControl_P1)) 1621 if (hw20k2_i2c_read(hw, CS4382_XC1, &cs_read.mix_control_P1))
1613 continue; 1622 continue;
1614 1623
1615 if (I2CRead(hw, CS4382_VCA1, &cs4382_Read.dwVolControl_A1)) 1624 if (hw20k2_i2c_read(hw, CS4382_VCA1, &cs_read.vol_control_A1))
1616 continue; 1625 continue;
1617 1626
1618 if (I2CRead(hw, CS4382_VCB1, &cs4382_Read.dwVolControl_B1)) 1627 if (hw20k2_i2c_read(hw, CS4382_VCB1, &cs_read.vol_control_B1))
1619 continue; 1628 continue;
1620 1629
1621 if (I2CRead(hw, CS4382_XC2, &cs4382_Read.dwMixControl_P2)) 1630 if (hw20k2_i2c_read(hw, CS4382_XC2, &cs_read.mix_control_P2))
1622 continue; 1631 continue;
1623 1632
1624 if (I2CRead(hw, CS4382_VCA2, &cs4382_Read.dwVolControl_A2)) 1633 if (hw20k2_i2c_read(hw, CS4382_VCA2, &cs_read.vol_control_A2))
1625 continue; 1634 continue;
1626 1635
1627 if (I2CRead(hw, CS4382_VCB2, &cs4382_Read.dwVolControl_B2)) 1636 if (hw20k2_i2c_read(hw, CS4382_VCB2, &cs_read.vol_control_B2))
1628 continue; 1637 continue;
1629 1638
1630 if (I2CRead(hw, CS4382_XC3, &cs4382_Read.dwMixControl_P3)) 1639 if (hw20k2_i2c_read(hw, CS4382_XC3, &cs_read.mix_control_P3))
1631 continue; 1640 continue;
1632 1641
1633 if (I2CRead(hw, CS4382_VCA3, &cs4382_Read.dwVolControl_A3)) 1642 if (hw20k2_i2c_read(hw, CS4382_VCA3, &cs_read.vol_control_A3))
1634 continue; 1643 continue;
1635 1644
1636 if (I2CRead(hw, CS4382_VCB3, &cs4382_Read.dwVolControl_B3)) 1645 if (hw20k2_i2c_read(hw, CS4382_VCB3, &cs_read.vol_control_B3))
1637 continue; 1646 continue;
1638 1647
1639 if (I2CRead(hw, CS4382_XC4, &cs4382_Read.dwMixControl_P4)) 1648 if (hw20k2_i2c_read(hw, CS4382_XC4, &cs_read.mix_control_P4))
1640 continue; 1649 continue;
1641 1650
1642 if (I2CRead(hw, CS4382_VCA4, &cs4382_Read.dwVolControl_A4)) 1651 if (hw20k2_i2c_read(hw, CS4382_VCA4, &cs_read.vol_control_A4))
1643 continue; 1652 continue;
1644 1653
1645 if (I2CRead(hw, CS4382_VCB4, &cs4382_Read.dwVolControl_B4)) 1654 if (hw20k2_i2c_read(hw, CS4382_VCB4, &cs_read.vol_control_B4))
1646 continue; 1655 continue;
1647 1656
1648 if (memcmp(&cs4382_Read, &cs4382_Def, 1657 if (memcmp(&cs_read, &cs_def, sizeof(cs_read)))
1649 sizeof(struct REGS_CS4382)))
1650 continue; 1658 continue;
1651 else 1659 else
1652 break; 1660 break;
@@ -1657,29 +1665,29 @@ static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1657 1665
1658 /* Note: Every I2C write must have some delay. 1666 /* Note: Every I2C write must have some delay.
1659 * This is not a requirement but the delay works here... */ 1667 * This is not a requirement but the delay works here... */
1660 I2CWrite(hw, CS4382_MC1, 0x80); 1668 hw20k2_i2c_write(hw, CS4382_MC1, 0x80);
1661 I2CWrite(hw, CS4382_MC2, 0x10); 1669 hw20k2_i2c_write(hw, CS4382_MC2, 0x10);
1662 if (1 == info->msr) { 1670 if (1 == info->msr) {
1663 I2CWrite(hw, CS4382_XC1, 0x24); 1671 hw20k2_i2c_write(hw, CS4382_XC1, 0x24);
1664 I2CWrite(hw, CS4382_XC2, 0x24); 1672 hw20k2_i2c_write(hw, CS4382_XC2, 0x24);
1665 I2CWrite(hw, CS4382_XC3, 0x24); 1673 hw20k2_i2c_write(hw, CS4382_XC3, 0x24);
1666 I2CWrite(hw, CS4382_XC4, 0x24); 1674 hw20k2_i2c_write(hw, CS4382_XC4, 0x24);
1667 } else if (2 == info->msr) { 1675 } else if (2 == info->msr) {
1668 I2CWrite(hw, CS4382_XC1, 0x25); 1676 hw20k2_i2c_write(hw, CS4382_XC1, 0x25);
1669 I2CWrite(hw, CS4382_XC2, 0x25); 1677 hw20k2_i2c_write(hw, CS4382_XC2, 0x25);
1670 I2CWrite(hw, CS4382_XC3, 0x25); 1678 hw20k2_i2c_write(hw, CS4382_XC3, 0x25);
1671 I2CWrite(hw, CS4382_XC4, 0x25); 1679 hw20k2_i2c_write(hw, CS4382_XC4, 0x25);
1672 } else { 1680 } else {
1673 I2CWrite(hw, CS4382_XC1, 0x26); 1681 hw20k2_i2c_write(hw, CS4382_XC1, 0x26);
1674 I2CWrite(hw, CS4382_XC2, 0x26); 1682 hw20k2_i2c_write(hw, CS4382_XC2, 0x26);
1675 I2CWrite(hw, CS4382_XC3, 0x26); 1683 hw20k2_i2c_write(hw, CS4382_XC3, 0x26);
1676 I2CWrite(hw, CS4382_XC4, 0x26); 1684 hw20k2_i2c_write(hw, CS4382_XC4, 0x26);
1677 } 1685 }
1678 1686
1679 return 0; 1687 return 0;
1680End: 1688End:
1681 1689
1682 I2CUninit(hw); 1690 hw20k2_i2c_uninit(hw);
1683 return -1; 1691 return -1;
1684} 1692}
1685 1693
@@ -1721,21 +1729,21 @@ static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1721 case ADC_MICIN: 1729 case ADC_MICIN:
1722 data |= (0x1 << 14); 1730 data |= (0x1 << 14);
1723 hw_write_20kx(hw, GPIO_DATA, data); 1731 hw_write_20kx(hw, GPIO_DATA, data);
1724 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101), 1732 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
1725 MAKE_WM8775_DATA(0x101)); /* Mic-in */ 1733 MAKE_WM8775_DATA(0x101)); /* Mic-in */
1726 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7), 1734 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
1727 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */ 1735 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1728 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7), 1736 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
1729 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */ 1737 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1730 break; 1738 break;
1731 case ADC_LINEIN: 1739 case ADC_LINEIN:
1732 data &= ~(0x1 << 14); 1740 data &= ~(0x1 << 14);
1733 hw_write_20kx(hw, GPIO_DATA, data); 1741 hw_write_20kx(hw, GPIO_DATA, data);
1734 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102), 1742 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
1735 MAKE_WM8775_DATA(0x102)); /* Line-in */ 1743 MAKE_WM8775_DATA(0x102)); /* Line-in */
1736 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF), 1744 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
1737 MAKE_WM8775_DATA(0xCF)); /* No boost */ 1745 MAKE_WM8775_DATA(0xCF)); /* No boost */
1738 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF), 1746 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
1739 MAKE_WM8775_DATA(0xCF)); /* No boost */ 1747 MAKE_WM8775_DATA(0xCF)); /* No boost */
1740 break; 1748 break;
1741 default: 1749 default:
@@ -1748,34 +1756,34 @@ static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1748static int hw_adc_init(struct hw *hw, const struct adc_conf *info) 1756static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1749{ 1757{
1750 int err; 1758 int err;
1751 u32 dwMux = 2, dwData, dwCtl; 1759 u32 mux = 2, data, ctl;
1752 1760
1753 /* Set ADC reset bit as output */ 1761 /* Set ADC reset bit as output */
1754 dwData = hw_read_20kx(hw, GPIO_CTRL); 1762 data = hw_read_20kx(hw, GPIO_CTRL);
1755 dwData |= (0x1 << 15); 1763 data |= (0x1 << 15);
1756 hw_write_20kx(hw, GPIO_CTRL, dwData); 1764 hw_write_20kx(hw, GPIO_CTRL, data);
1757 1765
1758 /* Initialize I2C */ 1766 /* Initialize I2C */
1759 err = I2CInit(hw, 0x1A, 1, 1); 1767 err = hw20k2_i2c_init(hw, 0x1A, 1, 1);
1760 if (err < 0) { 1768 if (err < 0) {
1761 printk(KERN_ALERT "ctxfi: Failure to acquire I2C!!!\n"); 1769 printk(KERN_ALERT "ctxfi: Failure to acquire I2C!!!\n");
1762 goto error; 1770 goto error;
1763 } 1771 }
1764 1772
1765 /* Make ADC in normal operation */ 1773 /* Make ADC in normal operation */
1766 dwData = hw_read_20kx(hw, GPIO_DATA); 1774 data = hw_read_20kx(hw, GPIO_DATA);
1767 dwData &= ~(0x1 << 15); 1775 data &= ~(0x1 << 15);
1768 mdelay(10); 1776 mdelay(10);
1769 dwData |= (0x1 << 15); 1777 data |= (0x1 << 15);
1770 hw_write_20kx(hw, GPIO_DATA, dwData); 1778 hw_write_20kx(hw, GPIO_DATA, data);
1771 mdelay(50); 1779 mdelay(50);
1772 1780
1773 /* Set the master mode (256fs) */ 1781 /* Set the master mode (256fs) */
1774 if (1 == info->msr) { 1782 if (1 == info->msr) {
1775 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02), 1783 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02),
1776 MAKE_WM8775_DATA(0x02)); 1784 MAKE_WM8775_DATA(0x02));
1777 } else if (2 == info->msr) { 1785 } else if (2 == info->msr) {
1778 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A), 1786 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A),
1779 MAKE_WM8775_DATA(0x0A)); 1787 MAKE_WM8775_DATA(0x0A));
1780 } else { 1788 } else {
1781 printk(KERN_ALERT "ctxfi: Invalid master sampling " 1789 printk(KERN_ALERT "ctxfi: Invalid master sampling "
@@ -1785,35 +1793,35 @@ static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1785 } 1793 }
1786 1794
1787 /* Configure GPIO bit 14 change to line-in/mic-in */ 1795 /* Configure GPIO bit 14 change to line-in/mic-in */
1788 dwCtl = hw_read_20kx(hw, GPIO_CTRL); 1796 ctl = hw_read_20kx(hw, GPIO_CTRL);
1789 dwCtl |= 0x1<<14; 1797 ctl |= 0x1 << 14;
1790 hw_write_20kx(hw, GPIO_CTRL, dwCtl); 1798 hw_write_20kx(hw, GPIO_CTRL, ctl);
1791 1799
1792 /* Check using Mic-in or Line-in */ 1800 /* Check using Mic-in or Line-in */
1793 dwData = hw_read_20kx(hw, GPIO_DATA); 1801 data = hw_read_20kx(hw, GPIO_DATA);
1794 1802
1795 if (dwMux == 1) { 1803 if (mux == 1) {
1796 /* Configures GPIO data to select Mic-in */ 1804 /* Configures GPIO data to select Mic-in */
1797 dwData |= 0x1<<14; 1805 data |= 0x1 << 14;
1798 hw_write_20kx(hw, GPIO_DATA, dwData); 1806 hw_write_20kx(hw, GPIO_DATA, data);
1799 1807
1800 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101), 1808 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
1801 MAKE_WM8775_DATA(0x101)); /* Mic-in */ 1809 MAKE_WM8775_DATA(0x101)); /* Mic-in */
1802 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7), 1810 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
1803 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */ 1811 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1804 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7), 1812 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
1805 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */ 1813 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1806 } else if (dwMux == 2) { 1814 } else if (mux == 2) {
1807 /* Configures GPIO data to select Line-in */ 1815 /* Configures GPIO data to select Line-in */
1808 dwData &= ~(0x1<<14); 1816 data &= ~(0x1 << 14);
1809 hw_write_20kx(hw, GPIO_DATA, dwData); 1817 hw_write_20kx(hw, GPIO_DATA, data);
1810 1818
1811 /* Setup ADC */ 1819 /* Setup ADC */
1812 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102), 1820 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
1813 MAKE_WM8775_DATA(0x102)); /* Line-in */ 1821 MAKE_WM8775_DATA(0x102)); /* Line-in */
1814 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF), 1822 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
1815 MAKE_WM8775_DATA(0xCF)); /* No boost */ 1823 MAKE_WM8775_DATA(0xCF)); /* No boost */
1816 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF), 1824 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
1817 MAKE_WM8775_DATA(0xCF)); /* No boost */ 1825 MAKE_WM8775_DATA(0xCF)); /* No boost */
1818 } else { 1826 } else {
1819 printk(KERN_ALERT "ctxfi: ERROR!!! Invalid input mux!!!\n"); 1827 printk(KERN_ALERT "ctxfi: ERROR!!! Invalid input mux!!!\n");
@@ -1824,7 +1832,7 @@ static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1824 return 0; 1832 return 0;
1825 1833
1826error: 1834error:
1827 I2CUninit(hw); 1835 hw20k2_i2c_uninit(hw);
1828 return err; 1836 return err;
1829} 1837}
1830 1838
@@ -2106,15 +2114,15 @@ static struct hw ct20k2_preset __devinitdata = {
2106 2114
2107int __devinit create_20k2_hw_obj(struct hw **rhw) 2115int __devinit create_20k2_hw_obj(struct hw **rhw)
2108{ 2116{
2109 struct hw *hw; 2117 struct hw20k2 *hw20k2;
2110 2118
2111 *rhw = NULL; 2119 *rhw = NULL;
2112 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 2120 hw20k2 = kzalloc(sizeof(*hw20k2), GFP_KERNEL);
2113 if (NULL == hw) 2121 if (!hw20k2)
2114 return -ENOMEM; 2122 return -ENOMEM;
2115 2123
2116 *hw = ct20k2_preset; 2124 hw20k2->hw = ct20k2_preset;
2117 *rhw = hw; 2125 *rhw = &hw20k2->hw;
2118 2126
2119 return 0; 2127 return 0;
2120} 2128}