diff options
author | James Courtier-Dutton <James@superbug.co.uk> | 2005-05-27 16:07:23 -0400 |
---|---|---|
committer | Jaroslav Kysela <perex@suse.cz> | 2005-06-22 06:27:06 -0400 |
commit | 7199acdc74dc16d2e75f83b8c65301ad19c40ef3 (patch) | |
tree | 923cbbe39b3e82e3f24ffcc04dce864995d6a199 /sound/pci/ca0106/ca0106.h | |
parent | da04b128cf0d74dd4cab270c53d9264e70f9203e (diff) |
[ALSA] Implement support for Line-in capture on SB Live 24bit.
CA0106 driver
Notes: MIC capture not tested yet.
Signed-off-by: James Courtier-Dutton <James@superbug.co.uk>
Diffstat (limited to 'sound/pci/ca0106/ca0106.h')
-rw-r--r-- | sound/pci/ca0106/ca0106.h | 61 |
1 files changed, 57 insertions, 4 deletions
diff --git a/sound/pci/ca0106/ca0106.h b/sound/pci/ca0106/ca0106.h index c623858428cd..67e56a530b22 100644 --- a/sound/pci/ca0106/ca0106.h +++ b/sound/pci/ca0106/ca0106.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk> | 2 | * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk> |
3 | * Driver CA0106 chips. e.g. Sound Blaster Audigy LS and Live 24bit | 3 | * Driver CA0106 chips. e.g. Sound Blaster Audigy LS and Live 24bit |
4 | * Version: 0.0.20 | 4 | * Version: 0.0.21 |
5 | * | 5 | * |
6 | * FEATURES currently supported: | 6 | * FEATURES currently supported: |
7 | * See ca0106_main.c for features. | 7 | * See ca0106_main.c for features. |
@@ -45,6 +45,8 @@ | |||
45 | * Added I2C and SPI registers. Filled in interrupt enable. | 45 | * Added I2C and SPI registers. Filled in interrupt enable. |
46 | * 0.0.20 | 46 | * 0.0.20 |
47 | * Added GPIO info for SB Live 24bit. | 47 | * Added GPIO info for SB Live 24bit. |
48 | * 0.0.21 | ||
49 | * Implement support for Line-in capture on SB Live 24bit. | ||
48 | * | 50 | * |
49 | * | 51 | * |
50 | * This code was initally based on code from ALSA's emu10k1x.c which is: | 52 | * This code was initally based on code from ALSA's emu10k1x.c which is: |
@@ -475,9 +477,56 @@ | |||
475 | /* Causes interrupts based on timer intervals. */ | 477 | /* Causes interrupts based on timer intervals. */ |
476 | #define SPI 0x7a /* SPI: Serial Interface Register */ | 478 | #define SPI 0x7a /* SPI: Serial Interface Register */ |
477 | #define I2C_A 0x7b /* I2C Address. 32 bit */ | 479 | #define I2C_A 0x7b /* I2C Address. 32 bit */ |
478 | #define I2C_0 0x7c /* I2C Data Port 0. 32 bit */ | 480 | #define I2C_D0 0x7c /* I2C Data Port 0. 32 bit */ |
479 | #define I2C_1 0x7d /* I2C Data Port 1. 32 bit */ | 481 | #define I2C_D1 0x7d /* I2C Data Port 1. 32 bit */ |
480 | 482 | //I2C values | |
483 | #define I2C_A_ADC_ADD_MASK 0x000000fe //The address is a 7 bit address | ||
484 | #define I2C_A_ADC_RW_MASK 0x00000001 //bit mask for R/W | ||
485 | #define I2C_A_ADC_TRANS_MASK 0x00000010 //Bit mask for I2c address DAC value | ||
486 | #define I2C_A_ADC_ABORT_MASK 0x00000020 //Bit mask for I2C transaction abort flag | ||
487 | #define I2C_A_ADC_LAST_MASK 0x00000040 //Bit mask for Last word transaction | ||
488 | #define I2C_A_ADC_BYTE_MASK 0x00000080 //Bit mask for Byte Mode | ||
489 | |||
490 | #define I2C_A_ADC_ADD 0x00000034 //This is the Device address for ADC | ||
491 | #define I2C_A_ADC_READ 0x00000001 //To perform a read operation | ||
492 | #define I2C_A_ADC_START 0x00000100 //Start I2C transaction | ||
493 | #define I2C_A_ADC_ABORT 0x00000200 //I2C transaction abort | ||
494 | #define I2C_A_ADC_LAST 0x00000400 //I2C last transaction | ||
495 | #define I2C_A_ADC_BYTE 0x00000800 //I2C one byte mode | ||
496 | |||
497 | #define I2C_D_ADC_REG_MASK 0xfe000000 //ADC address register | ||
498 | #define I2C_D_ADC_DAT_MASK 0x01ff0000 //ADC data register | ||
499 | |||
500 | #define ADC_TIMEOUT 0x00000007 //ADC Timeout Clock Disable | ||
501 | #define ADC_IFC_CTRL 0x0000000b //ADC Interface Control | ||
502 | #define ADC_MASTER 0x0000000c //ADC Master Mode Control | ||
503 | #define ADC_POWER 0x0000000d //ADC PowerDown Control | ||
504 | #define ADC_ATTEN_ADCL 0x0000000e //ADC Attenuation ADCL | ||
505 | #define ADC_ATTEN_ADCR 0x0000000f //ADC Attenuation ADCR | ||
506 | #define ADC_ALC_CTRL1 0x00000010 //ADC ALC Control 1 | ||
507 | #define ADC_ALC_CTRL2 0x00000011 //ADC ALC Control 2 | ||
508 | #define ADC_ALC_CTRL3 0x00000012 //ADC ALC Control 3 | ||
509 | #define ADC_NOISE_CTRL 0x00000013 //ADC Noise Gate Control | ||
510 | #define ADC_LIMIT_CTRL 0x00000014 //ADC Limiter Control | ||
511 | #define ADC_MUX 0x00000015 //ADC Mux offset | ||
512 | |||
513 | #if 0 | ||
514 | /* FIXME: Not tested yet. */ | ||
515 | #define ADC_GAIN_MASK 0x000000ff //Mask for ADC Gain | ||
516 | #define ADC_ZERODB 0x000000cf //Value to set ADC to 0dB | ||
517 | #define ADC_MUTE_MASK 0x000000c0 //Mask for ADC mute | ||
518 | #define ADC_MUTE 0x000000c0 //Value to mute ADC | ||
519 | #define ADC_OSR 0x00000008 //Mask for ADC oversample rate select | ||
520 | #define ADC_TIMEOUT_DISABLE 0x00000008 //Value and mask to disable Timeout clock | ||
521 | #define ADC_HPF_DISABLE 0x00000100 //Value and mask to disable High pass filter | ||
522 | #define ADC_TRANWIN_MASK 0x00000070 //Mask for Length of Transient Window | ||
523 | #endif | ||
524 | |||
525 | #define ADC_MUX_MASK 0x0000000f //Mask for ADC Mux | ||
526 | #define ADC_MUX_MIC 0x00000002 //Value to select Mic at ADC Mux | ||
527 | #define ADC_MUX_LINEIN 0x00000004 //Value to select LineIn at ADC Mux | ||
528 | #define ADC_MUX_PHONE 0x00000001 //Value to select TAD at ADC Mux (Not used) | ||
529 | #define ADC_MUX_AUX 0x00000008 //Value to select Aux at ADC Mux | ||
481 | 530 | ||
482 | #define SET_CHANNEL 0 /* Testing channel outputs 0=Front, 1=Center/LFE, 2=Unknown, 3=Rear */ | 531 | #define SET_CHANNEL 0 /* Testing channel outputs 0=Front, 1=Center/LFE, 2=Unknown, 3=Rear */ |
483 | #define PCM_FRONT_CHANNEL 0 | 532 | #define PCM_FRONT_CHANNEL 0 |
@@ -513,6 +562,7 @@ typedef struct { | |||
513 | char * name; | 562 | char * name; |
514 | int ac97; | 563 | int ac97; |
515 | int gpio_type; | 564 | int gpio_type; |
565 | int i2c_adc; | ||
516 | } ca0106_details_t; | 566 | } ca0106_details_t; |
517 | 567 | ||
518 | // definition of the chip-specific record | 568 | // definition of the chip-specific record |
@@ -555,3 +605,6 @@ void snd_ca0106_ptr_write(ca0106_t *emu, | |||
555 | unsigned int chn, | 605 | unsigned int chn, |
556 | unsigned int data); | 606 | unsigned int data); |
557 | 607 | ||
608 | int snd_ca0106_i2c_write(ca0106_t *emu, u32 reg, u32 value); | ||
609 | |||
610 | |||