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authorAndreas Mohr <andi@lisas.de>2009-07-05 07:55:46 -0400
committerTakashi Iwai <tiwai@suse.de>2009-07-06 02:24:47 -0400
commitdfbf9511155d3584b8747c935216077f46eb9a4f (patch)
tree0591d571c38dd032eff9c2ca41ab1c34e19aa4f8 /sound/pci/azt3328.h
parent3eff8958308ed875a4e845d59a498288f8bbad77 (diff)
ALSA: azt3328: large codec cleanup, add I2S port etc.
- fully separate codec I/O port handling, enabling the use of a single function each for all codecs (playback, capture, I2S out) - add a new separate pcm for I2S out port (UNTESTED, no I2S DAC available yet) - switch gameport to low frequency while idle, to try to reduce noise/power - improve snd_azf3328_codec_setdmaa() calculation - minor variable type cleanup (u16, bool etc.) - add some doc updates (help those lost Windows users, debug help, ...) Note that due to the large cleanup aspect of the codec I/O change, I was able to fit everything including all improvements into the same binary size!! (a measly 10 bytes more or so) This should now be the almost last patch to this driver (minus some possible kernel clocksource patch and x86_64 fixes or so). I just felt like taking a break from the usual stuff and wanted to get this driver's structure finished, and it's rather clean now... Tested, working and checkpatch.pl:ed on 2.6.30-rc5, applies cleanly to 2.6.30 proper. Signed-off-by: Andreas Mohr <andi@lisas.de> Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/pci/azt3328.h')
-rw-r--r--sound/pci/azt3328.h87
1 files changed, 40 insertions, 47 deletions
diff --git a/sound/pci/azt3328.h b/sound/pci/azt3328.h
index 974e05122f00..11d4b108b8db 100644
--- a/sound/pci/azt3328.h
+++ b/sound/pci/azt3328.h
@@ -6,50 +6,59 @@
6 6
7/*** main I/O area port indices ***/ 7/*** main I/O area port indices ***/
8/* (only 0x70 of 0x80 bytes saved/restored by Windows driver) */ 8/* (only 0x70 of 0x80 bytes saved/restored by Windows driver) */
9#define AZF_IO_SIZE_CODEC 0x80 9#define AZF_IO_SIZE_CTRL 0x80
10#define AZF_IO_SIZE_CODEC_PM 0x70 10#define AZF_IO_SIZE_CTRL_PM 0x70
11 11
12/* the driver initialisation suggests a layout of 4 main areas: 12/* the driver initialisation suggests a layout of 4 areas
13 * from 0x00 (playback), from 0x20 (recording) and from 0x40 (maybe MPU401??). 13 * within the main card control I/O:
14 * from 0x00 (playback codec), from 0x20 (recording codec)
15 * and from 0x40 (most certainly I2S out codec).
14 * And another area from 0x60 to 0x6f (DirectX timer, IRQ management, 16 * And another area from 0x60 to 0x6f (DirectX timer, IRQ management,
15 * power management etc.???). */ 17 * power management etc.???). */
16 18
17/** playback area **/ 19#define AZF_IO_OFFS_CODEC_PLAYBACK 0x00
18#define IDX_IO_PLAY_FLAGS 0x00 /* PU:0x0000 */ 20#define AZF_IO_OFFS_CODEC_CAPTURE 0x20
21#define AZF_IO_OFFS_CODEC_I2S_OUT 0x40
22
23#define IDX_IO_CODEC_DMA_FLAGS 0x00 /* PU:0x0000 */
19 /* able to reactivate output after output muting due to 8/16bit 24 /* able to reactivate output after output muting due to 8/16bit
20 * output change, just like 0x0002. 25 * output change, just like 0x0002.
21 * 0x0001 is the only bit that's able to start the DMA counter */ 26 * 0x0001 is the only bit that's able to start the DMA counter */
22 #define DMA_RESUME 0x0001 /* paused if cleared ? */ 27 #define DMA_RESUME 0x0001 /* paused if cleared? */
23 /* 0x0002 *temporarily* set during DMA stopping. hmm 28 /* 0x0002 *temporarily* set during DMA stopping. hmm
24 * both 0x0002 and 0x0004 set in playback setup. */ 29 * both 0x0002 and 0x0004 set in playback setup. */
25 /* able to reactivate output after output muting due to 8/16bit 30 /* able to reactivate output after output muting due to 8/16bit
26 * output change, just like 0x0001. */ 31 * output change, just like 0x0001. */
27 #define DMA_PLAY_SOMETHING1 0x0002 /* \ alternated (toggled) */ 32 #define DMA_RUN_SOMETHING1 0x0002 /* \ alternated (toggled) */
28 /* 0x0004: NOT able to reactivate output */ 33 /* 0x0004: NOT able to reactivate output */
29 #define DMA_PLAY_SOMETHING2 0x0004 /* / bits */ 34 #define DMA_RUN_SOMETHING2 0x0004 /* / bits */
30 #define SOMETHING_ALMOST_ALWAYS_SET 0x0008 /* ???; can be modified */ 35 #define SOMETHING_ALMOST_ALWAYS_SET 0x0008 /* ???; can be modified */
31 #define DMA_EPILOGUE_SOMETHING 0x0010 36 #define DMA_EPILOGUE_SOMETHING 0x0010
32 #define DMA_SOMETHING_ELSE 0x0020 /* ??? */ 37 #define DMA_SOMETHING_ELSE 0x0020 /* ??? */
33 #define SOMETHING_UNMODIFIABLE 0xffc0 /* unused ? not modifiable */ 38 #define SOMETHING_UNMODIFIABLE 0xffc0 /* unused? not modifiable */
34#define IDX_IO_PLAY_IRQTYPE 0x02 /* PU:0x0001 */ 39#define IDX_IO_CODEC_IRQTYPE 0x02 /* PU:0x0001 */
35 /* write back to flags in case flags are set, in order to ACK IRQ in handler 40 /* write back to flags in case flags are set, in order to ACK IRQ in handler
36 * (bit 1 of port 0x64 indicates interrupt for one of these three types) 41 * (bit 1 of port 0x64 indicates interrupt for one of these three types)
37 * sometimes in this case it just writes 0xffff to globally ACK all IRQs 42 * sometimes in this case it just writes 0xffff to globally ACK all IRQs
38 * settings written are not reflected when reading back, though. 43 * settings written are not reflected when reading back, though.
39 * seems to be IRQ, too (frequently used: port |= 0x07 !), but who knows ? */ 44 * seems to be IRQ, too (frequently used: port |= 0x07 !), but who knows? */
40 #define IRQ_PLAY_SOMETHING 0x0001 /* something & ACK */ 45 #define IRQ_SOMETHING 0x0001 /* something & ACK */
41 #define IRQ_FINISHED_PLAYBUF_1 0x0002 /* 1st dmabuf finished & ACK */ 46 #define IRQ_FINISHED_DMABUF_1 0x0002 /* 1st dmabuf finished & ACK */
42 #define IRQ_FINISHED_PLAYBUF_2 0x0004 /* 2nd dmabuf finished & ACK */ 47 #define IRQ_FINISHED_DMABUF_2 0x0004 /* 2nd dmabuf finished & ACK */
43 #define IRQMASK_SOME_STATUS_1 0x0008 /* \ related bits */ 48 #define IRQMASK_SOME_STATUS_1 0x0008 /* \ related bits */
44 #define IRQMASK_SOME_STATUS_2 0x0010 /* / (checked together in loop) */ 49 #define IRQMASK_SOME_STATUS_2 0x0010 /* / (checked together in loop) */
45 #define IRQMASK_UNMODIFIABLE 0xffe0 /* unused ? not modifiable */ 50 #define IRQMASK_UNMODIFIABLE 0xffe0 /* unused? not modifiable */
46#define IDX_IO_PLAY_DMA_START_1 0x04 /* start address of 1st DMA play area, PU:0x00000000 */ 51 /* start address of 1st DMA transfer area, PU:0x00000000 */
47#define IDX_IO_PLAY_DMA_START_2 0x08 /* start address of 2nd DMA play area, PU:0x00000000 */ 52#define IDX_IO_CODEC_DMA_START_1 0x04
48#define IDX_IO_PLAY_DMA_LEN_1 0x0c /* length of 1st DMA play area, PU:0x0000 */ 53 /* start address of 2nd DMA transfer area, PU:0x00000000 */
49#define IDX_IO_PLAY_DMA_LEN_2 0x0e /* length of 2nd DMA play area, PU:0x0000 */ 54#define IDX_IO_CODEC_DMA_START_2 0x08
50#define IDX_IO_PLAY_DMA_CURRPOS 0x10 /* current DMA position, PU:0x00000000 */ 55 /* both lengths of DMA transfer areas, PU:0x00000000
51#define IDX_IO_PLAY_DMA_CURROFS 0x14 /* offset within current DMA play area, PU:0x0000 */ 56 length1: offset 0x0c, length2: offset 0x0e */
52#define IDX_IO_PLAY_SOUNDFORMAT 0x16 /* PU:0x0010 */ 57#define IDX_IO_CODEC_DMA_LENGTHS 0x0c
58#define IDX_IO_CODEC_DMA_CURRPOS 0x10 /* current DMA position, PU:0x00000000 */
59 /* offset within current DMA transfer area, PU:0x0000 */
60#define IDX_IO_CODEC_DMA_CURROFS 0x14
61#define IDX_IO_CODEC_SOUNDFORMAT 0x16 /* PU:0x0010 */
53 /* all unspecified bits can't be modified */ 62 /* all unspecified bits can't be modified */
54 #define SOUNDFORMAT_FREQUENCY_MASK 0x000f 63 #define SOUNDFORMAT_FREQUENCY_MASK 0x000f
55 #define SOUNDFORMAT_XTAL1 0x00 64 #define SOUNDFORMAT_XTAL1 0x00
@@ -76,6 +85,7 @@
76 #define SOUNDFORMAT_FLAG_16BIT 0x0010 85 #define SOUNDFORMAT_FLAG_16BIT 0x0010
77 #define SOUNDFORMAT_FLAG_2CHANNELS 0x0020 86 #define SOUNDFORMAT_FLAG_2CHANNELS 0x0020
78 87
88
79/* define frequency helpers, for maximum value safety */ 89/* define frequency helpers, for maximum value safety */
80enum azf_freq_t { 90enum azf_freq_t {
81#define AZF_FREQ(rate) AZF_FREQ_##rate = rate 91#define AZF_FREQ(rate) AZF_FREQ_##rate = rate
@@ -96,29 +106,6 @@ enum azf_freq_t {
96#undef AZF_FREQ 106#undef AZF_FREQ
97}; 107};
98 108
99/** recording area (see also: playback bit flag definitions) **/
100#define IDX_IO_REC_FLAGS 0x20 /* ??, PU:0x0000 */
101#define IDX_IO_REC_IRQTYPE 0x22 /* ??, PU:0x0000 */
102 #define IRQ_REC_SOMETHING 0x0001 /* something & ACK */
103 #define IRQ_FINISHED_RECBUF_1 0x0002 /* 1st dmabuf finished & ACK */
104 #define IRQ_FINISHED_RECBUF_2 0x0004 /* 2nd dmabuf finished & ACK */
105 /* hmm, maybe these are just the corresponding *recording* flags ?
106 * but OTOH they are most likely at port 0x22 instead */
107 #define IRQMASK_SOME_STATUS_1 0x0008 /* \ related bits */
108 #define IRQMASK_SOME_STATUS_2 0x0010 /* / (checked together in loop) */
109#define IDX_IO_REC_DMA_START_1 0x24 /* PU:0x00000000 */
110#define IDX_IO_REC_DMA_START_2 0x28 /* PU:0x00000000 */
111#define IDX_IO_REC_DMA_LEN_1 0x2c /* PU:0x0000 */
112#define IDX_IO_REC_DMA_LEN_2 0x2e /* PU:0x0000 */
113#define IDX_IO_REC_DMA_CURRPOS 0x30 /* PU:0x00000000 */
114#define IDX_IO_REC_DMA_CURROFS 0x34 /* PU:0x00000000 */
115#define IDX_IO_REC_SOUNDFORMAT 0x36 /* PU:0x0000 */
116
117/** hmm, what is this I/O area for? MPU401?? or external DAC via I2S?? (after playback, recording, ???, timer) **/
118#define IDX_IO_SOMETHING_FLAGS 0x40 /* gets set to 0x34 just like port 0x0 and 0x20 on card init, PU:0x0000 */
119/* general */
120#define IDX_IO_42H 0x42 /* PU:0x0001 */
121
122/** DirectX timer, main interrupt area (FIXME: and something else?) **/ 109/** DirectX timer, main interrupt area (FIXME: and something else?) **/
123#define IDX_IO_TIMER_VALUE 0x60 /* found this timer area by pure luck :-) */ 110#define IDX_IO_TIMER_VALUE 0x60 /* found this timer area by pure luck :-) */
124 /* timer countdown value; triggers IRQ when timer is finished */ 111 /* timer countdown value; triggers IRQ when timer is finished */
@@ -138,7 +125,7 @@ enum azf_freq_t {
138 125
139 #define IRQ_PLAYBACK 0x0001 126 #define IRQ_PLAYBACK 0x0001
140 #define IRQ_RECORDING 0x0002 127 #define IRQ_RECORDING 0x0002
141 #define IRQ_UNKNOWN1 0x0004 /* most probably I2S port */ 128 #define IRQ_I2S_OUT 0x0004 /* this IS I2S, right!? (untested) */
142 #define IRQ_GAMEPORT 0x0008 /* Interrupt of Digital(ly) Enhanced Game Port */ 129 #define IRQ_GAMEPORT 0x0008 /* Interrupt of Digital(ly) Enhanced Game Port */
143 #define IRQ_MPU401 0x0010 130 #define IRQ_MPU401 0x0010
144 #define IRQ_TIMER 0x0020 /* DirectX timer */ 131 #define IRQ_TIMER 0x0020 /* DirectX timer */
@@ -272,6 +259,12 @@ enum {
272 * 11 --> 1/200: */ 259 * 11 --> 1/200: */
273 #define GAME_HWCFG_ADC_COUNTER_FREQ_MASK 0x06 260 #define GAME_HWCFG_ADC_COUNTER_FREQ_MASK 0x06
274 261
262 /* FIXME: these values might be reversed... */
263 #define GAME_HWCFG_ADC_COUNTER_FREQ_STD 0
264 #define GAME_HWCFG_ADC_COUNTER_FREQ_1_2 1
265 #define GAME_HWCFG_ADC_COUNTER_FREQ_1_20 2
266 #define GAME_HWCFG_ADC_COUNTER_FREQ_1_200 3
267
275 /* enable gameport legacy I/O address (0x200) 268 /* enable gameport legacy I/O address (0x200)
276 * I was unable to locate any configurability for a different address: */ 269 * I was unable to locate any configurability for a different address: */
277 #define GAME_HWCFG_LEGACY_ADDRESS_ENABLE 0x08 270 #define GAME_HWCFG_LEGACY_ADDRESS_ENABLE 0x08