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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /sound/oss/maestro3.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'sound/oss/maestro3.c')
-rw-r--r--sound/oss/maestro3.c2973
1 files changed, 2973 insertions, 0 deletions
diff --git a/sound/oss/maestro3.c b/sound/oss/maestro3.c
new file mode 100644
index 000000000000..f3dec70fcb9b
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+++ b/sound/oss/maestro3.c
@@ -0,0 +1,2973 @@
1/*****************************************************************************
2 *
3 * ESS Maestro3/Allegro driver for Linux 2.4.x
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * (c) Copyright 2000 Zach Brown <zab@zabbo.net>
20 *
21 * I need to thank many people for helping make this driver happen.
22 * As always, Eric Brombaugh was a hacking machine and killed many bugs
23 * that I was too dumb to notice. Howard Kim at ESS provided reference boards
24 * and as much docs as he could. Todd and Mick at Dell tested snapshots on
25 * an army of laptops. msw and deviant at Red Hat also humoured me by hanging
26 * their laptops every few hours in the name of science.
27 *
28 * Shouts go out to Mike "DJ XPCom" Ang.
29 *
30 * History
31 * v1.23 - Jun 5 2002 - Michael Olson <olson@cs.odu.edu>
32 * added a module option to allow selection of GPIO pin number
33 * for external amp
34 * v1.22 - Feb 28 2001 - Zach Brown <zab@zabbo.net>
35 * allocate mem at insmod/setup, rather than open
36 * limit pci dma addresses to 28bit, thanks guys.
37 * v1.21 - Feb 04 2001 - Zach Brown <zab@zabbo.net>
38 * fix up really dumb notifier -> suspend oops
39 * v1.20 - Jan 30 2001 - Zach Brown <zab@zabbo.net>
40 * get rid of pm callback and use pci_dev suspend/resume instead
41 * m3_probe cleanups, including pm oops think-o
42 * v1.10 - Jan 6 2001 - Zach Brown <zab@zabbo.net>
43 * revert to lame remap_page_range mmap() just to make it work
44 * record mmap fixed.
45 * fix up incredibly broken open/release resource management
46 * duh. fix record format setting.
47 * add SMP locking and cleanup formatting here and there
48 * v1.00 - Dec 16 2000 - Zach Brown <zab@zabbo.net>
49 * port to sexy 2.4 interfaces
50 * properly align instance allocations so recording works
51 * clean up function namespace a little :/
52 * update PCI IDs based on mail from ESS
53 * arbitrarily bump version number to show its 2.4 now,
54 * 2.2 will stay 0., oss_audio port gets 2.
55 * v0.03 - Nov 05 2000 - Zach Brown <zab@zabbo.net>
56 * disable recording but allow dsp to be opened read
57 * pull out most silly compat defines
58 * v0.02 - Nov 04 2000 - Zach Brown <zab@zabbo.net>
59 * changed clocking setup for m3, slowdown fixed.
60 * codec reset is hopefully reliable now
61 * rudimentary apm/power management makes suspend/resume work
62 * v0.01 - Oct 31 2000 - Zach Brown <zab@zabbo.net>
63 * first release
64 * v0.00 - Sep 09 2000 - Zach Brown <zab@zabbo.net>
65 * first pass derivation from maestro.c
66 *
67 * TODO
68 * in/out allocated contiguously so fullduplex mmap will work?
69 * no beep on init (mute)
70 * resetup msrc data memory if freq changes?
71 *
72 * --
73 *
74 * Allow me to ramble a bit about the m3 architecture. The core of the
75 * chip is the 'assp', the custom ESS dsp that runs the show. It has
76 * a small amount of code and data ram. ESS drops binary dsp code images
77 * on our heads, but we don't get to see specs on the dsp.
78 *
79 * The constant piece of code on the dsp is the 'kernel'. It also has a
80 * chunk of the dsp memory that is statically set aside for its control
81 * info. This is the KDATA defines in maestro3.h. Part of its core
82 * data is a list of code addresses that point to the pieces of DSP code
83 * that it should walk through in its loop. These other pieces of code
84 * do the real work. The kernel presumably jumps into each of them in turn.
85 * These code images tend to have their own data area, and one can have
86 * multiple data areas representing different states for each of the 'client
87 * instance' code portions. There is generally a list in the kernel data
88 * that points to the data instances for a given piece of code.
89 *
90 * We've only been given the binary image for the 'minisrc', mini sample
91 * rate converter. This is rather annoying because it limits the work
92 * we can do on the dsp, but it also greatly simplifies the job of managing
93 * dsp data memory for the code and data for our playing streams :). We
94 * statically allocate the minisrc code into a region we 'know' to be free
95 * based on the map of the binary kernel image we're loading. We also
96 * statically allocate the data areas for the maximum number of pcm streams
97 * we can be dealing with. This max is set by the length of the static list
98 * in the kernel data that records the number of minisrc data regions we
99 * can have. Thats right, all software dsp mixing with static code list
100 * limits. Rock.
101 *
102 * How sound goes in and out is still a relative mystery. It appears
103 * that the dsp has the ability to get input and output through various
104 * 'connections'. To do IO from or to a connection, you put the address
105 * of the minisrc client area in the static kernel data lists for that
106 * input or output. so for pcm -> dsp -> mixer, we put the minisrc data
107 * instance in the DMA list and also in the list for the mixer. I guess
108 * it Just Knows which is in/out, and we give some dma control info that
109 * helps. There are all sorts of cool inputs/outputs that it seems we can't
110 * use without dsp code images that know how to use them.
111 *
112 * So at init time we preload all the memory allocation stuff and set some
113 * system wide parameters. When we really get a sound to play we build
114 * up its minisrc header (stream parameters, buffer addresses, input/output
115 * settings). Then we throw its header on the various lists. We also
116 * tickle some KDATA settings that ask the assp to raise clock interrupts
117 * and do some amount of software mixing before handing data to the ac97.
118 *
119 * Sorry for the vague details. Feel free to ask Eric or myself if you
120 * happen to be trying to use this driver elsewhere. Please accept my
121 * apologies for the quality of the OSS support code, its passed through
122 * too many hands now and desperately wants to be rethought.
123 */
124
125/*****************************************************************************/
126
127#include <linux/config.h>
128#include <linux/module.h>
129#include <linux/kernel.h>
130#include <linux/string.h>
131#include <linux/ctype.h>
132#include <linux/ioport.h>
133#include <linux/sched.h>
134#include <linux/delay.h>
135#include <linux/sound.h>
136#include <linux/slab.h>
137#include <linux/soundcard.h>
138#include <linux/pci.h>
139#include <linux/vmalloc.h>
140#include <linux/init.h>
141#include <linux/interrupt.h>
142#include <linux/poll.h>
143#include <linux/reboot.h>
144#include <linux/spinlock.h>
145#include <linux/ac97_codec.h>
146#include <linux/wait.h>
147
148#include <asm/io.h>
149#include <asm/dma.h>
150#include <asm/uaccess.h>
151
152#include "maestro3.h"
153
154#define M_DEBUG 1
155
156#define DRIVER_VERSION "1.23"
157#define M3_MODULE_NAME "maestro3"
158#define PFX M3_MODULE_NAME ": "
159
160#define M3_STATE_MAGIC 0x734d724d
161#define M3_CARD_MAGIC 0x646e6f50
162
163#define ESS_FMT_STEREO 0x01
164#define ESS_FMT_16BIT 0x02
165#define ESS_FMT_MASK 0x03
166#define ESS_DAC_SHIFT 0
167#define ESS_ADC_SHIFT 4
168
169#define DAC_RUNNING 1
170#define ADC_RUNNING 2
171
172#define SND_DEV_DSP16 5
173
174#ifdef M_DEBUG
175static int debug;
176#define DPMOD 1 /* per module load */
177#define DPSTR 2 /* per 'stream' */
178#define DPSYS 3 /* per syscall */
179#define DPCRAP 4 /* stuff the user shouldn't see unless they're really debuggin */
180#define DPINT 5 /* per interrupt, LOTS */
181#define DPRINTK(DP, args...) {if (debug >= (DP)) printk(KERN_DEBUG PFX args);}
182#else
183#define DPRINTK(x)
184#endif
185
186struct m3_list {
187 int curlen;
188 u16 mem_addr;
189 int max;
190};
191
192static int external_amp = 1;
193static int gpio_pin = -1;
194
195struct m3_state {
196 unsigned int magic;
197 struct m3_card *card;
198 unsigned char fmt, enable;
199
200 int index;
201
202 /* this locks around the oss state in the driver */
203 /* no, this lock is removed - only use card->lock */
204 /* otherwise: against what are you protecting on SMP
205 when irqhandler uses s->lock
206 and m3_assp_read uses card->lock ?
207 */
208 struct semaphore open_sem;
209 wait_queue_head_t open_wait;
210 mode_t open_mode;
211
212 int dev_audio;
213
214 struct assp_instance {
215 u16 code, data;
216 } dac_inst, adc_inst;
217
218 /* should be in dmabuf */
219 unsigned int rateadc, ratedac;
220
221 struct dmabuf {
222 void *rawbuf;
223 unsigned buforder;
224 unsigned numfrag;
225 unsigned fragshift;
226 unsigned hwptr, swptr;
227 unsigned total_bytes;
228 int count;
229 unsigned error; /* over/underrun */
230 wait_queue_head_t wait;
231 /* redundant, but makes calculations easier */
232 unsigned fragsize;
233 unsigned dmasize;
234 unsigned fragsamples;
235 /* OSS stuff */
236 unsigned mapped:1;
237 unsigned ready:1;
238 unsigned endcleared:1;
239 unsigned ossfragshift;
240 int ossmaxfrags;
241 unsigned subdivision;
242 /* new in m3 */
243 int mixer_index, dma_index, msrc_index, adc1_index;
244 int in_lists;
245 /* 2.4.. */
246 dma_addr_t handle;
247
248 } dma_dac, dma_adc;
249};
250
251struct m3_card {
252 unsigned int magic;
253
254 struct m3_card *next;
255
256 struct ac97_codec *ac97;
257 spinlock_t ac97_lock;
258
259 int card_type;
260
261#define NR_DSPS 1
262#define MAX_DSPS NR_DSPS
263 struct m3_state channels[MAX_DSPS];
264
265 /* this locks around the physical registers on the card */
266 spinlock_t lock;
267
268 /* hardware resources */
269 struct pci_dev *pcidev;
270 u32 iobase;
271 u32 irq;
272
273 int dacs_active;
274
275 int timer_users;
276
277 struct m3_list msrc_list,
278 mixer_list,
279 adc1_list,
280 dma_list;
281
282 /* for storing reset state..*/
283 u8 reset_state;
284
285 u16 *suspend_mem;
286 int in_suspend;
287 wait_queue_head_t suspend_queue;
288};
289
290/*
291 * an arbitrary volume we set the internal
292 * volume settings to so that the ac97 volume
293 * range is a little less insane. 0x7fff is
294 * max.
295 */
296#define ARB_VOLUME ( 0x6800 )
297
298static const unsigned sample_shift[] = { 0, 1, 1, 2 };
299
300enum {
301 ESS_ALLEGRO,
302 ESS_MAESTRO3,
303 /*
304 * a maestro3 with 'hardware strapping', only
305 * found inside ESS?
306 */
307 ESS_MAESTRO3HW,
308};
309
310static char *card_names[] = {
311 [ESS_ALLEGRO] = "Allegro",
312 [ESS_MAESTRO3] = "Maestro3(i)",
313 [ESS_MAESTRO3HW] = "Maestro3(i)hw"
314};
315
316#ifndef PCI_VENDOR_ESS
317#define PCI_VENDOR_ESS 0x125D
318#endif
319
320#define M3_DEVICE(DEV, TYPE) \
321{ \
322.vendor = PCI_VENDOR_ESS, \
323.device = DEV, \
324.subvendor = PCI_ANY_ID, \
325.subdevice = PCI_ANY_ID, \
326.class = PCI_CLASS_MULTIMEDIA_AUDIO << 8, \
327.class_mask = 0xffff << 8, \
328.driver_data = TYPE, \
329}
330
331static struct pci_device_id m3_id_table[] = {
332 M3_DEVICE(0x1988, ESS_ALLEGRO),
333 M3_DEVICE(0x1998, ESS_MAESTRO3),
334 M3_DEVICE(0x199a, ESS_MAESTRO3HW),
335 {0,}
336};
337
338MODULE_DEVICE_TABLE (pci, m3_id_table);
339
340/*
341 * reports seem to indicate that the m3 is limited
342 * to 28bit bus addresses. aaaargggh...
343 */
344#define M3_PCI_DMA_MASK 0x0fffffff
345
346static unsigned
347ld2(unsigned int x)
348{
349 unsigned r = 0;
350
351 if (x >= 0x10000) {
352 x >>= 16;
353 r += 16;
354 }
355 if (x >= 0x100) {
356 x >>= 8;
357 r += 8;
358 }
359 if (x >= 0x10) {
360 x >>= 4;
361 r += 4;
362 }
363 if (x >= 4) {
364 x >>= 2;
365 r += 2;
366 }
367 if (x >= 2)
368 r++;
369 return r;
370}
371
372static struct m3_card *devs;
373
374/*
375 * I'm not very good at laying out functions in a file :)
376 */
377static int m3_notifier(struct notifier_block *nb, unsigned long event, void *buf);
378static int m3_suspend(struct pci_dev *pci_dev, pm_message_t state);
379static void check_suspend(struct m3_card *card);
380
381static struct notifier_block m3_reboot_nb = {
382 .notifier_call = m3_notifier,
383};
384
385static void m3_outw(struct m3_card *card,
386 u16 value, unsigned long reg)
387{
388 check_suspend(card);
389 outw(value, card->iobase + reg);
390}
391
392static u16 m3_inw(struct m3_card *card, unsigned long reg)
393{
394 check_suspend(card);
395 return inw(card->iobase + reg);
396}
397static void m3_outb(struct m3_card *card,
398 u8 value, unsigned long reg)
399{
400 check_suspend(card);
401 outb(value, card->iobase + reg);
402}
403static u8 m3_inb(struct m3_card *card, unsigned long reg)
404{
405 check_suspend(card);
406 return inb(card->iobase + reg);
407}
408
409/*
410 * access 16bit words to the code or data regions of the dsp's memory.
411 * index addresses 16bit words.
412 */
413static u16 __m3_assp_read(struct m3_card *card, u16 region, u16 index)
414{
415 m3_outw(card, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
416 m3_outw(card, index, DSP_PORT_MEMORY_INDEX);
417 return m3_inw(card, DSP_PORT_MEMORY_DATA);
418}
419static u16 m3_assp_read(struct m3_card *card, u16 region, u16 index)
420{
421 unsigned long flags;
422 u16 ret;
423
424 spin_lock_irqsave(&(card->lock), flags);
425 ret = __m3_assp_read(card, region, index);
426 spin_unlock_irqrestore(&(card->lock), flags);
427
428 return ret;
429}
430
431static void __m3_assp_write(struct m3_card *card,
432 u16 region, u16 index, u16 data)
433{
434 m3_outw(card, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
435 m3_outw(card, index, DSP_PORT_MEMORY_INDEX);
436 m3_outw(card, data, DSP_PORT_MEMORY_DATA);
437}
438static void m3_assp_write(struct m3_card *card,
439 u16 region, u16 index, u16 data)
440{
441 unsigned long flags;
442
443 spin_lock_irqsave(&(card->lock), flags);
444 __m3_assp_write(card, region, index, data);
445 spin_unlock_irqrestore(&(card->lock), flags);
446}
447
448static void m3_assp_halt(struct m3_card *card)
449{
450 card->reset_state = m3_inb(card, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
451 mdelay(10);
452 m3_outb(card, card->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
453}
454
455static void m3_assp_continue(struct m3_card *card)
456{
457 m3_outb(card, card->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
458}
459
460/*
461 * This makes me sad. the maestro3 has lists
462 * internally that must be packed.. 0 terminates,
463 * apparently, or maybe all unused entries have
464 * to be 0, the lists have static lengths set
465 * by the binary code images.
466 */
467
468static int m3_add_list(struct m3_card *card,
469 struct m3_list *list, u16 val)
470{
471 DPRINTK(DPSTR, "adding val 0x%x to list 0x%p at pos %d\n",
472 val, list, list->curlen);
473
474 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
475 list->mem_addr + list->curlen,
476 val);
477
478 return list->curlen++;
479
480}
481
482static void m3_remove_list(struct m3_card *card,
483 struct m3_list *list, int index)
484{
485 u16 val;
486 int lastindex = list->curlen - 1;
487
488 DPRINTK(DPSTR, "removing ind %d from list 0x%p\n",
489 index, list);
490
491 if(index != lastindex) {
492 val = m3_assp_read(card, MEMTYPE_INTERNAL_DATA,
493 list->mem_addr + lastindex);
494 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
495 list->mem_addr + index,
496 val);
497 }
498
499 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
500 list->mem_addr + lastindex,
501 0);
502
503 list->curlen--;
504}
505
506static void set_fmt(struct m3_state *s, unsigned char mask, unsigned char data)
507{
508 int tmp;
509
510 s->fmt = (s->fmt & mask) | data;
511
512 tmp = (s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_MASK;
513
514 /* write to 'mono' word */
515 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
516 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 1,
517 (tmp & ESS_FMT_STEREO) ? 0 : 1);
518 /* write to '8bit' word */
519 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
520 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 2,
521 (tmp & ESS_FMT_16BIT) ? 0 : 1);
522
523 tmp = (s->fmt >> ESS_ADC_SHIFT) & ESS_FMT_MASK;
524
525 /* write to 'mono' word */
526 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
527 s->adc_inst.data + SRC3_DIRECTION_OFFSET + 1,
528 (tmp & ESS_FMT_STEREO) ? 0 : 1);
529 /* write to '8bit' word */
530 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
531 s->adc_inst.data + SRC3_DIRECTION_OFFSET + 2,
532 (tmp & ESS_FMT_16BIT) ? 0 : 1);
533}
534
535static void set_dac_rate(struct m3_state *s, unsigned int rate)
536{
537 u32 freq;
538
539 if (rate > 48000)
540 rate = 48000;
541 if (rate < 8000)
542 rate = 8000;
543
544 s->ratedac = rate;
545
546 freq = ((rate << 15) + 24000 ) / 48000;
547 if(freq)
548 freq--;
549
550 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
551 s->dac_inst.data + CDATA_FREQUENCY,
552 freq);
553}
554
555static void set_adc_rate(struct m3_state *s, unsigned int rate)
556{
557 u32 freq;
558
559 if (rate > 48000)
560 rate = 48000;
561 if (rate < 8000)
562 rate = 8000;
563
564 s->rateadc = rate;
565
566 freq = ((rate << 15) + 24000 ) / 48000;
567 if(freq)
568 freq--;
569
570 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
571 s->adc_inst.data + CDATA_FREQUENCY,
572 freq);
573}
574
575static void inc_timer_users(struct m3_card *card)
576{
577 unsigned long flags;
578
579 spin_lock_irqsave(&card->lock, flags);
580
581 card->timer_users++;
582 DPRINTK(DPSYS, "inc timer users now %d\n",
583 card->timer_users);
584 if(card->timer_users != 1)
585 goto out;
586
587 __m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
588 KDATA_TIMER_COUNT_RELOAD,
589 240 ) ;
590
591 __m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
592 KDATA_TIMER_COUNT_CURRENT,
593 240 ) ;
594
595 m3_outw(card,
596 m3_inw(card, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
597 HOST_INT_CTRL);
598out:
599 spin_unlock_irqrestore(&card->lock, flags);
600}
601
602static void dec_timer_users(struct m3_card *card)
603{
604 unsigned long flags;
605
606 spin_lock_irqsave(&card->lock, flags);
607
608 card->timer_users--;
609 DPRINTK(DPSYS, "dec timer users now %d\n",
610 card->timer_users);
611 if(card->timer_users > 0 )
612 goto out;
613
614 __m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
615 KDATA_TIMER_COUNT_RELOAD,
616 0 ) ;
617
618 __m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
619 KDATA_TIMER_COUNT_CURRENT,
620 0 ) ;
621
622 m3_outw(card, m3_inw(card, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
623 HOST_INT_CTRL);
624out:
625 spin_unlock_irqrestore(&card->lock, flags);
626}
627
628/*
629 * {start,stop}_{adc,dac} should be called
630 * while holding the 'state' lock and they
631 * will try to grab the 'card' lock..
632 */
633static void stop_adc(struct m3_state *s)
634{
635 if (! (s->enable & ADC_RUNNING))
636 return;
637
638 s->enable &= ~ADC_RUNNING;
639 dec_timer_users(s->card);
640
641 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
642 s->adc_inst.data + CDATA_INSTANCE_READY, 0);
643
644 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
645 KDATA_ADC1_REQUEST, 0);
646}
647
648static void stop_dac(struct m3_state *s)
649{
650 if (! (s->enable & DAC_RUNNING))
651 return;
652
653 DPRINTK(DPSYS, "stop_dac()\n");
654
655 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
656 s->dac_inst.data + CDATA_INSTANCE_READY, 0);
657
658 s->enable &= ~DAC_RUNNING;
659 s->card->dacs_active--;
660 dec_timer_users(s->card);
661
662 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
663 KDATA_MIXER_TASK_NUMBER,
664 s->card->dacs_active ) ;
665}
666
667static void start_dac(struct m3_state *s)
668{
669 if( (!s->dma_dac.mapped && s->dma_dac.count < 1) ||
670 !s->dma_dac.ready ||
671 (s->enable & DAC_RUNNING))
672 return;
673
674 DPRINTK(DPSYS, "start_dac()\n");
675
676 s->enable |= DAC_RUNNING;
677 s->card->dacs_active++;
678 inc_timer_users(s->card);
679
680 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
681 s->dac_inst.data + CDATA_INSTANCE_READY, 1);
682
683 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
684 KDATA_MIXER_TASK_NUMBER,
685 s->card->dacs_active ) ;
686}
687
688static void start_adc(struct m3_state *s)
689{
690 if ((! s->dma_adc.mapped &&
691 s->dma_adc.count >= (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
692 || !s->dma_adc.ready
693 || (s->enable & ADC_RUNNING) )
694 return;
695
696 DPRINTK(DPSYS, "start_adc()\n");
697
698 s->enable |= ADC_RUNNING;
699 inc_timer_users(s->card);
700
701 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
702 KDATA_ADC1_REQUEST, 1);
703
704 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
705 s->adc_inst.data + CDATA_INSTANCE_READY, 1);
706}
707
708static struct play_vals {
709 u16 addr, val;
710} pv[] = {
711 {CDATA_LEFT_VOLUME, ARB_VOLUME},
712 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
713 {SRC3_DIRECTION_OFFSET, 0} ,
714 /* +1, +2 are stereo/16 bit */
715 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
716 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
717 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
718 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
719 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
720 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
721 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
722 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
723 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
724 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
725 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
726 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
727 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
728 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
729 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
730 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
731 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
732};
733
734
735/* the mode passed should be already shifted and masked */
736static void m3_play_setup(struct m3_state *s, int mode, u32 rate, void *buffer, int size)
737{
738 int dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
739 int dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
740 int dsp_in_buffer = s->dac_inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
741 int dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
742 struct dmabuf *db = &s->dma_dac;
743 int i;
744
745 DPRINTK(DPSTR, "mode=%d rate=%d buf=%p len=%d.\n",
746 mode, rate, buffer, size);
747
748#define LO(x) ((x) & 0xffff)
749#define HI(x) LO((x) >> 16)
750
751 /* host dma buffer pointers */
752
753 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
754 s->dac_inst.data + CDATA_HOST_SRC_ADDRL,
755 LO(virt_to_bus(buffer)));
756
757 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
758 s->dac_inst.data + CDATA_HOST_SRC_ADDRH,
759 HI(virt_to_bus(buffer)));
760
761 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
762 s->dac_inst.data + CDATA_HOST_SRC_END_PLUS_1L,
763 LO(virt_to_bus(buffer) + size));
764
765 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
766 s->dac_inst.data + CDATA_HOST_SRC_END_PLUS_1H,
767 HI(virt_to_bus(buffer) + size));
768
769 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
770 s->dac_inst.data + CDATA_HOST_SRC_CURRENTL,
771 LO(virt_to_bus(buffer)));
772
773 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
774 s->dac_inst.data + CDATA_HOST_SRC_CURRENTH,
775 HI(virt_to_bus(buffer)));
776#undef LO
777#undef HI
778
779 /* dsp buffers */
780
781 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
782 s->dac_inst.data + CDATA_IN_BUF_BEGIN,
783 dsp_in_buffer);
784
785 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
786 s->dac_inst.data + CDATA_IN_BUF_END_PLUS_1,
787 dsp_in_buffer + (dsp_in_size / 2));
788
789 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
790 s->dac_inst.data + CDATA_IN_BUF_HEAD,
791 dsp_in_buffer);
792
793 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
794 s->dac_inst.data + CDATA_IN_BUF_TAIL,
795 dsp_in_buffer);
796
797 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
798 s->dac_inst.data + CDATA_OUT_BUF_BEGIN,
799 dsp_out_buffer);
800
801 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
802 s->dac_inst.data + CDATA_OUT_BUF_END_PLUS_1,
803 dsp_out_buffer + (dsp_out_size / 2));
804
805 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
806 s->dac_inst.data + CDATA_OUT_BUF_HEAD,
807 dsp_out_buffer);
808
809 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
810 s->dac_inst.data + CDATA_OUT_BUF_TAIL,
811 dsp_out_buffer);
812
813 /*
814 * some per client initializers
815 */
816
817 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
818 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 12,
819 s->dac_inst.data + 40 + 8);
820
821 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
822 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 19,
823 s->dac_inst.code + MINISRC_COEF_LOC);
824
825 /* enable or disable low pass filter? */
826 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
827 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 22,
828 s->ratedac > 45000 ? 0xff : 0 );
829
830 /* tell it which way dma is going? */
831 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
832 s->dac_inst.data + CDATA_DMA_CONTROL,
833 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
834
835 /*
836 * set an armload of static initializers
837 */
838 for(i = 0 ; i < (sizeof(pv) / sizeof(pv[0])) ; i++)
839 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
840 s->dac_inst.data + pv[i].addr, pv[i].val);
841
842 /*
843 * put us in the lists if we're not already there
844 */
845
846 if(db->in_lists == 0) {
847
848 db->msrc_index = m3_add_list(s->card, &s->card->msrc_list,
849 s->dac_inst.data >> DP_SHIFT_COUNT);
850
851 db->dma_index = m3_add_list(s->card, &s->card->dma_list,
852 s->dac_inst.data >> DP_SHIFT_COUNT);
853
854 db->mixer_index = m3_add_list(s->card, &s->card->mixer_list,
855 s->dac_inst.data >> DP_SHIFT_COUNT);
856
857 db->in_lists = 1;
858 }
859
860 set_dac_rate(s,rate);
861 start_dac(s);
862}
863
864/*
865 * Native record driver
866 */
867static struct rec_vals {
868 u16 addr, val;
869} rv[] = {
870 {CDATA_LEFT_VOLUME, ARB_VOLUME},
871 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
872 {SRC3_DIRECTION_OFFSET, 1} ,
873 /* +1, +2 are stereo/16 bit */
874 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
875 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
876 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
877 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
878 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
879 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
880 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
881 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
882 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
883 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
884 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
885 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
886 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
887 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
888 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
889 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
890 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
891 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
892 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
893};
894
895/* again, passed mode is alrady shifted/masked */
896static void m3_rec_setup(struct m3_state *s, int mode, u32 rate, void *buffer, int size)
897{
898 int dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2);
899 int dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
900 int dsp_in_buffer = s->adc_inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
901 int dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
902 struct dmabuf *db = &s->dma_adc;
903 int i;
904
905 DPRINTK(DPSTR, "rec_setup mode=%d rate=%d buf=%p len=%d.\n",
906 mode, rate, buffer, size);
907
908#define LO(x) ((x) & 0xffff)
909#define HI(x) LO((x) >> 16)
910
911 /* host dma buffer pointers */
912
913 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
914 s->adc_inst.data + CDATA_HOST_SRC_ADDRL,
915 LO(virt_to_bus(buffer)));
916
917 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
918 s->adc_inst.data + CDATA_HOST_SRC_ADDRH,
919 HI(virt_to_bus(buffer)));
920
921 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
922 s->adc_inst.data + CDATA_HOST_SRC_END_PLUS_1L,
923 LO(virt_to_bus(buffer) + size));
924
925 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
926 s->adc_inst.data + CDATA_HOST_SRC_END_PLUS_1H,
927 HI(virt_to_bus(buffer) + size));
928
929 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
930 s->adc_inst.data + CDATA_HOST_SRC_CURRENTL,
931 LO(virt_to_bus(buffer)));
932
933 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
934 s->adc_inst.data + CDATA_HOST_SRC_CURRENTH,
935 HI(virt_to_bus(buffer)));
936#undef LO
937#undef HI
938
939 /* dsp buffers */
940
941 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
942 s->adc_inst.data + CDATA_IN_BUF_BEGIN,
943 dsp_in_buffer);
944
945 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
946 s->adc_inst.data + CDATA_IN_BUF_END_PLUS_1,
947 dsp_in_buffer + (dsp_in_size / 2));
948
949 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
950 s->adc_inst.data + CDATA_IN_BUF_HEAD,
951 dsp_in_buffer);
952
953 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
954 s->adc_inst.data + CDATA_IN_BUF_TAIL,
955 dsp_in_buffer);
956
957 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
958 s->adc_inst.data + CDATA_OUT_BUF_BEGIN,
959 dsp_out_buffer);
960
961 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
962 s->adc_inst.data + CDATA_OUT_BUF_END_PLUS_1,
963 dsp_out_buffer + (dsp_out_size / 2));
964
965 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
966 s->adc_inst.data + CDATA_OUT_BUF_HEAD,
967 dsp_out_buffer);
968
969 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
970 s->adc_inst.data + CDATA_OUT_BUF_TAIL,
971 dsp_out_buffer);
972
973 /*
974 * some per client initializers
975 */
976
977 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
978 s->adc_inst.data + SRC3_DIRECTION_OFFSET + 12,
979 s->adc_inst.data + 40 + 8);
980
981 /* tell it which way dma is going? */
982 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
983 s->adc_inst.data + CDATA_DMA_CONTROL,
984 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
985 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
986
987 /*
988 * set an armload of static initializers
989 */
990 for(i = 0 ; i < (sizeof(rv) / sizeof(rv[0])) ; i++)
991 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
992 s->adc_inst.data + rv[i].addr, rv[i].val);
993
994 /*
995 * put us in the lists if we're not already there
996 */
997
998 if(db->in_lists == 0) {
999
1000 db->adc1_index = m3_add_list(s->card, &s->card->adc1_list,
1001 s->adc_inst.data >> DP_SHIFT_COUNT);
1002
1003 db->dma_index = m3_add_list(s->card, &s->card->dma_list,
1004 s->adc_inst.data >> DP_SHIFT_COUNT);
1005
1006 db->msrc_index = m3_add_list(s->card, &s->card->msrc_list,
1007 s->adc_inst.data >> DP_SHIFT_COUNT);
1008
1009 db->in_lists = 1;
1010 }
1011
1012 set_adc_rate(s,rate);
1013 start_adc(s);
1014}
1015/* --------------------------------------------------------------------- */
1016
1017static void set_dmaa(struct m3_state *s, unsigned int addr, unsigned int count)
1018{
1019 DPRINTK(DPINT,"set_dmaa??\n");
1020}
1021
1022static void set_dmac(struct m3_state *s, unsigned int addr, unsigned int count)
1023{
1024 DPRINTK(DPINT,"set_dmac??\n");
1025}
1026
1027static u32 get_dma_pos(struct m3_card *card,
1028 int instance_addr)
1029{
1030 u16 hi = 0, lo = 0;
1031 int retry = 10;
1032
1033 /*
1034 * try and get a valid answer
1035 */
1036 while(retry--) {
1037 hi = m3_assp_read(card, MEMTYPE_INTERNAL_DATA,
1038 instance_addr + CDATA_HOST_SRC_CURRENTH);
1039
1040 lo = m3_assp_read(card, MEMTYPE_INTERNAL_DATA,
1041 instance_addr + CDATA_HOST_SRC_CURRENTL);
1042
1043 if(hi == m3_assp_read(card, MEMTYPE_INTERNAL_DATA,
1044 instance_addr + CDATA_HOST_SRC_CURRENTH))
1045 break;
1046 }
1047 return lo | (hi<<16);
1048}
1049
1050static u32 get_dmaa(struct m3_state *s)
1051{
1052 u32 offset;
1053
1054 offset = get_dma_pos(s->card, s->dac_inst.data) -
1055 virt_to_bus(s->dma_dac.rawbuf);
1056
1057 DPRINTK(DPINT,"get_dmaa: 0x%08x\n",offset);
1058
1059 return offset;
1060}
1061
1062static u32 get_dmac(struct m3_state *s)
1063{
1064 u32 offset;
1065
1066 offset = get_dma_pos(s->card, s->adc_inst.data) -
1067 virt_to_bus(s->dma_adc.rawbuf);
1068
1069 DPRINTK(DPINT,"get_dmac: 0x%08x\n",offset);
1070
1071 return offset;
1072
1073}
1074
1075static int
1076prog_dmabuf(struct m3_state *s, unsigned rec)
1077{
1078 struct dmabuf *db = rec ? &s->dma_adc : &s->dma_dac;
1079 unsigned rate = rec ? s->rateadc : s->ratedac;
1080 unsigned bytepersec;
1081 unsigned bufs;
1082 unsigned char fmt;
1083 unsigned long flags;
1084
1085 spin_lock_irqsave(&s->card->lock, flags);
1086
1087 fmt = s->fmt;
1088 if (rec) {
1089 stop_adc(s);
1090 fmt >>= ESS_ADC_SHIFT;
1091 } else {
1092 stop_dac(s);
1093 fmt >>= ESS_DAC_SHIFT;
1094 }
1095 fmt &= ESS_FMT_MASK;
1096
1097 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
1098
1099 bytepersec = rate << sample_shift[fmt];
1100 bufs = PAGE_SIZE << db->buforder;
1101 if (db->ossfragshift) {
1102 if ((1000 << db->ossfragshift) < bytepersec)
1103 db->fragshift = ld2(bytepersec/1000);
1104 else
1105 db->fragshift = db->ossfragshift;
1106 } else {
1107 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
1108 if (db->fragshift < 3)
1109 db->fragshift = 3;
1110 }
1111 db->numfrag = bufs >> db->fragshift;
1112 while (db->numfrag < 4 && db->fragshift > 3) {
1113 db->fragshift--;
1114 db->numfrag = bufs >> db->fragshift;
1115 }
1116 db->fragsize = 1 << db->fragshift;
1117 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
1118 db->numfrag = db->ossmaxfrags;
1119 db->fragsamples = db->fragsize >> sample_shift[fmt];
1120 db->dmasize = db->numfrag << db->fragshift;
1121
1122 DPRINTK(DPSTR,"prog_dmabuf: numfrag: %d fragsize: %d dmasize: %d\n",db->numfrag,db->fragsize,db->dmasize);
1123
1124 memset(db->rawbuf, (fmt & ESS_FMT_16BIT) ? 0 : 0x80, db->dmasize);
1125
1126 if (rec)
1127 m3_rec_setup(s, fmt, s->rateadc, db->rawbuf, db->dmasize);
1128 else
1129 m3_play_setup(s, fmt, s->ratedac, db->rawbuf, db->dmasize);
1130
1131 db->ready = 1;
1132
1133 spin_unlock_irqrestore(&s->card->lock, flags);
1134
1135 return 0;
1136}
1137
1138static void clear_advance(struct m3_state *s)
1139{
1140 unsigned char c = ((s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_16BIT) ? 0 : 0x80;
1141
1142 unsigned char *buf = s->dma_dac.rawbuf;
1143 unsigned bsize = s->dma_dac.dmasize;
1144 unsigned bptr = s->dma_dac.swptr;
1145 unsigned len = s->dma_dac.fragsize;
1146
1147 if (bptr + len > bsize) {
1148 unsigned x = bsize - bptr;
1149 memset(buf + bptr, c, x);
1150 /* account for wrapping? */
1151 bptr = 0;
1152 len -= x;
1153 }
1154 memset(buf + bptr, c, len);
1155}
1156
1157/* call with spinlock held! */
1158static void m3_update_ptr(struct m3_state *s)
1159{
1160 unsigned hwptr;
1161 int diff;
1162
1163 /* update ADC pointer */
1164 if (s->dma_adc.ready) {
1165 hwptr = get_dmac(s) % s->dma_adc.dmasize;
1166 diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
1167 s->dma_adc.hwptr = hwptr;
1168 s->dma_adc.total_bytes += diff;
1169 s->dma_adc.count += diff;
1170 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1171 wake_up(&s->dma_adc.wait);
1172 if (!s->dma_adc.mapped) {
1173 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1174 stop_adc(s);
1175 /* brute force everyone back in sync, sigh */
1176 s->dma_adc.count = 0;
1177 s->dma_adc.swptr = 0;
1178 s->dma_adc.hwptr = 0;
1179 s->dma_adc.error++;
1180 }
1181 }
1182 }
1183 /* update DAC pointer */
1184 if (s->dma_dac.ready) {
1185 hwptr = get_dmaa(s) % s->dma_dac.dmasize;
1186 diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
1187
1188 DPRINTK(DPINT,"updating dac: hwptr: %6d diff: %6d count: %6d\n",
1189 hwptr,diff,s->dma_dac.count);
1190
1191 s->dma_dac.hwptr = hwptr;
1192 s->dma_dac.total_bytes += diff;
1193
1194 if (s->dma_dac.mapped) {
1195
1196 s->dma_dac.count += diff;
1197 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize) {
1198 wake_up(&s->dma_dac.wait);
1199 }
1200 } else {
1201
1202 s->dma_dac.count -= diff;
1203
1204 if (s->dma_dac.count <= 0) {
1205 DPRINTK(DPCRAP,"underflow! diff: %d (0x%x) count: %d (0x%x) hw: %d (0x%x) sw: %d (0x%x)\n",
1206 diff, diff,
1207 s->dma_dac.count,
1208 s->dma_dac.count,
1209 hwptr, hwptr,
1210 s->dma_dac.swptr,
1211 s->dma_dac.swptr);
1212 stop_dac(s);
1213 /* brute force everyone back in sync, sigh */
1214 s->dma_dac.count = 0;
1215 s->dma_dac.swptr = hwptr;
1216 s->dma_dac.error++;
1217 } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
1218 clear_advance(s);
1219 s->dma_dac.endcleared = 1;
1220 }
1221 if (s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize) {
1222 wake_up(&s->dma_dac.wait);
1223 DPRINTK(DPINT,"waking up DAC count: %d sw: %d hw: %d\n",
1224 s->dma_dac.count, s->dma_dac.swptr, hwptr);
1225 }
1226 }
1227 }
1228}
1229
1230static irqreturn_t m3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1231{
1232 struct m3_card *c = (struct m3_card *)dev_id;
1233 struct m3_state *s = &c->channels[0];
1234 u8 status;
1235
1236 status = inb(c->iobase+0x1A);
1237
1238 if(status == 0xff)
1239 return IRQ_NONE;
1240
1241 /* presumably acking the ints? */
1242 outw(status, c->iobase+0x1A);
1243
1244 if(c->in_suspend)
1245 return IRQ_HANDLED;
1246
1247 /*
1248 * ack an assp int if its running
1249 * and has an int pending
1250 */
1251 if( status & ASSP_INT_PENDING) {
1252 u8 ctl = inb(c->iobase + ASSP_CONTROL_B);
1253 if( !(ctl & STOP_ASSP_CLOCK)) {
1254 ctl = inb(c->iobase + ASSP_HOST_INT_STATUS );
1255 if(ctl & DSP2HOST_REQ_TIMER) {
1256 outb( DSP2HOST_REQ_TIMER, c->iobase + ASSP_HOST_INT_STATUS);
1257 /* update adc/dac info if it was a timer int */
1258 spin_lock(&c->lock);
1259 m3_update_ptr(s);
1260 spin_unlock(&c->lock);
1261 }
1262 }
1263 }
1264
1265 /* XXX is this needed? */
1266 if(status & 0x40)
1267 outb(0x40, c->iobase+0x1A);
1268 return IRQ_HANDLED;
1269}
1270
1271
1272/* --------------------------------------------------------------------- */
1273
1274static const char invalid_magic[] = KERN_CRIT PFX "invalid magic value in %s\n";
1275
1276#define VALIDATE_MAGIC(FOO,MAG) \
1277({ \
1278 if (!(FOO) || (FOO)->magic != MAG) { \
1279 printk(invalid_magic,__FUNCTION__); \
1280 return -ENXIO; \
1281 } \
1282})
1283
1284#define VALIDATE_STATE(a) VALIDATE_MAGIC(a,M3_STATE_MAGIC)
1285#define VALIDATE_CARD(a) VALIDATE_MAGIC(a,M3_CARD_MAGIC)
1286
1287/* --------------------------------------------------------------------- */
1288
1289static int drain_dac(struct m3_state *s, int nonblock)
1290{
1291 DECLARE_WAITQUEUE(wait,current);
1292 unsigned long flags;
1293 int count;
1294 signed long tmo;
1295
1296 if (s->dma_dac.mapped || !s->dma_dac.ready)
1297 return 0;
1298 set_current_state(TASK_INTERRUPTIBLE);
1299 add_wait_queue(&s->dma_dac.wait, &wait);
1300 for (;;) {
1301 spin_lock_irqsave(&s->card->lock, flags);
1302 count = s->dma_dac.count;
1303 spin_unlock_irqrestore(&s->card->lock, flags);
1304 if (count <= 0)
1305 break;
1306 if (signal_pending(current))
1307 break;
1308 if (nonblock) {
1309 remove_wait_queue(&s->dma_dac.wait, &wait);
1310 set_current_state(TASK_RUNNING);
1311 return -EBUSY;
1312 }
1313 tmo = (count * HZ) / s->ratedac;
1314 tmo >>= sample_shift[(s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_MASK];
1315 /* XXX this is just broken. someone is waking us up alot, or schedule_timeout is broken.
1316 or something. who cares. - zach */
1317 if (!schedule_timeout(tmo ? tmo : 1) && tmo)
1318 DPRINTK(DPCRAP,"dma timed out?? %ld\n",jiffies);
1319 }
1320 remove_wait_queue(&s->dma_dac.wait, &wait);
1321 set_current_state(TASK_RUNNING);
1322 if (signal_pending(current))
1323 return -ERESTARTSYS;
1324 return 0;
1325}
1326
1327static ssize_t m3_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1328{
1329 struct m3_state *s = (struct m3_state *)file->private_data;
1330 ssize_t ret;
1331 unsigned long flags;
1332 unsigned swptr;
1333 int cnt;
1334
1335 VALIDATE_STATE(s);
1336 if (s->dma_adc.mapped)
1337 return -ENXIO;
1338 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1339 return ret;
1340 if (!access_ok(VERIFY_WRITE, buffer, count))
1341 return -EFAULT;
1342 ret = 0;
1343
1344 spin_lock_irqsave(&s->card->lock, flags);
1345
1346 while (count > 0) {
1347 int timed_out;
1348
1349 swptr = s->dma_adc.swptr;
1350 cnt = s->dma_adc.dmasize-swptr;
1351 if (s->dma_adc.count < cnt)
1352 cnt = s->dma_adc.count;
1353
1354 if (cnt > count)
1355 cnt = count;
1356
1357 if (cnt <= 0) {
1358 start_adc(s);
1359 if (file->f_flags & O_NONBLOCK)
1360 {
1361 ret = ret ? ret : -EAGAIN;
1362 goto out;
1363 }
1364
1365 spin_unlock_irqrestore(&s->card->lock, flags);
1366 timed_out = interruptible_sleep_on_timeout(&s->dma_adc.wait, HZ) == 0;
1367 spin_lock_irqsave(&s->card->lock, flags);
1368
1369 if(timed_out) {
1370 printk("read: chip lockup? dmasz %u fragsz %u count %u hwptr %u swptr %u\n",
1371 s->dma_adc.dmasize, s->dma_adc.fragsize, s->dma_adc.count,
1372 s->dma_adc.hwptr, s->dma_adc.swptr);
1373 stop_adc(s);
1374 set_dmac(s, virt_to_bus(s->dma_adc.rawbuf), s->dma_adc.numfrag << s->dma_adc.fragshift);
1375 s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
1376 }
1377 if (signal_pending(current))
1378 {
1379 ret = ret ? ret : -ERESTARTSYS;
1380 goto out;
1381 }
1382 continue;
1383 }
1384
1385 spin_unlock_irqrestore(&s->card->lock, flags);
1386 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1387 ret = ret ? ret : -EFAULT;
1388 return ret;
1389 }
1390 spin_lock_irqsave(&s->card->lock, flags);
1391
1392 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1393 s->dma_adc.swptr = swptr;
1394 s->dma_adc.count -= cnt;
1395 count -= cnt;
1396 buffer += cnt;
1397 ret += cnt;
1398 start_adc(s);
1399 }
1400
1401out:
1402 spin_unlock_irqrestore(&s->card->lock, flags);
1403 return ret;
1404}
1405
1406static ssize_t m3_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1407{
1408 struct m3_state *s = (struct m3_state *)file->private_data;
1409 ssize_t ret;
1410 unsigned long flags;
1411 unsigned swptr;
1412 int cnt;
1413
1414 VALIDATE_STATE(s);
1415 if (s->dma_dac.mapped)
1416 return -ENXIO;
1417 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
1418 return ret;
1419 if (!access_ok(VERIFY_READ, buffer, count))
1420 return -EFAULT;
1421 ret = 0;
1422
1423 spin_lock_irqsave(&s->card->lock, flags);
1424
1425 while (count > 0) {
1426 int timed_out;
1427
1428 if (s->dma_dac.count < 0) {
1429 s->dma_dac.count = 0;
1430 s->dma_dac.swptr = s->dma_dac.hwptr;
1431 }
1432 swptr = s->dma_dac.swptr;
1433
1434 cnt = s->dma_dac.dmasize-swptr;
1435
1436 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
1437 cnt = s->dma_dac.dmasize - s->dma_dac.count;
1438
1439
1440 if (cnt > count)
1441 cnt = count;
1442
1443 if (cnt <= 0) {
1444 start_dac(s);
1445 if (file->f_flags & O_NONBLOCK) {
1446 if(!ret) ret = -EAGAIN;
1447 goto out;
1448 }
1449 spin_unlock_irqrestore(&s->card->lock, flags);
1450 timed_out = interruptible_sleep_on_timeout(&s->dma_dac.wait, HZ) == 0;
1451 spin_lock_irqsave(&s->card->lock, flags);
1452 if(timed_out) {
1453 DPRINTK(DPCRAP,"write: chip lockup? dmasz %u fragsz %u count %u hwptr %u swptr %u\n",
1454 s->dma_dac.dmasize, s->dma_dac.fragsize, s->dma_dac.count,
1455 s->dma_dac.hwptr, s->dma_dac.swptr);
1456 stop_dac(s);
1457 set_dmaa(s, virt_to_bus(s->dma_dac.rawbuf), s->dma_dac.numfrag << s->dma_dac.fragshift);
1458 s->dma_dac.count = s->dma_dac.hwptr = s->dma_dac.swptr = 0;
1459 }
1460 if (signal_pending(current)) {
1461 if (!ret) ret = -ERESTARTSYS;
1462 goto out;
1463 }
1464 continue;
1465 }
1466 spin_unlock_irqrestore(&s->card->lock, flags);
1467 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
1468 if (!ret) ret = -EFAULT;
1469 return ret;
1470 }
1471 spin_lock_irqsave(&s->card->lock, flags);
1472
1473 DPRINTK(DPSYS,"wrote %6d bytes at sw: %6d cnt: %6d while hw: %6d\n",
1474 cnt, swptr, s->dma_dac.count, s->dma_dac.hwptr);
1475
1476 swptr = (swptr + cnt) % s->dma_dac.dmasize;
1477
1478 s->dma_dac.swptr = swptr;
1479 s->dma_dac.count += cnt;
1480 s->dma_dac.endcleared = 0;
1481 count -= cnt;
1482 buffer += cnt;
1483 ret += cnt;
1484 start_dac(s);
1485 }
1486out:
1487 spin_unlock_irqrestore(&s->card->lock, flags);
1488 return ret;
1489}
1490
1491static unsigned int m3_poll(struct file *file, struct poll_table_struct *wait)
1492{
1493 struct m3_state *s = (struct m3_state *)file->private_data;
1494 unsigned long flags;
1495 unsigned int mask = 0;
1496
1497 VALIDATE_STATE(s);
1498 if (file->f_mode & FMODE_WRITE)
1499 poll_wait(file, &s->dma_dac.wait, wait);
1500 if (file->f_mode & FMODE_READ)
1501 poll_wait(file, &s->dma_adc.wait, wait);
1502
1503 spin_lock_irqsave(&s->card->lock, flags);
1504 m3_update_ptr(s);
1505
1506 if (file->f_mode & FMODE_READ) {
1507 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1508 mask |= POLLIN | POLLRDNORM;
1509 }
1510 if (file->f_mode & FMODE_WRITE) {
1511 if (s->dma_dac.mapped) {
1512 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1513 mask |= POLLOUT | POLLWRNORM;
1514 } else {
1515 if ((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize)
1516 mask |= POLLOUT | POLLWRNORM;
1517 }
1518 }
1519
1520 spin_unlock_irqrestore(&s->card->lock, flags);
1521 return mask;
1522}
1523
1524static int m3_mmap(struct file *file, struct vm_area_struct *vma)
1525{
1526 struct m3_state *s = (struct m3_state *)file->private_data;
1527 unsigned long max_size, size, start, offset;
1528 struct dmabuf *db;
1529 int ret = -EINVAL;
1530
1531 VALIDATE_STATE(s);
1532 if (vma->vm_flags & VM_WRITE) {
1533 if ((ret = prog_dmabuf(s, 0)) != 0)
1534 return ret;
1535 db = &s->dma_dac;
1536 } else
1537 if (vma->vm_flags & VM_READ) {
1538 if ((ret = prog_dmabuf(s, 1)) != 0)
1539 return ret;
1540 db = &s->dma_adc;
1541 } else
1542 return -EINVAL;
1543
1544 max_size = db->dmasize;
1545
1546 start = vma->vm_start;
1547 offset = (vma->vm_pgoff << PAGE_SHIFT);
1548 size = vma->vm_end - vma->vm_start;
1549
1550 if(size > max_size)
1551 goto out;
1552 if(offset > max_size - size)
1553 goto out;
1554
1555 /*
1556 * this will be ->nopage() once I can
1557 * ask Jeff what the hell I'm doing wrong.
1558 */
1559 ret = -EAGAIN;
1560 if (remap_pfn_range(vma, vma->vm_start,
1561 virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
1562 size, vma->vm_page_prot))
1563 goto out;
1564
1565 db->mapped = 1;
1566 ret = 0;
1567
1568out:
1569 return ret;
1570}
1571
1572/*
1573 * this function is a disaster..
1574 */
1575#define get_user_ret(x, ptr, ret) ({ if(get_user(x, ptr)) return ret; })
1576static int m3_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1577{
1578 struct m3_state *s = (struct m3_state *)file->private_data;
1579 struct m3_card *card=s->card;
1580 unsigned long flags;
1581 audio_buf_info abinfo;
1582 count_info cinfo;
1583 int val, mapped, ret;
1584 unsigned char fmtm, fmtd;
1585 void __user *argp = (void __user *)arg;
1586 int __user *p = argp;
1587
1588 VALIDATE_STATE(s);
1589
1590 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1591 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1592
1593 DPRINTK(DPSYS,"m3_ioctl: cmd %d\n", cmd);
1594
1595 switch (cmd) {
1596 case OSS_GETVERSION:
1597 return put_user(SOUND_VERSION, p);
1598
1599 case SNDCTL_DSP_SYNC:
1600 if (file->f_mode & FMODE_WRITE)
1601 return drain_dac(s, file->f_flags & O_NONBLOCK);
1602 return 0;
1603
1604 case SNDCTL_DSP_SETDUPLEX:
1605 /* XXX fix */
1606 return 0;
1607
1608 case SNDCTL_DSP_GETCAPS:
1609 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
1610
1611 case SNDCTL_DSP_RESET:
1612 spin_lock_irqsave(&card->lock, flags);
1613 if (file->f_mode & FMODE_WRITE) {
1614 stop_dac(s);
1615 synchronize_irq(s->card->pcidev->irq);
1616 s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
1617 }
1618 if (file->f_mode & FMODE_READ) {
1619 stop_adc(s);
1620 synchronize_irq(s->card->pcidev->irq);
1621 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1622 }
1623 spin_unlock_irqrestore(&card->lock, flags);
1624 return 0;
1625
1626 case SNDCTL_DSP_SPEED:
1627 get_user_ret(val, p, -EFAULT);
1628 spin_lock_irqsave(&card->lock, flags);
1629 if (val >= 0) {
1630 if (file->f_mode & FMODE_READ) {
1631 stop_adc(s);
1632 s->dma_adc.ready = 0;
1633 set_adc_rate(s, val);
1634 }
1635 if (file->f_mode & FMODE_WRITE) {
1636 stop_dac(s);
1637 s->dma_dac.ready = 0;
1638 set_dac_rate(s, val);
1639 }
1640 }
1641 spin_unlock_irqrestore(&card->lock, flags);
1642 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
1643
1644 case SNDCTL_DSP_STEREO:
1645 get_user_ret(val, p, -EFAULT);
1646 spin_lock_irqsave(&card->lock, flags);
1647 fmtd = 0;
1648 fmtm = ~0;
1649 if (file->f_mode & FMODE_READ) {
1650 stop_adc(s);
1651 s->dma_adc.ready = 0;
1652 if (val)
1653 fmtd |= ESS_FMT_STEREO << ESS_ADC_SHIFT;
1654 else
1655 fmtm &= ~(ESS_FMT_STEREO << ESS_ADC_SHIFT);
1656 }
1657 if (file->f_mode & FMODE_WRITE) {
1658 stop_dac(s);
1659 s->dma_dac.ready = 0;
1660 if (val)
1661 fmtd |= ESS_FMT_STEREO << ESS_DAC_SHIFT;
1662 else
1663 fmtm &= ~(ESS_FMT_STEREO << ESS_DAC_SHIFT);
1664 }
1665 set_fmt(s, fmtm, fmtd);
1666 spin_unlock_irqrestore(&card->lock, flags);
1667 return 0;
1668
1669 case SNDCTL_DSP_CHANNELS:
1670 get_user_ret(val, p, -EFAULT);
1671 spin_lock_irqsave(&card->lock, flags);
1672 if (val != 0) {
1673 fmtd = 0;
1674 fmtm = ~0;
1675 if (file->f_mode & FMODE_READ) {
1676 stop_adc(s);
1677 s->dma_adc.ready = 0;
1678 if (val >= 2)
1679 fmtd |= ESS_FMT_STEREO << ESS_ADC_SHIFT;
1680 else
1681 fmtm &= ~(ESS_FMT_STEREO << ESS_ADC_SHIFT);
1682 }
1683 if (file->f_mode & FMODE_WRITE) {
1684 stop_dac(s);
1685 s->dma_dac.ready = 0;
1686 if (val >= 2)
1687 fmtd |= ESS_FMT_STEREO << ESS_DAC_SHIFT;
1688 else
1689 fmtm &= ~(ESS_FMT_STEREO << ESS_DAC_SHIFT);
1690 }
1691 set_fmt(s, fmtm, fmtd);
1692 }
1693 spin_unlock_irqrestore(&card->lock, flags);
1694 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_FMT_STEREO << ESS_ADC_SHIFT)
1695 : (ESS_FMT_STEREO << ESS_DAC_SHIFT))) ? 2 : 1, p);
1696
1697 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1698 return put_user(AFMT_U8|AFMT_S16_LE, p);
1699
1700 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1701 get_user_ret(val, p, -EFAULT);
1702 spin_lock_irqsave(&card->lock, flags);
1703 if (val != AFMT_QUERY) {
1704 fmtd = 0;
1705 fmtm = ~0;
1706 if (file->f_mode & FMODE_READ) {
1707 stop_adc(s);
1708 s->dma_adc.ready = 0;
1709 if (val == AFMT_S16_LE)
1710 fmtd |= ESS_FMT_16BIT << ESS_ADC_SHIFT;
1711 else
1712 fmtm &= ~(ESS_FMT_16BIT << ESS_ADC_SHIFT);
1713 }
1714 if (file->f_mode & FMODE_WRITE) {
1715 stop_dac(s);
1716 s->dma_dac.ready = 0;
1717 if (val == AFMT_S16_LE)
1718 fmtd |= ESS_FMT_16BIT << ESS_DAC_SHIFT;
1719 else
1720 fmtm &= ~(ESS_FMT_16BIT << ESS_DAC_SHIFT);
1721 }
1722 set_fmt(s, fmtm, fmtd);
1723 }
1724 spin_unlock_irqrestore(&card->lock, flags);
1725 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ?
1726 (ESS_FMT_16BIT << ESS_ADC_SHIFT)
1727 : (ESS_FMT_16BIT << ESS_DAC_SHIFT))) ?
1728 AFMT_S16_LE :
1729 AFMT_U8,
1730 p);
1731
1732 case SNDCTL_DSP_POST:
1733 return 0;
1734
1735 case SNDCTL_DSP_GETTRIGGER:
1736 val = 0;
1737 if ((file->f_mode & FMODE_READ) && (s->enable & ADC_RUNNING))
1738 val |= PCM_ENABLE_INPUT;
1739 if ((file->f_mode & FMODE_WRITE) && (s->enable & DAC_RUNNING))
1740 val |= PCM_ENABLE_OUTPUT;
1741 return put_user(val, p);
1742
1743 case SNDCTL_DSP_SETTRIGGER:
1744 get_user_ret(val, p, -EFAULT);
1745 if (file->f_mode & FMODE_READ) {
1746 if (val & PCM_ENABLE_INPUT) {
1747 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1748 return ret;
1749 start_adc(s);
1750 } else
1751 stop_adc(s);
1752 }
1753 if (file->f_mode & FMODE_WRITE) {
1754 if (val & PCM_ENABLE_OUTPUT) {
1755 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
1756 return ret;
1757 start_dac(s);
1758 } else
1759 stop_dac(s);
1760 }
1761 return 0;
1762
1763 case SNDCTL_DSP_GETOSPACE:
1764 if (!(file->f_mode & FMODE_WRITE))
1765 return -EINVAL;
1766 if (!(s->enable & DAC_RUNNING) && (val = prog_dmabuf(s, 0)) != 0)
1767 return val;
1768 spin_lock_irqsave(&card->lock, flags);
1769 m3_update_ptr(s);
1770 abinfo.fragsize = s->dma_dac.fragsize;
1771 abinfo.bytes = s->dma_dac.dmasize - s->dma_dac.count;
1772 abinfo.fragstotal = s->dma_dac.numfrag;
1773 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1774 spin_unlock_irqrestore(&card->lock, flags);
1775 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1776
1777 case SNDCTL_DSP_GETISPACE:
1778 if (!(file->f_mode & FMODE_READ))
1779 return -EINVAL;
1780 if (!(s->enable & ADC_RUNNING) && (val = prog_dmabuf(s, 1)) != 0)
1781 return val;
1782 spin_lock_irqsave(&card->lock, flags);
1783 m3_update_ptr(s);
1784 abinfo.fragsize = s->dma_adc.fragsize;
1785 abinfo.bytes = s->dma_adc.count;
1786 abinfo.fragstotal = s->dma_adc.numfrag;
1787 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1788 spin_unlock_irqrestore(&card->lock, flags);
1789 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1790
1791 case SNDCTL_DSP_NONBLOCK:
1792 file->f_flags |= O_NONBLOCK;
1793 return 0;
1794
1795 case SNDCTL_DSP_GETODELAY:
1796 if (!(file->f_mode & FMODE_WRITE))
1797 return -EINVAL;
1798 spin_lock_irqsave(&card->lock, flags);
1799 m3_update_ptr(s);
1800 val = s->dma_dac.count;
1801 spin_unlock_irqrestore(&card->lock, flags);
1802 return put_user(val, p);
1803
1804 case SNDCTL_DSP_GETIPTR:
1805 if (!(file->f_mode & FMODE_READ))
1806 return -EINVAL;
1807 spin_lock_irqsave(&card->lock, flags);
1808 m3_update_ptr(s);
1809 cinfo.bytes = s->dma_adc.total_bytes;
1810 cinfo.blocks = s->dma_adc.count >> s->dma_adc.fragshift;
1811 cinfo.ptr = s->dma_adc.hwptr;
1812 if (s->dma_adc.mapped)
1813 s->dma_adc.count &= s->dma_adc.fragsize-1;
1814 spin_unlock_irqrestore(&card->lock, flags);
1815 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1816 return -EFAULT;
1817 return 0;
1818
1819 case SNDCTL_DSP_GETOPTR:
1820 if (!(file->f_mode & FMODE_WRITE))
1821 return -EINVAL;
1822 spin_lock_irqsave(&card->lock, flags);
1823 m3_update_ptr(s);
1824 cinfo.bytes = s->dma_dac.total_bytes;
1825 cinfo.blocks = s->dma_dac.count >> s->dma_dac.fragshift;
1826 cinfo.ptr = s->dma_dac.hwptr;
1827 if (s->dma_dac.mapped)
1828 s->dma_dac.count &= s->dma_dac.fragsize-1;
1829 spin_unlock_irqrestore(&card->lock, flags);
1830 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1831 return -EFAULT;
1832 return 0;
1833
1834 case SNDCTL_DSP_GETBLKSIZE:
1835 if (file->f_mode & FMODE_WRITE) {
1836 if ((val = prog_dmabuf(s, 0)))
1837 return val;
1838 return put_user(s->dma_dac.fragsize, p);
1839 }
1840 if ((val = prog_dmabuf(s, 1)))
1841 return val;
1842 return put_user(s->dma_adc.fragsize, p);
1843
1844 case SNDCTL_DSP_SETFRAGMENT:
1845 get_user_ret(val, p, -EFAULT);
1846 spin_lock_irqsave(&card->lock, flags);
1847 if (file->f_mode & FMODE_READ) {
1848 s->dma_adc.ossfragshift = val & 0xffff;
1849 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1850 if (s->dma_adc.ossfragshift < 4)
1851 s->dma_adc.ossfragshift = 4;
1852 if (s->dma_adc.ossfragshift > 15)
1853 s->dma_adc.ossfragshift = 15;
1854 if (s->dma_adc.ossmaxfrags < 4)
1855 s->dma_adc.ossmaxfrags = 4;
1856 }
1857 if (file->f_mode & FMODE_WRITE) {
1858 s->dma_dac.ossfragshift = val & 0xffff;
1859 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1860 if (s->dma_dac.ossfragshift < 4)
1861 s->dma_dac.ossfragshift = 4;
1862 if (s->dma_dac.ossfragshift > 15)
1863 s->dma_dac.ossfragshift = 15;
1864 if (s->dma_dac.ossmaxfrags < 4)
1865 s->dma_dac.ossmaxfrags = 4;
1866 }
1867 spin_unlock_irqrestore(&card->lock, flags);
1868 return 0;
1869
1870 case SNDCTL_DSP_SUBDIVIDE:
1871 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1872 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1873 return -EINVAL;
1874 get_user_ret(val, p, -EFAULT);
1875 if (val != 1 && val != 2 && val != 4)
1876 return -EINVAL;
1877 if (file->f_mode & FMODE_READ)
1878 s->dma_adc.subdivision = val;
1879 if (file->f_mode & FMODE_WRITE)
1880 s->dma_dac.subdivision = val;
1881 return 0;
1882
1883 case SOUND_PCM_READ_RATE:
1884 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
1885
1886 case SOUND_PCM_READ_CHANNELS:
1887 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_FMT_STEREO << ESS_ADC_SHIFT)
1888 : (ESS_FMT_STEREO << ESS_DAC_SHIFT))) ? 2 : 1, p);
1889
1890 case SOUND_PCM_READ_BITS:
1891 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_FMT_16BIT << ESS_ADC_SHIFT)
1892 : (ESS_FMT_16BIT << ESS_DAC_SHIFT))) ? 16 : 8, p);
1893
1894 case SOUND_PCM_WRITE_FILTER:
1895 case SNDCTL_DSP_SETSYNCRO:
1896 case SOUND_PCM_READ_FILTER:
1897 return -EINVAL;
1898
1899 }
1900 return -EINVAL;
1901}
1902
1903static int
1904allocate_dmabuf(struct pci_dev *pci_dev, struct dmabuf *db)
1905{
1906 int order;
1907
1908 DPRINTK(DPSTR,"allocating for dmabuf %p\n", db);
1909
1910 /*
1911 * alloc as big a chunk as we can, start with
1912 * 64k 'cause we're insane. based on order cause
1913 * the amazingly complicated prog_dmabuf wants it.
1914 *
1915 * pci_alloc_sonsistent guarantees that it won't cross a natural
1916 * boundary; the m3 hardware can't have dma cross a 64k bus
1917 * address boundary.
1918 */
1919 for (order = 16-PAGE_SHIFT; order >= 1; order--) {
1920 db->rawbuf = pci_alloc_consistent(pci_dev, PAGE_SIZE << order,
1921 &(db->handle));
1922 if(db->rawbuf)
1923 break;
1924 }
1925
1926 if (!db->rawbuf)
1927 return 1;
1928
1929 DPRINTK(DPSTR,"allocated %ld (%d) bytes at %p\n",
1930 PAGE_SIZE<<order, order, db->rawbuf);
1931
1932 {
1933 struct page *page, *pend;
1934
1935 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << order) - 1);
1936 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
1937 SetPageReserved(page);
1938 }
1939
1940
1941 db->buforder = order;
1942 db->ready = 0;
1943 db->mapped = 0;
1944
1945 return 0;
1946}
1947
1948static void
1949nuke_lists(struct m3_card *card, struct dmabuf *db)
1950{
1951 m3_remove_list(card, &(card->dma_list), db->dma_index);
1952 m3_remove_list(card, &(card->msrc_list), db->msrc_index);
1953 db->in_lists = 0;
1954}
1955
1956static void
1957free_dmabuf(struct pci_dev *pci_dev, struct dmabuf *db)
1958{
1959 if(db->rawbuf == NULL)
1960 return;
1961
1962 DPRINTK(DPSTR,"freeing %p from dmabuf %p\n",db->rawbuf, db);
1963
1964 {
1965 struct page *page, *pend;
1966 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
1967 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
1968 ClearPageReserved(page);
1969 }
1970
1971
1972 pci_free_consistent(pci_dev, PAGE_SIZE << db->buforder,
1973 db->rawbuf, db->handle);
1974
1975 db->rawbuf = NULL;
1976 db->buforder = 0;
1977 db->mapped = 0;
1978 db->ready = 0;
1979}
1980
1981static int m3_open(struct inode *inode, struct file *file)
1982{
1983 unsigned int minor = iminor(inode);
1984 struct m3_card *c;
1985 struct m3_state *s = NULL;
1986 int i;
1987 unsigned char fmtm = ~0, fmts = 0;
1988 unsigned long flags;
1989
1990 /*
1991 * Scan the cards and find the channel. We only
1992 * do this at open time so it is ok
1993 */
1994 for(c = devs ; c != NULL ; c = c->next) {
1995
1996 for(i=0;i<NR_DSPS;i++) {
1997
1998 if(c->channels[i].dev_audio < 0)
1999 continue;
2000 if((c->channels[i].dev_audio ^ minor) & ~0xf)
2001 continue;
2002
2003 s = &c->channels[i];
2004 break;
2005 }
2006 }
2007
2008 if (!s)
2009 return -ENODEV;
2010
2011 VALIDATE_STATE(s);
2012
2013 file->private_data = s;
2014
2015 /* wait for device to become free */
2016 down(&s->open_sem);
2017 while (s->open_mode & file->f_mode) {
2018 if (file->f_flags & O_NONBLOCK) {
2019 up(&s->open_sem);
2020 return -EWOULDBLOCK;
2021 }
2022 up(&s->open_sem);
2023 interruptible_sleep_on(&s->open_wait);
2024 if (signal_pending(current))
2025 return -ERESTARTSYS;
2026 down(&s->open_sem);
2027 }
2028
2029 spin_lock_irqsave(&c->lock, flags);
2030
2031 if (file->f_mode & FMODE_READ) {
2032 fmtm &= ~((ESS_FMT_STEREO | ESS_FMT_16BIT) << ESS_ADC_SHIFT);
2033 if ((minor & 0xf) == SND_DEV_DSP16)
2034 fmts |= ESS_FMT_16BIT << ESS_ADC_SHIFT;
2035
2036 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
2037 set_adc_rate(s, 8000);
2038 }
2039 if (file->f_mode & FMODE_WRITE) {
2040 fmtm &= ~((ESS_FMT_STEREO | ESS_FMT_16BIT) << ESS_DAC_SHIFT);
2041 if ((minor & 0xf) == SND_DEV_DSP16)
2042 fmts |= ESS_FMT_16BIT << ESS_DAC_SHIFT;
2043
2044 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
2045 set_dac_rate(s, 8000);
2046 }
2047 set_fmt(s, fmtm, fmts);
2048 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2049
2050 up(&s->open_sem);
2051 spin_unlock_irqrestore(&c->lock, flags);
2052 return nonseekable_open(inode, file);
2053}
2054
2055static int m3_release(struct inode *inode, struct file *file)
2056{
2057 struct m3_state *s = (struct m3_state *)file->private_data;
2058 struct m3_card *card=s->card;
2059 unsigned long flags;
2060
2061 VALIDATE_STATE(s);
2062 if (file->f_mode & FMODE_WRITE)
2063 drain_dac(s, file->f_flags & O_NONBLOCK);
2064
2065 down(&s->open_sem);
2066 spin_lock_irqsave(&card->lock, flags);
2067
2068 if (file->f_mode & FMODE_WRITE) {
2069 stop_dac(s);
2070 if(s->dma_dac.in_lists) {
2071 m3_remove_list(s->card, &(s->card->mixer_list), s->dma_dac.mixer_index);
2072 nuke_lists(s->card, &(s->dma_dac));
2073 }
2074 }
2075 if (file->f_mode & FMODE_READ) {
2076 stop_adc(s);
2077 if(s->dma_adc.in_lists) {
2078 m3_remove_list(s->card, &(s->card->adc1_list), s->dma_adc.adc1_index);
2079 nuke_lists(s->card, &(s->dma_adc));
2080 }
2081 }
2082
2083 s->open_mode &= (~file->f_mode) & (FMODE_READ|FMODE_WRITE);
2084
2085 spin_unlock_irqrestore(&card->lock, flags);
2086 up(&s->open_sem);
2087 wake_up(&s->open_wait);
2088
2089 return 0;
2090}
2091
2092/*
2093 * Wait for the ac97 serial bus to be free.
2094 * return nonzero if the bus is still busy.
2095 */
2096static int m3_ac97_wait(struct m3_card *card)
2097{
2098 int i = 10000;
2099
2100 while( (m3_inb(card, 0x30) & 1) && i--) ;
2101
2102 return i == 0;
2103}
2104
2105static u16 m3_ac97_read(struct ac97_codec *codec, u8 reg)
2106{
2107 u16 ret = 0;
2108 struct m3_card *card = codec->private_data;
2109
2110 spin_lock(&card->ac97_lock);
2111
2112 if(m3_ac97_wait(card)) {
2113 printk(KERN_ERR PFX "serial bus busy reading reg 0x%x\n",reg);
2114 goto out;
2115 }
2116
2117 m3_outb(card, 0x80 | (reg & 0x7f), 0x30);
2118
2119 if(m3_ac97_wait(card)) {
2120 printk(KERN_ERR PFX "serial bus busy finishing read reg 0x%x\n",reg);
2121 goto out;
2122 }
2123
2124 ret = m3_inw(card, 0x32);
2125 DPRINTK(DPCRAP,"reading 0x%04x from 0x%02x\n",ret, reg);
2126
2127out:
2128 spin_unlock(&card->ac97_lock);
2129 return ret;
2130}
2131
2132static void m3_ac97_write(struct ac97_codec *codec, u8 reg, u16 val)
2133{
2134 struct m3_card *card = codec->private_data;
2135
2136 spin_lock(&card->ac97_lock);
2137
2138 if(m3_ac97_wait(card)) {
2139 printk(KERN_ERR PFX "serial bus busy writing 0x%x to 0x%x\n",val, reg);
2140 goto out;
2141 }
2142 DPRINTK(DPCRAP,"writing 0x%04x to 0x%02x\n", val, reg);
2143
2144 m3_outw(card, val, 0x32);
2145 m3_outb(card, reg & 0x7f, 0x30);
2146out:
2147 spin_unlock(&card->ac97_lock);
2148}
2149/* OSS /dev/mixer file operation methods */
2150static int m3_open_mixdev(struct inode *inode, struct file *file)
2151{
2152 unsigned int minor = iminor(inode);
2153 struct m3_card *card = devs;
2154
2155 for (card = devs; card != NULL; card = card->next) {
2156 if((card->ac97 != NULL) && (card->ac97->dev_mixer == minor))
2157 break;
2158 }
2159
2160 if (!card) {
2161 return -ENODEV;
2162 }
2163
2164 file->private_data = card->ac97;
2165
2166 return nonseekable_open(inode, file);
2167}
2168
2169static int m3_release_mixdev(struct inode *inode, struct file *file)
2170{
2171 return 0;
2172}
2173
2174static int m3_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd,
2175 unsigned long arg)
2176{
2177 struct ac97_codec *codec = (struct ac97_codec *)file->private_data;
2178
2179 return codec->mixer_ioctl(codec, cmd, arg);
2180}
2181
2182static struct file_operations m3_mixer_fops = {
2183 .owner = THIS_MODULE,
2184 .llseek = no_llseek,
2185 .ioctl = m3_ioctl_mixdev,
2186 .open = m3_open_mixdev,
2187 .release = m3_release_mixdev,
2188};
2189
2190static void remote_codec_config(int io, int isremote)
2191{
2192 isremote = isremote ? 1 : 0;
2193
2194 outw( (inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
2195 io + RING_BUS_CTRL_B);
2196 outw( (inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
2197 io + SDO_OUT_DEST_CTRL);
2198 outw( (inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
2199 io + SDO_IN_DEST_CTRL);
2200}
2201
2202/*
2203 * hack, returns non zero on err
2204 */
2205static int try_read_vendor(struct m3_card *card)
2206{
2207 u16 ret;
2208
2209 if(m3_ac97_wait(card))
2210 return 1;
2211
2212 m3_outb(card, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
2213
2214 if(m3_ac97_wait(card))
2215 return 1;
2216
2217 ret = m3_inw(card, 0x32);
2218
2219 return (ret == 0) || (ret == 0xffff);
2220}
2221
2222static void m3_codec_reset(struct m3_card *card, int busywait)
2223{
2224 u16 dir;
2225 int delay1 = 0, delay2 = 0, i;
2226 int io = card->iobase;
2227
2228 switch (card->card_type) {
2229 /*
2230 * the onboard codec on the allegro seems
2231 * to want to wait a very long time before
2232 * coming back to life
2233 */
2234 case ESS_ALLEGRO:
2235 delay1 = 50;
2236 delay2 = 800;
2237 break;
2238 case ESS_MAESTRO3:
2239 case ESS_MAESTRO3HW:
2240 delay1 = 20;
2241 delay2 = 500;
2242 break;
2243 }
2244
2245 for(i = 0; i < 5; i ++) {
2246 dir = inw(io + GPIO_DIRECTION);
2247 dir |= 0x10; /* assuming pci bus master? */
2248
2249 remote_codec_config(io, 0);
2250
2251 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2252 udelay(20);
2253
2254 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2255 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2256 outw(0, io + GPIO_DATA);
2257 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2258
2259 if(busywait) {
2260 mdelay(delay1);
2261 } else {
2262 set_current_state(TASK_UNINTERRUPTIBLE);
2263 schedule_timeout((delay1 * HZ) / 1000);
2264 }
2265
2266 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2267 udelay(5);
2268 /* ok, bring back the ac-link */
2269 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2270 outw(~0, io + GPIO_MASK);
2271
2272 if(busywait) {
2273 mdelay(delay2);
2274 } else {
2275 set_current_state(TASK_UNINTERRUPTIBLE);
2276 schedule_timeout((delay2 * HZ) / 1000);
2277 }
2278 if(! try_read_vendor(card))
2279 break;
2280
2281 delay1 += 10;
2282 delay2 += 100;
2283
2284 DPRINTK(DPMOD, "retrying codec reset with delays of %d and %d ms\n",
2285 delay1, delay2);
2286 }
2287
2288#if 0
2289 /* more gung-ho reset that doesn't
2290 * seem to work anywhere :)
2291 */
2292 tmp = inw(io + RING_BUS_CTRL_A);
2293 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2294 mdelay(20);
2295 outw(tmp, io + RING_BUS_CTRL_A);
2296 mdelay(50);
2297#endif
2298}
2299
2300static int __devinit m3_codec_install(struct m3_card *card)
2301{
2302 struct ac97_codec *codec;
2303
2304 if ((codec = ac97_alloc_codec()) == NULL)
2305 return -ENOMEM;
2306
2307 codec->private_data = card;
2308 codec->codec_read = m3_ac97_read;
2309 codec->codec_write = m3_ac97_write;
2310 /* someday we should support secondary codecs.. */
2311 codec->id = 0;
2312
2313 if (ac97_probe_codec(codec) == 0) {
2314 printk(KERN_ERR PFX "codec probe failed\n");
2315 ac97_release_codec(codec);
2316 return -1;
2317 }
2318
2319 if ((codec->dev_mixer = register_sound_mixer(&m3_mixer_fops, -1)) < 0) {
2320 printk(KERN_ERR PFX "couldn't register mixer!\n");
2321 ac97_release_codec(codec);
2322 return -1;
2323 }
2324
2325 card->ac97 = codec;
2326
2327 return 0;
2328}
2329
2330
2331#define MINISRC_LPF_LEN 10
2332static u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2333 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2334 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2335};
2336static void m3_assp_init(struct m3_card *card)
2337{
2338 int i;
2339
2340 /* zero kernel data */
2341 for(i = 0 ; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2342 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2343 KDATA_BASE_ADDR + i, 0);
2344
2345 /* zero mixer data? */
2346 for(i = 0 ; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2347 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2348 KDATA_BASE_ADDR2 + i, 0);
2349
2350 /* init dma pointer */
2351 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2352 KDATA_CURRENT_DMA,
2353 KDATA_DMA_XFER0);
2354
2355 /* write kernel into code memory.. */
2356 for(i = 0 ; i < sizeof(assp_kernel_image) / 2; i++) {
2357 m3_assp_write(card, MEMTYPE_INTERNAL_CODE,
2358 REV_B_CODE_MEMORY_BEGIN + i,
2359 assp_kernel_image[i]);
2360 }
2361
2362 /*
2363 * We only have this one client and we know that 0x400
2364 * is free in our kernel's mem map, so lets just
2365 * drop it there. It seems that the minisrc doesn't
2366 * need vectors, so we won't bother with them..
2367 */
2368 for(i = 0 ; i < sizeof(assp_minisrc_image) / 2; i++) {
2369 m3_assp_write(card, MEMTYPE_INTERNAL_CODE,
2370 0x400 + i,
2371 assp_minisrc_image[i]);
2372 }
2373
2374 /*
2375 * write the coefficients for the low pass filter?
2376 */
2377 for(i = 0; i < MINISRC_LPF_LEN ; i++) {
2378 m3_assp_write(card, MEMTYPE_INTERNAL_CODE,
2379 0x400 + MINISRC_COEF_LOC + i,
2380 minisrc_lpf[i]);
2381 }
2382
2383 m3_assp_write(card, MEMTYPE_INTERNAL_CODE,
2384 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2385 0x8000);
2386
2387 /*
2388 * the minisrc is the only thing on
2389 * our task list..
2390 */
2391 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2392 KDATA_TASK0,
2393 0x400);
2394
2395 /*
2396 * init the mixer number..
2397 */
2398
2399 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2400 KDATA_MIXER_TASK_NUMBER,0);
2401
2402 /*
2403 * EXTREME KERNEL MASTER VOLUME
2404 */
2405 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2406 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2407 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2408 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2409
2410 card->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2411 card->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2412 card->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2413 card->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2414 card->dma_list.mem_addr = KDATA_DMA_XFER0;
2415 card->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2416 card->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2417 card->msrc_list.max = MAX_INSTANCE_MINISRC;
2418}
2419
2420static int setup_msrc(struct m3_card *card,
2421 struct assp_instance *inst, int index)
2422{
2423 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2424 MINISRC_IN_BUFFER_SIZE / 2 +
2425 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2426 int address, i;
2427
2428 /*
2429 * the revb memory map has 0x1100 through 0x1c00
2430 * free.
2431 */
2432
2433 /*
2434 * align instance address to 256 bytes so that it's
2435 * shifted list address is aligned.
2436 * list address = (mem address >> 1) >> 7;
2437 */
2438 data_bytes = (data_bytes + 255) & ~255;
2439 address = 0x1100 + ((data_bytes/2) * index);
2440
2441 if((address + (data_bytes/2)) >= 0x1c00) {
2442 printk(KERN_ERR PFX "no memory for %d bytes at ind %d (addr 0x%x)\n",
2443 data_bytes, index, address);
2444 return -1;
2445 }
2446
2447 for(i = 0; i < data_bytes/2 ; i++)
2448 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2449 address + i, 0);
2450
2451 inst->code = 0x400;
2452 inst->data = address;
2453
2454 return 0;
2455}
2456
2457static int m3_assp_client_init(struct m3_state *s)
2458{
2459 setup_msrc(s->card, &(s->dac_inst), s->index * 2);
2460 setup_msrc(s->card, &(s->adc_inst), (s->index * 2) + 1);
2461
2462 return 0;
2463}
2464
2465static void m3_amp_enable(struct m3_card *card, int enable)
2466{
2467 /*
2468 * this works for the reference board, have to find
2469 * out about others
2470 *
2471 * this needs more magic for 4 speaker, but..
2472 */
2473 int io = card->iobase;
2474 u16 gpo, polarity_port, polarity;
2475
2476 if(!external_amp)
2477 return;
2478
2479 if (gpio_pin >= 0 && gpio_pin <= 15) {
2480 polarity_port = 0x1000 + (0x100 * gpio_pin);
2481 } else {
2482 switch (card->card_type) {
2483 case ESS_ALLEGRO:
2484 polarity_port = 0x1800;
2485 break;
2486 default:
2487 polarity_port = 0x1100;
2488 /* Panasonic toughbook CF72 has to be different... */
2489 if(card->pcidev->subsystem_vendor == 0x10F7 && card->pcidev->subsystem_device == 0x833D)
2490 polarity_port = 0x1D00;
2491 break;
2492 }
2493 }
2494
2495 gpo = (polarity_port >> 8) & 0x0F;
2496 polarity = polarity_port >> 12;
2497 if ( enable )
2498 polarity = !polarity;
2499 polarity = polarity << gpo;
2500 gpo = 1 << gpo;
2501
2502 outw(~gpo , io + GPIO_MASK);
2503
2504 outw( inw(io + GPIO_DIRECTION) | gpo ,
2505 io + GPIO_DIRECTION);
2506
2507 outw( (GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity) ,
2508 io + GPIO_DATA);
2509
2510 outw(0xffff , io + GPIO_MASK);
2511}
2512
2513static int
2514maestro_config(struct m3_card *card)
2515{
2516 struct pci_dev *pcidev = card->pcidev;
2517 u32 n;
2518 u8 t; /* makes as much sense as 'n', no? */
2519
2520 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2521 n &= REDUCED_DEBOUNCE;
2522 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2523 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2524
2525 outb(RESET_ASSP, card->iobase + ASSP_CONTROL_B);
2526 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2527 n &= ~INT_CLK_SELECT;
2528 if(card->card_type >= ESS_MAESTRO3) {
2529 n &= ~INT_CLK_MULT_ENABLE;
2530 n |= INT_CLK_SRC_NOT_PCI;
2531 }
2532 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2533 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2534
2535 if(card->card_type <= ESS_ALLEGRO) {
2536 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2537 n |= IN_CLK_12MHZ_SELECT;
2538 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2539 }
2540
2541 t = inb(card->iobase + ASSP_CONTROL_A);
2542 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2543 t |= ASSP_CLK_49MHZ_SELECT;
2544 t |= ASSP_0_WS_ENABLE;
2545 outb(t, card->iobase + ASSP_CONTROL_A);
2546
2547 outb(RUN_ASSP, card->iobase + ASSP_CONTROL_B);
2548
2549 return 0;
2550}
2551
2552static void m3_enable_ints(struct m3_card *card)
2553{
2554 unsigned long io = card->iobase;
2555
2556 outw(ASSP_INT_ENABLE, io + HOST_INT_CTRL);
2557 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2558 io + ASSP_CONTROL_C);
2559}
2560
2561static struct file_operations m3_audio_fops = {
2562 .owner = THIS_MODULE,
2563 .llseek = no_llseek,
2564 .read = m3_read,
2565 .write = m3_write,
2566 .poll = m3_poll,
2567 .ioctl = m3_ioctl,
2568 .mmap = m3_mmap,
2569 .open = m3_open,
2570 .release = m3_release,
2571};
2572
2573#ifdef CONFIG_PM
2574static int alloc_dsp_suspendmem(struct m3_card *card)
2575{
2576 int len = sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH);
2577
2578 if( (card->suspend_mem = vmalloc(len)) == NULL)
2579 return 1;
2580
2581 return 0;
2582}
2583static void free_dsp_suspendmem(struct m3_card *card)
2584{
2585 if(card->suspend_mem)
2586 vfree(card->suspend_mem);
2587}
2588
2589#else
2590#define alloc_dsp_suspendmem(args...) 0
2591#define free_dsp_suspendmem(args...)
2592#endif
2593
2594/*
2595 * great day! this function is ugly as hell.
2596 */
2597static int __devinit m3_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_id)
2598{
2599 u32 n;
2600 int i;
2601 struct m3_card *card = NULL;
2602 int ret = 0;
2603 int card_type = pci_id->driver_data;
2604
2605 DPRINTK(DPMOD, "in maestro_install\n");
2606
2607 if (pci_enable_device(pci_dev))
2608 return -EIO;
2609
2610 if (pci_set_dma_mask(pci_dev, M3_PCI_DMA_MASK)) {
2611 printk(KERN_ERR PFX "architecture does not support limiting to 28bit PCI bus addresses\n");
2612 return -ENODEV;
2613 }
2614
2615 pci_set_master(pci_dev);
2616
2617 if( (card = kmalloc(sizeof(struct m3_card), GFP_KERNEL)) == NULL) {
2618 printk(KERN_WARNING PFX "out of memory\n");
2619 return -ENOMEM;
2620 }
2621 memset(card, 0, sizeof(struct m3_card));
2622 card->pcidev = pci_dev;
2623 init_waitqueue_head(&card->suspend_queue);
2624
2625 if ( ! request_region(pci_resource_start(pci_dev, 0),
2626 pci_resource_len (pci_dev, 0), M3_MODULE_NAME)) {
2627
2628 printk(KERN_WARNING PFX "unable to reserve I/O space.\n");
2629 ret = -EBUSY;
2630 goto out;
2631 }
2632
2633 card->iobase = pci_resource_start(pci_dev, 0);
2634
2635 if(alloc_dsp_suspendmem(card)) {
2636 printk(KERN_WARNING PFX "couldn't alloc %d bytes for saving dsp state on suspend\n",
2637 REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH);
2638 ret = -ENOMEM;
2639 goto out;
2640 }
2641
2642 card->card_type = card_type;
2643 card->irq = pci_dev->irq;
2644 card->next = devs;
2645 card->magic = M3_CARD_MAGIC;
2646 spin_lock_init(&card->lock);
2647 spin_lock_init(&card->ac97_lock);
2648 devs = card;
2649 for(i = 0; i<NR_DSPS; i++) {
2650 struct m3_state *s = &(card->channels[i]);
2651 s->dev_audio = -1;
2652 }
2653
2654 printk(KERN_INFO PFX "Configuring ESS %s found at IO 0x%04X IRQ %d\n",
2655 card_names[card->card_type], card->iobase, card->irq);
2656
2657 pci_read_config_dword(pci_dev, PCI_SUBSYSTEM_VENDOR_ID, &n);
2658 printk(KERN_INFO PFX " subvendor id: 0x%08x\n",n);
2659
2660 maestro_config(card);
2661 m3_assp_halt(card);
2662
2663 m3_codec_reset(card, 0);
2664
2665 if(m3_codec_install(card)) {
2666 ret = -EIO;
2667 goto out;
2668 }
2669
2670 m3_assp_init(card);
2671 m3_amp_enable(card, 1);
2672
2673 for(i=0;i<NR_DSPS;i++) {
2674 struct m3_state *s=&card->channels[i];
2675
2676 s->index = i;
2677
2678 s->card = card;
2679 init_waitqueue_head(&s->dma_adc.wait);
2680 init_waitqueue_head(&s->dma_dac.wait);
2681 init_waitqueue_head(&s->open_wait);
2682 init_MUTEX(&(s->open_sem));
2683 s->magic = M3_STATE_MAGIC;
2684
2685 m3_assp_client_init(s);
2686
2687 if(s->dma_adc.ready || s->dma_dac.ready || s->dma_adc.rawbuf)
2688 printk(KERN_WARNING PFX "initing a dsp device that is already in use?\n");
2689 /* register devices */
2690 if ((s->dev_audio = register_sound_dsp(&m3_audio_fops, -1)) < 0) {
2691 break;
2692 }
2693
2694 if( allocate_dmabuf(card->pcidev, &(s->dma_adc)) ||
2695 allocate_dmabuf(card->pcidev, &(s->dma_dac))) {
2696 ret = -ENOMEM;
2697 goto out;
2698 }
2699 }
2700
2701 if(request_irq(card->irq, m3_interrupt, SA_SHIRQ, card_names[card->card_type], card)) {
2702
2703 printk(KERN_ERR PFX "unable to allocate irq %d,\n", card->irq);
2704
2705 ret = -EIO;
2706 goto out;
2707 }
2708
2709 pci_set_drvdata(pci_dev, card);
2710
2711 m3_enable_ints(card);
2712 m3_assp_continue(card);
2713
2714out:
2715 if(ret) {
2716 if(card->iobase)
2717 release_region(pci_resource_start(pci_dev, 0), pci_resource_len(pci_dev, 0));
2718 free_dsp_suspendmem(card);
2719 if(card->ac97) {
2720 unregister_sound_mixer(card->ac97->dev_mixer);
2721 kfree(card->ac97);
2722 }
2723 for(i=0;i<NR_DSPS;i++)
2724 {
2725 struct m3_state *s = &card->channels[i];
2726 if(s->dev_audio != -1)
2727 unregister_sound_dsp(s->dev_audio);
2728 }
2729 kfree(card);
2730 }
2731
2732 return ret;
2733}
2734
2735static void m3_remove(struct pci_dev *pci_dev)
2736{
2737 struct m3_card *card;
2738
2739 unregister_reboot_notifier(&m3_reboot_nb);
2740
2741 while ((card = devs)) {
2742 int i;
2743 devs = devs->next;
2744
2745 free_irq(card->irq, card);
2746 unregister_sound_mixer(card->ac97->dev_mixer);
2747 kfree(card->ac97);
2748
2749 for(i=0;i<NR_DSPS;i++)
2750 {
2751 struct m3_state *s = &card->channels[i];
2752 if(s->dev_audio < 0)
2753 continue;
2754
2755 unregister_sound_dsp(s->dev_audio);
2756 free_dmabuf(card->pcidev, &s->dma_adc);
2757 free_dmabuf(card->pcidev, &s->dma_dac);
2758 }
2759
2760 release_region(card->iobase, 256);
2761 free_dsp_suspendmem(card);
2762 kfree(card);
2763 }
2764 devs = NULL;
2765}
2766
2767/*
2768 * some bioses like the sound chip to be powered down
2769 * at shutdown. We're just calling _suspend to
2770 * achieve that..
2771 */
2772static int m3_notifier(struct notifier_block *nb, unsigned long event, void *buf)
2773{
2774 struct m3_card *card;
2775
2776 DPRINTK(DPMOD, "notifier suspending all cards\n");
2777
2778 for(card = devs; card != NULL; card = card->next) {
2779 if(!card->in_suspend)
2780 m3_suspend(card->pcidev, PMSG_SUSPEND); /* XXX legal? */
2781 }
2782 return 0;
2783}
2784
2785static int m3_suspend(struct pci_dev *pci_dev, pm_message_t state)
2786{
2787 unsigned long flags;
2788 int i;
2789 struct m3_card *card = pci_get_drvdata(pci_dev);
2790
2791 /* must be a better way.. */
2792 spin_lock_irqsave(&card->lock, flags);
2793
2794 DPRINTK(DPMOD, "pm in dev %p\n",card);
2795
2796 for(i=0;i<NR_DSPS;i++) {
2797 struct m3_state *s = &card->channels[i];
2798
2799 if(s->dev_audio == -1)
2800 continue;
2801
2802 DPRINTK(DPMOD, "stop_adc/dac() device %d\n",i);
2803 stop_dac(s);
2804 stop_adc(s);
2805 }
2806
2807 mdelay(10); /* give the assp a chance to idle.. */
2808
2809 m3_assp_halt(card);
2810
2811 if(card->suspend_mem) {
2812 int index = 0;
2813
2814 DPRINTK(DPMOD, "saving code\n");
2815 for(i = REV_B_CODE_MEMORY_BEGIN ; i <= REV_B_CODE_MEMORY_END; i++)
2816 card->suspend_mem[index++] =
2817 m3_assp_read(card, MEMTYPE_INTERNAL_CODE, i);
2818 DPRINTK(DPMOD, "saving data\n");
2819 for(i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2820 card->suspend_mem[index++] =
2821 m3_assp_read(card, MEMTYPE_INTERNAL_DATA, i);
2822 }
2823
2824 DPRINTK(DPMOD, "powering down apci regs\n");
2825 m3_outw(card, 0xffff, 0x54);
2826 m3_outw(card, 0xffff, 0x56);
2827
2828 card->in_suspend = 1;
2829
2830 spin_unlock_irqrestore(&card->lock, flags);
2831
2832 return 0;
2833}
2834
2835static int m3_resume(struct pci_dev *pci_dev)
2836{
2837 unsigned long flags;
2838 int index;
2839 int i;
2840 struct m3_card *card = pci_get_drvdata(pci_dev);
2841
2842 spin_lock_irqsave(&card->lock, flags);
2843 card->in_suspend = 0;
2844
2845 DPRINTK(DPMOD, "resuming\n");
2846
2847 /* first lets just bring everything back. .*/
2848
2849 DPRINTK(DPMOD, "bringing power back on card 0x%p\n",card);
2850 m3_outw(card, 0, 0x54);
2851 m3_outw(card, 0, 0x56);
2852
2853 DPRINTK(DPMOD, "restoring pci configs and reseting codec\n");
2854 maestro_config(card);
2855 m3_assp_halt(card);
2856 m3_codec_reset(card, 1);
2857
2858 DPRINTK(DPMOD, "restoring dsp code card\n");
2859 index = 0;
2860 for(i = REV_B_CODE_MEMORY_BEGIN ; i <= REV_B_CODE_MEMORY_END; i++)
2861 m3_assp_write(card, MEMTYPE_INTERNAL_CODE, i,
2862 card->suspend_mem[index++]);
2863 for(i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2864 m3_assp_write(card, MEMTYPE_INTERNAL_DATA, i,
2865 card->suspend_mem[index++]);
2866
2867 /* tell the dma engine to restart itself */
2868 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2869 KDATA_DMA_ACTIVE, 0);
2870
2871 DPRINTK(DPMOD, "resuming dsp\n");
2872 m3_assp_continue(card);
2873
2874 DPRINTK(DPMOD, "enabling ints\n");
2875 m3_enable_ints(card);
2876
2877 /* bring back the old school flavor */
2878 for(i = 0; i < SOUND_MIXER_NRDEVICES ; i++) {
2879 int state = card->ac97->mixer_state[i];
2880 if (!supported_mixer(card->ac97, i))
2881 continue;
2882
2883 card->ac97->write_mixer(card->ac97, i,
2884 state & 0xff, (state >> 8) & 0xff);
2885 }
2886
2887 m3_amp_enable(card, 1);
2888
2889 /*
2890 * now we flip on the music
2891 */
2892 for(i=0;i<NR_DSPS;i++) {
2893 struct m3_state *s = &card->channels[i];
2894 if(s->dev_audio == -1)
2895 continue;
2896 /*
2897 * db->ready makes it so these guys can be
2898 * called unconditionally..
2899 */
2900 DPRINTK(DPMOD, "turning on dacs ind %d\n",i);
2901 start_dac(s);
2902 start_adc(s);
2903 }
2904
2905 spin_unlock_irqrestore(&card->lock, flags);
2906
2907 /*
2908 * all right, we think things are ready,
2909 * wake up people who were using the device
2910 * when we suspended
2911 */
2912 wake_up(&card->suspend_queue);
2913
2914 return 0;
2915}
2916
2917MODULE_AUTHOR("Zach Brown <zab@zabbo.net>");
2918MODULE_DESCRIPTION("ESS Maestro3/Allegro Driver");
2919MODULE_LICENSE("GPL");
2920
2921#ifdef M_DEBUG
2922module_param(debug, int, 0);
2923#endif
2924module_param(external_amp, int, 0);
2925module_param(gpio_pin, int, 0);
2926
2927static struct pci_driver m3_pci_driver = {
2928 .name = "ess_m3_audio",
2929 .id_table = m3_id_table,
2930 .probe = m3_probe,
2931 .remove = m3_remove,
2932 .suspend = m3_suspend,
2933 .resume = m3_resume,
2934};
2935
2936static int __init m3_init_module(void)
2937{
2938 printk(KERN_INFO PFX "version " DRIVER_VERSION " built at " __TIME__ " " __DATE__ "\n");
2939
2940 if (register_reboot_notifier(&m3_reboot_nb)) {
2941 printk(KERN_WARNING PFX "reboot notifier registration failed\n");
2942 return -ENODEV; /* ? */
2943 }
2944
2945 if (pci_register_driver(&m3_pci_driver)) {
2946 unregister_reboot_notifier(&m3_reboot_nb);
2947 return -ENODEV;
2948 }
2949 return 0;
2950}
2951
2952static void __exit m3_cleanup_module(void)
2953{
2954 pci_unregister_driver(&m3_pci_driver);
2955}
2956
2957module_init(m3_init_module);
2958module_exit(m3_cleanup_module);
2959
2960void check_suspend(struct m3_card *card)
2961{
2962 DECLARE_WAITQUEUE(wait, current);
2963
2964 if(!card->in_suspend)
2965 return;
2966
2967 card->in_suspend++;
2968 add_wait_queue(&card->suspend_queue, &wait);
2969 set_current_state(TASK_UNINTERRUPTIBLE);
2970 schedule();
2971 remove_wait_queue(&card->suspend_queue, &wait);
2972 set_current_state(TASK_RUNNING);
2973}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 04:44:57 -0500