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authorAdrian Bunk <bunk@stusta.de>2007-07-16 02:39:01 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-16 12:05:40 -0400
commitb5d425c97f7d4e92151167b01ca038e7853c6b37 (patch)
treee2a888ad0e79325b3eecd60738ddd92aba770ebf /sound/oss/cs461x.h
parent786d7e1612f0b0adb6046f19b906609e4fe8b1ba (diff)
more scheduled OSS driver removal
This patch contains the scheduled removal of OSS drivers that: - have ALSA drivers for the same hardware without known regressions and - whose Kconfig options have been removed in 2.6.20. Signed-off-by: Adrian Bunk <bunk@stusta.de> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'sound/oss/cs461x.h')
-rw-r--r--sound/oss/cs461x.h1691
1 files changed, 0 insertions, 1691 deletions
diff --git a/sound/oss/cs461x.h b/sound/oss/cs461x.h
deleted file mode 100644
index 0ce41338e6dd..000000000000
--- a/sound/oss/cs461x.h
+++ /dev/null
@@ -1,1691 +0,0 @@
1#ifndef __CS461X_H
2#define __CS461X_H
3
4/*
5 * Copyright (c) by Cirrus Logic Corporation <pcaudio@crystal.cirrus.com>
6 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
7 * Definitions for Cirrus Logic CS461x chips
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 */
25
26#ifndef PCI_VENDOR_ID_CIRRUS
27#define PCI_VENDOR_ID_CIRRUS 0x1013
28#endif
29#ifndef PCI_DEVICE_ID_CIRRUS_4610
30#define PCI_DEVICE_ID_CIRRUS_4610 0x6001
31#endif
32#ifndef PCI_DEVICE_ID_CIRRUS_4612
33#define PCI_DEVICE_ID_CIRRUS_4612 0x6003
34#endif
35#ifndef PCI_DEVICE_ID_CIRRUS_4615
36#define PCI_DEVICE_ID_CIRRUS_4615 0x6004
37#endif
38
39/*
40 * Direct registers
41 */
42
43/*
44 * The following define the offsets of the registers accessed via base address
45 * register zero on the CS461x part.
46 */
47#define BA0_HISR 0x00000000
48#define BA0_HSR0 0x00000004
49#define BA0_HICR 0x00000008
50#define BA0_DMSR 0x00000100
51#define BA0_HSAR 0x00000110
52#define BA0_HDAR 0x00000114
53#define BA0_HDMR 0x00000118
54#define BA0_HDCR 0x0000011C
55#define BA0_PFMC 0x00000200
56#define BA0_PFCV1 0x00000204
57#define BA0_PFCV2 0x00000208
58#define BA0_PCICFG00 0x00000300
59#define BA0_PCICFG04 0x00000304
60#define BA0_PCICFG08 0x00000308
61#define BA0_PCICFG0C 0x0000030C
62#define BA0_PCICFG10 0x00000310
63#define BA0_PCICFG14 0x00000314
64#define BA0_PCICFG18 0x00000318
65#define BA0_PCICFG1C 0x0000031C
66#define BA0_PCICFG20 0x00000320
67#define BA0_PCICFG24 0x00000324
68#define BA0_PCICFG28 0x00000328
69#define BA0_PCICFG2C 0x0000032C
70#define BA0_PCICFG30 0x00000330
71#define BA0_PCICFG34 0x00000334
72#define BA0_PCICFG38 0x00000338
73#define BA0_PCICFG3C 0x0000033C
74#define BA0_CLKCR1 0x00000400
75#define BA0_CLKCR2 0x00000404
76#define BA0_PLLM 0x00000408
77#define BA0_PLLCC 0x0000040C
78#define BA0_FRR 0x00000410
79#define BA0_CFL1 0x00000414
80#define BA0_CFL2 0x00000418
81#define BA0_SERMC1 0x00000420
82#define BA0_SERMC2 0x00000424
83#define BA0_SERC1 0x00000428
84#define BA0_SERC2 0x0000042C
85#define BA0_SERC3 0x00000430
86#define BA0_SERC4 0x00000434
87#define BA0_SERC5 0x00000438
88#define BA0_SERBSP 0x0000043C
89#define BA0_SERBST 0x00000440
90#define BA0_SERBCM 0x00000444
91#define BA0_SERBAD 0x00000448
92#define BA0_SERBCF 0x0000044C
93#define BA0_SERBWP 0x00000450
94#define BA0_SERBRP 0x00000454
95#ifndef NO_CS4612
96#define BA0_ASER_FADDR 0x00000458
97#endif
98#define BA0_ACCTL 0x00000460
99#define BA0_ACSTS 0x00000464
100#define BA0_ACOSV 0x00000468
101#define BA0_ACCAD 0x0000046C
102#define BA0_ACCDA 0x00000470
103#define BA0_ACISV 0x00000474
104#define BA0_ACSAD 0x00000478
105#define BA0_ACSDA 0x0000047C
106#define BA0_JSPT 0x00000480
107#define BA0_JSCTL 0x00000484
108#define BA0_JSC1 0x00000488
109#define BA0_JSC2 0x0000048C
110#define BA0_MIDCR 0x00000490
111#define BA0_MIDSR 0x00000494
112#define BA0_MIDWP 0x00000498
113#define BA0_MIDRP 0x0000049C
114#define BA0_JSIO 0x000004A0
115#ifndef NO_CS4612
116#define BA0_ASER_MASTER 0x000004A4
117#endif
118#define BA0_CFGI 0x000004B0
119#define BA0_SSVID 0x000004B4
120#define BA0_GPIOR 0x000004B8
121#ifndef NO_CS4612
122#define BA0_EGPIODR 0x000004BC
123#define BA0_EGPIOPTR 0x000004C0
124#define BA0_EGPIOTR 0x000004C4
125#define BA0_EGPIOWR 0x000004C8
126#define BA0_EGPIOSR 0x000004CC
127#define BA0_SERC6 0x000004D0
128#define BA0_SERC7 0x000004D4
129#define BA0_SERACC 0x000004D8
130#define BA0_ACCTL2 0x000004E0
131#define BA0_ACSTS2 0x000004E4
132#define BA0_ACOSV2 0x000004E8
133#define BA0_ACCAD2 0x000004EC
134#define BA0_ACCDA2 0x000004F0
135#define BA0_ACISV2 0x000004F4
136#define BA0_ACSAD2 0x000004F8
137#define BA0_ACSDA2 0x000004FC
138#define BA0_IOTAC0 0x00000500
139#define BA0_IOTAC1 0x00000504
140#define BA0_IOTAC2 0x00000508
141#define BA0_IOTAC3 0x0000050C
142#define BA0_IOTAC4 0x00000510
143#define BA0_IOTAC5 0x00000514
144#define BA0_IOTAC6 0x00000518
145#define BA0_IOTAC7 0x0000051C
146#define BA0_IOTAC8 0x00000520
147#define BA0_IOTAC9 0x00000524
148#define BA0_IOTAC10 0x00000528
149#define BA0_IOTAC11 0x0000052C
150#define BA0_IOTFR0 0x00000540
151#define BA0_IOTFR1 0x00000544
152#define BA0_IOTFR2 0x00000548
153#define BA0_IOTFR3 0x0000054C
154#define BA0_IOTFR4 0x00000550
155#define BA0_IOTFR5 0x00000554
156#define BA0_IOTFR6 0x00000558
157#define BA0_IOTFR7 0x0000055C
158#define BA0_IOTFIFO 0x00000580
159#define BA0_IOTRRD 0x00000584
160#define BA0_IOTFP 0x00000588
161#define BA0_IOTCR 0x0000058C
162#define BA0_DPCID 0x00000590
163#define BA0_DPCIA 0x00000594
164#define BA0_DPCIC 0x00000598
165#define BA0_PCPCIR 0x00000600
166#define BA0_PCPCIG 0x00000604
167#define BA0_PCPCIEN 0x00000608
168#define BA0_EPCIPMC 0x00000610
169#endif
170
171/*
172 * The following define the offsets of the registers and memories accessed via
173 * base address register one on the CS461x part.
174 */
175#define BA1_SP_DMEM0 0x00000000
176#define BA1_SP_DMEM1 0x00010000
177#define BA1_SP_PMEM 0x00020000
178#define BA1_SP_REG 0x00030000
179#define BA1_SPCR 0x00030000
180#define BA1_DREG 0x00030004
181#define BA1_DSRWP 0x00030008
182#define BA1_TWPR 0x0003000C
183#define BA1_SPWR 0x00030010
184#define BA1_SPIR 0x00030014
185#define BA1_FGR1 0x00030020
186#define BA1_SPCS 0x00030028
187#define BA1_SDSR 0x0003002C
188#define BA1_FRMT 0x00030030
189#define BA1_FRCC 0x00030034
190#define BA1_FRSC 0x00030038
191#define BA1_OMNI_MEM 0x000E0000
192
193/*
194 * The following defines are for the flags in the host interrupt status
195 * register.
196 */
197#define HISR_VC_MASK 0x0000FFFF
198#define HISR_VC0 0x00000001
199#define HISR_VC1 0x00000002
200#define HISR_VC2 0x00000004
201#define HISR_VC3 0x00000008
202#define HISR_VC4 0x00000010
203#define HISR_VC5 0x00000020
204#define HISR_VC6 0x00000040
205#define HISR_VC7 0x00000080
206#define HISR_VC8 0x00000100
207#define HISR_VC9 0x00000200
208#define HISR_VC10 0x00000400
209#define HISR_VC11 0x00000800
210#define HISR_VC12 0x00001000
211#define HISR_VC13 0x00002000
212#define HISR_VC14 0x00004000
213#define HISR_VC15 0x00008000
214#define HISR_INT0 0x00010000
215#define HISR_INT1 0x00020000
216#define HISR_DMAI 0x00040000
217#define HISR_FROVR 0x00080000
218#define HISR_MIDI 0x00100000
219#ifdef NO_CS4612
220#define HISR_RESERVED 0x0FE00000
221#else
222#define HISR_SBINT 0x00200000
223#define HISR_RESERVED 0x0FC00000
224#endif
225#define HISR_H0P 0x40000000
226#define HISR_INTENA 0x80000000
227
228/*
229 * The following defines are for the flags in the host signal register 0.
230 */
231#define HSR0_VC_MASK 0xFFFFFFFF
232#define HSR0_VC16 0x00000001
233#define HSR0_VC17 0x00000002
234#define HSR0_VC18 0x00000004
235#define HSR0_VC19 0x00000008
236#define HSR0_VC20 0x00000010
237#define HSR0_VC21 0x00000020
238#define HSR0_VC22 0x00000040
239#define HSR0_VC23 0x00000080
240#define HSR0_VC24 0x00000100
241#define HSR0_VC25 0x00000200
242#define HSR0_VC26 0x00000400
243#define HSR0_VC27 0x00000800
244#define HSR0_VC28 0x00001000
245#define HSR0_VC29 0x00002000
246#define HSR0_VC30 0x00004000
247#define HSR0_VC31 0x00008000
248#define HSR0_VC32 0x00010000
249#define HSR0_VC33 0x00020000
250#define HSR0_VC34 0x00040000
251#define HSR0_VC35 0x00080000
252#define HSR0_VC36 0x00100000
253#define HSR0_VC37 0x00200000
254#define HSR0_VC38 0x00400000
255#define HSR0_VC39 0x00800000
256#define HSR0_VC40 0x01000000
257#define HSR0_VC41 0x02000000
258#define HSR0_VC42 0x04000000
259#define HSR0_VC43 0x08000000
260#define HSR0_VC44 0x10000000
261#define HSR0_VC45 0x20000000
262#define HSR0_VC46 0x40000000
263#define HSR0_VC47 0x80000000
264
265/*
266 * The following defines are for the flags in the host interrupt control
267 * register.
268 */
269#define HICR_IEV 0x00000001
270#define HICR_CHGM 0x00000002
271
272/*
273 * The following defines are for the flags in the DMA status register.
274 */
275#define DMSR_HP 0x00000001
276#define DMSR_HR 0x00000002
277#define DMSR_SP 0x00000004
278#define DMSR_SR 0x00000008
279
280/*
281 * The following defines are for the flags in the host DMA source address
282 * register.
283 */
284#define HSAR_HOST_ADDR_MASK 0xFFFFFFFF
285#define HSAR_DSP_ADDR_MASK 0x0000FFFF
286#define HSAR_MEMID_MASK 0x000F0000
287#define HSAR_MEMID_SP_DMEM0 0x00000000
288#define HSAR_MEMID_SP_DMEM1 0x00010000
289#define HSAR_MEMID_SP_PMEM 0x00020000
290#define HSAR_MEMID_SP_DEBUG 0x00030000
291#define HSAR_MEMID_OMNI_MEM 0x000E0000
292#define HSAR_END 0x40000000
293#define HSAR_ERR 0x80000000
294
295/*
296 * The following defines are for the flags in the host DMA destination address
297 * register.
298 */
299#define HDAR_HOST_ADDR_MASK 0xFFFFFFFF
300#define HDAR_DSP_ADDR_MASK 0x0000FFFF
301#define HDAR_MEMID_MASK 0x000F0000
302#define HDAR_MEMID_SP_DMEM0 0x00000000
303#define HDAR_MEMID_SP_DMEM1 0x00010000
304#define HDAR_MEMID_SP_PMEM 0x00020000
305#define HDAR_MEMID_SP_DEBUG 0x00030000
306#define HDAR_MEMID_OMNI_MEM 0x000E0000
307#define HDAR_END 0x40000000
308#define HDAR_ERR 0x80000000
309
310/*
311 * The following defines are for the flags in the host DMA control register.
312 */
313#define HDMR_AC_MASK 0x0000F000
314#define HDMR_AC_8_16 0x00001000
315#define HDMR_AC_M_S 0x00002000
316#define HDMR_AC_B_L 0x00004000
317#define HDMR_AC_S_U 0x00008000
318
319/*
320 * The following defines are for the flags in the host DMA control register.
321 */
322#define HDCR_COUNT_MASK 0x000003FF
323#define HDCR_DONE 0x00004000
324#define HDCR_OPT 0x00008000
325#define HDCR_WBD 0x00400000
326#define HDCR_WBS 0x00800000
327#define HDCR_DMS_MASK 0x07000000
328#define HDCR_DMS_LINEAR 0x00000000
329#define HDCR_DMS_16_DWORDS 0x01000000
330#define HDCR_DMS_32_DWORDS 0x02000000
331#define HDCR_DMS_64_DWORDS 0x03000000
332#define HDCR_DMS_128_DWORDS 0x04000000
333#define HDCR_DMS_256_DWORDS 0x05000000
334#define HDCR_DMS_512_DWORDS 0x06000000
335#define HDCR_DMS_1024_DWORDS 0x07000000
336#define HDCR_DH 0x08000000
337#define HDCR_SMS_MASK 0x70000000
338#define HDCR_SMS_LINEAR 0x00000000
339#define HDCR_SMS_16_DWORDS 0x10000000
340#define HDCR_SMS_32_DWORDS 0x20000000
341#define HDCR_SMS_64_DWORDS 0x30000000
342#define HDCR_SMS_128_DWORDS 0x40000000
343#define HDCR_SMS_256_DWORDS 0x50000000
344#define HDCR_SMS_512_DWORDS 0x60000000
345#define HDCR_SMS_1024_DWORDS 0x70000000
346#define HDCR_SH 0x80000000
347#define HDCR_COUNT_SHIFT 0
348
349/*
350 * The following defines are for the flags in the performance monitor control
351 * register.
352 */
353#define PFMC_C1SS_MASK 0x0000001F
354#define PFMC_C1EV 0x00000020
355#define PFMC_C1RS 0x00008000
356#define PFMC_C2SS_MASK 0x001F0000
357#define PFMC_C2EV 0x00200000
358#define PFMC_C2RS 0x80000000
359#define PFMC_C1SS_SHIFT 0
360#define PFMC_C2SS_SHIFT 16
361#define PFMC_BUS_GRANT 0
362#define PFMC_GRANT_AFTER_REQ 1
363#define PFMC_TRANSACTION 2
364#define PFMC_DWORD_TRANSFER 3
365#define PFMC_SLAVE_READ 4
366#define PFMC_SLAVE_WRITE 5
367#define PFMC_PREEMPTION 6
368#define PFMC_DISCONNECT_RETRY 7
369#define PFMC_INTERRUPT 8
370#define PFMC_BUS_OWNERSHIP 9
371#define PFMC_TRANSACTION_LAG 10
372#define PFMC_PCI_CLOCK 11
373#define PFMC_SERIAL_CLOCK 12
374#define PFMC_SP_CLOCK 13
375
376/*
377 * The following defines are for the flags in the performance counter value 1
378 * register.
379 */
380#define PFCV1_PC1V_MASK 0xFFFFFFFF
381#define PFCV1_PC1V_SHIFT 0
382
383/*
384 * The following defines are for the flags in the performance counter value 2
385 * register.
386 */
387#define PFCV2_PC2V_MASK 0xFFFFFFFF
388#define PFCV2_PC2V_SHIFT 0
389
390/*
391 * The following defines are for the flags in the clock control register 1.
392 */
393#define CLKCR1_OSCS 0x00000001
394#define CLKCR1_OSCP 0x00000002
395#define CLKCR1_PLLSS_MASK 0x0000000C
396#define CLKCR1_PLLSS_SERIAL 0x00000000
397#define CLKCR1_PLLSS_CRYSTAL 0x00000004
398#define CLKCR1_PLLSS_PCI 0x00000008
399#define CLKCR1_PLLSS_RESERVED 0x0000000C
400#define CLKCR1_PLLP 0x00000010
401#define CLKCR1_SWCE 0x00000020
402#define CLKCR1_PLLOS 0x00000040
403
404/*
405 * The following defines are for the flags in the clock control register 2.
406 */
407#define CLKCR2_PDIVS_MASK 0x0000000F
408#define CLKCR2_PDIVS_1 0x00000001
409#define CLKCR2_PDIVS_2 0x00000002
410#define CLKCR2_PDIVS_4 0x00000004
411#define CLKCR2_PDIVS_7 0x00000007
412#define CLKCR2_PDIVS_8 0x00000008
413#define CLKCR2_PDIVS_16 0x00000000
414
415/*
416 * The following defines are for the flags in the PLL multiplier register.
417 */
418#define PLLM_MASK 0x000000FF
419#define PLLM_SHIFT 0
420
421/*
422 * The following defines are for the flags in the PLL capacitor coefficient
423 * register.
424 */
425#define PLLCC_CDR_MASK 0x00000007
426#ifndef NO_CS4610
427#define PLLCC_CDR_240_350_MHZ 0x00000000
428#define PLLCC_CDR_184_265_MHZ 0x00000001
429#define PLLCC_CDR_144_205_MHZ 0x00000002
430#define PLLCC_CDR_111_160_MHZ 0x00000003
431#define PLLCC_CDR_87_123_MHZ 0x00000004
432#define PLLCC_CDR_67_96_MHZ 0x00000005
433#define PLLCC_CDR_52_74_MHZ 0x00000006
434#define PLLCC_CDR_45_58_MHZ 0x00000007
435#endif
436#ifndef NO_CS4612
437#define PLLCC_CDR_271_398_MHZ 0x00000000
438#define PLLCC_CDR_227_330_MHZ 0x00000001
439#define PLLCC_CDR_167_239_MHZ 0x00000002
440#define PLLCC_CDR_150_215_MHZ 0x00000003
441#define PLLCC_CDR_107_154_MHZ 0x00000004
442#define PLLCC_CDR_98_140_MHZ 0x00000005
443#define PLLCC_CDR_73_104_MHZ 0x00000006
444#define PLLCC_CDR_63_90_MHZ 0x00000007
445#endif
446#define PLLCC_LPF_MASK 0x000000F8
447#ifndef NO_CS4610
448#define PLLCC_LPF_23850_60000_KHZ 0x00000000
449#define PLLCC_LPF_7960_26290_KHZ 0x00000008
450#define PLLCC_LPF_4160_10980_KHZ 0x00000018
451#define PLLCC_LPF_1740_4580_KHZ 0x00000038
452#define PLLCC_LPF_724_1910_KHZ 0x00000078
453#define PLLCC_LPF_317_798_KHZ 0x000000F8
454#endif
455#ifndef NO_CS4612
456#define PLLCC_LPF_25580_64530_KHZ 0x00000000
457#define PLLCC_LPF_14360_37270_KHZ 0x00000008
458#define PLLCC_LPF_6100_16020_KHZ 0x00000018
459#define PLLCC_LPF_2540_6690_KHZ 0x00000038
460#define PLLCC_LPF_1050_2780_KHZ 0x00000078
461#define PLLCC_LPF_450_1160_KHZ 0x000000F8
462#endif
463
464/*
465 * The following defines are for the flags in the feature reporting register.
466 */
467#define FRR_FAB_MASK 0x00000003
468#define FRR_MASK_MASK 0x0000001C
469#ifdef NO_CS4612
470#define FRR_CFOP_MASK 0x000000E0
471#else
472#define FRR_CFOP_MASK 0x00000FE0
473#endif
474#define FRR_CFOP_NOT_DVD 0x00000020
475#define FRR_CFOP_A3D 0x00000040
476#define FRR_CFOP_128_PIN 0x00000080
477#ifndef NO_CS4612
478#define FRR_CFOP_CS4280 0x00000800
479#endif
480#define FRR_FAB_SHIFT 0
481#define FRR_MASK_SHIFT 2
482#define FRR_CFOP_SHIFT 5
483
484/*
485 * The following defines are for the flags in the configuration load 1
486 * register.
487 */
488#define CFL1_CLOCK_SOURCE_MASK 0x00000003
489#define CFL1_CLOCK_SOURCE_CS423X 0x00000000
490#define CFL1_CLOCK_SOURCE_AC97 0x00000001
491#define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002
492#define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003
493#define CFL1_VALID_DATA_MASK 0x000000FF
494
495/*
496 * The following defines are for the flags in the configuration load 2
497 * register.
498 */
499#define CFL2_VALID_DATA_MASK 0x000000FF
500
501/*
502 * The following defines are for the flags in the serial port master control
503 * register 1.
504 */
505#define SERMC1_MSPE 0x00000001
506#define SERMC1_PTC_MASK 0x0000000E
507#define SERMC1_PTC_CS423X 0x00000000
508#define SERMC1_PTC_AC97 0x00000002
509#define SERMC1_PTC_DAC 0x00000004
510#define SERMC1_PLB 0x00000010
511#define SERMC1_XLB 0x00000020
512
513/*
514 * The following defines are for the flags in the serial port master control
515 * register 2.
516 */
517#define SERMC2_LROE 0x00000001
518#define SERMC2_MCOE 0x00000002
519#define SERMC2_MCDIV 0x00000004
520
521/*
522 * The following defines are for the flags in the serial port 1 configuration
523 * register.
524 */
525#define SERC1_SO1EN 0x00000001
526#define SERC1_SO1F_MASK 0x0000000E
527#define SERC1_SO1F_CS423X 0x00000000
528#define SERC1_SO1F_AC97 0x00000002
529#define SERC1_SO1F_DAC 0x00000004
530#define SERC1_SO1F_SPDIF 0x00000006
531
532/*
533 * The following defines are for the flags in the serial port 2 configuration
534 * register.
535 */
536#define SERC2_SI1EN 0x00000001
537#define SERC2_SI1F_MASK 0x0000000E
538#define SERC2_SI1F_CS423X 0x00000000
539#define SERC2_SI1F_AC97 0x00000002
540#define SERC2_SI1F_ADC 0x00000004
541#define SERC2_SI1F_SPDIF 0x00000006
542
543/*
544 * The following defines are for the flags in the serial port 3 configuration
545 * register.
546 */
547#define SERC3_SO2EN 0x00000001
548#define SERC3_SO2F_MASK 0x00000006
549#define SERC3_SO2F_DAC 0x00000000
550#define SERC3_SO2F_SPDIF 0x00000002
551
552/*
553 * The following defines are for the flags in the serial port 4 configuration
554 * register.
555 */
556#define SERC4_SO3EN 0x00000001
557#define SERC4_SO3F_MASK 0x00000006
558#define SERC4_SO3F_DAC 0x00000000
559#define SERC4_SO3F_SPDIF 0x00000002
560
561/*
562 * The following defines are for the flags in the serial port 5 configuration
563 * register.
564 */
565#define SERC5_SI2EN 0x00000001
566#define SERC5_SI2F_MASK 0x00000006
567#define SERC5_SI2F_ADC 0x00000000
568#define SERC5_SI2F_SPDIF 0x00000002
569
570/*
571 * The following defines are for the flags in the serial port backdoor sample
572 * pointer register.
573 */
574#define SERBSP_FSP_MASK 0x0000000F
575#define SERBSP_FSP_SHIFT 0
576
577/*
578 * The following defines are for the flags in the serial port backdoor status
579 * register.
580 */
581#define SERBST_RRDY 0x00000001
582#define SERBST_WBSY 0x00000002
583
584/*
585 * The following defines are for the flags in the serial port backdoor command
586 * register.
587 */
588#define SERBCM_RDC 0x00000001
589#define SERBCM_WRC 0x00000002
590
591/*
592 * The following defines are for the flags in the serial port backdoor address
593 * register.
594 */
595#ifdef NO_CS4612
596#define SERBAD_FAD_MASK 0x000000FF
597#else
598#define SERBAD_FAD_MASK 0x000001FF
599#endif
600#define SERBAD_FAD_SHIFT 0
601
602/*
603 * The following defines are for the flags in the serial port backdoor
604 * configuration register.
605 */
606#define SERBCF_HBP 0x00000001
607
608/*
609 * The following defines are for the flags in the serial port backdoor write
610 * port register.
611 */
612#define SERBWP_FWD_MASK 0x000FFFFF
613#define SERBWP_FWD_SHIFT 0
614
615/*
616 * The following defines are for the flags in the serial port backdoor read
617 * port register.
618 */
619#define SERBRP_FRD_MASK 0x000FFFFF
620#define SERBRP_FRD_SHIFT 0
621
622/*
623 * The following defines are for the flags in the async FIFO address register.
624 */
625#ifndef NO_CS4612
626#define ASER_FADDR_A1_MASK 0x000001FF
627#define ASER_FADDR_EN1 0x00008000
628#define ASER_FADDR_A2_MASK 0x01FF0000
629#define ASER_FADDR_EN2 0x80000000
630#define ASER_FADDR_A1_SHIFT 0
631#define ASER_FADDR_A2_SHIFT 16
632#endif
633
634/*
635 * The following defines are for the flags in the AC97 control register.
636 */
637#define ACCTL_RSTN 0x00000001
638#define ACCTL_ESYN 0x00000002
639#define ACCTL_VFRM 0x00000004
640#define ACCTL_DCV 0x00000008
641#define ACCTL_CRW 0x00000010
642#define ACCTL_ASYN 0x00000020
643#ifndef NO_CS4612
644#define ACCTL_TC 0x00000040
645#endif
646
647/*
648 * The following defines are for the flags in the AC97 status register.
649 */
650#define ACSTS_CRDY 0x00000001
651#define ACSTS_VSTS 0x00000002
652#ifndef NO_CS4612
653#define ACSTS_WKUP 0x00000004
654#endif
655
656/*
657 * The following defines are for the flags in the AC97 output slot valid
658 * register.
659 */
660#define ACOSV_SLV3 0x00000001
661#define ACOSV_SLV4 0x00000002
662#define ACOSV_SLV5 0x00000004
663#define ACOSV_SLV6 0x00000008
664#define ACOSV_SLV7 0x00000010
665#define ACOSV_SLV8 0x00000020
666#define ACOSV_SLV9 0x00000040
667#define ACOSV_SLV10 0x00000080
668#define ACOSV_SLV11 0x00000100
669#define ACOSV_SLV12 0x00000200
670
671/*
672 * The following defines are for the flags in the AC97 command address
673 * register.
674 */
675#define ACCAD_CI_MASK 0x0000007F
676#define ACCAD_CI_SHIFT 0
677
678/*
679 * The following defines are for the flags in the AC97 command data register.
680 */
681#define ACCDA_CD_MASK 0x0000FFFF
682#define ACCDA_CD_SHIFT 0
683
684/*
685 * The following defines are for the flags in the AC97 input slot valid
686 * register.
687 */
688#define ACISV_ISV3 0x00000001
689#define ACISV_ISV4 0x00000002
690#define ACISV_ISV5 0x00000004
691#define ACISV_ISV6 0x00000008
692#define ACISV_ISV7 0x00000010
693#define ACISV_ISV8 0x00000020
694#define ACISV_ISV9 0x00000040
695#define ACISV_ISV10 0x00000080
696#define ACISV_ISV11 0x00000100
697#define ACISV_ISV12 0x00000200
698
699/*
700 * The following defines are for the flags in the AC97 status address
701 * register.
702 */
703#define ACSAD_SI_MASK 0x0000007F
704#define ACSAD_SI_SHIFT 0
705
706/*
707 * The following defines are for the flags in the AC97 status data register.
708 */
709#define ACSDA_SD_MASK 0x0000FFFF
710#define ACSDA_SD_SHIFT 0
711
712/*
713 * The following defines are for the flags in the joystick poll/trigger
714 * register.
715 */
716#define JSPT_CAX 0x00000001
717#define JSPT_CAY 0x00000002
718#define JSPT_CBX 0x00000004
719#define JSPT_CBY 0x00000008
720#define JSPT_BA1 0x00000010
721#define JSPT_BA2 0x00000020
722#define JSPT_BB1 0x00000040
723#define JSPT_BB2 0x00000080
724
725/*
726 * The following defines are for the flags in the joystick control register.
727 */
728#define JSCTL_SP_MASK 0x00000003
729#define JSCTL_SP_SLOW 0x00000000
730#define JSCTL_SP_MEDIUM_SLOW 0x00000001
731#define JSCTL_SP_MEDIUM_FAST 0x00000002
732#define JSCTL_SP_FAST 0x00000003
733#define JSCTL_ARE 0x00000004
734
735/*
736 * The following defines are for the flags in the joystick coordinate pair 1
737 * readback register.
738 */
739#define JSC1_Y1V_MASK 0x0000FFFF
740#define JSC1_X1V_MASK 0xFFFF0000
741#define JSC1_Y1V_SHIFT 0
742#define JSC1_X1V_SHIFT 16
743
744/*
745 * The following defines are for the flags in the joystick coordinate pair 2
746 * readback register.
747 */
748#define JSC2_Y2V_MASK 0x0000FFFF
749#define JSC2_X2V_MASK 0xFFFF0000
750#define JSC2_Y2V_SHIFT 0
751#define JSC2_X2V_SHIFT 16
752
753/*
754 * The following defines are for the flags in the MIDI control register.
755 */
756#define MIDCR_TXE 0x00000001 /* Enable transmitting. */
757#define MIDCR_RXE 0x00000002 /* Enable receiving. */
758#define MIDCR_RIE 0x00000004 /* Interrupt upon tx ready. */
759#define MIDCR_TIE 0x00000008 /* Interrupt upon rx ready. */
760#define MIDCR_MLB 0x00000010 /* Enable midi loopback. */
761#define MIDCR_MRST 0x00000020 /* Reset interface. */
762
763/*
764 * The following defines are for the flags in the MIDI status register.
765 */
766#define MIDSR_TBF 0x00000001 /* Tx FIFO is full. */
767#define MIDSR_RBE 0x00000002 /* Rx FIFO is empty. */
768
769/*
770 * The following defines are for the flags in the MIDI write port register.
771 */
772#define MIDWP_MWD_MASK 0x000000FF
773#define MIDWP_MWD_SHIFT 0
774
775/*
776 * The following defines are for the flags in the MIDI read port register.
777 */
778#define MIDRP_MRD_MASK 0x000000FF
779#define MIDRP_MRD_SHIFT 0
780
781/*
782 * The following defines are for the flags in the joystick GPIO register.
783 */
784#define JSIO_DAX 0x00000001
785#define JSIO_DAY 0x00000002
786#define JSIO_DBX 0x00000004
787#define JSIO_DBY 0x00000008
788#define JSIO_AXOE 0x00000010
789#define JSIO_AYOE 0x00000020
790#define JSIO_BXOE 0x00000040
791#define JSIO_BYOE 0x00000080
792
793/*
794 * The following defines are for the flags in the master async/sync serial
795 * port enable register.
796 */
797#ifndef NO_CS4612
798#define ASER_MASTER_ME 0x00000001
799#endif
800
801/*
802 * The following defines are for the flags in the configuration interface
803 * register.
804 */
805#define CFGI_CLK 0x00000001
806#define CFGI_DOUT 0x00000002
807#define CFGI_DIN_EEN 0x00000004
808#define CFGI_EELD 0x00000008
809
810/*
811 * The following defines are for the flags in the subsystem ID and vendor ID
812 * register.
813 */
814#define SSVID_VID_MASK 0x0000FFFF
815#define SSVID_SID_MASK 0xFFFF0000
816#define SSVID_VID_SHIFT 0
817#define SSVID_SID_SHIFT 16
818
819/*
820 * The following defines are for the flags in the GPIO pin interface register.
821 */
822#define GPIOR_VOLDN 0x00000001
823#define GPIOR_VOLUP 0x00000002
824#define GPIOR_SI2D 0x00000004
825#define GPIOR_SI2OE 0x00000008
826
827/*
828 * The following defines are for the flags in the extended GPIO pin direction
829 * register.
830 */
831#ifndef NO_CS4612
832#define EGPIODR_GPOE0 0x00000001
833#define EGPIODR_GPOE1 0x00000002
834#define EGPIODR_GPOE2 0x00000004
835#define EGPIODR_GPOE3 0x00000008
836#define EGPIODR_GPOE4 0x00000010
837#define EGPIODR_GPOE5 0x00000020
838#define EGPIODR_GPOE6 0x00000040
839#define EGPIODR_GPOE7 0x00000080
840#define EGPIODR_GPOE8 0x00000100
841#endif
842
843/*
844 * The following defines are for the flags in the extended GPIO pin polarity/
845 * type register.
846 */
847#ifndef NO_CS4612
848#define EGPIOPTR_GPPT0 0x00000001
849#define EGPIOPTR_GPPT1 0x00000002
850#define EGPIOPTR_GPPT2 0x00000004
851#define EGPIOPTR_GPPT3 0x00000008
852#define EGPIOPTR_GPPT4 0x00000010
853#define EGPIOPTR_GPPT5 0x00000020
854#define EGPIOPTR_GPPT6 0x00000040
855#define EGPIOPTR_GPPT7 0x00000080
856#define EGPIOPTR_GPPT8 0x00000100
857#endif
858
859/*
860 * The following defines are for the flags in the extended GPIO pin sticky
861 * register.
862 */
863#ifndef NO_CS4612
864#define EGPIOTR_GPS0 0x00000001
865#define EGPIOTR_GPS1 0x00000002
866#define EGPIOTR_GPS2 0x00000004
867#define EGPIOTR_GPS3 0x00000008
868#define EGPIOTR_GPS4 0x00000010
869#define EGPIOTR_GPS5 0x00000020
870#define EGPIOTR_GPS6 0x00000040
871#define EGPIOTR_GPS7 0x00000080
872#define EGPIOTR_GPS8 0x00000100
873#endif
874
875/*
876 * The following defines are for the flags in the extended GPIO ping wakeup
877 * register.
878 */
879#ifndef NO_CS4612
880#define EGPIOWR_GPW0 0x00000001
881#define EGPIOWR_GPW1 0x00000002
882#define EGPIOWR_GPW2 0x00000004
883#define EGPIOWR_GPW3 0x00000008
884#define EGPIOWR_GPW4 0x00000010
885#define EGPIOWR_GPW5 0x00000020
886#define EGPIOWR_GPW6 0x00000040
887#define EGPIOWR_GPW7 0x00000080
888#define EGPIOWR_GPW8 0x00000100
889#endif
890
891/*
892 * The following defines are for the flags in the extended GPIO pin status
893 * register.
894 */
895#ifndef NO_CS4612
896#define EGPIOSR_GPS0 0x00000001
897#define EGPIOSR_GPS1 0x00000002
898#define EGPIOSR_GPS2 0x00000004
899#define EGPIOSR_GPS3 0x00000008
900#define EGPIOSR_GPS4 0x00000010
901#define EGPIOSR_GPS5 0x00000020
902#define EGPIOSR_GPS6 0x00000040
903#define EGPIOSR_GPS7 0x00000080
904#define EGPIOSR_GPS8 0x00000100
905#endif
906
907/*
908 * The following defines are for the flags in the serial port 6 configuration
909 * register.
910 */
911#ifndef NO_CS4612
912#define SERC6_ASDO2EN 0x00000001
913#endif
914
915/*
916 * The following defines are for the flags in the serial port 7 configuration
917 * register.
918 */
919#ifndef NO_CS4612
920#define SERC7_ASDI2EN 0x00000001
921#define SERC7_POSILB 0x00000002
922#define SERC7_SIPOLB 0x00000004
923#define SERC7_SOSILB 0x00000008
924#define SERC7_SISOLB 0x00000010
925#endif
926
927/*
928 * The following defines are for the flags in the serial port AC link
929 * configuration register.
930 */
931#ifndef NO_CS4612
932#define SERACC_CODEC_TYPE_MASK 0x00000001
933#define SERACC_CODEC_TYPE_1_03 0x00000000
934#define SERACC_CODEC_TYPE_2_0 0x00000001
935#define SERACC_TWO_CODECS 0x00000002
936#define SERACC_MDM 0x00000004
937#define SERACC_HSP 0x00000008
938#endif
939
940/*
941 * The following defines are for the flags in the AC97 control register 2.
942 */
943#ifndef NO_CS4612
944#define ACCTL2_RSTN 0x00000001
945#define ACCTL2_ESYN 0x00000002
946#define ACCTL2_VFRM 0x00000004
947#define ACCTL2_DCV 0x00000008
948#define ACCTL2_CRW 0x00000010
949#define ACCTL2_ASYN 0x00000020
950#endif
951
952/*
953 * The following defines are for the flags in the AC97 status register 2.
954 */
955#ifndef NO_CS4612
956#define ACSTS2_CRDY 0x00000001
957#define ACSTS2_VSTS 0x00000002
958#endif
959
960/*
961 * The following defines are for the flags in the AC97 output slot valid
962 * register 2.
963 */
964#ifndef NO_CS4612
965#define ACOSV2_SLV3 0x00000001
966#define ACOSV2_SLV4 0x00000002
967#define ACOSV2_SLV5 0x00000004
968#define ACOSV2_SLV6 0x00000008
969#define ACOSV2_SLV7 0x00000010
970#define ACOSV2_SLV8 0x00000020
971#define ACOSV2_SLV9 0x00000040
972#define ACOSV2_SLV10 0x00000080
973#define ACOSV2_SLV11 0x00000100
974#define ACOSV2_SLV12 0x00000200
975#endif
976
977/*
978 * The following defines are for the flags in the AC97 command address
979 * register 2.
980 */
981#ifndef NO_CS4612
982#define ACCAD2_CI_MASK 0x0000007F
983#define ACCAD2_CI_SHIFT 0
984#endif
985
986/*
987 * The following defines are for the flags in the AC97 command data register
988 * 2.
989 */
990#ifndef NO_CS4612
991#define ACCDA2_CD_MASK 0x0000FFFF
992#define ACCDA2_CD_SHIFT 0
993#endif
994
995/*
996 * The following defines are for the flags in the AC97 input slot valid
997 * register 2.
998 */
999#ifndef NO_CS4612
1000#define ACISV2_ISV3 0x00000001
1001#define ACISV2_ISV4 0x00000002
1002#define ACISV2_ISV5 0x00000004
1003#define ACISV2_ISV6 0x00000008
1004#define ACISV2_ISV7 0x00000010
1005#define ACISV2_ISV8 0x00000020
1006#define ACISV2_ISV9 0x00000040
1007#define ACISV2_ISV10 0x00000080
1008#define ACISV2_ISV11 0x00000100
1009#define ACISV2_ISV12 0x00000200
1010#endif
1011
1012/*
1013 * The following defines are for the flags in the AC97 status address
1014 * register 2.
1015 */
1016#ifndef NO_CS4612
1017#define ACSAD2_SI_MASK 0x0000007F
1018#define ACSAD2_SI_SHIFT 0
1019#endif
1020
1021/*
1022 * The following defines are for the flags in the AC97 status data register 2.
1023 */
1024#ifndef NO_CS4612
1025#define ACSDA2_SD_MASK 0x0000FFFF
1026#define ACSDA2_SD_SHIFT 0
1027#endif
1028
1029/*
1030 * The following defines are for the flags in the I/O trap address and control
1031 * registers (all 12).
1032 */
1033#ifndef NO_CS4612
1034#define IOTAC_SA_MASK 0x0000FFFF
1035#define IOTAC_MSK_MASK 0x000F0000
1036#define IOTAC_IODC_MASK 0x06000000
1037#define IOTAC_IODC_16_BIT 0x00000000
1038#define IOTAC_IODC_10_BIT 0x02000000
1039#define IOTAC_IODC_12_BIT 0x04000000
1040#define IOTAC_WSPI 0x08000000
1041#define IOTAC_RSPI 0x10000000
1042#define IOTAC_WSE 0x20000000
1043#define IOTAC_WE 0x40000000
1044#define IOTAC_RE 0x80000000
1045#define IOTAC_SA_SHIFT 0
1046#define IOTAC_MSK_SHIFT 16
1047#endif
1048
1049/*
1050 * The following defines are for the flags in the I/O trap fast read registers
1051 * (all 8).
1052 */
1053#ifndef NO_CS4612
1054#define IOTFR_D_MASK 0x0000FFFF
1055#define IOTFR_A_MASK 0x000F0000
1056#define IOTFR_R_MASK 0x0F000000
1057#define IOTFR_ALL 0x40000000
1058#define IOTFR_VL 0x80000000
1059#define IOTFR_D_SHIFT 0
1060#define IOTFR_A_SHIFT 16
1061#define IOTFR_R_SHIFT 24
1062#endif
1063
1064/*
1065 * The following defines are for the flags in the I/O trap FIFO register.
1066 */
1067#ifndef NO_CS4612
1068#define IOTFIFO_BA_MASK 0x00003FFF
1069#define IOTFIFO_S_MASK 0x00FF0000
1070#define IOTFIFO_OF 0x40000000
1071#define IOTFIFO_SPIOF 0x80000000
1072#define IOTFIFO_BA_SHIFT 0
1073#define IOTFIFO_S_SHIFT 16
1074#endif
1075
1076/*
1077 * The following defines are for the flags in the I/O trap retry read data
1078 * register.
1079 */
1080#ifndef NO_CS4612
1081#define IOTRRD_D_MASK 0x0000FFFF
1082#define IOTRRD_RDV 0x80000000
1083#define IOTRRD_D_SHIFT 0
1084#endif
1085
1086/*
1087 * The following defines are for the flags in the I/O trap FIFO pointer
1088 * register.
1089 */
1090#ifndef NO_CS4612
1091#define IOTFP_CA_MASK 0x00003FFF
1092#define IOTFP_PA_MASK 0x3FFF0000
1093#define IOTFP_CA_SHIFT 0
1094#define IOTFP_PA_SHIFT 16
1095#endif
1096
1097/*
1098 * The following defines are for the flags in the I/O trap control register.
1099 */
1100#ifndef NO_CS4612
1101#define IOTCR_ITD 0x00000001
1102#define IOTCR_HRV 0x00000002
1103#define IOTCR_SRV 0x00000004
1104#define IOTCR_DTI 0x00000008
1105#define IOTCR_DFI 0x00000010
1106#define IOTCR_DDP 0x00000020
1107#define IOTCR_JTE 0x00000040
1108#define IOTCR_PPE 0x00000080
1109#endif
1110
1111/*
1112 * The following defines are for the flags in the direct PCI data register.
1113 */
1114#ifndef NO_CS4612
1115#define DPCID_D_MASK 0xFFFFFFFF
1116#define DPCID_D_SHIFT 0
1117#endif
1118
1119/*
1120 * The following defines are for the flags in the direct PCI address register.
1121 */
1122#ifndef NO_CS4612
1123#define DPCIA_A_MASK 0xFFFFFFFF
1124#define DPCIA_A_SHIFT 0
1125#endif
1126
1127/*
1128 * The following defines are for the flags in the direct PCI command register.
1129 */
1130#ifndef NO_CS4612
1131#define DPCIC_C_MASK 0x0000000F
1132#define DPCIC_C_IOREAD 0x00000002
1133#define DPCIC_C_IOWRITE 0x00000003
1134#define DPCIC_BE_MASK 0x000000F0
1135#endif
1136
1137/*
1138 * The following defines are for the flags in the PC/PCI request register.
1139 */
1140#ifndef NO_CS4612
1141#define PCPCIR_RDC_MASK 0x00000007
1142#define PCPCIR_C_MASK 0x00007000
1143#define PCPCIR_REQ 0x00008000
1144#define PCPCIR_RDC_SHIFT 0
1145#define PCPCIR_C_SHIFT 12
1146#endif
1147
1148/*
1149 * The following defines are for the flags in the PC/PCI grant register.
1150 */
1151#ifndef NO_CS4612
1152#define PCPCIG_GDC_MASK 0x00000007
1153#define PCPCIG_VL 0x00008000
1154#define PCPCIG_GDC_SHIFT 0
1155#endif
1156
1157/*
1158 * The following defines are for the flags in the PC/PCI master enable
1159 * register.
1160 */
1161#ifndef NO_CS4612
1162#define PCPCIEN_EN 0x00000001
1163#endif
1164
1165/*
1166 * The following defines are for the flags in the extended PCI power
1167 * management control register.
1168 */
1169#ifndef NO_CS4612
1170#define EPCIPMC_GWU 0x00000001
1171#define EPCIPMC_FSPC 0x00000002
1172#endif
1173
1174/*
1175 * The following defines are for the flags in the SP control register.
1176 */
1177#define SPCR_RUN 0x00000001
1178#define SPCR_STPFR 0x00000002
1179#define SPCR_RUNFR 0x00000004
1180#define SPCR_TICK 0x00000008
1181#define SPCR_DRQEN 0x00000020
1182#define SPCR_RSTSP 0x00000040
1183#define SPCR_OREN 0x00000080
1184#ifndef NO_CS4612
1185#define SPCR_PCIINT 0x00000100
1186#define SPCR_OINTD 0x00000200
1187#define SPCR_CRE 0x00008000
1188#endif
1189
1190/*
1191 * The following defines are for the flags in the debug index register.
1192 */
1193#define DREG_REGID_MASK 0x0000007F
1194#define DREG_DEBUG 0x00000080
1195#define DREG_RGBK_MASK 0x00000700
1196#define DREG_TRAP 0x00000800
1197#if !defined(NO_CS4612)
1198#if !defined(NO_CS4615)
1199#define DREG_TRAPX 0x00001000
1200#endif
1201#endif
1202#define DREG_REGID_SHIFT 0
1203#define DREG_RGBK_SHIFT 8
1204#define DREG_RGBK_REGID_MASK 0x0000077F
1205#define DREG_REGID_R0 0x00000010
1206#define DREG_REGID_R1 0x00000011
1207#define DREG_REGID_R2 0x00000012
1208#define DREG_REGID_R3 0x00000013
1209#define DREG_REGID_R4 0x00000014
1210#define DREG_REGID_R5 0x00000015
1211#define DREG_REGID_R6 0x00000016
1212#define DREG_REGID_R7 0x00000017
1213#define DREG_REGID_R8 0x00000018
1214#define DREG_REGID_R9 0x00000019
1215#define DREG_REGID_RA 0x0000001A
1216#define DREG_REGID_RB 0x0000001B
1217#define DREG_REGID_RC 0x0000001C
1218#define DREG_REGID_RD 0x0000001D
1219#define DREG_REGID_RE 0x0000001E
1220#define DREG_REGID_RF 0x0000001F
1221#define DREG_REGID_RA_BUS_LOW 0x00000020
1222#define DREG_REGID_RA_BUS_HIGH 0x00000038
1223#define DREG_REGID_YBUS_LOW 0x00000050
1224#define DREG_REGID_YBUS_HIGH 0x00000058
1225#define DREG_REGID_TRAP_0 0x00000100
1226#define DREG_REGID_TRAP_1 0x00000101
1227#define DREG_REGID_TRAP_2 0x00000102
1228#define DREG_REGID_TRAP_3 0x00000103
1229#define DREG_REGID_TRAP_4 0x00000104
1230#define DREG_REGID_TRAP_5 0x00000105
1231#define DREG_REGID_TRAP_6 0x00000106
1232#define DREG_REGID_TRAP_7 0x00000107
1233#define DREG_REGID_INDIRECT_ADDRESS 0x0000010E
1234#define DREG_REGID_TOP_OF_STACK 0x0000010F
1235#if !defined(NO_CS4612)
1236#if !defined(NO_CS4615)
1237#define DREG_REGID_TRAP_8 0x00000110
1238#define DREG_REGID_TRAP_9 0x00000111
1239#define DREG_REGID_TRAP_10 0x00000112
1240#define DREG_REGID_TRAP_11 0x00000113
1241#define DREG_REGID_TRAP_12 0x00000114
1242#define DREG_REGID_TRAP_13 0x00000115
1243#define DREG_REGID_TRAP_14 0x00000116
1244#define DREG_REGID_TRAP_15 0x00000117
1245#define DREG_REGID_TRAP_16 0x00000118
1246#define DREG_REGID_TRAP_17 0x00000119
1247#define DREG_REGID_TRAP_18 0x0000011A
1248#define DREG_REGID_TRAP_19 0x0000011B
1249#define DREG_REGID_TRAP_20 0x0000011C
1250#define DREG_REGID_TRAP_21 0x0000011D
1251#define DREG_REGID_TRAP_22 0x0000011E
1252#define DREG_REGID_TRAP_23 0x0000011F
1253#endif
1254#endif
1255#define DREG_REGID_RSA0_LOW 0x00000200
1256#define DREG_REGID_RSA0_HIGH 0x00000201
1257#define DREG_REGID_RSA1_LOW 0x00000202
1258#define DREG_REGID_RSA1_HIGH 0x00000203
1259#define DREG_REGID_RSA2 0x00000204
1260#define DREG_REGID_RSA3 0x00000205
1261#define DREG_REGID_RSI0_LOW 0x00000206
1262#define DREG_REGID_RSI0_HIGH 0x00000207
1263#define DREG_REGID_RSI1 0x00000208
1264#define DREG_REGID_RSI2 0x00000209
1265#define DREG_REGID_SAGUSTATUS 0x0000020A
1266#define DREG_REGID_RSCONFIG01_LOW 0x0000020B
1267#define DREG_REGID_RSCONFIG01_HIGH 0x0000020C
1268#define DREG_REGID_RSCONFIG23_LOW 0x0000020D
1269#define DREG_REGID_RSCONFIG23_HIGH 0x0000020E
1270#define DREG_REGID_RSDMA01E 0x0000020F
1271#define DREG_REGID_RSDMA23E 0x00000210
1272#define DREG_REGID_RSD0_LOW 0x00000211
1273#define DREG_REGID_RSD0_HIGH 0x00000212
1274#define DREG_REGID_RSD1_LOW 0x00000213
1275#define DREG_REGID_RSD1_HIGH 0x00000214
1276#define DREG_REGID_RSD2_LOW 0x00000215
1277#define DREG_REGID_RSD2_HIGH 0x00000216
1278#define DREG_REGID_RSD3_LOW 0x00000217
1279#define DREG_REGID_RSD3_HIGH 0x00000218
1280#define DREG_REGID_SRAR_HIGH 0x0000021A
1281#define DREG_REGID_SRAR_LOW 0x0000021B
1282#define DREG_REGID_DMA_STATE 0x0000021C
1283#define DREG_REGID_CURRENT_DMA_STREAM 0x0000021D
1284#define DREG_REGID_NEXT_DMA_STREAM 0x0000021E
1285#define DREG_REGID_CPU_STATUS 0x00000300
1286#define DREG_REGID_MAC_MODE 0x00000301
1287#define DREG_REGID_STACK_AND_REPEAT 0x00000302
1288#define DREG_REGID_INDEX0 0x00000304
1289#define DREG_REGID_INDEX1 0x00000305
1290#define DREG_REGID_DMA_STATE_0_3 0x00000400
1291#define DREG_REGID_DMA_STATE_4_7 0x00000404
1292#define DREG_REGID_DMA_STATE_8_11 0x00000408
1293#define DREG_REGID_DMA_STATE_12_15 0x0000040C
1294#define DREG_REGID_DMA_STATE_16_19 0x00000410
1295#define DREG_REGID_DMA_STATE_20_23 0x00000414
1296#define DREG_REGID_DMA_STATE_24_27 0x00000418
1297#define DREG_REGID_DMA_STATE_28_31 0x0000041C
1298#define DREG_REGID_DMA_STATE_32_35 0x00000420
1299#define DREG_REGID_DMA_STATE_36_39 0x00000424
1300#define DREG_REGID_DMA_STATE_40_43 0x00000428
1301#define DREG_REGID_DMA_STATE_44_47 0x0000042C
1302#define DREG_REGID_DMA_STATE_48_51 0x00000430
1303#define DREG_REGID_DMA_STATE_52_55 0x00000434
1304#define DREG_REGID_DMA_STATE_56_59 0x00000438
1305#define DREG_REGID_DMA_STATE_60_63 0x0000043C
1306#define DREG_REGID_DMA_STATE_64_67 0x00000440
1307#define DREG_REGID_DMA_STATE_68_71 0x00000444
1308#define DREG_REGID_DMA_STATE_72_75 0x00000448
1309#define DREG_REGID_DMA_STATE_76_79 0x0000044C
1310#define DREG_REGID_DMA_STATE_80_83 0x00000450
1311#define DREG_REGID_DMA_STATE_84_87 0x00000454
1312#define DREG_REGID_DMA_STATE_88_91 0x00000458
1313#define DREG_REGID_DMA_STATE_92_95 0x0000045C
1314#define DREG_REGID_TRAP_SELECT 0x00000500
1315#define DREG_REGID_TRAP_WRITE_0 0x00000500
1316#define DREG_REGID_TRAP_WRITE_1 0x00000501
1317#define DREG_REGID_TRAP_WRITE_2 0x00000502
1318#define DREG_REGID_TRAP_WRITE_3 0x00000503
1319#define DREG_REGID_TRAP_WRITE_4 0x00000504
1320#define DREG_REGID_TRAP_WRITE_5 0x00000505
1321#define DREG_REGID_TRAP_WRITE_6 0x00000506
1322#define DREG_REGID_TRAP_WRITE_7 0x00000507
1323#if !defined(NO_CS4612)
1324#if !defined(NO_CS4615)
1325#define DREG_REGID_TRAP_WRITE_8 0x00000510
1326#define DREG_REGID_TRAP_WRITE_9 0x00000511
1327#define DREG_REGID_TRAP_WRITE_10 0x00000512
1328#define DREG_REGID_TRAP_WRITE_11 0x00000513
1329#define DREG_REGID_TRAP_WRITE_12 0x00000514
1330#define DREG_REGID_TRAP_WRITE_13 0x00000515
1331#define DREG_REGID_TRAP_WRITE_14 0x00000516
1332#define DREG_REGID_TRAP_WRITE_15 0x00000517
1333#define DREG_REGID_TRAP_WRITE_16 0x00000518
1334#define DREG_REGID_TRAP_WRITE_17 0x00000519
1335#define DREG_REGID_TRAP_WRITE_18 0x0000051A
1336#define DREG_REGID_TRAP_WRITE_19 0x0000051B
1337#define DREG_REGID_TRAP_WRITE_20 0x0000051C
1338#define DREG_REGID_TRAP_WRITE_21 0x0000051D
1339#define DREG_REGID_TRAP_WRITE_22 0x0000051E
1340#define DREG_REGID_TRAP_WRITE_23 0x0000051F
1341#endif
1342#endif
1343#define DREG_REGID_MAC0_ACC0_LOW 0x00000600
1344#define DREG_REGID_MAC0_ACC1_LOW 0x00000601
1345#define DREG_REGID_MAC0_ACC2_LOW 0x00000602
1346#define DREG_REGID_MAC0_ACC3_LOW 0x00000603
1347#define DREG_REGID_MAC1_ACC0_LOW 0x00000604
1348#define DREG_REGID_MAC1_ACC1_LOW 0x00000605
1349#define DREG_REGID_MAC1_ACC2_LOW 0x00000606
1350#define DREG_REGID_MAC1_ACC3_LOW 0x00000607
1351#define DREG_REGID_MAC0_ACC0_MID 0x00000608
1352#define DREG_REGID_MAC0_ACC1_MID 0x00000609
1353#define DREG_REGID_MAC0_ACC2_MID 0x0000060A
1354#define DREG_REGID_MAC0_ACC3_MID 0x0000060B
1355#define DREG_REGID_MAC1_ACC0_MID 0x0000060C
1356#define DREG_REGID_MAC1_ACC1_MID 0x0000060D
1357#define DREG_REGID_MAC1_ACC2_MID 0x0000060E
1358#define DREG_REGID_MAC1_ACC3_MID 0x0000060F
1359#define DREG_REGID_MAC0_ACC0_HIGH 0x00000610
1360#define DREG_REGID_MAC0_ACC1_HIGH 0x00000611
1361#define DREG_REGID_MAC0_ACC2_HIGH 0x00000612
1362#define DREG_REGID_MAC0_ACC3_HIGH 0x00000613
1363#define DREG_REGID_MAC1_ACC0_HIGH 0x00000614
1364#define DREG_REGID_MAC1_ACC1_HIGH 0x00000615
1365#define DREG_REGID_MAC1_ACC2_HIGH 0x00000616
1366#define DREG_REGID_MAC1_ACC3_HIGH 0x00000617
1367#define DREG_REGID_RSHOUT_LOW 0x00000620
1368#define DREG_REGID_RSHOUT_MID 0x00000628
1369#define DREG_REGID_RSHOUT_HIGH 0x00000630
1370
1371/*
1372 * The following defines are for the flags in the DMA stream requestor write
1373 */
1374#define DSRWP_DSR_MASK 0x0000000F
1375#define DSRWP_DSR_BG_RQ 0x00000001
1376#define DSRWP_DSR_PRIORITY_MASK 0x00000006
1377#define DSRWP_DSR_PRIORITY_0 0x00000000
1378#define DSRWP_DSR_PRIORITY_1 0x00000002
1379#define DSRWP_DSR_PRIORITY_2 0x00000004
1380#define DSRWP_DSR_PRIORITY_3 0x00000006
1381#define DSRWP_DSR_RQ_PENDING 0x00000008
1382
1383/*
1384 * The following defines are for the flags in the trap write port register.
1385 */
1386#define TWPR_TW_MASK 0x0000FFFF
1387#define TWPR_TW_SHIFT 0
1388
1389/*
1390 * The following defines are for the flags in the stack pointer write
1391 * register.
1392 */
1393#define SPWR_STKP_MASK 0x0000000F
1394#define SPWR_STKP_SHIFT 0
1395
1396/*
1397 * The following defines are for the flags in the SP interrupt register.
1398 */
1399#define SPIR_FRI 0x00000001
1400#define SPIR_DOI 0x00000002
1401#define SPIR_GPI2 0x00000004
1402#define SPIR_GPI3 0x00000008
1403#define SPIR_IP0 0x00000010
1404#define SPIR_IP1 0x00000020
1405#define SPIR_IP2 0x00000040
1406#define SPIR_IP3 0x00000080
1407
1408/*
1409 * The following defines are for the flags in the functional group 1 register.
1410 */
1411#define FGR1_F1S_MASK 0x0000FFFF
1412#define FGR1_F1S_SHIFT 0
1413
1414/*
1415 * The following defines are for the flags in the SP clock status register.
1416 */
1417#define SPCS_FRI 0x00000001
1418#define SPCS_DOI 0x00000002
1419#define SPCS_GPI2 0x00000004
1420#define SPCS_GPI3 0x00000008
1421#define SPCS_IP0 0x00000010
1422#define SPCS_IP1 0x00000020
1423#define SPCS_IP2 0x00000040
1424#define SPCS_IP3 0x00000080
1425#define SPCS_SPRUN 0x00000100
1426#define SPCS_SLEEP 0x00000200
1427#define SPCS_FG 0x00000400
1428#define SPCS_ORUN 0x00000800
1429#define SPCS_IRQ 0x00001000
1430#define SPCS_FGN_MASK 0x0000E000
1431#define SPCS_FGN_SHIFT 13
1432
1433/*
1434 * The following defines are for the flags in the SP DMA requestor status
1435 * register.
1436 */
1437#define SDSR_DCS_MASK 0x000000FF
1438#define SDSR_DCS_SHIFT 0
1439#define SDSR_DCS_NONE 0x00000007
1440
1441/*
1442 * The following defines are for the flags in the frame timer register.
1443 */
1444#define FRMT_FTV_MASK 0x0000FFFF
1445#define FRMT_FTV_SHIFT 0
1446
1447/*
1448 * The following defines are for the flags in the frame timer current count
1449 * register.
1450 */
1451#define FRCC_FCC_MASK 0x0000FFFF
1452#define FRCC_FCC_SHIFT 0
1453
1454/*
1455 * The following defines are for the flags in the frame timer save count
1456 * register.
1457 */
1458#define FRSC_FCS_MASK 0x0000FFFF
1459#define FRSC_FCS_SHIFT 0
1460
1461/*
1462 * The following define the various flags stored in the scatter/gather
1463 * descriptors.
1464 */
1465#define DMA_SG_NEXT_ENTRY_MASK 0x00000FF8
1466#define DMA_SG_SAMPLE_END_MASK 0x0FFF0000
1467#define DMA_SG_SAMPLE_END_FLAG 0x10000000
1468#define DMA_SG_LOOP_END_FLAG 0x20000000
1469#define DMA_SG_SIGNAL_END_FLAG 0x40000000
1470#define DMA_SG_SIGNAL_PAGE_FLAG 0x80000000
1471#define DMA_SG_NEXT_ENTRY_SHIFT 3
1472#define DMA_SG_SAMPLE_END_SHIFT 16
1473
1474/*
1475 * The following define the offsets of the fields within the on-chip generic
1476 * DMA requestor.
1477 */
1478#define DMA_RQ_CONTROL1 0x00000000
1479#define DMA_RQ_CONTROL2 0x00000004
1480#define DMA_RQ_SOURCE_ADDR 0x00000008
1481#define DMA_RQ_DESTINATION_ADDR 0x0000000C
1482#define DMA_RQ_NEXT_PAGE_ADDR 0x00000010
1483#define DMA_RQ_NEXT_PAGE_SGDESC 0x00000014
1484#define DMA_RQ_LOOP_START_ADDR 0x00000018
1485#define DMA_RQ_POST_LOOP_ADDR 0x0000001C
1486#define DMA_RQ_PAGE_MAP_ADDR 0x00000020
1487
1488/*
1489 * The following defines are for the flags in the first control word of the
1490 * on-chip generic DMA requestor.
1491 */
1492#define DMA_RQ_C1_COUNT_MASK 0x000003FF
1493#define DMA_RQ_C1_DESTINATION_SCATTER 0x00001000
1494#define DMA_RQ_C1_SOURCE_GATHER 0x00002000
1495#define DMA_RQ_C1_DONE_FLAG 0x00004000
1496#define DMA_RQ_C1_OPTIMIZE_STATE 0x00008000
1497#define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x00030000
1498#define DMA_RQ_C1_FULL_PAGE 0x00000000
1499#define DMA_RQ_C1_BEFORE_SAMPLE_END 0x00010000
1500#define DMA_RQ_C1_PAGE_MAP_ERROR 0x00020000
1501#define DMA_RQ_C1_AT_SAMPLE_END 0x00030000
1502#define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C0000
1503#define DMA_RQ_C1_NOT_LOOP_END 0x00000000
1504#define DMA_RQ_C1_BEFORE_LOOP_END 0x00040000
1505#define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x00080000
1506#define DMA_RQ_C1_LOOP_BEGIN 0x000C0000
1507#define DMA_RQ_C1_PAGE_MAP_MASK 0x00300000
1508#define DMA_RQ_C1_PM_NONE_PENDING 0x00000000
1509#define DMA_RQ_C1_PM_NEXT_PENDING 0x00100000
1510#define DMA_RQ_C1_PM_RESERVED 0x00200000
1511#define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x00300000
1512#define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x00400000
1513#define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x00800000
1514#define DMA_RQ_C1_DEST_SIZE_MASK 0x07000000
1515#define DMA_RQ_C1_DEST_LINEAR 0x00000000
1516#define DMA_RQ_C1_DEST_MOD16 0x01000000
1517#define DMA_RQ_C1_DEST_MOD32 0x02000000
1518#define DMA_RQ_C1_DEST_MOD64 0x03000000
1519#define DMA_RQ_C1_DEST_MOD128 0x04000000
1520#define DMA_RQ_C1_DEST_MOD256 0x05000000
1521#define DMA_RQ_C1_DEST_MOD512 0x06000000
1522#define DMA_RQ_C1_DEST_MOD1024 0x07000000
1523#define DMA_RQ_C1_DEST_ON_HOST 0x08000000
1524#define DMA_RQ_C1_SOURCE_SIZE_MASK 0x70000000
1525#define DMA_RQ_C1_SOURCE_LINEAR 0x00000000
1526#define DMA_RQ_C1_SOURCE_MOD16 0x10000000
1527#define DMA_RQ_C1_SOURCE_MOD32 0x20000000
1528#define DMA_RQ_C1_SOURCE_MOD64 0x30000000
1529#define DMA_RQ_C1_SOURCE_MOD128 0x40000000
1530#define DMA_RQ_C1_SOURCE_MOD256 0x50000000
1531#define DMA_RQ_C1_SOURCE_MOD512 0x60000000
1532#define DMA_RQ_C1_SOURCE_MOD1024 0x70000000
1533#define DMA_RQ_C1_SOURCE_ON_HOST 0x80000000
1534#define DMA_RQ_C1_COUNT_SHIFT 0
1535
1536/*
1537 * The following defines are for the flags in the second control word of the
1538 * on-chip generic DMA requestor.
1539 */
1540#define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003F
1541#define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x00000300
1542#define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x00000000
1543#define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x00000100
1544#define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x00000200
1545#define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x00000300
1546#define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000
1547#define DMA_RQ_C2_AC_NONE 0x00000000
1548#define DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000
1549#define DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000
1550#define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000
1551#define DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000
1552#define DMA_RQ_C2_LOOP_END_MASK 0x0FFF0000
1553#define DMA_RQ_C2_LOOP_MASK 0x30000000
1554#define DMA_RQ_C2_NO_LOOP 0x00000000
1555#define DMA_RQ_C2_ONE_PAGE_LOOP 0x10000000
1556#define DMA_RQ_C2_TWO_PAGE_LOOP 0x20000000
1557#define DMA_RQ_C2_MULTI_PAGE_LOOP 0x30000000
1558#define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x40000000
1559#define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x80000000
1560#define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 0
1561#define DMA_RQ_C2_LOOP_END_SHIFT 16
1562
1563/*
1564 * The following defines are for the flags in the source and destination words
1565 * of the on-chip generic DMA requestor.
1566 */
1567#define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFF
1568#define DMA_RQ_SD_MEMORY_ID_MASK 0x000F0000
1569#define DMA_RQ_SD_SP_PARAM_ADDR 0x00000000
1570#define DMA_RQ_SD_SP_SAMPLE_ADDR 0x00010000
1571#define DMA_RQ_SD_SP_PROGRAM_ADDR 0x00020000
1572#define DMA_RQ_SD_SP_DEBUG_ADDR 0x00030000
1573#define DMA_RQ_SD_OMNIMEM_ADDR 0x000E0000
1574#define DMA_RQ_SD_END_FLAG 0x40000000
1575#define DMA_RQ_SD_ERROR_FLAG 0x80000000
1576#define DMA_RQ_SD_ADDRESS_SHIFT 0
1577
1578/*
1579 * The following defines are for the flags in the page map address word of the
1580 * on-chip generic DMA requestor.
1581 */
1582#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF8
1583#define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF000
1584#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 3
1585#define DMA_RQ_PMA_PAGE_TABLE_SHIFT 12
1586
1587#define BA1_VARIDEC_BUF_1 0x000
1588
1589#define BA1_PDTC 0x0c0 /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */
1590#define BA1_PFIE 0x0c4 /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */
1591#define BA1_PBA 0x0c8 /* BA1_PLAY_BUFFER_ADDRESS */
1592#define BA1_PVOL 0x0f8 /* BA1_PLAY_VOLUME_REG */
1593#define BA1_PSRC 0x288 /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */
1594#define BA1_PCTL 0x2a4 /* BA1_PLAY_CONTROL_REG */
1595#define BA1_PPI 0x2b4 /* BA1_PLAY_PHASE_INCREMENT_REG */
1596
1597#define BA1_CCTL 0x064 /* BA1_CAPTURE_CONTROL_REG */
1598#define BA1_CIE 0x104 /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */
1599#define BA1_CBA 0x10c /* BA1_CAPTURE_BUFFER_ADDRESS */
1600#define BA1_CSRC 0x2c8 /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */
1601#define BA1_CCI 0x2d8 /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */
1602#define BA1_CD 0x2e0 /* BA1_CAPTURE_DELAY_REG */
1603#define BA1_CPI 0x2f4 /* BA1_CAPTURE_PHASE_INCREMENT_REG */
1604#define BA1_CVOL 0x2f8 /* BA1_CAPTURE_VOLUME_REG */
1605
1606#define BA1_CFG1 0x134 /* BA1_CAPTURE_FRAME_GROUP_1_REG */
1607#define BA1_CFG2 0x138 /* BA1_CAPTURE_FRAME_GROUP_2_REG */
1608#define BA1_CCST 0x13c /* BA1_CAPTURE_CONSTANT_REG */
1609#define BA1_CSPB 0x340 /* BA1_CAPTURE_SPB_ADDRESS */
1610
1611/*
1612 *
1613 */
1614
1615#define CS461X_MODE_OUTPUT (1<<0) /* MIDI UART - output */
1616#define CS461X_MODE_INPUT (1<<1) /* MIDI UART - input */
1617
1618//****************************************************************************
1619//
1620// The following define the offsets of the AC97 shadow registers, which appear
1621// as a virtual extension to the base address register zero memory range.
1622//
1623//****************************************************************************
1624#define AC97_REG_OFFSET_MASK 0x0000007EL
1625#define AC97_CODEC_NUMBER_MASK 0x00003000L
1626
1627#define BA0_AC97_RESET 0x00001000L
1628#define BA0_AC97_MASTER_VOLUME 0x00001002L
1629#define BA0_AC97_HEADPHONE_VOLUME 0x00001004L
1630#define BA0_AC97_MASTER_VOLUME_MONO 0x00001006L
1631#define BA0_AC97_MASTER_TONE 0x00001008L
1632#define BA0_AC97_PC_BEEP_VOLUME 0x0000100AL
1633#define BA0_AC97_PHONE_VOLUME 0x0000100CL
1634#define BA0_AC97_MIC_VOLUME 0x0000100EL
1635#define BA0_AC97_LINE_IN_VOLUME 0x00001010L
1636#define BA0_AC97_CD_VOLUME 0x00001012L
1637#define BA0_AC97_VIDEO_VOLUME 0x00001014L
1638#define BA0_AC97_AUX_VOLUME 0x00001016L
1639#define BA0_AC97_PCM_OUT_VOLUME 0x00001018L
1640#define BA0_AC97_RECORD_SELECT 0x0000101AL
1641#define BA0_AC97_RECORD_GAIN 0x0000101CL
1642#define BA0_AC97_RECORD_GAIN_MIC 0x0000101EL
1643#define BA0_AC97_GENERAL_PURPOSE 0x00001020L
1644#define BA0_AC97_3D_CONTROL 0x00001022L
1645#define BA0_AC97_MODEM_RATE 0x00001024L
1646#define BA0_AC97_POWERDOWN 0x00001026L
1647#define BA0_AC97_EXT_AUDIO_ID 0x00001028L
1648#define BA0_AC97_EXT_AUDIO_POWER 0x0000102AL
1649#define BA0_AC97_PCM_FRONT_DAC_RATE 0x0000102CL
1650#define BA0_AC97_PCM_SURR_DAC_RATE 0x0000102EL
1651#define BA0_AC97_PCM_LFE_DAC_RATE 0x00001030L
1652#define BA0_AC97_PCM_LR_ADC_RATE 0x00001032L
1653#define BA0_AC97_MIC_ADC_RATE 0x00001034L
1654#define BA0_AC97_6CH_VOL_C_LFE 0x00001036L
1655#define BA0_AC97_6CH_VOL_SURROUND 0x00001038L
1656#define BA0_AC97_RESERVED_3A 0x0000103AL
1657#define BA0_AC97_EXT_MODEM_ID 0x0000103CL
1658#define BA0_AC97_EXT_MODEM_POWER 0x0000103EL
1659#define BA0_AC97_LINE1_CODEC_RATE 0x00001040L
1660#define BA0_AC97_LINE2_CODEC_RATE 0x00001042L
1661#define BA0_AC97_HANDSET_CODEC_RATE 0x00001044L
1662#define BA0_AC97_LINE1_CODEC_LEVEL 0x00001046L
1663#define BA0_AC97_LINE2_CODEC_LEVEL 0x00001048L
1664#define BA0_AC97_HANDSET_CODEC_LEVEL 0x0000104AL
1665#define BA0_AC97_GPIO_PIN_CONFIG 0x0000104CL
1666#define BA0_AC97_GPIO_PIN_TYPE 0x0000104EL
1667#define BA0_AC97_GPIO_PIN_STICKY 0x00001050L
1668#define BA0_AC97_GPIO_PIN_WAKEUP 0x00001052L
1669#define BA0_AC97_GPIO_PIN_STATUS 0x00001054L
1670#define BA0_AC97_MISC_MODEM_AFE_STAT 0x00001056L
1671#define BA0_AC97_RESERVED_58 0x00001058L
1672#define BA0_AC97_CRYSTAL_REV_N_FAB_ID 0x0000105AL
1673#define BA0_AC97_TEST_AND_MISC_CTRL 0x0000105CL
1674#define BA0_AC97_AC_MODE 0x0000105EL
1675#define BA0_AC97_MISC_CRYSTAL_CONTROL 0x00001060L
1676#define BA0_AC97_LINE1_HYPRID_CTRL 0x00001062L
1677#define BA0_AC97_VENDOR_RESERVED_64 0x00001064L
1678#define BA0_AC97_VENDOR_RESERVED_66 0x00001066L
1679#define BA0_AC97_SPDIF_CONTROL 0x00001068L
1680#define BA0_AC97_VENDOR_RESERVED_6A 0x0000106AL
1681#define BA0_AC97_VENDOR_RESERVED_6C 0x0000106CL
1682#define BA0_AC97_VENDOR_RESERVED_6E 0x0000106EL
1683#define BA0_AC97_VENDOR_RESERVED_70 0x00001070L
1684#define BA0_AC97_VENDOR_RESERVED_72 0x00001072L
1685#define BA0_AC97_VENDOR_RESERVED_74 0x00001074L
1686#define BA0_AC97_CAL_ADDRESS 0x00001076L
1687#define BA0_AC97_CAL_DATA 0x00001078L
1688#define BA0_AC97_VENDOR_RESERVED_7A 0x0000107AL
1689#define BA0_AC97_VENDOR_ID1 0x0000107CL
1690#define BA0_AC97_VENDOR_ID2 0x0000107EL
1691#endif /* __CS461X_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 06:02:46 -0500