diff options
| author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
| commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
| tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /sound/oss/cs4281 | |
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'sound/oss/cs4281')
| -rw-r--r-- | sound/oss/cs4281/Makefile | 6 | ||||
| -rw-r--r-- | sound/oss/cs4281/cs4281_hwdefs.h | 1234 | ||||
| -rw-r--r-- | sound/oss/cs4281/cs4281_wrapper-24.c | 41 | ||||
| -rw-r--r-- | sound/oss/cs4281/cs4281m.c | 4505 | ||||
| -rw-r--r-- | sound/oss/cs4281/cs4281pm-24.c | 84 | ||||
| -rw-r--r-- | sound/oss/cs4281/cs4281pm.h | 74 |
6 files changed, 5944 insertions, 0 deletions
diff --git a/sound/oss/cs4281/Makefile b/sound/oss/cs4281/Makefile new file mode 100644 index 000000000000..6d527e8530d6 --- /dev/null +++ b/sound/oss/cs4281/Makefile | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | # Makefile for Cirrus Logic-Crystal CS4281 | ||
| 2 | # | ||
| 3 | |||
| 4 | obj-$(CONFIG_SOUND_CS4281) += cs4281.o | ||
| 5 | |||
| 6 | cs4281-objs += cs4281m.o | ||
diff --git a/sound/oss/cs4281/cs4281_hwdefs.h b/sound/oss/cs4281/cs4281_hwdefs.h new file mode 100644 index 000000000000..701d595e33f5 --- /dev/null +++ b/sound/oss/cs4281/cs4281_hwdefs.h | |||
| @@ -0,0 +1,1234 @@ | |||
| 1 | //**************************************************************************** | ||
| 2 | // | ||
| 3 | // HWDEFS.H - Definitions of the registers and data structures used by the | ||
| 4 | // CS4281 | ||
| 5 | // | ||
| 6 | // Copyright (c) 1999,2000,2001 Crystal Semiconductor Corp. | ||
| 7 | // | ||
| 8 | //**************************************************************************** | ||
| 9 | |||
| 10 | #ifndef _H_HWDEFS | ||
| 11 | #define _H_HWDEFS | ||
| 12 | |||
| 13 | //**************************************************************************** | ||
| 14 | // | ||
| 15 | // The following define the offsets of the registers located in the PCI | ||
| 16 | // configuration space of the CS4281 part. | ||
| 17 | // | ||
| 18 | //**************************************************************************** | ||
| 19 | #define PCICONFIG_DEVID_VENID 0x00000000L | ||
| 20 | #define PCICONFIG_STATUS_COMMAND 0x00000004L | ||
| 21 | #define PCICONFIG_CLASS_REVISION 0x00000008L | ||
| 22 | #define PCICONFIG_LATENCY_TIMER 0x0000000CL | ||
| 23 | #define PCICONFIG_BA0 0x00000010L | ||
| 24 | #define PCICONFIG_BA1 0x00000014L | ||
| 25 | #define PCICONFIG_SUBSYSID_SUBSYSVENID 0x0000002CL | ||
| 26 | #define PCICONFIG_INTERRUPT 0x0000003CL | ||
| 27 | |||
| 28 | //**************************************************************************** | ||
| 29 | // | ||
| 30 | // The following define the offsets of the registers accessed via base address | ||
| 31 | // register zero on the CS4281 part. | ||
| 32 | // | ||
| 33 | //**************************************************************************** | ||
| 34 | #define BA0_HISR 0x00000000L | ||
| 35 | #define BA0_HICR 0x00000008L | ||
| 36 | #define BA0_HIMR 0x0000000CL | ||
| 37 | #define BA0_IIER 0x00000010L | ||
| 38 | #define BA0_HDSR0 0x000000F0L | ||
| 39 | #define BA0_HDSR1 0x000000F4L | ||
| 40 | #define BA0_HDSR2 0x000000F8L | ||
| 41 | #define BA0_HDSR3 0x000000FCL | ||
| 42 | #define BA0_DCA0 0x00000110L | ||
| 43 | #define BA0_DCC0 0x00000114L | ||
| 44 | #define BA0_DBA0 0x00000118L | ||
| 45 | #define BA0_DBC0 0x0000011CL | ||
| 46 | #define BA0_DCA1 0x00000120L | ||
| 47 | #define BA0_DCC1 0x00000124L | ||
| 48 | #define BA0_DBA1 0x00000128L | ||
| 49 | #define BA0_DBC1 0x0000012CL | ||
| 50 | #define BA0_DCA2 0x00000130L | ||
| 51 | #define BA0_DCC2 0x00000134L | ||
| 52 | #define BA0_DBA2 0x00000138L | ||
| 53 | #define BA0_DBC2 0x0000013CL | ||
| 54 | #define BA0_DCA3 0x00000140L | ||
| 55 | #define BA0_DCC3 0x00000144L | ||
| 56 | #define BA0_DBA3 0x00000148L | ||
| 57 | #define BA0_DBC3 0x0000014CL | ||
| 58 | #define BA0_DMR0 0x00000150L | ||
| 59 | #define BA0_DCR0 0x00000154L | ||
| 60 | #define BA0_DMR1 0x00000158L | ||
| 61 | #define BA0_DCR1 0x0000015CL | ||
| 62 | #define BA0_DMR2 0x00000160L | ||
| 63 | #define BA0_DCR2 0x00000164L | ||
| 64 | #define BA0_DMR3 0x00000168L | ||
| 65 | #define BA0_DCR3 0x0000016CL | ||
| 66 | #define BA0_DLMR 0x00000170L | ||
| 67 | #define BA0_DLSR 0x00000174L | ||
| 68 | #define BA0_FCR0 0x00000180L | ||
| 69 | #define BA0_FCR1 0x00000184L | ||
| 70 | #define BA0_FCR2 0x00000188L | ||
| 71 | #define BA0_FCR3 0x0000018CL | ||
| 72 | #define BA0_FPDR0 0x00000190L | ||
| 73 | #define BA0_FPDR1 0x00000194L | ||
| 74 | #define BA0_FPDR2 0x00000198L | ||
| 75 | #define BA0_FPDR3 0x0000019CL | ||
| 76 | #define BA0_FCHS 0x0000020CL | ||
| 77 | #define BA0_FSIC0 0x00000210L | ||
| 78 | #define BA0_FSIC1 0x00000214L | ||
| 79 | #define BA0_FSIC2 0x00000218L | ||
| 80 | #define BA0_FSIC3 0x0000021CL | ||
| 81 | #define BA0_PCICFG00 0x00000300L | ||
| 82 | #define BA0_PCICFG04 0x00000304L | ||
| 83 | #define BA0_PCICFG08 0x00000308L | ||
| 84 | #define BA0_PCICFG0C 0x0000030CL | ||
| 85 | #define BA0_PCICFG10 0x00000310L | ||
| 86 | #define BA0_PCICFG14 0x00000314L | ||
| 87 | #define BA0_PCICFG18 0x00000318L | ||
| 88 | #define BA0_PCICFG1C 0x0000031CL | ||
| 89 | #define BA0_PCICFG20 0x00000320L | ||
| 90 | #define BA0_PCICFG24 0x00000324L | ||
| 91 | #define BA0_PCICFG28 0x00000328L | ||
| 92 | #define BA0_PCICFG2C 0x0000032CL | ||
| 93 | #define BA0_PCICFG30 0x00000330L | ||
| 94 | #define BA0_PCICFG34 0x00000334L | ||
| 95 | #define BA0_PCICFG38 0x00000338L | ||
| 96 | #define BA0_PCICFG3C 0x0000033CL | ||
| 97 | #define BA0_PCICFG40 0x00000340L | ||
| 98 | #define BA0_PMCS 0x00000344L | ||
| 99 | #define BA0_CWPR 0x000003E0L | ||
| 100 | #define BA0_EPPMC 0x000003E4L | ||
| 101 | #define BA0_GPIOR 0x000003E8L | ||
| 102 | #define BA0_SPMC 0x000003ECL | ||
| 103 | #define BA0_CFLR 0x000003F0L | ||
| 104 | #define BA0_IISR 0x000003F4L | ||
| 105 | #define BA0_TMS 0x000003F8L | ||
| 106 | #define BA0_SSVID 0x000003FCL | ||
| 107 | #define BA0_CLKCR1 0x00000400L | ||
| 108 | #define BA0_FRR 0x00000410L | ||
| 109 | #define BA0_SLT12O 0x0000041CL | ||
| 110 | #define BA0_SERMC 0x00000420L | ||
| 111 | #define BA0_SERC1 0x00000428L | ||
| 112 | #define BA0_SERC2 0x0000042CL | ||
| 113 | #define BA0_SLT12M 0x0000045CL | ||
| 114 | #define BA0_ACCTL 0x00000460L | ||
| 115 | #define BA0_ACSTS 0x00000464L | ||
| 116 | #define BA0_ACOSV 0x00000468L | ||
| 117 | #define BA0_ACCAD 0x0000046CL | ||
| 118 | #define BA0_ACCDA 0x00000470L | ||
| 119 | #define BA0_ACISV 0x00000474L | ||
| 120 | #define BA0_ACSAD 0x00000478L | ||
| 121 | #define BA0_ACSDA 0x0000047CL | ||
| 122 | #define BA0_JSPT 0x00000480L | ||
| 123 | #define BA0_JSCTL 0x00000484L | ||
| 124 | #define BA0_MIDCR 0x00000490L | ||
| 125 | #define BA0_MIDCMD 0x00000494L | ||
| 126 | #define BA0_MIDSR 0x00000494L | ||
| 127 | #define BA0_MIDWP 0x00000498L | ||
| 128 | #define BA0_MIDRP 0x0000049CL | ||
| 129 | #define BA0_AODSD1 0x000004A8L | ||
| 130 | #define BA0_AODSD2 0x000004ACL | ||
| 131 | #define BA0_CFGI 0x000004B0L | ||
| 132 | #define BA0_SLT12M2 0x000004DCL | ||
| 133 | #define BA0_ACSTS2 0x000004E4L | ||
| 134 | #define BA0_ACISV2 0x000004F4L | ||
| 135 | #define BA0_ACSAD2 0x000004F8L | ||
| 136 | #define BA0_ACSDA2 0x000004FCL | ||
| 137 | #define BA0_IOTGP 0x00000500L | ||
| 138 | #define BA0_IOTSB 0x00000504L | ||
| 139 | #define BA0_IOTFM 0x00000508L | ||
| 140 | #define BA0_IOTDMA 0x0000050CL | ||
| 141 | #define BA0_IOTAC0 0x00000500L | ||
| 142 | #define BA0_IOTAC1 0x00000504L | ||
| 143 | #define BA0_IOTAC2 0x00000508L | ||
| 144 | #define BA0_IOTAC3 0x0000050CL | ||
| 145 | #define BA0_IOTPCP 0x0000052CL | ||
| 146 | #define BA0_IOTCC 0x00000530L | ||
| 147 | #define BA0_IOTCR 0x0000058CL | ||
| 148 | #define BA0_PCPRR 0x00000600L | ||
| 149 | #define BA0_PCPGR 0x00000604L | ||
| 150 | #define BA0_PCPCR 0x00000608L | ||
| 151 | #define BA0_PCPCIEN 0x00000608L | ||
| 152 | #define BA0_SBMAR 0x00000700L | ||
| 153 | #define BA0_SBMDR 0x00000704L | ||
| 154 | #define BA0_SBRR 0x00000708L | ||
| 155 | #define BA0_SBRDP 0x0000070CL | ||
| 156 | #define BA0_SBWDP 0x00000710L | ||
| 157 | #define BA0_SBWBS 0x00000710L | ||
| 158 | #define BA0_SBRBS 0x00000714L | ||
| 159 | #define BA0_FMSR 0x00000730L | ||
| 160 | #define BA0_B0AP 0x00000730L | ||
| 161 | #define BA0_FMDP 0x00000734L | ||
| 162 | #define BA0_B1AP 0x00000738L | ||
| 163 | #define BA0_B1DP 0x0000073CL | ||
| 164 | #define BA0_SSPM 0x00000740L | ||
| 165 | #define BA0_DACSR 0x00000744L | ||
| 166 | #define BA0_ADCSR 0x00000748L | ||
| 167 | #define BA0_SSCR 0x0000074CL | ||
| 168 | #define BA0_FMLVC 0x00000754L | ||
| 169 | #define BA0_FMRVC 0x00000758L | ||
| 170 | #define BA0_SRCSA 0x0000075CL | ||
| 171 | #define BA0_PPLVC 0x00000760L | ||
| 172 | #define BA0_PPRVC 0x00000764L | ||
| 173 | #define BA0_PASR 0x00000768L | ||
| 174 | #define BA0_CASR 0x0000076CL | ||
| 175 | |||
| 176 | //**************************************************************************** | ||
| 177 | // | ||
| 178 | // The following define the offsets of the AC97 shadow registers, which appear | ||
| 179 | // as a virtual extension to the base address register zero memory range. | ||
| 180 | // | ||
| 181 | //**************************************************************************** | ||
| 182 | #define AC97_REG_OFFSET_MASK 0x0000007EL | ||
| 183 | #define AC97_CODEC_NUMBER_MASK 0x00003000L | ||
| 184 | |||
| 185 | #define BA0_AC97_RESET 0x00001000L | ||
| 186 | #define BA0_AC97_MASTER_VOLUME 0x00001002L | ||
| 187 | #define BA0_AC97_HEADPHONE_VOLUME 0x00001004L | ||
| 188 | #define BA0_AC97_MASTER_VOLUME_MONO 0x00001006L | ||
| 189 | #define BA0_AC97_MASTER_TONE 0x00001008L | ||
| 190 | #define BA0_AC97_PC_BEEP_VOLUME 0x0000100AL | ||
| 191 | #define BA0_AC97_PHONE_VOLUME 0x0000100CL | ||
| 192 | #define BA0_AC97_MIC_VOLUME 0x0000100EL | ||
| 193 | #define BA0_AC97_LINE_IN_VOLUME 0x00001010L | ||
| 194 | #define BA0_AC97_CD_VOLUME 0x00001012L | ||
| 195 | #define BA0_AC97_VIDEO_VOLUME 0x00001014L | ||
| 196 | #define BA0_AC97_AUX_VOLUME 0x00001016L | ||
| 197 | #define BA0_AC97_PCM_OUT_VOLUME 0x00001018L | ||
| 198 | #define BA0_AC97_RECORD_SELECT 0x0000101AL | ||
| 199 | #define BA0_AC97_RECORD_GAIN 0x0000101CL | ||
| 200 | #define BA0_AC97_RECORD_GAIN_MIC 0x0000101EL | ||
| 201 | #define BA0_AC97_GENERAL_PURPOSE 0x00001020L | ||
| 202 | #define BA0_AC97_3D_CONTROL 0x00001022L | ||
| 203 | #define BA0_AC97_MODEM_RATE 0x00001024L | ||
| 204 | #define BA0_AC97_POWERDOWN 0x00001026L | ||
| 205 | #define BA0_AC97_EXT_AUDIO_ID 0x00001028L | ||
| 206 | #define BA0_AC97_EXT_AUDIO_POWER 0x0000102AL | ||
| 207 | #define BA0_AC97_PCM_FRONT_DAC_RATE 0x0000102CL | ||
| 208 | #define BA0_AC97_PCM_SURR_DAC_RATE 0x0000102EL | ||
| 209 | #define BA0_AC97_PCM_LFE_DAC_RATE 0x00001030L | ||
| 210 | #define BA0_AC97_PCM_LR_ADC_RATE 0x00001032L | ||
| 211 | #define BA0_AC97_MIC_ADC_RATE 0x00001034L | ||
| 212 | #define BA0_AC97_6CH_VOL_C_LFE 0x00001036L | ||
| 213 | #define BA0_AC97_6CH_VOL_SURROUND 0x00001038L | ||
| 214 | #define BA0_AC97_RESERVED_3A 0x0000103AL | ||
| 215 | #define BA0_AC97_EXT_MODEM_ID 0x0000103CL | ||
| 216 | #define BA0_AC97_EXT_MODEM_POWER 0x0000103EL | ||
| 217 | #define BA0_AC97_LINE1_CODEC_RATE 0x00001040L | ||
| 218 | #define BA0_AC97_LINE2_CODEC_RATE 0x00001042L | ||
| 219 | #define BA0_AC97_HANDSET_CODEC_RATE 0x00001044L | ||
| 220 | #define BA0_AC97_LINE1_CODEC_LEVEL 0x00001046L | ||
| 221 | #define BA0_AC97_LINE2_CODEC_LEVEL 0x00001048L | ||
| 222 | #define BA0_AC97_HANDSET_CODEC_LEVEL 0x0000104AL | ||
| 223 | #define BA0_AC97_GPIO_PIN_CONFIG 0x0000104CL | ||
| 224 | #define BA0_AC97_GPIO_PIN_TYPE 0x0000104EL | ||
| 225 | #define BA0_AC97_GPIO_PIN_STICKY 0x00001050L | ||
| 226 | #define BA0_AC97_GPIO_PIN_WAKEUP 0x00001052L | ||
| 227 | #define BA0_AC97_GPIO_PIN_STATUS 0x00001054L | ||
| 228 | #define BA0_AC97_MISC_MODEM_AFE_STAT 0x00001056L | ||
| 229 | #define BA0_AC97_RESERVED_58 0x00001058L | ||
| 230 | #define BA0_AC97_CRYSTAL_REV_N_FAB_ID 0x0000105AL | ||
| 231 | #define BA0_AC97_TEST_AND_MISC_CTRL 0x0000105CL | ||
| 232 | #define BA0_AC97_AC_MODE 0x0000105EL | ||
| 233 | #define BA0_AC97_MISC_CRYSTAL_CONTROL 0x00001060L | ||
| 234 | #define BA0_AC97_LINE1_HYPRID_CTRL 0x00001062L | ||
| 235 | #define BA0_AC97_VENDOR_RESERVED_64 0x00001064L | ||
| 236 | #define BA0_AC97_VENDOR_RESERVED_66 0x00001066L | ||
| 237 | #define BA0_AC97_SPDIF_CONTROL 0x00001068L | ||
| 238 | #define BA0_AC97_VENDOR_RESERVED_6A 0x0000106AL | ||
| 239 | #define BA0_AC97_VENDOR_RESERVED_6C 0x0000106CL | ||
| 240 | #define BA0_AC97_VENDOR_RESERVED_6E 0x0000106EL | ||
| 241 | #define BA0_AC97_VENDOR_RESERVED_70 0x00001070L | ||
| 242 | #define BA0_AC97_VENDOR_RESERVED_72 0x00001072L | ||
| 243 | #define BA0_AC97_VENDOR_RESERVED_74 0x00001074L | ||
| 244 | #define BA0_AC97_CAL_ADDRESS 0x00001076L | ||
| 245 | #define BA0_AC97_CAL_DATA 0x00001078L | ||
| 246 | #define BA0_AC97_VENDOR_RESERVED_7A 0x0000107AL | ||
| 247 | #define BA0_AC97_VENDOR_ID1 0x0000107CL | ||
| 248 | #define BA0_AC97_VENDOR_ID2 0x0000107EL | ||
| 249 | |||
| 250 | //**************************************************************************** | ||
| 251 | // | ||
| 252 | // The following define the offsets of the registers and memories accessed via | ||
| 253 | // base address register one on the CS4281 part. | ||
| 254 | // | ||
| 255 | //**************************************************************************** | ||
| 256 | |||
| 257 | //**************************************************************************** | ||
| 258 | // | ||
| 259 | // The following defines are for the flags in the PCI device ID/vendor ID | ||
| 260 | // register. | ||
| 261 | // | ||
| 262 | //**************************************************************************** | ||
| 263 | #define PDV_VENID_MASK 0x0000FFFFL | ||
| 264 | #define PDV_DEVID_MASK 0xFFFF0000L | ||
| 265 | #define PDV_VENID_SHIFT 0L | ||
| 266 | #define PDV_DEVID_SHIFT 16L | ||
| 267 | #define VENID_CIRRUS_LOGIC 0x1013L | ||
| 268 | #define DEVID_CS4281 0x6005L | ||
| 269 | |||
| 270 | //**************************************************************************** | ||
| 271 | // | ||
| 272 | // The following defines are for the flags in the PCI status and command | ||
| 273 | // register. | ||
| 274 | // | ||
| 275 | //**************************************************************************** | ||
| 276 | #define PSC_IO_SPACE_ENABLE 0x00000001L | ||
| 277 | #define PSC_MEMORY_SPACE_ENABLE 0x00000002L | ||
| 278 | #define PSC_BUS_MASTER_ENABLE 0x00000004L | ||
| 279 | #define PSC_SPECIAL_CYCLES 0x00000008L | ||
| 280 | #define PSC_MWI_ENABLE 0x00000010L | ||
| 281 | #define PSC_VGA_PALETTE_SNOOP 0x00000020L | ||
| 282 | #define PSC_PARITY_RESPONSE 0x00000040L | ||
| 283 | #define PSC_WAIT_CONTROL 0x00000080L | ||
| 284 | #define PSC_SERR_ENABLE 0x00000100L | ||
| 285 | #define PSC_FAST_B2B_ENABLE 0x00000200L | ||
| 286 | #define PSC_UDF_MASK 0x007F0000L | ||
| 287 | #define PSC_FAST_B2B_CAPABLE 0x00800000L | ||
| 288 | #define PSC_PARITY_ERROR_DETECTED 0x01000000L | ||
| 289 | #define PSC_DEVSEL_TIMING_MASK 0x06000000L | ||
| 290 | #define PSC_TARGET_ABORT_SIGNALLED 0x08000000L | ||
| 291 | #define PSC_RECEIVED_TARGET_ABORT 0x10000000L | ||
| 292 | #define PSC_RECEIVED_MASTER_ABORT 0x20000000L | ||
| 293 | #define PSC_SIGNALLED_SERR 0x40000000L | ||
| 294 | #define PSC_DETECTED_PARITY_ERROR 0x80000000L | ||
| 295 | #define PSC_UDF_SHIFT 16L | ||
| 296 | #define PSC_DEVSEL_TIMING_SHIFT 25L | ||
| 297 | |||
| 298 | //**************************************************************************** | ||
| 299 | // | ||
| 300 | // The following defines are for the flags in the PCI class/revision ID | ||
| 301 | // register. | ||
| 302 | // | ||
| 303 | //**************************************************************************** | ||
| 304 | #define PCR_REVID_MASK 0x000000FFL | ||
| 305 | #define PCR_INTERFACE_MASK 0x0000FF00L | ||
| 306 | #define PCR_SUBCLASS_MASK 0x00FF0000L | ||
| 307 | #define PCR_CLASS_MASK 0xFF000000L | ||
| 308 | #define PCR_REVID_SHIFT 0L | ||
| 309 | #define PCR_INTERFACE_SHIFT 8L | ||
| 310 | #define PCR_SUBCLASS_SHIFT 16L | ||
| 311 | #define PCR_CLASS_SHIFT 24L | ||
| 312 | |||
| 313 | //**************************************************************************** | ||
| 314 | // | ||
| 315 | // The following defines are for the flags in the PCI latency timer register. | ||
| 316 | // | ||
| 317 | //**************************************************************************** | ||
| 318 | #define PLT_CACHE_LINE_SIZE_MASK 0x000000FFL | ||
| 319 | #define PLT_LATENCY_TIMER_MASK 0x0000FF00L | ||
| 320 | #define PLT_HEADER_TYPE_MASK 0x00FF0000L | ||
| 321 | #define PLT_BIST_MASK 0xFF000000L | ||
| 322 | #define PLT_CACHE_LINE_SIZE_SHIFT 0L | ||
| 323 | #define PLT_LATENCY_TIMER_SHIFT 8L | ||
| 324 | #define PLT_HEADER_TYPE_SHIFT 16L | ||
| 325 | #define PLT_BIST_SHIFT 24L | ||
| 326 | |||
| 327 | //**************************************************************************** | ||
| 328 | // | ||
| 329 | // The following defines are for the flags in the PCI base address registers. | ||
| 330 | // | ||
| 331 | //**************************************************************************** | ||
| 332 | #define PBAR_MEMORY_SPACE_INDICATOR 0x00000001L | ||
| 333 | #define PBAR_LOCATION_TYPE_MASK 0x00000006L | ||
| 334 | #define PBAR_NOT_PREFETCHABLE 0x00000008L | ||
| 335 | #define PBAR_ADDRESS_MASK 0xFFFFFFF0L | ||
| 336 | #define PBAR_LOCATION_TYPE_SHIFT 1L | ||
| 337 | |||
| 338 | //**************************************************************************** | ||
| 339 | // | ||
| 340 | // The following defines are for the flags in the PCI subsystem ID/subsystem | ||
| 341 | // vendor ID register. | ||
| 342 | // | ||
| 343 | //**************************************************************************** | ||
| 344 | #define PSS_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL | ||
| 345 | #define PSS_SUBSYSTEM_ID_MASK 0xFFFF0000L | ||
| 346 | #define PSS_SUBSYSTEM_VENDOR_ID_SHIFT 0L | ||
| 347 | #define PSS_SUBSYSTEM_ID_SHIFT 16L | ||
| 348 | |||
| 349 | //**************************************************************************** | ||
| 350 | // | ||
| 351 | // The following defines are for the flags in the PCI interrupt register. | ||
| 352 | // | ||
| 353 | //**************************************************************************** | ||
| 354 | #define PI_LINE_MASK 0x000000FFL | ||
| 355 | #define PI_PIN_MASK 0x0000FF00L | ||
| 356 | #define PI_MIN_GRANT_MASK 0x00FF0000L | ||
| 357 | #define PI_MAX_LATENCY_MASK 0xFF000000L | ||
| 358 | #define PI_LINE_SHIFT 0L | ||
| 359 | #define PI_PIN_SHIFT 8L | ||
| 360 | #define PI_MIN_GRANT_SHIFT 16L | ||
| 361 | #define PI_MAX_LATENCY_SHIFT 24L | ||
| 362 | |||
| 363 | //**************************************************************************** | ||
| 364 | // | ||
| 365 | // The following defines are for the flags in the host interrupt status | ||
| 366 | // register. | ||
| 367 | // | ||
| 368 | //**************************************************************************** | ||
| 369 | #define HISR_HVOLMASK 0x00000003L | ||
| 370 | #define HISR_VDNI 0x00000001L | ||
| 371 | #define HISR_VUPI 0x00000002L | ||
| 372 | #define HISR_GP1I 0x00000004L | ||
| 373 | #define HISR_GP3I 0x00000008L | ||
| 374 | #define HISR_GPSI 0x00000010L | ||
| 375 | #define HISR_GPPI 0x00000020L | ||
| 376 | #define HISR_DMAI 0x00040000L | ||
| 377 | #define HISR_FIFOI 0x00100000L | ||
| 378 | #define HISR_HVOL 0x00200000L | ||
| 379 | #define HISR_MIDI 0x00400000L | ||
| 380 | #define HISR_SBINT 0x00800000L | ||
| 381 | #define HISR_INTENA 0x80000000L | ||
| 382 | #define HISR_DMA_MASK 0x00000F00L | ||
| 383 | #define HISR_FIFO_MASK 0x0000F000L | ||
| 384 | #define HISR_DMA_SHIFT 8L | ||
| 385 | #define HISR_FIFO_SHIFT 12L | ||
| 386 | #define HISR_FIFO0 0x00001000L | ||
| 387 | #define HISR_FIFO1 0x00002000L | ||
| 388 | #define HISR_FIFO2 0x00004000L | ||
| 389 | #define HISR_FIFO3 0x00008000L | ||
| 390 | #define HISR_DMA0 0x00000100L | ||
| 391 | #define HISR_DMA1 0x00000200L | ||
| 392 | #define HISR_DMA2 0x00000400L | ||
| 393 | #define HISR_DMA3 0x00000800L | ||
| 394 | #define HISR_RESERVED 0x40000000L | ||
| 395 | |||
| 396 | //**************************************************************************** | ||
| 397 | // | ||
| 398 | // The following defines are for the flags in the host interrupt control | ||
| 399 | // register. | ||
| 400 | // | ||
| 401 | //**************************************************************************** | ||
| 402 | #define HICR_IEV 0x00000001L | ||
| 403 | #define HICR_CHGM 0x00000002L | ||
| 404 | |||
| 405 | //**************************************************************************** | ||
| 406 | // | ||
| 407 | // The following defines are for the flags in the DMA Mode Register n | ||
| 408 | // (DMRn) | ||
| 409 | // | ||
| 410 | //**************************************************************************** | ||
| 411 | #define DMRn_TR_MASK 0x0000000CL | ||
| 412 | #define DMRn_TR_SHIFT 2L | ||
| 413 | #define DMRn_AUTO 0x00000010L | ||
| 414 | #define DMRn_TR_READ 0x00000008L | ||
| 415 | #define DMRn_TR_WRITE 0x00000004L | ||
| 416 | #define DMRn_TYPE_MASK 0x000000C0L | ||
| 417 | #define DMRn_TYPE_SHIFT 6L | ||
| 418 | #define DMRn_SIZE8 0x00010000L | ||
| 419 | #define DMRn_MONO 0x00020000L | ||
| 420 | #define DMRn_BEND 0x00040000L | ||
| 421 | #define DMRn_USIGN 0x00080000L | ||
| 422 | #define DMRn_SIZE20 0x00100000L | ||
| 423 | #define DMRn_SWAPC 0x00400000L | ||
| 424 | #define DMRn_CBC 0x01000000L | ||
| 425 | #define DMRn_TBC 0x02000000L | ||
| 426 | #define DMRn_POLL 0x10000000L | ||
| 427 | #define DMRn_DMA 0x20000000L | ||
| 428 | #define DMRn_FSEL_MASK 0xC0000000L | ||
| 429 | #define DMRn_FSEL_SHIFT 30L | ||
| 430 | #define DMRn_FSEL0 0x00000000L | ||
| 431 | #define DMRn_FSEL1 0x40000000L | ||
| 432 | #define DMRn_FSEL2 0x80000000L | ||
| 433 | #define DMRn_FSEL3 0xC0000000L | ||
| 434 | |||
| 435 | //**************************************************************************** | ||
| 436 | // | ||
| 437 | // The following defines are for the flags in the DMA Command Register n | ||
| 438 | // (DCRn) | ||
| 439 | // | ||
| 440 | //**************************************************************************** | ||
| 441 | #define DCRn_HTCIE 0x00020000L | ||
| 442 | #define DCRn_TCIE 0x00010000L | ||
| 443 | #define DCRn_MSK 0x00000001L | ||
| 444 | |||
| 445 | //**************************************************************************** | ||
| 446 | // | ||
| 447 | // The following defines are for the flags in the FIFO Control | ||
| 448 | // register n.(FCRn) | ||
| 449 | // | ||
| 450 | //**************************************************************************** | ||
| 451 | #define FCRn_OF_MASK 0x0000007FL | ||
| 452 | #define FCRn_OF_SHIFT 0L | ||
| 453 | #define FCRn_SZ_MASK 0x00007F00L | ||
| 454 | #define FCRn_SZ_SHIFT 8L | ||
| 455 | #define FCRn_LS_MASK 0x001F0000L | ||
| 456 | #define FCRn_LS_SHIFT 16L | ||
| 457 | #define FCRn_RS_MASK 0x1F000000L | ||
| 458 | #define FCRn_RS_SHIFT 24L | ||
| 459 | #define FCRn_FEN 0x80000000L | ||
| 460 | #define FCRn_PSH 0x20000000L | ||
| 461 | #define FCRn_DACZ 0x40000000L | ||
| 462 | |||
| 463 | //**************************************************************************** | ||
| 464 | // | ||
| 465 | // The following defines are for the flags in the serial port Power Management | ||
| 466 | // control register.(SPMC) | ||
| 467 | // | ||
| 468 | //**************************************************************************** | ||
| 469 | #define SPMC_RSTN 0x00000001L | ||
| 470 | #define SPMC_ASYN 0x00000002L | ||
| 471 | #define SPMC_WUP1 0x00000004L | ||
| 472 | #define SPMC_WUP2 0x00000008L | ||
| 473 | #define SPMC_ASDI2E 0x00000100L | ||
| 474 | #define SPMC_ESSPD 0x00000200L | ||
| 475 | #define SPMC_GISPEN 0x00004000L | ||
| 476 | #define SPMC_GIPPEN 0x00008000L | ||
| 477 | |||
| 478 | //**************************************************************************** | ||
| 479 | // | ||
| 480 | // The following defines are for the flags in the Configuration Load register. | ||
| 481 | // (CFLR) | ||
| 482 | // | ||
| 483 | //**************************************************************************** | ||
| 484 | #define CFLR_CLOCK_SOURCE_MASK 0x00000003L | ||
| 485 | #define CFLR_CLOCK_SOURCE_AC97 0x00000001L | ||
| 486 | |||
| 487 | #define CFLR_CB0_MASK 0x000000FFL | ||
| 488 | #define CFLR_CB1_MASK 0x0000FF00L | ||
| 489 | #define CFLR_CB2_MASK 0x00FF0000L | ||
| 490 | #define CFLR_CB3_MASK 0xFF000000L | ||
| 491 | #define CFLR_CB0_SHIFT 0L | ||
| 492 | #define CFLR_CB1_SHIFT 8L | ||
| 493 | #define CFLR_CB2_SHIFT 16L | ||
| 494 | #define CFLR_CB3_SHIFT 24L | ||
| 495 | |||
| 496 | #define IOTCR_DMA0 0x00000000L | ||
| 497 | #define IOTCR_DMA1 0x00000400L | ||
| 498 | #define IOTCR_DMA2 0x00000800L | ||
| 499 | #define IOTCR_DMA3 0x00000C00L | ||
| 500 | #define IOTCR_CCLS 0x00000100L | ||
| 501 | #define IOTCR_PCPCI 0x00000200L | ||
| 502 | #define IOTCR_DDMA 0x00000300L | ||
| 503 | |||
| 504 | #define SBWBS_WBB 0x00000080L | ||
| 505 | |||
| 506 | //**************************************************************************** | ||
| 507 | // | ||
| 508 | // The following defines are for the flags in the SRC Slot Assignment Register | ||
| 509 | // (SRCSA) | ||
| 510 | // | ||
| 511 | //**************************************************************************** | ||
| 512 | #define SRCSA_PLSS_MASK 0x0000001FL | ||
| 513 | #define SRCSA_PLSS_SHIFT 0L | ||
| 514 | #define SRCSA_PRSS_MASK 0x00001F00L | ||
| 515 | #define SRCSA_PRSS_SHIFT 8L | ||
| 516 | #define SRCSA_CLSS_MASK 0x001F0000L | ||
| 517 | #define SRCSA_CLSS_SHIFT 16L | ||
| 518 | #define SRCSA_CRSS_MASK 0x1F000000L | ||
| 519 | #define SRCSA_CRSS_SHIFT 24L | ||
| 520 | |||
| 521 | //**************************************************************************** | ||
| 522 | // | ||
| 523 | // The following defines are for the flags in the Sound System Power Management | ||
| 524 | // register.(SSPM) | ||
| 525 | // | ||
| 526 | //**************************************************************************** | ||
| 527 | #define SSPM_FPDN 0x00000080L | ||
| 528 | #define SSPM_MIXEN 0x00000040L | ||
| 529 | #define SSPM_CSRCEN 0x00000020L | ||
| 530 | #define SSPM_PSRCEN 0x00000010L | ||
| 531 | #define SSPM_JSEN 0x00000008L | ||
| 532 | #define SSPM_ACLEN 0x00000004L | ||
| 533 | #define SSPM_FMEN 0x00000002L | ||
| 534 | |||
| 535 | //**************************************************************************** | ||
| 536 | // | ||
| 537 | // The following defines are for the flags in the Sound System Control | ||
| 538 | // Register. (SSCR) | ||
| 539 | // | ||
| 540 | //**************************************************************************** | ||
| 541 | #define SSCR_SB 0x00000004L | ||
| 542 | #define SSCR_HVC 0x00000008L | ||
| 543 | #define SSCR_LPFIFO 0x00000040L | ||
| 544 | #define SSCR_LPSRC 0x00000080L | ||
| 545 | #define SSCR_XLPSRC 0x00000100L | ||
| 546 | #define SSCR_MVMD 0x00010000L | ||
| 547 | #define SSCR_MVAD 0x00020000L | ||
| 548 | #define SSCR_MVLD 0x00040000L | ||
| 549 | #define SSCR_MVCS 0x00080000L | ||
| 550 | |||
| 551 | //**************************************************************************** | ||
| 552 | // | ||
| 553 | // The following defines are for the flags in the Clock Control Register 1. | ||
| 554 | // (CLKCR1) | ||
| 555 | // | ||
| 556 | //**************************************************************************** | ||
| 557 | #define CLKCR1_DLLSS_MASK 0x0000000CL | ||
| 558 | #define CLKCR1_DLLSS_SHIFT 2L | ||
| 559 | #define CLKCR1_DLLP 0x00000010L | ||
| 560 | #define CLKCR1_SWCE 0x00000020L | ||
| 561 | #define CLKCR1_DLLOS 0x00000040L | ||
| 562 | #define CLKCR1_CKRA 0x00010000L | ||
| 563 | #define CLKCR1_CKRN 0x00020000L | ||
| 564 | #define CLKCR1_DLLRDY 0x01000000L | ||
| 565 | #define CLKCR1_CLKON 0x02000000L | ||
| 566 | |||
| 567 | //**************************************************************************** | ||
| 568 | // | ||
| 569 | // The following defines are for the flags in the Sound Blaster Read Buffer | ||
| 570 | // Status.(SBRBS) | ||
| 571 | // | ||
| 572 | //**************************************************************************** | ||
| 573 | #define SBRBS_RD_MASK 0x0000007FL | ||
| 574 | #define SBRBS_RD_SHIFT 0L | ||
| 575 | #define SBRBS_RBF 0x00000080L | ||
| 576 | |||
| 577 | //**************************************************************************** | ||
| 578 | // | ||
| 579 | // The following defines are for the flags in the serial port master control | ||
| 580 | // register.(SERMC) | ||
| 581 | // | ||
| 582 | //**************************************************************************** | ||
| 583 | #define SERMC_MSPE 0x00000001L | ||
| 584 | #define SERMC_PTC_MASK 0x0000000EL | ||
| 585 | #define SERMC_PTC_SHIFT 1L | ||
| 586 | #define SERMC_PTC_AC97 0x00000002L | ||
| 587 | #define SERMC_PLB 0x00000010L | ||
| 588 | #define SERMC_PXLB 0x00000020L | ||
| 589 | #define SERMC_LOFV 0x00080000L | ||
| 590 | #define SERMC_SLB 0x00100000L | ||
| 591 | #define SERMC_SXLB 0x00200000L | ||
| 592 | #define SERMC_ODSEN1 0x01000000L | ||
| 593 | #define SERMC_ODSEN2 0x02000000L | ||
| 594 | |||
| 595 | //**************************************************************************** | ||
| 596 | // | ||
| 597 | // The following defines are for the flags in the General Purpose I/O Register. | ||
| 598 | // (GPIOR) | ||
| 599 | // | ||
| 600 | //**************************************************************************** | ||
| 601 | #define GPIOR_VDNS 0x00000001L | ||
| 602 | #define GPIOR_VUPS 0x00000002L | ||
| 603 | #define GPIOR_GP1S 0x00000004L | ||
| 604 | #define GPIOR_GP3S 0x00000008L | ||
| 605 | #define GPIOR_GPSS 0x00000010L | ||
| 606 | #define GPIOR_GPPS 0x00000020L | ||
| 607 | #define GPIOR_GP1D 0x00000400L | ||
| 608 | #define GPIOR_GP3D 0x00000800L | ||
| 609 | #define GPIOR_VDNLT 0x00010000L | ||
| 610 | #define GPIOR_VDNPO 0x00020000L | ||
| 611 | #define GPIOR_VDNST 0x00040000L | ||
| 612 | #define GPIOR_VDNW 0x00080000L | ||
| 613 | #define GPIOR_VUPLT 0x00100000L | ||
| 614 | #define GPIOR_VUPPO 0x00200000L | ||
| 615 | #define GPIOR_VUPST 0x00400000L | ||
| 616 | #define GPIOR_VUPW 0x00800000L | ||
| 617 | #define GPIOR_GP1OE 0x01000000L | ||
| 618 | #define GPIOR_GP1PT 0x02000000L | ||
| 619 | #define GPIOR_GP1ST 0x04000000L | ||
| 620 | #define GPIOR_GP1W 0x08000000L | ||
| 621 | #define GPIOR_GP3OE 0x10000000L | ||
| 622 | #define GPIOR_GP3PT 0x20000000L | ||
| 623 | #define GPIOR_GP3ST 0x40000000L | ||
| 624 | #define GPIOR_GP3W 0x80000000L | ||
| 625 | |||
| 626 | //**************************************************************************** | ||
| 627 | // | ||
| 628 | // The following defines are for the flags in the clock control register 1. | ||
| 629 | // | ||
| 630 | //**************************************************************************** | ||
| 631 | #define CLKCR1_PLLSS_MASK 0x0000000CL | ||
| 632 | #define CLKCR1_PLLSS_SERIAL 0x00000000L | ||
| 633 | #define CLKCR1_PLLSS_CRYSTAL 0x00000004L | ||
| 634 | #define CLKCR1_PLLSS_PCI 0x00000008L | ||
| 635 | #define CLKCR1_PLLSS_RESERVED 0x0000000CL | ||
| 636 | #define CLKCR1_PLLP 0x00000010L | ||
| 637 | #define CLKCR1_SWCE 0x00000020L | ||
| 638 | #define CLKCR1_PLLOS 0x00000040L | ||
| 639 | |||
| 640 | //**************************************************************************** | ||
| 641 | // | ||
| 642 | // The following defines are for the flags in the feature reporting register. | ||
| 643 | // | ||
| 644 | //**************************************************************************** | ||
| 645 | #define FRR_FAB_MASK 0x00000003L | ||
| 646 | #define FRR_MASK_MASK 0x0000001CL | ||
| 647 | #define FRR_ID_MASK 0x00003000L | ||
| 648 | #define FRR_FAB_SHIFT 0L | ||
| 649 | #define FRR_MASK_SHIFT 2L | ||
| 650 | #define FRR_ID_SHIFT 12L | ||
| 651 | |||
| 652 | //**************************************************************************** | ||
| 653 | // | ||
| 654 | // The following defines are for the flags in the serial port 1 configuration | ||
| 655 | // register. | ||
| 656 | // | ||
| 657 | //**************************************************************************** | ||
| 658 | #define SERC1_VALUE 0x00000003L | ||
| 659 | #define SERC1_SO1EN 0x00000001L | ||
| 660 | #define SERC1_SO1F_MASK 0x0000000EL | ||
| 661 | #define SERC1_SO1F_CS423X 0x00000000L | ||
| 662 | #define SERC1_SO1F_AC97 0x00000002L | ||
| 663 | #define SERC1_SO1F_DAC 0x00000004L | ||
| 664 | #define SERC1_SO1F_SPDIF 0x00000006L | ||
| 665 | |||
| 666 | //**************************************************************************** | ||
| 667 | // | ||
| 668 | // The following defines are for the flags in the serial port 2 configuration | ||
| 669 | // register. | ||
| 670 | // | ||
| 671 | //**************************************************************************** | ||
| 672 | #define SERC2_VALUE 0x00000003L | ||
| 673 | #define SERC2_SI1EN 0x00000001L | ||
| 674 | #define SERC2_SI1F_MASK 0x0000000EL | ||
| 675 | #define SERC2_SI1F_CS423X 0x00000000L | ||
| 676 | #define SERC2_SI1F_AC97 0x00000002L | ||
| 677 | #define SERC2_SI1F_ADC 0x00000004L | ||
| 678 | #define SERC2_SI1F_SPDIF 0x00000006L | ||
| 679 | |||
| 680 | //**************************************************************************** | ||
| 681 | // | ||
| 682 | // The following defines are for the flags in the AC97 control register. | ||
| 683 | // | ||
| 684 | //**************************************************************************** | ||
| 685 | #define ACCTL_ESYN 0x00000002L | ||
| 686 | #define ACCTL_VFRM 0x00000004L | ||
| 687 | #define ACCTL_DCV 0x00000008L | ||
| 688 | #define ACCTL_CRW 0x00000010L | ||
| 689 | #define ACCTL_TC 0x00000040L | ||
| 690 | |||
| 691 | //**************************************************************************** | ||
| 692 | // | ||
| 693 | // The following defines are for the flags in the AC97 status register. | ||
| 694 | // | ||
| 695 | //**************************************************************************** | ||
| 696 | #define ACSTS_CRDY 0x00000001L | ||
| 697 | #define ACSTS_VSTS 0x00000002L | ||
| 698 | |||
| 699 | //**************************************************************************** | ||
| 700 | // | ||
| 701 | // The following defines are for the flags in the AC97 output slot valid | ||
| 702 | // register. | ||
| 703 | // | ||
| 704 | //**************************************************************************** | ||
| 705 | #define ACOSV_SLV3 0x00000001L | ||
| 706 | #define ACOSV_SLV4 0x00000002L | ||
| 707 | #define ACOSV_SLV5 0x00000004L | ||
| 708 | #define ACOSV_SLV6 0x00000008L | ||
| 709 | #define ACOSV_SLV7 0x00000010L | ||
| 710 | #define ACOSV_SLV8 0x00000020L | ||
| 711 | #define ACOSV_SLV9 0x00000040L | ||
| 712 | #define ACOSV_SLV10 0x00000080L | ||
| 713 | #define ACOSV_SLV11 0x00000100L | ||
| 714 | #define ACOSV_SLV12 0x00000200L | ||
| 715 | |||
| 716 | //**************************************************************************** | ||
| 717 | // | ||
| 718 | // The following defines are for the flags in the AC97 command address | ||
| 719 | // register. | ||
| 720 | // | ||
| 721 | //**************************************************************************** | ||
| 722 | #define ACCAD_CI_MASK 0x0000007FL | ||
| 723 | #define ACCAD_CI_SHIFT 0L | ||
| 724 | |||
| 725 | //**************************************************************************** | ||
| 726 | // | ||
| 727 | // The following defines are for the flags in the AC97 command data register. | ||
| 728 | // | ||
| 729 | //**************************************************************************** | ||
| 730 | #define ACCDA_CD_MASK 0x0000FFFFL | ||
| 731 | #define ACCDA_CD_SHIFT 0L | ||
| 732 | |||
| 733 | //**************************************************************************** | ||
| 734 | // | ||
| 735 | // The following defines are for the flags in the AC97 input slot valid | ||
| 736 | // register. | ||
| 737 | // | ||
| 738 | //**************************************************************************** | ||
| 739 | #define ACISV_ISV3 0x00000001L | ||
| 740 | #define ACISV_ISV4 0x00000002L | ||
| 741 | #define ACISV_ISV5 0x00000004L | ||
| 742 | #define ACISV_ISV6 0x00000008L | ||
| 743 | #define ACISV_ISV7 0x00000010L | ||
| 744 | #define ACISV_ISV8 0x00000020L | ||
| 745 | #define ACISV_ISV9 0x00000040L | ||
| 746 | #define ACISV_ISV10 0x00000080L | ||
| 747 | #define ACISV_ISV11 0x00000100L | ||
| 748 | #define ACISV_ISV12 0x00000200L | ||
| 749 | |||
| 750 | //**************************************************************************** | ||
| 751 | // | ||
| 752 | // The following defines are for the flags in the AC97 status address | ||
| 753 | // register. | ||
| 754 | // | ||
| 755 | //**************************************************************************** | ||
| 756 | #define ACSAD_SI_MASK 0x0000007FL | ||
| 757 | #define ACSAD_SI_SHIFT 0L | ||
| 758 | |||
| 759 | //**************************************************************************** | ||
| 760 | // | ||
| 761 | // The following defines are for the flags in the AC97 status data register. | ||
| 762 | // | ||
| 763 | //**************************************************************************** | ||
| 764 | #define ACSDA_SD_MASK 0x0000FFFFL | ||
| 765 | #define ACSDA_SD_SHIFT 0L | ||
| 766 | |||
| 767 | //**************************************************************************** | ||
| 768 | // | ||
| 769 | // The following defines are for the flags in the I/O trap address and control | ||
| 770 | // registers (all 12). | ||
| 771 | // | ||
| 772 | //**************************************************************************** | ||
| 773 | #define IOTAC_SA_MASK 0x0000FFFFL | ||
| 774 | #define IOTAC_MSK_MASK 0x000F0000L | ||
| 775 | #define IOTAC_IODC_MASK 0x06000000L | ||
| 776 | #define IOTAC_IODC_16_BIT 0x00000000L | ||
| 777 | #define IOTAC_IODC_10_BIT 0x02000000L | ||
| 778 | #define IOTAC_IODC_12_BIT 0x04000000L | ||
| 779 | #define IOTAC_WSPI 0x08000000L | ||
| 780 | #define IOTAC_RSPI 0x10000000L | ||
| 781 | #define IOTAC_WSE 0x20000000L | ||
| 782 | #define IOTAC_WE 0x40000000L | ||
| 783 | #define IOTAC_RE 0x80000000L | ||
| 784 | #define IOTAC_SA_SHIFT 0L | ||
| 785 | #define IOTAC_MSK_SHIFT 16L | ||
| 786 | |||
| 787 | //**************************************************************************** | ||
| 788 | // | ||
| 789 | // The following defines are for the flags in the PC/PCI master enable | ||
| 790 | // register. | ||
| 791 | // | ||
| 792 | //**************************************************************************** | ||
| 793 | #define PCPCIEN_EN 0x00000001L | ||
| 794 | |||
| 795 | //**************************************************************************** | ||
| 796 | // | ||
| 797 | // The following defines are for the flags in the joystick poll/trigger | ||
| 798 | // register. | ||
| 799 | // | ||
| 800 | //**************************************************************************** | ||
| 801 | #define JSPT_CAX 0x00000001L | ||
| 802 | #define JSPT_CAY 0x00000002L | ||
| 803 | #define JSPT_CBX 0x00000004L | ||
| 804 | #define JSPT_CBY 0x00000008L | ||
| 805 | #define JSPT_BA1 0x00000010L | ||
| 806 | #define JSPT_BA2 0x00000020L | ||
| 807 | #define JSPT_BB1 0x00000040L | ||
| 808 | #define JSPT_BB2 0x00000080L | ||
| 809 | |||
| 810 | //**************************************************************************** | ||
| 811 | // | ||
| 812 | // The following defines are for the flags in the joystick control register. | ||
| 813 | // The TBF bit has been moved from MIDSR register to JSCTL register bit 8. | ||
| 814 | // | ||
| 815 | //**************************************************************************** | ||
| 816 | #define JSCTL_SP_MASK 0x00000003L | ||
| 817 | #define JSCTL_SP_SLOW 0x00000000L | ||
| 818 | #define JSCTL_SP_MEDIUM_SLOW 0x00000001L | ||
| 819 | #define JSCTL_SP_MEDIUM_FAST 0x00000002L | ||
| 820 | #define JSCTL_SP_FAST 0x00000003L | ||
| 821 | #define JSCTL_ARE 0x00000004L | ||
| 822 | #define JSCTL_TBF 0x00000100L | ||
| 823 | |||
| 824 | |||
| 825 | //**************************************************************************** | ||
| 826 | // | ||
| 827 | // The following defines are for the flags in the MIDI control register. | ||
| 828 | // | ||
| 829 | //**************************************************************************** | ||
| 830 | #define MIDCR_TXE 0x00000001L | ||
| 831 | #define MIDCR_RXE 0x00000002L | ||
| 832 | #define MIDCR_RIE 0x00000004L | ||
| 833 | #define MIDCR_TIE 0x00000008L | ||
| 834 | #define MIDCR_MLB 0x00000010L | ||
| 835 | #define MIDCR_MRST 0x00000020L | ||
| 836 | |||
| 837 | //**************************************************************************** | ||
| 838 | // | ||
| 839 | // The following defines are for the flags in the MIDI status register. | ||
| 840 | // | ||
| 841 | //**************************************************************************** | ||
| 842 | #define MIDSR_RBE 0x00000080L | ||
| 843 | #define MIDSR_RDA 0x00008000L | ||
| 844 | |||
| 845 | //**************************************************************************** | ||
| 846 | // | ||
| 847 | // The following defines are for the flags in the MIDI write port register. | ||
| 848 | // | ||
| 849 | //**************************************************************************** | ||
| 850 | #define MIDWP_MWD_MASK 0x000000FFL | ||
| 851 | #define MIDWP_MWD_SHIFT 0L | ||
| 852 | |||
| 853 | //**************************************************************************** | ||
| 854 | // | ||
| 855 | // The following defines are for the flags in the MIDI read port register. | ||
| 856 | // | ||
| 857 | //**************************************************************************** | ||
| 858 | #define MIDRP_MRD_MASK 0x000000FFL | ||
| 859 | #define MIDRP_MRD_SHIFT 0L | ||
| 860 | |||
| 861 | //**************************************************************************** | ||
| 862 | // | ||
| 863 | // The following defines are for the flags in the configuration interface | ||
| 864 | // register. | ||
| 865 | // | ||
| 866 | //**************************************************************************** | ||
| 867 | #define CFGI_CLK 0x00000001L | ||
| 868 | #define CFGI_DOUT 0x00000002L | ||
| 869 | #define CFGI_DIN_EEN 0x00000004L | ||
| 870 | #define CFGI_EELD 0x00000008L | ||
| 871 | |||
| 872 | //**************************************************************************** | ||
| 873 | // | ||
| 874 | // The following defines are for the flags in the subsystem ID and vendor ID | ||
| 875 | // register. | ||
| 876 | // | ||
| 877 | //**************************************************************************** | ||
| 878 | #define SSVID_VID_MASK 0x0000FFFFL | ||
| 879 | #define SSVID_SID_MASK 0xFFFF0000L | ||
| 880 | #define SSVID_VID_SHIFT 0L | ||
| 881 | #define SSVID_SID_SHIFT 16L | ||
| 882 | |||
| 883 | //**************************************************************************** | ||
| 884 | // | ||
| 885 | // The following defines are for the flags in the GPIO pin interface register. | ||
| 886 | // | ||
| 887 | //**************************************************************************** | ||
| 888 | #define GPIOR_VOLDN 0x00000001L | ||
| 889 | #define GPIOR_VOLUP 0x00000002L | ||
| 890 | #define GPIOR_SI2D 0x00000004L | ||
| 891 | #define GPIOR_SI2OE 0x00000008L | ||
| 892 | |||
| 893 | //**************************************************************************** | ||
| 894 | // | ||
| 895 | // The following defines are for the flags in the AC97 status register 2. | ||
| 896 | // | ||
| 897 | //**************************************************************************** | ||
| 898 | #define ACSTS2_CRDY 0x00000001L | ||
| 899 | #define ACSTS2_VSTS 0x00000002L | ||
| 900 | |||
| 901 | //**************************************************************************** | ||
| 902 | // | ||
| 903 | // The following defines are for the flags in the AC97 input slot valid | ||
| 904 | // register 2. | ||
| 905 | // | ||
| 906 | //**************************************************************************** | ||
| 907 | #define ACISV2_ISV3 0x00000001L | ||
| 908 | #define ACISV2_ISV4 0x00000002L | ||
| 909 | #define ACISV2_ISV5 0x00000004L | ||
| 910 | #define ACISV2_ISV6 0x00000008L | ||
| 911 | #define ACISV2_ISV7 0x00000010L | ||
| 912 | #define ACISV2_ISV8 0x00000020L | ||
| 913 | #define ACISV2_ISV9 0x00000040L | ||
| 914 | #define ACISV2_ISV10 0x00000080L | ||
| 915 | #define ACISV2_ISV11 0x00000100L | ||
| 916 | #define ACISV2_ISV12 0x00000200L | ||
| 917 | |||
| 918 | //**************************************************************************** | ||
| 919 | // | ||
| 920 | // The following defines are for the flags in the AC97 status address | ||
| 921 | // register 2. | ||
| 922 | // | ||
| 923 | //**************************************************************************** | ||
| 924 | #define ACSAD2_SI_MASK 0x0000007FL | ||
| 925 | #define ACSAD2_SI_SHIFT 0L | ||
| 926 | |||
| 927 | //**************************************************************************** | ||
| 928 | // | ||
| 929 | // The following defines are for the flags in the AC97 status data register 2. | ||
| 930 | // | ||
| 931 | //**************************************************************************** | ||
| 932 | #define ACSDA2_SD_MASK 0x0000FFFFL | ||
| 933 | #define ACSDA2_SD_SHIFT 0L | ||
| 934 | |||
| 935 | //**************************************************************************** | ||
| 936 | // | ||
| 937 | // The following defines are for the flags in the I/O trap control register. | ||
| 938 | // | ||
| 939 | //**************************************************************************** | ||
| 940 | #define IOTCR_ITD 0x00000001L | ||
| 941 | #define IOTCR_HRV 0x00000002L | ||
| 942 | #define IOTCR_SRV 0x00000004L | ||
| 943 | #define IOTCR_DTI 0x00000008L | ||
| 944 | #define IOTCR_DFI 0x00000010L | ||
| 945 | #define IOTCR_DDP 0x00000020L | ||
| 946 | #define IOTCR_JTE 0x00000040L | ||
| 947 | #define IOTCR_PPE 0x00000080L | ||
| 948 | |||
| 949 | //**************************************************************************** | ||
| 950 | // | ||
| 951 | // The following defines are for the flags in the I/O trap address and control | ||
| 952 | // registers for Hardware Master Volume. | ||
| 953 | // | ||
| 954 | //**************************************************************************** | ||
| 955 | #define IOTGP_SA_MASK 0x0000FFFFL | ||
| 956 | #define IOTGP_MSK_MASK 0x000F0000L | ||
| 957 | #define IOTGP_IODC_MASK 0x06000000L | ||
| 958 | #define IOTGP_IODC_16_BIT 0x00000000L | ||
| 959 | #define IOTGP_IODC_10_BIT 0x02000000L | ||
| 960 | #define IOTGP_IODC_12_BIT 0x04000000L | ||
| 961 | #define IOTGP_WSPI 0x08000000L | ||
| 962 | #define IOTGP_RSPI 0x10000000L | ||
| 963 | #define IOTGP_WSE 0x20000000L | ||
| 964 | #define IOTGP_WE 0x40000000L | ||
| 965 | #define IOTGP_RE 0x80000000L | ||
| 966 | #define IOTGP_SA_SHIFT 0L | ||
| 967 | #define IOTGP_MSK_SHIFT 16L | ||
| 968 | |||
| 969 | //**************************************************************************** | ||
| 970 | // | ||
| 971 | // The following defines are for the flags in the I/O trap address and control | ||
| 972 | // registers for Sound Blaster | ||
| 973 | // | ||
| 974 | //**************************************************************************** | ||
| 975 | #define IOTSB_SA_MASK 0x0000FFFFL | ||
| 976 | #define IOTSB_MSK_MASK 0x000F0000L | ||
| 977 | #define IOTSB_IODC_MASK 0x06000000L | ||
| 978 | #define IOTSB_IODC_16_BIT 0x00000000L | ||
| 979 | #define IOTSB_IODC_10_BIT 0x02000000L | ||
| 980 | #define IOTSB_IODC_12_BIT 0x04000000L | ||
| 981 | #define IOTSB_WSPI 0x08000000L | ||
| 982 | #define IOTSB_RSPI 0x10000000L | ||
| 983 | #define IOTSB_WSE 0x20000000L | ||
| 984 | #define IOTSB_WE 0x40000000L | ||
| 985 | #define IOTSB_RE 0x80000000L | ||
| 986 | #define IOTSB_SA_SHIFT 0L | ||
| 987 | #define IOTSB_MSK_SHIFT 16L | ||
| 988 | |||
| 989 | //**************************************************************************** | ||
| 990 | // | ||
| 991 | // The following defines are for the flags in the I/O trap address and control | ||
| 992 | // registers for FM. | ||
| 993 | // | ||
| 994 | //**************************************************************************** | ||
| 995 | #define IOTFM_SA_MASK 0x0000FFFFL | ||
| 996 | #define IOTFM_MSK_MASK 0x000F0000L | ||
| 997 | #define IOTFM_IODC_MASK 0x06000000L | ||
| 998 | #define IOTFM_IODC_16_BIT 0x00000000L | ||
| 999 | #define IOTFM_IODC_10_BIT 0x02000000L | ||
| 1000 | #define IOTFM_IODC_12_BIT 0x04000000L | ||
| 1001 | #define IOTFM_WSPI 0x08000000L | ||
| 1002 | #define IOTFM_RSPI 0x10000000L | ||
| 1003 | #define IOTFM_WSE 0x20000000L | ||
| 1004 | #define IOTFM_WE 0x40000000L | ||
| 1005 | #define IOTFM_RE 0x80000000L | ||
| 1006 | #define IOTFM_SA_SHIFT 0L | ||
| 1007 | #define IOTFM_MSK_SHIFT 16L | ||
| 1008 | |||
| 1009 | //**************************************************************************** | ||
| 1010 | // | ||
| 1011 | // The following defines are for the flags in the PC/PCI request register. | ||
| 1012 | // | ||
| 1013 | //**************************************************************************** | ||
| 1014 | #define PCPRR_RDC_MASK 0x00000007L | ||
| 1015 | #define PCPRR_REQ 0x00008000L | ||
| 1016 | #define PCPRR_RDC_SHIFT 0L | ||
| 1017 | |||
| 1018 | //**************************************************************************** | ||
| 1019 | // | ||
| 1020 | // The following defines are for the flags in the PC/PCI grant register. | ||
| 1021 | // | ||
| 1022 | //**************************************************************************** | ||
| 1023 | #define PCPGR_GDC_MASK 0x00000007L | ||
| 1024 | #define PCPGR_VL 0x00008000L | ||
| 1025 | #define PCPGR_GDC_SHIFT 0L | ||
| 1026 | |||
| 1027 | //**************************************************************************** | ||
| 1028 | // | ||
| 1029 | // The following defines are for the flags in the PC/PCI Control Register. | ||
| 1030 | // | ||
| 1031 | //**************************************************************************** | ||
| 1032 | #define PCPCR_EN 0x00000001L | ||
| 1033 | |||
| 1034 | //**************************************************************************** | ||
| 1035 | // | ||
| 1036 | // The following defines are for the flags in the debug index register. | ||
| 1037 | // | ||
| 1038 | //**************************************************************************** | ||
| 1039 | #define DREG_REGID_MASK 0x0000007FL | ||
| 1040 | #define DREG_DEBUG 0x00000080L | ||
| 1041 | #define DREG_RGBK_MASK 0x00000700L | ||
| 1042 | #define DREG_TRAP 0x00000800L | ||
| 1043 | #if !defined(NO_CS4612) | ||
| 1044 | #if !defined(NO_CS4615) | ||
| 1045 | #define DREG_TRAPX 0x00001000L | ||
| 1046 | #endif | ||
| 1047 | #endif | ||
| 1048 | #define DREG_REGID_SHIFT 0L | ||
| 1049 | #define DREG_RGBK_SHIFT 8L | ||
| 1050 | #define DREG_RGBK_REGID_MASK 0x0000077FL | ||
| 1051 | #define DREG_REGID_R0 0x00000010L | ||
| 1052 | #define DREG_REGID_R1 0x00000011L | ||
| 1053 | #define DREG_REGID_R2 0x00000012L | ||
| 1054 | #define DREG_REGID_R3 0x00000013L | ||
| 1055 | #define DREG_REGID_R4 0x00000014L | ||
| 1056 | #define DREG_REGID_R5 0x00000015L | ||
| 1057 | #define DREG_REGID_R6 0x00000016L | ||
| 1058 | #define DREG_REGID_R7 0x00000017L | ||
| 1059 | #define DREG_REGID_R8 0x00000018L | ||
| 1060 | #define DREG_REGID_R9 0x00000019L | ||
| 1061 | #define DREG_REGID_RA 0x0000001AL | ||
| 1062 | #define DREG_REGID_RB 0x0000001BL | ||
| 1063 | #define DREG_REGID_RC 0x0000001CL | ||
| 1064 | #define DREG_REGID_RD 0x0000001DL | ||
| 1065 | #define DREG_REGID_RE 0x0000001EL | ||
| 1066 | #define DREG_REGID_RF 0x0000001FL | ||
| 1067 | #define DREG_REGID_RA_BUS_LOW 0x00000020L | ||
| 1068 | #define DREG_REGID_RA_BUS_HIGH 0x00000038L | ||
| 1069 | #define DREG_REGID_YBUS_LOW 0x00000050L | ||
| 1070 | #define DREG_REGID_YBUS_HIGH 0x00000058L | ||
| 1071 | #define DREG_REGID_TRAP_0 0x00000100L | ||
| 1072 | #define DREG_REGID_TRAP_1 0x00000101L | ||
| 1073 | #define DREG_REGID_TRAP_2 0x00000102L | ||
| 1074 | #define DREG_REGID_TRAP_3 0x00000103L | ||
| 1075 | #define DREG_REGID_TRAP_4 0x00000104L | ||
| 1076 | #define DREG_REGID_TRAP_5 0x00000105L | ||
| 1077 | #define DREG_REGID_TRAP_6 0x00000106L | ||
| 1078 | #define DREG_REGID_TRAP_7 0x00000107L | ||
| 1079 | #define DREG_REGID_INDIRECT_ADDRESS 0x0000010EL | ||
| 1080 | #define DREG_REGID_TOP_OF_STACK 0x0000010FL | ||
| 1081 | #if !defined(NO_CS4612) | ||
| 1082 | #if !defined(NO_CS4615) | ||
| 1083 | #define DREG_REGID_TRAP_8 0x00000110L | ||
| 1084 | #define DREG_REGID_TRAP_9 0x00000111L | ||
| 1085 | #define DREG_REGID_TRAP_10 0x00000112L | ||
| 1086 | #define DREG_REGID_TRAP_11 0x00000113L | ||
| 1087 | #define DREG_REGID_TRAP_12 0x00000114L | ||
| 1088 | #define DREG_REGID_TRAP_13 0x00000115L | ||
| 1089 | #define DREG_REGID_TRAP_14 0x00000116L | ||
| 1090 | #define DREG_REGID_TRAP_15 0x00000117L | ||
| 1091 | #define DREG_REGID_TRAP_16 0x00000118L | ||
| 1092 | #define DREG_REGID_TRAP_17 0x00000119L | ||
| 1093 | #define DREG_REGID_TRAP_18 0x0000011AL | ||
| 1094 | #define DREG_REGID_TRAP_19 0x0000011BL | ||
| 1095 | #define DREG_REGID_TRAP_20 0x0000011CL | ||
| 1096 | #define DREG_REGID_TRAP_21 0x0000011DL | ||
| 1097 | #define DREG_REGID_TRAP_22 0x0000011EL | ||
| 1098 | #define DREG_REGID_TRAP_23 0x0000011FL | ||
| 1099 | #endif | ||
| 1100 | #endif | ||
| 1101 | #define DREG_REGID_RSA0_LOW 0x00000200L | ||
| 1102 | #define DREG_REGID_RSA0_HIGH 0x00000201L | ||
| 1103 | #define DREG_REGID_RSA1_LOW 0x00000202L | ||
| 1104 | #define DREG_REGID_RSA1_HIGH 0x00000203L | ||
| 1105 | #define DREG_REGID_RSA2 0x00000204L | ||
| 1106 | #define DREG_REGID_RSA3 0x00000205L | ||
| 1107 | #define DREG_REGID_RSI0_LOW 0x00000206L | ||
| 1108 | #define DREG_REGID_RSI0_HIGH 0x00000207L | ||
| 1109 | #define DREG_REGID_RSI1 0x00000208L | ||
| 1110 | #define DREG_REGID_RSI2 0x00000209L | ||
| 1111 | #define DREG_REGID_SAGUSTATUS 0x0000020AL | ||
| 1112 | #define DREG_REGID_RSCONFIG01_LOW 0x0000020BL | ||
| 1113 | #define DREG_REGID_RSCONFIG01_HIGH 0x0000020CL | ||
| 1114 | #define DREG_REGID_RSCONFIG23_LOW 0x0000020DL | ||
| 1115 | #define DREG_REGID_RSCONFIG23_HIGH 0x0000020EL | ||
| 1116 | #define DREG_REGID_RSDMA01E 0x0000020FL | ||
| 1117 | #define DREG_REGID_RSDMA23E 0x00000210L | ||
| 1118 | #define DREG_REGID_RSD0_LOW 0x00000211L | ||
| 1119 | #define DREG_REGID_RSD0_HIGH 0x00000212L | ||
| 1120 | #define DREG_REGID_RSD1_LOW 0x00000213L | ||
| 1121 | #define DREG_REGID_RSD1_HIGH 0x00000214L | ||
| 1122 | #define DREG_REGID_RSD2_LOW 0x00000215L | ||
| 1123 | #define DREG_REGID_RSD2_HIGH 0x00000216L | ||
| 1124 | #define DREG_REGID_RSD3_LOW 0x00000217L | ||
| 1125 | #define DREG_REGID_RSD3_HIGH 0x00000218L | ||
| 1126 | #define DREG_REGID_SRAR_HIGH 0x0000021AL | ||
| 1127 | #define DREG_REGID_SRAR_LOW 0x0000021BL | ||
| 1128 | #define DREG_REGID_DMA_STATE 0x0000021CL | ||
| 1129 | #define DREG_REGID_CURRENT_DMA_STREAM 0x0000021DL | ||
| 1130 | #define DREG_REGID_NEXT_DMA_STREAM 0x0000021EL | ||
| 1131 | #define DREG_REGID_CPU_STATUS 0x00000300L | ||
| 1132 | #define DREG_REGID_MAC_MODE 0x00000301L | ||
| 1133 | #define DREG_REGID_STACK_AND_REPEAT 0x00000302L | ||
| 1134 | #define DREG_REGID_INDEX0 0x00000304L | ||
| 1135 | #define DREG_REGID_INDEX1 0x00000305L | ||
| 1136 | #define DREG_REGID_DMA_STATE_0_3 0x00000400L | ||
| 1137 | #define DREG_REGID_DMA_STATE_4_7 0x00000404L | ||
| 1138 | #define DREG_REGID_DMA_STATE_8_11 0x00000408L | ||
| 1139 | #define DREG_REGID_DMA_STATE_12_15 0x0000040CL | ||
| 1140 | #define DREG_REGID_DMA_STATE_16_19 0x00000410L | ||
| 1141 | #define DREG_REGID_DMA_STATE_20_23 0x00000414L | ||
| 1142 | #define DREG_REGID_DMA_STATE_24_27 0x00000418L | ||
| 1143 | #define DREG_REGID_DMA_STATE_28_31 0x0000041CL | ||
| 1144 | #define DREG_REGID_DMA_STATE_32_35 0x00000420L | ||
| 1145 | #define DREG_REGID_DMA_STATE_36_39 0x00000424L | ||
| 1146 | #define DREG_REGID_DMA_STATE_40_43 0x00000428L | ||
| 1147 | #define DREG_REGID_DMA_STATE_44_47 0x0000042CL | ||
| 1148 | #define DREG_REGID_DMA_STATE_48_51 0x00000430L | ||
| 1149 | #define DREG_REGID_DMA_STATE_52_55 0x00000434L | ||
| 1150 | #define DREG_REGID_DMA_STATE_56_59 0x00000438L | ||
| 1151 | #define DREG_REGID_DMA_STATE_60_63 0x0000043CL | ||
| 1152 | #define DREG_REGID_DMA_STATE_64_67 0x00000440L | ||
| 1153 | #define DREG_REGID_DMA_STATE_68_71 0x00000444L | ||
| 1154 | #define DREG_REGID_DMA_STATE_72_75 0x00000448L | ||
| 1155 | #define DREG_REGID_DMA_STATE_76_79 0x0000044CL | ||
| 1156 | #define DREG_REGID_DMA_STATE_80_83 0x00000450L | ||
| 1157 | #define DREG_REGID_DMA_STATE_84_87 0x00000454L | ||
| 1158 | #define DREG_REGID_DMA_STATE_88_91 0x00000458L | ||
| 1159 | #define DREG_REGID_DMA_STATE_92_95 0x0000045CL | ||
| 1160 | #define DREG_REGID_TRAP_SELECT 0x00000500L | ||
| 1161 | #define DREG_REGID_TRAP_WRITE_0 0x00000500L | ||
| 1162 | #define DREG_REGID_TRAP_WRITE_1 0x00000501L | ||
| 1163 | #define DREG_REGID_TRAP_WRITE_2 0x00000502L | ||
| 1164 | #define DREG_REGID_TRAP_WRITE_3 0x00000503L | ||
| 1165 | #define DREG_REGID_TRAP_WRITE_4 0x00000504L | ||
| 1166 | #define DREG_REGID_TRAP_WRITE_5 0x00000505L | ||
| 1167 | #define DREG_REGID_TRAP_WRITE_6 0x00000506L | ||
| 1168 | #define DREG_REGID_TRAP_WRITE_7 0x00000507L | ||
| 1169 | #if !defined(NO_CS4612) | ||
| 1170 | #if !defined(NO_CS4615) | ||
| 1171 | #define DREG_REGID_TRAP_WRITE_8 0x00000510L | ||
| 1172 | #define DREG_REGID_TRAP_WRITE_9 0x00000511L | ||
| 1173 | #define DREG_REGID_TRAP_WRITE_10 0x00000512L | ||
| 1174 | #define DREG_REGID_TRAP_WRITE_11 0x00000513L | ||
| 1175 | #define DREG_REGID_TRAP_WRITE_12 0x00000514L | ||
| 1176 | #define DREG_REGID_TRAP_WRITE_13 0x00000515L | ||
| 1177 | #define DREG_REGID_TRAP_WRITE_14 0x00000516L | ||
| 1178 | #define DREG_REGID_TRAP_WRITE_15 0x00000517L | ||
| 1179 | #define DREG_REGID_TRAP_WRITE_16 0x00000518L | ||
| 1180 | #define DREG_REGID_TRAP_WRITE_17 0x00000519L | ||
| 1181 | #define DREG_REGID_TRAP_WRITE_18 0x0000051AL | ||
| 1182 | #define DREG_REGID_TRAP_WRITE_19 0x0000051BL | ||
| 1183 | #define DREG_REGID_TRAP_WRITE_20 0x0000051CL | ||
| 1184 | #define DREG_REGID_TRAP_WRITE_21 0x0000051DL | ||
| 1185 | #define DREG_REGID_TRAP_WRITE_22 0x0000051EL | ||
| 1186 | #define DREG_REGID_TRAP_WRITE_23 0x0000051FL | ||
| 1187 | #endif | ||
| 1188 | #endif | ||
| 1189 | #define DREG_REGID_MAC0_ACC0_LOW 0x00000600L | ||
| 1190 | #define DREG_REGID_MAC0_ACC1_LOW 0x00000601L | ||
| 1191 | #define DREG_REGID_MAC0_ACC2_LOW 0x00000602L | ||
| 1192 | #define DREG_REGID_MAC0_ACC3_LOW 0x00000603L | ||
| 1193 | #define DREG_REGID_MAC1_ACC0_LOW 0x00000604L | ||
| 1194 | #define DREG_REGID_MAC1_ACC1_LOW 0x00000605L | ||
| 1195 | #define DREG_REGID_MAC1_ACC2_LOW 0x00000606L | ||
| 1196 | #define DREG_REGID_MAC1_ACC3_LOW 0x00000607L | ||
| 1197 | #define DREG_REGID_MAC0_ACC0_MID 0x00000608L | ||
| 1198 | #define DREG_REGID_MAC0_ACC1_MID 0x00000609L | ||
| 1199 | #define DREG_REGID_MAC0_ACC2_MID 0x0000060AL | ||
| 1200 | #define DREG_REGID_MAC0_ACC3_MID 0x0000060BL | ||
| 1201 | #define DREG_REGID_MAC1_ACC0_MID 0x0000060CL | ||
| 1202 | #define DREG_REGID_MAC1_ACC1_MID 0x0000060DL | ||
| 1203 | #define DREG_REGID_MAC1_ACC2_MID 0x0000060EL | ||
| 1204 | #define DREG_REGID_MAC1_ACC3_MID 0x0000060FL | ||
| 1205 | #define DREG_REGID_MAC0_ACC0_HIGH 0x00000610L | ||
| 1206 | #define DREG_REGID_MAC0_ACC1_HIGH 0x00000611L | ||
| 1207 | #define DREG_REGID_MAC0_ACC2_HIGH 0x00000612L | ||
| 1208 | #define DREG_REGID_MAC0_ACC3_HIGH 0x00000613L | ||
| 1209 | #define DREG_REGID_MAC1_ACC0_HIGH 0x00000614L | ||
| 1210 | #define DREG_REGID_MAC1_ACC1_HIGH 0x00000615L | ||
| 1211 | #define DREG_REGID_MAC1_ACC2_HIGH 0x00000616L | ||
| 1212 | #define DREG_REGID_MAC1_ACC3_HIGH 0x00000617L | ||
| 1213 | #define DREG_REGID_RSHOUT_LOW 0x00000620L | ||
| 1214 | #define DREG_REGID_RSHOUT_MID 0x00000628L | ||
| 1215 | #define DREG_REGID_RSHOUT_HIGH 0x00000630L | ||
| 1216 | |||
| 1217 | //**************************************************************************** | ||
| 1218 | // | ||
| 1219 | // The following defines are for the flags in the AC97 S/PDIF Control register. | ||
| 1220 | // | ||
| 1221 | //**************************************************************************** | ||
| 1222 | #define SPDIF_CONTROL_SPDIF_EN 0x00008000L | ||
| 1223 | #define SPDIF_CONTROL_VAL 0x00004000L | ||
| 1224 | #define SPDIF_CONTROL_COPY 0x00000004L | ||
| 1225 | #define SPDIF_CONTROL_CC0 0x00000010L | ||
| 1226 | #define SPDIF_CONTROL_CC1 0x00000020L | ||
| 1227 | #define SPDIF_CONTROL_CC2 0x00000040L | ||
| 1228 | #define SPDIF_CONTROL_CC3 0x00000080L | ||
| 1229 | #define SPDIF_CONTROL_CC4 0x00000100L | ||
| 1230 | #define SPDIF_CONTROL_CC5 0x00000200L | ||
| 1231 | #define SPDIF_CONTROL_CC6 0x00000400L | ||
| 1232 | #define SPDIF_CONTROL_L 0x00000800L | ||
| 1233 | |||
| 1234 | #endif // _H_HWDEFS | ||
diff --git a/sound/oss/cs4281/cs4281_wrapper-24.c b/sound/oss/cs4281/cs4281_wrapper-24.c new file mode 100644 index 000000000000..4559f02c9969 --- /dev/null +++ b/sound/oss/cs4281/cs4281_wrapper-24.c | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /******************************************************************************* | ||
| 2 | * | ||
| 3 | * "cs4281_wrapper.c" -- Cirrus Logic-Crystal CS4281 linux audio driver. | ||
| 4 | * | ||
| 5 | * Copyright (C) 2000,2001 Cirrus Logic Corp. | ||
| 6 | * -- tom woller (twoller@crystal.cirrus.com) or | ||
| 7 | * (audio@crystal.cirrus.com). | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this program; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 22 | * | ||
| 23 | * 12/20/00 trw - new file. | ||
| 24 | * | ||
| 25 | *******************************************************************************/ | ||
| 26 | |||
| 27 | #include <linux/spinlock.h> | ||
| 28 | |||
| 29 | static int cs4281_resume_null(struct pci_dev *pcidev) { return 0; } | ||
| 30 | static int cs4281_suspend_null(struct pci_dev *pcidev, pm_message_t state) { return 0; } | ||
| 31 | |||
| 32 | #define free_dmabuf(state, dmabuf) \ | ||
| 33 | pci_free_consistent(state->pcidev, \ | ||
| 34 | PAGE_SIZE << (dmabuf)->buforder, \ | ||
| 35 | (dmabuf)->rawbuf, (dmabuf)->dmaaddr); | ||
| 36 | #define free_dmabuf2(state, dmabuf) \ | ||
| 37 | pci_free_consistent((state)->pcidev, \ | ||
| 38 | PAGE_SIZE << (state)->buforder_tmpbuff, \ | ||
| 39 | (state)->tmpbuff, (state)->dmaaddr_tmpbuff); | ||
| 40 | #define cs4x_pgoff(vma) ((vma)->vm_pgoff) | ||
| 41 | |||
diff --git a/sound/oss/cs4281/cs4281m.c b/sound/oss/cs4281/cs4281m.c new file mode 100644 index 000000000000..d0d3963e1b83 --- /dev/null +++ b/sound/oss/cs4281/cs4281m.c | |||
| @@ -0,0 +1,4505 @@ | |||
| 1 | /******************************************************************************* | ||
| 2 | * | ||
| 3 | * "cs4281.c" -- Cirrus Logic-Crystal CS4281 linux audio driver. | ||
| 4 | * | ||
| 5 | * Copyright (C) 2000,2001 Cirrus Logic Corp. | ||
| 6 | * -- adapted from drivers by Thomas Sailer, | ||
| 7 | * -- but don't bug him; Problems should go to: | ||
| 8 | * -- tom woller (twoller@crystal.cirrus.com) or | ||
| 9 | * (audio@crystal.cirrus.com). | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License as published by | ||
| 13 | * the Free Software Foundation; either version 2 of the License, or | ||
| 14 | * (at your option) any later version. | ||
| 15 | * | ||
| 16 | * This program is distributed in the hope that it will be useful, | ||
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 19 | * GNU General Public License for more details. | ||
| 20 | * | ||
| 21 | * You should have received a copy of the GNU General Public License | ||
| 22 | * along with this program; if not, write to the Free Software | ||
| 23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 24 | * | ||
| 25 | * Module command line parameters: | ||
| 26 | * none | ||
| 27 | * | ||
| 28 | * Supported devices: | ||
| 29 | * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible | ||
| 30 | * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible | ||
| 31 | * /dev/midi simple MIDI UART interface, no ioctl | ||
| 32 | * | ||
| 33 | * Modification History | ||
| 34 | * 08/20/00 trw - silence and no stopping DAC until release | ||
| 35 | * 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop. | ||
| 36 | * 09/18/00 trw - added 16bit only record with conversion | ||
| 37 | * 09/24/00 trw - added Enhanced Full duplex (separate simultaneous | ||
| 38 | * capture/playback rates) | ||
| 39 | * 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin | ||
| 40 | * libOSSm.so) | ||
| 41 | * 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal) | ||
| 42 | * 11/03/00 trw - fixed interrupt loss/stutter, added debug. | ||
| 43 | * 11/10/00 bkz - added __devinit to cs4281_hw_init() | ||
| 44 | * 11/10/00 trw - fixed SMP and capture spinlock hang. | ||
| 45 | * 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm. | ||
| 46 | * 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix. | ||
| 47 | * 12/08/00 trw - added PM support. | ||
| 48 | * 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8 | ||
| 49 | * (RH/Dell base), 2.2.18, 2.2.12. cleaned up code mods by ident. | ||
| 50 | * 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup. | ||
| 51 | * 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use | ||
| 52 | * defaultorder-100 as power of 2 for the buffer size. example: | ||
| 53 | * 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size. | ||
| 54 | * | ||
| 55 | *******************************************************************************/ | ||
| 56 | |||
| 57 | /* uncomment the following line to disable building PM support into the driver */ | ||
| 58 | //#define NOT_CS4281_PM 1 | ||
| 59 | |||
| 60 | #include <linux/list.h> | ||
| 61 | #include <linux/module.h> | ||
| 62 | #include <linux/string.h> | ||
| 63 | #include <linux/ioport.h> | ||
| 64 | #include <linux/sched.h> | ||
| 65 | #include <linux/delay.h> | ||
| 66 | #include <linux/sound.h> | ||
| 67 | #include <linux/slab.h> | ||
| 68 | #include <linux/soundcard.h> | ||
| 69 | #include <linux/pci.h> | ||
| 70 | #include <linux/bitops.h> | ||
| 71 | #include <linux/init.h> | ||
| 72 | #include <linux/interrupt.h> | ||
| 73 | #include <linux/poll.h> | ||
| 74 | #include <linux/fs.h> | ||
| 75 | #include <linux/wait.h> | ||
| 76 | |||
| 77 | #include <asm/current.h> | ||
| 78 | #include <asm/io.h> | ||
| 79 | #include <asm/dma.h> | ||
| 80 | #include <asm/page.h> | ||
| 81 | #include <asm/uaccess.h> | ||
| 82 | |||
| 83 | //#include "cs_dm.h" | ||
| 84 | #include "cs4281_hwdefs.h" | ||
| 85 | #include "cs4281pm.h" | ||
| 86 | |||
| 87 | struct cs4281_state; | ||
| 88 | |||
| 89 | static void stop_dac(struct cs4281_state *s); | ||
| 90 | static void stop_adc(struct cs4281_state *s); | ||
| 91 | static void start_dac(struct cs4281_state *s); | ||
| 92 | static void start_adc(struct cs4281_state *s); | ||
| 93 | #undef OSS_DOCUMENTED_MIXER_SEMANTICS | ||
| 94 | |||
| 95 | // --------------------------------------------------------------------- | ||
| 96 | |||
| 97 | #ifndef PCI_VENDOR_ID_CIRRUS | ||
| 98 | #define PCI_VENDOR_ID_CIRRUS 0x1013 | ||
| 99 | #endif | ||
| 100 | #ifndef PCI_DEVICE_ID_CRYSTAL_CS4281 | ||
| 101 | #define PCI_DEVICE_ID_CRYSTAL_CS4281 0x6005 | ||
| 102 | #endif | ||
| 103 | |||
| 104 | #define CS4281_MAGIC ((PCI_DEVICE_ID_CRYSTAL_CS4281<<16) | PCI_VENDOR_ID_CIRRUS) | ||
| 105 | #define CS4281_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */ | ||
| 106 | |||
| 107 | // buffer order determines the size of the dma buffer for the driver. | ||
| 108 | // under Linux, a smaller buffer allows more responsiveness from many of the | ||
| 109 | // applications (e.g. games). A larger buffer allows some of the apps (esound) | ||
| 110 | // to not underrun the dma buffer as easily. As default, use 32k (order=3) | ||
| 111 | // rather than 64k as some of the games work more responsively. | ||
| 112 | // log base 2( buff sz = 32k). | ||
| 113 | static unsigned long defaultorder = 3; | ||
| 114 | module_param(defaultorder, ulong, 0); | ||
| 115 | |||
| 116 | // | ||
| 117 | // Turn on/off debugging compilation by commenting out "#define CSDEBUG" | ||
| 118 | // | ||
| 119 | #define CSDEBUG 1 | ||
| 120 | #if CSDEBUG | ||
| 121 | #define CSDEBUG_INTERFACE 1 | ||
| 122 | #else | ||
| 123 | #undef CSDEBUG_INTERFACE | ||
| 124 | #endif | ||
| 125 | // | ||
| 126 | // cs_debugmask areas | ||
| 127 | // | ||
| 128 | #define CS_INIT 0x00000001 // initialization and probe functions | ||
| 129 | #define CS_ERROR 0x00000002 // tmp debugging bit placeholder | ||
| 130 | #define CS_INTERRUPT 0x00000004 // interrupt handler (separate from all other) | ||
| 131 | #define CS_FUNCTION 0x00000008 // enter/leave functions | ||
| 132 | #define CS_WAVE_WRITE 0x00000010 // write information for wave | ||
| 133 | #define CS_WAVE_READ 0x00000020 // read information for wave | ||
| 134 | #define CS_MIDI_WRITE 0x00000040 // write information for midi | ||
| 135 | #define CS_MIDI_READ 0x00000080 // read information for midi | ||
| 136 | #define CS_MPU401_WRITE 0x00000100 // write information for mpu401 | ||
| 137 | #define CS_MPU401_READ 0x00000200 // read information for mpu401 | ||
| 138 | #define CS_OPEN 0x00000400 // all open functions in the driver | ||
| 139 | #define CS_RELEASE 0x00000800 // all release functions in the driver | ||
| 140 | #define CS_PARMS 0x00001000 // functional and operational parameters | ||
| 141 | #define CS_IOCTL 0x00002000 // ioctl (non-mixer) | ||
| 142 | #define CS_PM 0x00004000 // power management | ||
| 143 | #define CS_TMP 0x10000000 // tmp debug mask bit | ||
| 144 | |||
| 145 | #define CS_IOCTL_CMD_SUSPEND 0x1 // suspend | ||
| 146 | #define CS_IOCTL_CMD_RESUME 0x2 // resume | ||
| 147 | // | ||
| 148 | // CSDEBUG is usual mode is set to 1, then use the | ||
| 149 | // cs_debuglevel and cs_debugmask to turn on or off debugging. | ||
| 150 | // Debug level of 1 has been defined to be kernel errors and info | ||
| 151 | // that should be printed on any released driver. | ||
| 152 | // | ||
| 153 | #if CSDEBUG | ||
| 154 | #define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;} | ||
| 155 | #else | ||
| 156 | #define CS_DBGOUT(mask,level,x) | ||
| 157 | #endif | ||
| 158 | |||
| 159 | #if CSDEBUG | ||
| 160 | static unsigned long cs_debuglevel = 1; // levels range from 1-9 | ||
| 161 | static unsigned long cs_debugmask = CS_INIT | CS_ERROR; // use CS_DBGOUT with various mask values | ||
| 162 | module_param(cs_debuglevel, ulong, 0); | ||
| 163 | module_param(cs_debugmask, ulong, 0); | ||
| 164 | #endif | ||
| 165 | #define CS_TRUE 1 | ||
| 166 | #define CS_FALSE 0 | ||
| 167 | |||
| 168 | // MIDI buffer sizes | ||
| 169 | #define MIDIINBUF 500 | ||
| 170 | #define MIDIOUTBUF 500 | ||
| 171 | |||
| 172 | #define FMODE_MIDI_SHIFT 3 | ||
| 173 | #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT) | ||
| 174 | #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT) | ||
| 175 | |||
| 176 | #define CS4281_MAJOR_VERSION 1 | ||
| 177 | #define CS4281_MINOR_VERSION 13 | ||
| 178 | #ifdef __ia64__ | ||
| 179 | #define CS4281_ARCH 64 //architecture key | ||
| 180 | #else | ||
| 181 | #define CS4281_ARCH 32 //architecture key | ||
| 182 | #endif | ||
| 183 | |||
| 184 | #define CS_TYPE_ADC 0 | ||
| 185 | #define CS_TYPE_DAC 1 | ||
| 186 | |||
| 187 | |||
| 188 | static const char invalid_magic[] = | ||
| 189 | KERN_CRIT "cs4281: invalid magic value\n"; | ||
| 190 | |||
| 191 | #define VALIDATE_STATE(s) \ | ||
| 192 | ({ \ | ||
| 193 | if (!(s) || (s)->magic != CS4281_MAGIC) { \ | ||
| 194 | printk(invalid_magic); \ | ||
| 195 | return -ENXIO; \ | ||
| 196 | } \ | ||
| 197 | }) | ||
| 198 | |||
| 199 | //LIST_HEAD(cs4281_devs); | ||
| 200 | static struct list_head cs4281_devs = { &cs4281_devs, &cs4281_devs }; | ||
| 201 | |||
| 202 | struct cs4281_state; | ||
| 203 | |||
| 204 | #include "cs4281_wrapper-24.c" | ||
| 205 | |||
| 206 | struct cs4281_state { | ||
| 207 | // magic | ||
| 208 | unsigned int magic; | ||
| 209 | |||
| 210 | // we keep the cards in a linked list | ||
| 211 | struct cs4281_state *next; | ||
| 212 | |||
| 213 | // pcidev is needed to turn off the DDMA controller at driver shutdown | ||
| 214 | struct pci_dev *pcidev; | ||
| 215 | struct list_head list; | ||
| 216 | |||
| 217 | // soundcore stuff | ||
| 218 | int dev_audio; | ||
| 219 | int dev_mixer; | ||
| 220 | int dev_midi; | ||
| 221 | |||
| 222 | // hardware resources | ||
| 223 | unsigned int pBA0phys, pBA1phys; | ||
| 224 | char __iomem *pBA0; | ||
| 225 | char __iomem *pBA1; | ||
| 226 | unsigned int irq; | ||
| 227 | |||
| 228 | // mixer registers | ||
| 229 | struct { | ||
| 230 | unsigned short vol[10]; | ||
| 231 | unsigned int recsrc; | ||
| 232 | unsigned int modcnt; | ||
| 233 | unsigned short micpreamp; | ||
| 234 | } mix; | ||
| 235 | |||
| 236 | // wave stuff | ||
| 237 | struct properties { | ||
| 238 | unsigned fmt; | ||
| 239 | unsigned fmt_original; // original requested format | ||
| 240 | unsigned channels; | ||
| 241 | unsigned rate; | ||
| 242 | unsigned char clkdiv; | ||
| 243 | } prop_dac, prop_adc; | ||
| 244 | unsigned conversion:1; // conversion from 16 to 8 bit in progress | ||
| 245 | void *tmpbuff; // tmp buffer for sample conversions | ||
| 246 | unsigned ena; | ||
| 247 | spinlock_t lock; | ||
| 248 | struct semaphore open_sem; | ||
| 249 | struct semaphore open_sem_adc; | ||
| 250 | struct semaphore open_sem_dac; | ||
| 251 | mode_t open_mode; | ||
| 252 | wait_queue_head_t open_wait; | ||
| 253 | wait_queue_head_t open_wait_adc; | ||
| 254 | wait_queue_head_t open_wait_dac; | ||
| 255 | |||
| 256 | dma_addr_t dmaaddr_tmpbuff; | ||
| 257 | unsigned buforder_tmpbuff; // Log base 2 of 'rawbuf' size in bytes.. | ||
| 258 | struct dmabuf { | ||
| 259 | void *rawbuf; // Physical address of | ||
| 260 | dma_addr_t dmaaddr; | ||
| 261 | unsigned buforder; // Log base 2 of 'rawbuf' size in bytes.. | ||
| 262 | unsigned numfrag; // # of 'fragments' in the buffer. | ||
| 263 | unsigned fragshift; // Log base 2 of fragment size. | ||
| 264 | unsigned hwptr, swptr; | ||
| 265 | unsigned total_bytes; // # bytes process since open. | ||
| 266 | unsigned blocks; // last returned blocks value GETOPTR | ||
| 267 | unsigned wakeup; // interrupt occurred on block | ||
| 268 | int count; | ||
| 269 | unsigned underrun; // underrun flag | ||
| 270 | unsigned error; // over/underrun | ||
| 271 | wait_queue_head_t wait; | ||
| 272 | // redundant, but makes calculations easier | ||
| 273 | unsigned fragsize; // 2**fragshift.. | ||
| 274 | unsigned dmasize; // 2**buforder. | ||
| 275 | unsigned fragsamples; | ||
| 276 | // OSS stuff | ||
| 277 | unsigned mapped:1; // Buffer mapped in cs4281_mmap()? | ||
| 278 | unsigned ready:1; // prog_dmabuf_dac()/adc() successful? | ||
| 279 | unsigned endcleared:1; | ||
| 280 | unsigned type:1; // adc or dac buffer (CS_TYPE_XXX) | ||
| 281 | unsigned ossfragshift; | ||
| 282 | int ossmaxfrags; | ||
| 283 | unsigned subdivision; | ||
| 284 | } dma_dac, dma_adc; | ||
| 285 | |||
| 286 | // midi stuff | ||
| 287 | struct { | ||
| 288 | unsigned ird, iwr, icnt; | ||
| 289 | unsigned ord, owr, ocnt; | ||
| 290 | wait_queue_head_t iwait; | ||
| 291 | wait_queue_head_t owait; | ||
| 292 | struct timer_list timer; | ||
| 293 | unsigned char ibuf[MIDIINBUF]; | ||
| 294 | unsigned char obuf[MIDIOUTBUF]; | ||
| 295 | } midi; | ||
| 296 | |||
| 297 | struct cs4281_pm pm; | ||
| 298 | struct cs4281_pipeline pl[CS4281_NUMBER_OF_PIPELINES]; | ||
| 299 | }; | ||
| 300 | |||
| 301 | #include "cs4281pm-24.c" | ||
| 302 | |||
| 303 | #if CSDEBUG | ||
| 304 | |||
| 305 | // DEBUG ROUTINES | ||
| 306 | |||
| 307 | #define SOUND_MIXER_CS_GETDBGLEVEL _SIOWR('M',120, int) | ||
| 308 | #define SOUND_MIXER_CS_SETDBGLEVEL _SIOWR('M',121, int) | ||
| 309 | #define SOUND_MIXER_CS_GETDBGMASK _SIOWR('M',122, int) | ||
| 310 | #define SOUND_MIXER_CS_SETDBGMASK _SIOWR('M',123, int) | ||
| 311 | |||
| 312 | #define SOUND_MIXER_CS_APM _SIOWR('M',124, int) | ||
| 313 | |||
| 314 | |||
| 315 | static void cs_printioctl(unsigned int x) | ||
| 316 | { | ||
| 317 | unsigned int i; | ||
| 318 | unsigned char vidx; | ||
| 319 | // Index of mixtable1[] member is Device ID | ||
| 320 | // and must be <= SOUND_MIXER_NRDEVICES. | ||
| 321 | // Value of array member is index into s->mix.vol[] | ||
| 322 | static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = { | ||
| 323 | [SOUND_MIXER_PCM] = 1, // voice | ||
| 324 | [SOUND_MIXER_LINE1] = 2, // AUX | ||
| 325 | [SOUND_MIXER_CD] = 3, // CD | ||
| 326 | [SOUND_MIXER_LINE] = 4, // Line | ||
| 327 | [SOUND_MIXER_SYNTH] = 5, // FM | ||
| 328 | [SOUND_MIXER_MIC] = 6, // Mic | ||
| 329 | [SOUND_MIXER_SPEAKER] = 7, // Speaker | ||
| 330 | [SOUND_MIXER_RECLEV] = 8, // Recording level | ||
| 331 | [SOUND_MIXER_VOLUME] = 9 // Master Volume | ||
| 332 | }; | ||
| 333 | |||
| 334 | switch (x) { | ||
| 335 | case SOUND_MIXER_CS_GETDBGMASK: | ||
| 336 | CS_DBGOUT(CS_IOCTL, 4, | ||
| 337 | printk("SOUND_MIXER_CS_GETDBGMASK:\n")); | ||
| 338 | break; | ||
| 339 | case SOUND_MIXER_CS_GETDBGLEVEL: | ||
| 340 | CS_DBGOUT(CS_IOCTL, 4, | ||
| 341 | printk("SOUND_MIXER_CS_GETDBGLEVEL:\n")); | ||
| 342 | break; | ||
| 343 | case SOUND_MIXER_CS_SETDBGMASK: | ||
| 344 | CS_DBGOUT(CS_IOCTL, 4, | ||
| 345 | printk("SOUND_MIXER_CS_SETDBGMASK:\n")); | ||
| 346 | break; | ||
| 347 | case SOUND_MIXER_CS_SETDBGLEVEL: | ||
| 348 | CS_DBGOUT(CS_IOCTL, 4, | ||
| 349 | printk("SOUND_MIXER_CS_SETDBGLEVEL:\n")); | ||
| 350 | break; | ||
| 351 | case OSS_GETVERSION: | ||
| 352 | CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n")); | ||
| 353 | break; | ||
| 354 | case SNDCTL_DSP_SYNC: | ||
| 355 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n")); | ||
| 356 | break; | ||
| 357 | case SNDCTL_DSP_SETDUPLEX: | ||
| 358 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n")); | ||
| 359 | break; | ||
| 360 | case SNDCTL_DSP_GETCAPS: | ||
| 361 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n")); | ||
| 362 | break; | ||
| 363 | case SNDCTL_DSP_RESET: | ||
| 364 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n")); | ||
| 365 | break; | ||
| 366 | case SNDCTL_DSP_SPEED: | ||
| 367 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n")); | ||
| 368 | break; | ||
| 369 | case SNDCTL_DSP_STEREO: | ||
| 370 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n")); | ||
| 371 | break; | ||
| 372 | case SNDCTL_DSP_CHANNELS: | ||
| 373 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n")); | ||
| 374 | break; | ||
| 375 | case SNDCTL_DSP_GETFMTS: | ||
| 376 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n")); | ||
| 377 | break; | ||
| 378 | case SNDCTL_DSP_SETFMT: | ||
| 379 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n")); | ||
| 380 | break; | ||
| 381 | case SNDCTL_DSP_POST: | ||
| 382 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n")); | ||
| 383 | break; | ||
| 384 | case SNDCTL_DSP_GETTRIGGER: | ||
| 385 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n")); | ||
| 386 | break; | ||
| 387 | case SNDCTL_DSP_SETTRIGGER: | ||
| 388 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n")); | ||
| 389 | break; | ||
| 390 | case SNDCTL_DSP_GETOSPACE: | ||
| 391 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n")); | ||
| 392 | break; | ||
| 393 | case SNDCTL_DSP_GETISPACE: | ||
| 394 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n")); | ||
| 395 | break; | ||
| 396 | case SNDCTL_DSP_NONBLOCK: | ||
| 397 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n")); | ||
| 398 | break; | ||
| 399 | case SNDCTL_DSP_GETODELAY: | ||
| 400 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n")); | ||
| 401 | break; | ||
| 402 | case SNDCTL_DSP_GETIPTR: | ||
| 403 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n")); | ||
| 404 | break; | ||
| 405 | case SNDCTL_DSP_GETOPTR: | ||
| 406 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n")); | ||
| 407 | break; | ||
| 408 | case SNDCTL_DSP_GETBLKSIZE: | ||
| 409 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n")); | ||
| 410 | break; | ||
| 411 | case SNDCTL_DSP_SETFRAGMENT: | ||
| 412 | CS_DBGOUT(CS_IOCTL, 4, | ||
| 413 | printk("SNDCTL_DSP_SETFRAGMENT:\n")); | ||
| 414 | break; | ||
| 415 | case SNDCTL_DSP_SUBDIVIDE: | ||
| 416 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n")); | ||
| 417 | break; | ||
| 418 | case SOUND_PCM_READ_RATE: | ||
| 419 | CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n")); | ||
| 420 | break; | ||
| 421 | case SOUND_PCM_READ_CHANNELS: | ||
| 422 | CS_DBGOUT(CS_IOCTL, 4, | ||
| 423 | printk("SOUND_PCM_READ_CHANNELS:\n")); | ||
| 424 | break; | ||
| 425 | case SOUND_PCM_READ_BITS: | ||
| 426 | CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n")); | ||
| 427 | break; | ||
| 428 | case SOUND_PCM_WRITE_FILTER: | ||
| 429 | CS_DBGOUT(CS_IOCTL, 4, | ||
| 430 | printk("SOUND_PCM_WRITE_FILTER:\n")); | ||
| 431 | break; | ||
| 432 | case SNDCTL_DSP_SETSYNCRO: | ||
| 433 | CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n")); | ||
| 434 | break; | ||
| 435 | case SOUND_PCM_READ_FILTER: | ||
| 436 | CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n")); | ||
| 437 | break; | ||
| 438 | case SOUND_MIXER_PRIVATE1: | ||
| 439 | CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n")); | ||
| 440 | break; | ||
| 441 | case SOUND_MIXER_PRIVATE2: | ||
| 442 | CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n")); | ||
| 443 | break; | ||
| 444 | case SOUND_MIXER_PRIVATE3: | ||
| 445 | CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n")); | ||
| 446 | break; | ||
| 447 | case SOUND_MIXER_PRIVATE4: | ||
| 448 | CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n")); | ||
| 449 | break; | ||
| 450 | case SOUND_MIXER_PRIVATE5: | ||
| 451 | CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n")); | ||
| 452 | break; | ||
| 453 | case SOUND_MIXER_INFO: | ||
| 454 | CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n")); | ||
| 455 | break; | ||
| 456 | case SOUND_OLD_MIXER_INFO: | ||
| 457 | CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n")); | ||
| 458 | break; | ||
| 459 | |||
| 460 | default: | ||
| 461 | switch (_IOC_NR(x)) { | ||
| 462 | case SOUND_MIXER_VOLUME: | ||
| 463 | CS_DBGOUT(CS_IOCTL, 4, | ||
| 464 | printk("SOUND_MIXER_VOLUME:\n")); | ||
| 465 | break; | ||
| 466 | case SOUND_MIXER_SPEAKER: | ||
| 467 | CS_DBGOUT(CS_IOCTL, 4, | ||
| 468 | printk("SOUND_MIXER_SPEAKER:\n")); | ||
| 469 | break; | ||
| 470 | case SOUND_MIXER_RECLEV: | ||
| 471 | CS_DBGOUT(CS_IOCTL, 4, | ||
| 472 | printk("SOUND_MIXER_RECLEV:\n")); | ||
| 473 | break; | ||
| 474 | case SOUND_MIXER_MIC: | ||
| 475 | CS_DBGOUT(CS_IOCTL, 4, | ||
| 476 | printk("SOUND_MIXER_MIC:\n")); | ||
| 477 | break; | ||
| 478 | case SOUND_MIXER_SYNTH: | ||
| 479 | CS_DBGOUT(CS_IOCTL, 4, | ||
| 480 | printk("SOUND_MIXER_SYNTH:\n")); | ||
| 481 | break; | ||
| 482 | case SOUND_MIXER_RECSRC: | ||
| 483 | CS_DBGOUT(CS_IOCTL, 4, | ||
| 484 | printk("SOUND_MIXER_RECSRC:\n")); | ||
| 485 | break; | ||
| 486 | case SOUND_MIXER_DEVMASK: | ||
| 487 | CS_DBGOUT(CS_IOCTL, 4, | ||
| 488 | printk("SOUND_MIXER_DEVMASK:\n")); | ||
| 489 | break; | ||
| 490 | case SOUND_MIXER_RECMASK: | ||
| 491 | CS_DBGOUT(CS_IOCTL, 4, | ||
| 492 | printk("SOUND_MIXER_RECMASK:\n")); | ||
| 493 | break; | ||
| 494 | case SOUND_MIXER_STEREODEVS: | ||
| 495 | CS_DBGOUT(CS_IOCTL, 4, | ||
| 496 | printk("SOUND_MIXER_STEREODEVS:\n")); | ||
| 497 | break; | ||
| 498 | case SOUND_MIXER_CAPS: | ||
| 499 | CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n")); | ||
| 500 | break; | ||
| 501 | default: | ||
| 502 | i = _IOC_NR(x); | ||
| 503 | if (i >= SOUND_MIXER_NRDEVICES | ||
| 504 | || !(vidx = mixtable1[i])) { | ||
| 505 | CS_DBGOUT(CS_IOCTL, 4, printk | ||
| 506 | ("UNKNOWN IOCTL: 0x%.8x NR=%d\n", | ||
| 507 | x, i)); | ||
| 508 | } else { | ||
| 509 | CS_DBGOUT(CS_IOCTL, 4, printk | ||
| 510 | ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n", | ||
| 511 | x, i)); | ||
| 512 | } | ||
| 513 | break; | ||
| 514 | } | ||
| 515 | } | ||
| 516 | } | ||
| 517 | #endif | ||
| 518 | static int prog_dmabuf_adc(struct cs4281_state *s); | ||
| 519 | static void prog_codec(struct cs4281_state *s, unsigned type); | ||
| 520 | |||
| 521 | // --------------------------------------------------------------------- | ||
| 522 | // | ||
| 523 | // Hardware Interfaces For the CS4281 | ||
| 524 | // | ||
| 525 | |||
| 526 | |||
| 527 | //****************************************************************************** | ||
| 528 | // "delayus()-- Delay for the specified # of microseconds. | ||
| 529 | //****************************************************************************** | ||
| 530 | static void delayus(struct cs4281_state *s, u32 delay) | ||
| 531 | { | ||
| 532 | u32 j; | ||
| 533 | if ((delay > 9999) && (s->pm.flags & CS4281_PM_IDLE)) { | ||
| 534 | j = (delay * HZ) / 1000000; /* calculate delay in jiffies */ | ||
| 535 | if (j < 1) | ||
| 536 | j = 1; /* minimum one jiffy. */ | ||
| 537 | current->state = TASK_UNINTERRUPTIBLE; | ||
| 538 | schedule_timeout(j); | ||
| 539 | } else | ||
| 540 | udelay(delay); | ||
| 541 | return; | ||
| 542 | } | ||
| 543 | |||
| 544 | |||
| 545 | //****************************************************************************** | ||
| 546 | // "cs4281_read_ac97" -- Reads a word from the specified location in the | ||
| 547 | // CS4281's address space(based on the BA0 register). | ||
| 548 | // | ||
| 549 | // 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address | ||
| 550 | // 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 register, | ||
| 551 | // 0h for reads. | ||
| 552 | // 3. Write ACCTL = Control Register = 460h for initiating the write | ||
| 553 | // 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h | ||
| 554 | // 5. if DCV not cleared, break and return error | ||
| 555 | // 6. Read ACSTS = Status Register = 464h, check VSTS bit | ||
| 556 | //**************************************************************************** | ||
| 557 | static int cs4281_read_ac97(struct cs4281_state *card, u32 offset, | ||
| 558 | u32 * value) | ||
| 559 | { | ||
| 560 | u32 count, status; | ||
| 561 | |||
| 562 | // Make sure that there is not data sitting | ||
| 563 | // around from a previous uncompleted access. | ||
| 564 | // ACSDA = Status Data Register = 47Ch | ||
| 565 | status = readl(card->pBA0 + BA0_ACSDA); | ||
| 566 | |||
| 567 | // Setup the AC97 control registers on the CS4281 to send the | ||
| 568 | // appropriate command to the AC97 to perform the read. | ||
| 569 | // ACCAD = Command Address Register = 46Ch | ||
| 570 | // ACCDA = Command Data Register = 470h | ||
| 571 | // ACCTL = Control Register = 460h | ||
| 572 | // bit DCV - will clear when process completed | ||
| 573 | // bit CRW - Read command | ||
| 574 | // bit VFRM - valid frame enabled | ||
| 575 | // bit ESYN - ASYNC generation enabled | ||
| 576 | |||
| 577 | // Get the actual AC97 register from the offset | ||
| 578 | writel(offset - BA0_AC97_RESET, card->pBA0 + BA0_ACCAD); | ||
| 579 | writel(0, card->pBA0 + BA0_ACCDA); | ||
| 580 | writel(ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN, | ||
| 581 | card->pBA0 + BA0_ACCTL); | ||
| 582 | |||
| 583 | // Wait for the read to occur. | ||
| 584 | for (count = 0; count < 10; count++) { | ||
| 585 | // First, we want to wait for a short time. | ||
| 586 | udelay(25); | ||
| 587 | |||
| 588 | // Now, check to see if the read has completed. | ||
| 589 | // ACCTL = 460h, DCV should be reset by now and 460h = 17h | ||
| 590 | if (!(readl(card->pBA0 + BA0_ACCTL) & ACCTL_DCV)) | ||
| 591 | break; | ||
| 592 | } | ||
| 593 | |||
| 594 | // Make sure the read completed. | ||
| 595 | if (readl(card->pBA0 + BA0_ACCTL) & ACCTL_DCV) | ||
| 596 | return 1; | ||
| 597 | |||
| 598 | // Wait for the valid status bit to go active. | ||
| 599 | for (count = 0; count < 10; count++) { | ||
| 600 | // Read the AC97 status register. | ||
| 601 | // ACSTS = Status Register = 464h | ||
| 602 | status = readl(card->pBA0 + BA0_ACSTS); | ||
| 603 | |||
| 604 | // See if we have valid status. | ||
| 605 | // VSTS - Valid Status | ||
| 606 | if (status & ACSTS_VSTS) | ||
| 607 | break; | ||
| 608 | // Wait for a short while. | ||
| 609 | udelay(25); | ||
| 610 | } | ||
| 611 | |||
| 612 | // Make sure we got valid status. | ||
| 613 | if (!(status & ACSTS_VSTS)) | ||
| 614 | return 1; | ||
| 615 | |||
| 616 | // Read the data returned from the AC97 register. | ||
| 617 | // ACSDA = Status Data Register = 474h | ||
| 618 | *value = readl(card->pBA0 + BA0_ACSDA); | ||
| 619 | |||
| 620 | // Success. | ||
| 621 | return (0); | ||
| 622 | } | ||
| 623 | |||
| 624 | |||
| 625 | //**************************************************************************** | ||
| 626 | // | ||
| 627 | // "cs4281_write_ac97()"-- writes a word to the specified location in the | ||
| 628 | // CS461x's address space (based on the part's base address zero register). | ||
| 629 | // | ||
| 630 | // 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address | ||
| 631 | // 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 reg. | ||
| 632 | // 3. Write ACCTL = Control Register = 460h for initiating the write | ||
| 633 | // 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h | ||
| 634 | // 5. if DCV not cleared, break and return error | ||
| 635 | // | ||
| 636 | //**************************************************************************** | ||
| 637 | static int cs4281_write_ac97(struct cs4281_state *card, u32 offset, | ||
| 638 | u32 value) | ||
| 639 | { | ||
| 640 | u32 count, status=0; | ||
| 641 | |||
| 642 | CS_DBGOUT(CS_FUNCTION, 2, | ||
| 643 | printk(KERN_INFO "cs4281: cs_4281_write_ac97()+ \n")); | ||
| 644 | |||
| 645 | // Setup the AC97 control registers on the CS4281 to send the | ||
| 646 | // appropriate command to the AC97 to perform the read. | ||
| 647 | // ACCAD = Command Address Register = 46Ch | ||
| 648 | // ACCDA = Command Data Register = 470h | ||
| 649 | // ACCTL = Control Register = 460h | ||
| 650 | // set DCV - will clear when process completed | ||
| 651 | // reset CRW - Write command | ||
| 652 | // set VFRM - valid frame enabled | ||
| 653 | // set ESYN - ASYNC generation enabled | ||
| 654 | // set RSTN - ARST# inactive, AC97 codec not reset | ||
| 655 | |||
| 656 | // Get the actual AC97 register from the offset | ||
| 657 | |||
| 658 | writel(offset - BA0_AC97_RESET, card->pBA0 + BA0_ACCAD); | ||
| 659 | writel(value, card->pBA0 + BA0_ACCDA); | ||
| 660 | writel(ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN, | ||
| 661 | card->pBA0 + BA0_ACCTL); | ||
| 662 | |||
| 663 | // Wait for the write to occur. | ||
| 664 | for (count = 0; count < 100; count++) { | ||
| 665 | // First, we want to wait for a short time. | ||
| 666 | udelay(25); | ||
| 667 | // Now, check to see if the write has completed. | ||
| 668 | // ACCTL = 460h, DCV should be reset by now and 460h = 07h | ||
| 669 | status = readl(card->pBA0 + BA0_ACCTL); | ||
| 670 | if (!(status & ACCTL_DCV)) | ||
| 671 | break; | ||
| 672 | } | ||
| 673 | |||
| 674 | // Make sure the write completed. | ||
| 675 | if (status & ACCTL_DCV) { | ||
| 676 | CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO | ||
| 677 | "cs4281: cs_4281_write_ac97()- unable to write. ACCTL_DCV active\n")); | ||
| 678 | return 1; | ||
| 679 | } | ||
| 680 | CS_DBGOUT(CS_FUNCTION, 2, | ||
| 681 | printk(KERN_INFO "cs4281: cs_4281_write_ac97()- 0\n")); | ||
| 682 | // Success. | ||
| 683 | return 0; | ||
| 684 | } | ||
| 685 | |||
| 686 | |||
| 687 | //****************************************************************************** | ||
| 688 | // "Init4281()" -- Bring up the part. | ||
| 689 | //****************************************************************************** | ||
| 690 | static __devinit int cs4281_hw_init(struct cs4281_state *card) | ||
| 691 | { | ||
| 692 | u32 ac97_slotid; | ||
| 693 | u32 temp1, temp2; | ||
| 694 | |||
| 695 | CS_DBGOUT(CS_FUNCTION, 2, | ||
| 696 | printk(KERN_INFO "cs4281: cs4281_hw_init()+ \n")); | ||
| 697 | #ifndef NOT_CS4281_PM | ||
| 698 | if(!card) | ||
| 699 | return 1; | ||
| 700 | #endif | ||
| 701 | temp2 = readl(card->pBA0 + BA0_CFLR); | ||
| 702 | CS_DBGOUT(CS_INIT | CS_ERROR | CS_PARMS, 4, printk(KERN_INFO | ||
| 703 | "cs4281: cs4281_hw_init() CFLR 0x%x\n", temp2)); | ||
| 704 | if(temp2 != CS4281_CFLR_DEFAULT) | ||
| 705 | { | ||
| 706 | CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO | ||
| 707 | "cs4281: cs4281_hw_init() CFLR invalid - resetting from 0x%x to 0x%x\n", | ||
| 708 | temp2,CS4281_CFLR_DEFAULT)); | ||
| 709 | writel(CS4281_CFLR_DEFAULT, card->pBA0 + BA0_CFLR); | ||
| 710 | temp2 = readl(card->pBA0 + BA0_CFLR); | ||
| 711 | if(temp2 != CS4281_CFLR_DEFAULT) | ||
| 712 | { | ||
| 713 | CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO | ||
| 714 | "cs4281: cs4281_hw_init() Invalid hardware - unable to configure CFLR\n")); | ||
| 715 | return 1; | ||
| 716 | } | ||
| 717 | } | ||
| 718 | |||
| 719 | //***************************************7 | ||
| 720 | // Set up the Sound System Configuration | ||
| 721 | //*************************************** | ||
| 722 | |||
| 723 | // Set the 'Configuration Write Protect' register | ||
| 724 | // to 4281h. Allows vendor-defined configuration | ||
| 725 | // space between 0e4h and 0ffh to be written. | ||
| 726 | |||
| 727 | writel(0x4281, card->pBA0 + BA0_CWPR); // (3e0h) | ||
| 728 | |||
| 729 | // (0), Blast the clock control register to zero so that the | ||
| 730 | // PLL starts out in a known state, and blast the master serial | ||
| 731 | // port control register to zero so that the serial ports also | ||
| 732 | // start out in a known state. | ||
| 733 | |||
| 734 | writel(0, card->pBA0 + BA0_CLKCR1); // (400h) | ||
| 735 | writel(0, card->pBA0 + BA0_SERMC); // (420h) | ||
| 736 | |||
| 737 | |||
| 738 | // (1), Make ESYN go to zero to turn off | ||
| 739 | // the Sync pulse on the AC97 link. | ||
| 740 | |||
| 741 | writel(0, card->pBA0 + BA0_ACCTL); | ||
| 742 | udelay(50); | ||
| 743 | |||
| 744 | |||
| 745 | // (2) Drive the ARST# pin low for a minimum of 1uS (as defined in | ||
| 746 | // the AC97 spec) and then drive it high. This is done for non | ||
| 747 | // AC97 modes since there might be logic external to the CS461x | ||
| 748 | // that uses the ARST# line for a reset. | ||
| 749 | |||
| 750 | writel(0, card->pBA0 + BA0_SPMC); // (3ech) | ||
| 751 | udelay(100); | ||
| 752 | writel(SPMC_RSTN, card->pBA0 + BA0_SPMC); | ||
| 753 | delayus(card,50000); // Wait 50 ms for ABITCLK to become stable. | ||
| 754 | |||
| 755 | // (3) Turn on the Sound System Clocks. | ||
| 756 | writel(CLKCR1_PLLP, card->pBA0 + BA0_CLKCR1); // (400h) | ||
| 757 | delayus(card,50000); // Wait for the PLL to stabilize. | ||
| 758 | // Turn on clocking of the core (CLKCR1(400h) = 0x00000030) | ||
| 759 | writel(CLKCR1_PLLP | CLKCR1_SWCE, card->pBA0 + BA0_CLKCR1); | ||
| 760 | |||
| 761 | // (4) Power on everything for now.. | ||
| 762 | writel(0x7E, card->pBA0 + BA0_SSPM); // (740h) | ||
| 763 | |||
| 764 | // (5) Wait for clock stabilization. | ||
| 765 | for (temp1 = 0; temp1 < 1000; temp1++) { | ||
| 766 | udelay(1000); | ||
| 767 | if (readl(card->pBA0 + BA0_CLKCR1) & CLKCR1_DLLRDY) | ||
| 768 | break; | ||
| 769 | } | ||
| 770 | if (!(readl(card->pBA0 + BA0_CLKCR1) & CLKCR1_DLLRDY)) { | ||
| 771 | CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR | ||
| 772 | "cs4281: DLLRDY failed!\n")); | ||
| 773 | return -EIO; | ||
| 774 | } | ||
| 775 | // (6) Enable ASYNC generation. | ||
| 776 | writel(ACCTL_ESYN, card->pBA0 + BA0_ACCTL); // (460h) | ||
| 777 | |||
| 778 | // Now wait 'for a short while' to allow the AC97 | ||
| 779 | // part to start generating bit clock. (so we don't | ||
| 780 | // Try to start the PLL without an input clock.) | ||
| 781 | delayus(card,50000); | ||
| 782 | |||
| 783 | // Set the serial port timing configuration, so that the | ||
| 784 | // clock control circuit gets its clock from the right place. | ||
| 785 | writel(SERMC_PTC_AC97, card->pBA0 + BA0_SERMC); // (420h)=2. | ||
| 786 | |||
| 787 | // (7) Wait for the codec ready signal from the AC97 codec. | ||
| 788 | |||
| 789 | for (temp1 = 0; temp1 < 1000; temp1++) { | ||
| 790 | // Delay a mil to let things settle out and | ||
| 791 | // to prevent retrying the read too quickly. | ||
| 792 | udelay(1000); | ||
| 793 | if (readl(card->pBA0 + BA0_ACSTS) & ACSTS_CRDY) // If ready, (464h) | ||
| 794 | break; // exit the 'for' loop. | ||
| 795 | } | ||
| 796 | if (!(readl(card->pBA0 + BA0_ACSTS) & ACSTS_CRDY)) // If never came ready, | ||
| 797 | { | ||
| 798 | CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_ERR | ||
| 799 | "cs4281: ACSTS never came ready!\n")); | ||
| 800 | return -EIO; // exit initialization. | ||
| 801 | } | ||
| 802 | // (8) Assert the 'valid frame' signal so we can | ||
| 803 | // begin sending commands to the AC97 codec. | ||
| 804 | writel(ACCTL_VFRM | ACCTL_ESYN, card->pBA0 + BA0_ACCTL); // (460h) | ||
| 805 | |||
| 806 | // (9), Wait until CODEC calibration is finished. | ||
| 807 | // Print an error message if it doesn't. | ||
| 808 | for (temp1 = 0; temp1 < 1000; temp1++) { | ||
| 809 | delayus(card,10000); | ||
| 810 | // Read the AC97 Powerdown Control/Status Register. | ||
| 811 | cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp2); | ||
| 812 | if ((temp2 & 0x0000000F) == 0x0000000F) | ||
| 813 | break; | ||
| 814 | } | ||
| 815 | if ((temp2 & 0x0000000F) != 0x0000000F) { | ||
| 816 | CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_ERR | ||
| 817 | "cs4281: Codec failed to calibrate. Status = %.8x.\n", | ||
| 818 | temp2)); | ||
| 819 | return -EIO; | ||
| 820 | } | ||
| 821 | // (10), Set the serial port timing configuration, so that the | ||
| 822 | // clock control circuit gets its clock from the right place. | ||
| 823 | writel(SERMC_PTC_AC97, card->pBA0 + BA0_SERMC); // (420h)=2. | ||
| 824 | |||
| 825 | |||
| 826 | // (11) Wait until we've sampled input slots 3 & 4 as valid, meaning | ||
| 827 | // that the codec is pumping ADC data across the AC link. | ||
| 828 | for (temp1 = 0; temp1 < 1000; temp1++) { | ||
| 829 | // Delay a mil to let things settle out and | ||
| 830 | // to prevent retrying the read too quickly. | ||
| 831 | delayus(card,1000); //(test) | ||
| 832 | |||
| 833 | // Read the input slot valid register; See | ||
| 834 | // if input slots 3 and 4 are valid yet. | ||
| 835 | if ( | ||
| 836 | (readl(card->pBA0 + BA0_ACISV) & | ||
| 837 | (ACISV_ISV3 | ACISV_ISV4)) == | ||
| 838 | (ACISV_ISV3 | ACISV_ISV4)) break; // Exit the 'for' if slots are valid. | ||
| 839 | } | ||
| 840 | // If we never got valid data, exit initialization. | ||
| 841 | if ((readl(card->pBA0 + BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) | ||
| 842 | != (ACISV_ISV3 | ACISV_ISV4)) { | ||
| 843 | CS_DBGOUT(CS_FUNCTION, 2, | ||
| 844 | printk(KERN_ERR | ||
| 845 | "cs4281: Never got valid data!\n")); | ||
| 846 | return -EIO; // If no valid data, exit initialization. | ||
| 847 | } | ||
| 848 | // (12), Start digital data transfer of audio data to the codec. | ||
| 849 | writel(ACOSV_SLV3 | ACOSV_SLV4, card->pBA0 + BA0_ACOSV); // (468h) | ||
| 850 | |||
| 851 | |||
| 852 | //************************************** | ||
| 853 | // Unmute the Master and Alternate | ||
| 854 | // (headphone) volumes. Set to max. | ||
| 855 | //************************************** | ||
| 856 | cs4281_write_ac97(card, BA0_AC97_HEADPHONE_VOLUME, 0); | ||
| 857 | cs4281_write_ac97(card, BA0_AC97_MASTER_VOLUME, 0); | ||
| 858 | |||
| 859 | //****************************************** | ||
| 860 | // Power on the DAC(AddDACUser()from main()) | ||
| 861 | //****************************************** | ||
| 862 | cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1); | ||
| 863 | cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfdff); | ||
| 864 | |||
| 865 | // Wait until we sample a DAC ready state. | ||
| 866 | for (temp2 = 0; temp2 < 32; temp2++) { | ||
| 867 | // Let's wait a mil to let things settle. | ||
| 868 | delayus(card,1000); | ||
| 869 | // Read the current state of the power control reg. | ||
| 870 | cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1); | ||
| 871 | // If the DAC ready state bit is set, stop waiting. | ||
| 872 | if (temp1 & 0x2) | ||
| 873 | break; | ||
| 874 | } | ||
| 875 | |||
| 876 | //****************************************** | ||
| 877 | // Power on the ADC(AddADCUser()from main()) | ||
| 878 | //****************************************** | ||
| 879 | cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1); | ||
| 880 | cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfeff); | ||
| 881 | |||
| 882 | // Wait until we sample ADC ready state. | ||
| 883 | for (temp2 = 0; temp2 < 32; temp2++) { | ||
| 884 | // Let's wait a mil to let things settle. | ||
| 885 | delayus(card,1000); | ||
| 886 | // Read the current state of the power control reg. | ||
| 887 | cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1); | ||
| 888 | // If the ADC ready state bit is set, stop waiting. | ||
| 889 | if (temp1 & 0x1) | ||
| 890 | break; | ||
| 891 | } | ||
| 892 | // Set up 4281 Register contents that | ||
| 893 | // don't change for boot duration. | ||
| 894 | |||
| 895 | // For playback, we map AC97 slot 3 and 4(Left | ||
| 896 | // & Right PCM playback) to DMA Channel 0. | ||
| 897 | // Set the fifo to be 15 bytes at offset zero. | ||
| 898 | |||
| 899 | ac97_slotid = 0x01000f00; // FCR0.RS[4:0]=1(=>slot4, right PCM playback). | ||
| 900 | // FCR0.LS[4:0]=0(=>slot3, left PCM playback). | ||
| 901 | // FCR0.SZ[6-0]=15; FCR0.OF[6-0]=0. | ||
| 902 | writel(ac97_slotid, card->pBA0 + BA0_FCR0); // (180h) | ||
| 903 | writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR0); // Turn on FIFO Enable. | ||
| 904 | |||
| 905 | // For capture, we map AC97 slot 10 and 11(Left | ||
| 906 | // and Right PCM Record) to DMA Channel 1. | ||
| 907 | // Set the fifo to be 15 bytes at offset sixteen. | ||
| 908 | ac97_slotid = 0x0B0A0f10; // FCR1.RS[4:0]=11(=>slot11, right PCM record). | ||
| 909 | // FCR1.LS[4:0]=10(=>slot10, left PCM record). | ||
| 910 | // FCR1.SZ[6-0]=15; FCR1.OF[6-0]=16. | ||
| 911 | writel(ac97_slotid | FCRn_PSH, card->pBA0 + BA0_FCR1); // (184h) | ||
| 912 | writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR1); // Turn on FIFO Enable. | ||
| 913 | |||
| 914 | // Map the Playback SRC to the same AC97 slots(3 & 4-- | ||
| 915 | // --Playback left & right)as DMA channel 0. | ||
| 916 | // Map the record SRC to the same AC97 slots(10 & 11-- | ||
| 917 | // -- Record left & right) as DMA channel 1. | ||
| 918 | |||
| 919 | ac97_slotid = 0x0b0a0100; // SCRSA.PRSS[4:0]=1(=>slot4, right PCM playback). | ||
| 920 | // SCRSA.PLSS[4:0]=0(=>slot3, left PCM playback). | ||
| 921 | // SCRSA.CRSS[4:0]=11(=>slot11, right PCM record) | ||
| 922 | // SCRSA.CLSS[4:0]=10(=>slot10, left PCM record). | ||
| 923 | writel(ac97_slotid, card->pBA0 + BA0_SRCSA); // (75ch) | ||
| 924 | |||
| 925 | // Set 'Half Terminal Count Interrupt Enable' and 'Terminal | ||
| 926 | // Count Interrupt Enable' in DMA Control Registers 0 & 1. | ||
| 927 | // Set 'MSK' flag to 1 to keep the DMA engines paused. | ||
| 928 | temp1 = (DCRn_HTCIE | DCRn_TCIE | DCRn_MSK); // (00030001h) | ||
| 929 | writel(temp1, card->pBA0 + BA0_DCR0); // (154h | ||
| 930 | writel(temp1, card->pBA0 + BA0_DCR1); // (15ch) | ||
| 931 | |||
| 932 | // Set 'Auto-Initialize Control' to 'enabled'; For playback, | ||
| 933 | // set 'Transfer Type Control'(TR[1:0]) to 'read transfer', | ||
| 934 | // for record, set Transfer Type Control to 'write transfer'. | ||
| 935 | // All other bits set to zero; Some will be changed @ transfer start. | ||
| 936 | temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); // (20000018h) | ||
| 937 | writel(temp1, card->pBA0 + BA0_DMR0); // (150h) | ||
| 938 | temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); // (20000014h) | ||
| 939 | writel(temp1, card->pBA0 + BA0_DMR1); // (158h) | ||
| 940 | |||
| 941 | // Enable DMA interrupts generally, and | ||
| 942 | // DMA0 & DMA1 interrupts specifically. | ||
| 943 | temp1 = readl(card->pBA0 + BA0_HIMR) & 0xfffbfcff; | ||
| 944 | writel(temp1, card->pBA0 + BA0_HIMR); | ||
| 945 | |||
| 946 | CS_DBGOUT(CS_FUNCTION, 2, | ||
| 947 | printk(KERN_INFO "cs4281: cs4281_hw_init()- 0\n")); | ||
| 948 | return 0; | ||
| 949 | } | ||
| 950 | |||
| 951 | #ifndef NOT_CS4281_PM | ||
| 952 | static void printpm(struct cs4281_state *s) | ||
| 953 | { | ||
| 954 | CS_DBGOUT(CS_PM, 9, printk("pm struct:\n")); | ||
| 955 | CS_DBGOUT(CS_PM, 9, printk("flags:0x%x u32CLKCR1_SAVE: 0%x u32SSPMValue: 0x%x\n", | ||
| 956 | (unsigned)s->pm.flags,s->pm.u32CLKCR1_SAVE,s->pm.u32SSPMValue)); | ||
| 957 | CS_DBGOUT(CS_PM, 9, printk("u32PPLVCvalue: 0x%x u32PPRVCvalue: 0x%x\n", | ||
| 958 | s->pm.u32PPLVCvalue,s->pm.u32PPRVCvalue)); | ||
| 959 | CS_DBGOUT(CS_PM, 9, printk("u32FMLVCvalue: 0x%x u32FMRVCvalue: 0x%x\n", | ||
| 960 | s->pm.u32FMLVCvalue,s->pm.u32FMRVCvalue)); | ||
| 961 | CS_DBGOUT(CS_PM, 9, printk("u32GPIORvalue: 0x%x u32JSCTLvalue: 0x%x\n", | ||
| 962 | s->pm.u32GPIORvalue,s->pm.u32JSCTLvalue)); | ||
| 963 | CS_DBGOUT(CS_PM, 9, printk("u32SSCR: 0x%x u32SRCSA: 0x%x\n", | ||
| 964 | s->pm.u32SSCR,s->pm.u32SRCSA)); | ||
| 965 | CS_DBGOUT(CS_PM, 9, printk("u32DacASR: 0x%x u32AdcASR: 0x%x\n", | ||
| 966 | s->pm.u32DacASR,s->pm.u32AdcASR)); | ||
| 967 | CS_DBGOUT(CS_PM, 9, printk("u32DacSR: 0x%x u32AdcSR: 0x%x\n", | ||
| 968 | s->pm.u32DacSR,s->pm.u32AdcSR)); | ||
| 969 | CS_DBGOUT(CS_PM, 9, printk("u32MIDCR_Save: 0x%x\n", | ||
| 970 | s->pm.u32MIDCR_Save)); | ||
| 971 | |||
| 972 | } | ||
| 973 | static void printpipe(struct cs4281_pipeline *pl) | ||
| 974 | { | ||
| 975 | |||
| 976 | CS_DBGOUT(CS_PM, 9, printk("pm struct:\n")); | ||
| 977 | CS_DBGOUT(CS_PM, 9, printk("flags:0x%x number: 0%x\n", | ||
| 978 | (unsigned)pl->flags,pl->number)); | ||
| 979 | CS_DBGOUT(CS_PM, 9, printk("u32DBAnValue: 0%x u32DBCnValue: 0x%x\n", | ||
| 980 | pl->u32DBAnValue,pl->u32DBCnValue)); | ||
| 981 | CS_DBGOUT(CS_PM, 9, printk("u32DMRnValue: 0x%x u32DCRnValue: 0x%x\n", | ||
| 982 | pl->u32DMRnValue,pl->u32DCRnValue)); | ||
| 983 | CS_DBGOUT(CS_PM, 9, printk("u32DBAnAddress: 0x%x u32DBCnAddress: 0x%x\n", | ||
| 984 | pl->u32DBAnAddress,pl->u32DBCnAddress)); | ||
| 985 | CS_DBGOUT(CS_PM, 9, printk("u32DCAnAddress: 0x%x u32DCCnAddress: 0x%x\n", | ||
| 986 | pl->u32DCCnAddress,pl->u32DCCnAddress)); | ||
| 987 | CS_DBGOUT(CS_PM, 9, printk("u32DMRnAddress: 0x%x u32DCRnAddress: 0x%x\n", | ||
| 988 | pl->u32DMRnAddress,pl->u32DCRnAddress)); | ||
| 989 | CS_DBGOUT(CS_PM, 9, printk("u32HDSRnAddress: 0x%x u32DBAn_Save: 0x%x\n", | ||
| 990 | pl->u32HDSRnAddress,pl->u32DBAn_Save)); | ||
| 991 | CS_DBGOUT(CS_PM, 9, printk("u32DBCn_Save: 0x%x u32DMRn_Save: 0x%x\n", | ||
| 992 | pl->u32DBCn_Save,pl->u32DMRn_Save)); | ||
| 993 | CS_DBGOUT(CS_PM, 9, printk("u32DCRn_Save: 0x%x u32DCCn_Save: 0x%x\n", | ||
| 994 | pl->u32DCRn_Save,pl->u32DCCn_Save)); | ||
| 995 | CS_DBGOUT(CS_PM, 9, printk("u32DCAn_Save: 0x%x\n", | ||
| 996 | pl->u32DCAn_Save)); | ||
| 997 | CS_DBGOUT(CS_PM, 9, printk("u32FCRn_Save: 0x%x u32FSICn_Save: 0x%x\n", | ||
| 998 | pl->u32FCRn_Save,pl->u32FSICn_Save)); | ||
| 999 | CS_DBGOUT(CS_PM, 9, printk("u32FCRnValue: 0x%x u32FSICnValue: 0x%x\n", | ||
| 1000 | pl->u32FCRnValue,pl->u32FSICnValue)); | ||
| 1001 | CS_DBGOUT(CS_PM, 9, printk("u32FCRnAddress: 0x%x u32FSICnAddress: 0x%x\n", | ||
| 1002 | pl->u32FCRnAddress,pl->u32FSICnAddress)); | ||
| 1003 | CS_DBGOUT(CS_PM, 9, printk("u32FPDRnValue: 0x%x u32FPDRnAddress: 0x%x\n", | ||
| 1004 | pl->u32FPDRnValue,pl->u32FPDRnAddress)); | ||
| 1005 | } | ||
| 1006 | static void printpipelines(struct cs4281_state *s) | ||
| 1007 | { | ||
| 1008 | int i; | ||
| 1009 | for(i=0;i<CS4281_NUMBER_OF_PIPELINES;i++) | ||
| 1010 | { | ||
| 1011 | if(s->pl[i].flags & CS4281_PIPELINE_VALID) | ||
| 1012 | { | ||
| 1013 | printpipe(&s->pl[i]); | ||
| 1014 | } | ||
| 1015 | } | ||
| 1016 | } | ||
| 1017 | /**************************************************************************** | ||
| 1018 | * | ||
| 1019 | * Suspend - save the ac97 regs, mute the outputs and power down the part. | ||
| 1020 | * | ||
| 1021 | ****************************************************************************/ | ||
| 1022 | static void cs4281_ac97_suspend(struct cs4281_state *s) | ||
| 1023 | { | ||
| 1024 | int Count,i; | ||
| 1025 | |||
| 1026 | CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_suspend()+\n")); | ||
| 1027 | /* | ||
| 1028 | * change the state, save the current hwptr, then stop the dac/adc | ||
| 1029 | */ | ||
| 1030 | s->pm.flags &= ~CS4281_PM_IDLE; | ||
| 1031 | s->pm.flags |= CS4281_PM_SUSPENDING; | ||
| 1032 | s->pm.u32hwptr_playback = readl(s->pBA0 + BA0_DCA0); | ||
| 1033 | s->pm.u32hwptr_capture = readl(s->pBA0 + BA0_DCA1); | ||
| 1034 | stop_dac(s); | ||
| 1035 | stop_adc(s); | ||
| 1036 | |||
| 1037 | for(Count = 0x2, i=0; (Count <= CS4281_AC97_HIGHESTREGTORESTORE) | ||
| 1038 | && (i < CS4281_AC97_NUMBER_RESTORE_REGS); | ||
| 1039 | Count += 2, i++) | ||
| 1040 | { | ||
| 1041 | cs4281_read_ac97(s, BA0_AC97_RESET + Count, &s->pm.ac97[i]); | ||
| 1042 | } | ||
| 1043 | /* | ||
| 1044 | * Save the ac97 volume registers as well as the current powerdown state. | ||
| 1045 | * Now, mute the all the outputs (master, headphone, and mono), as well | ||
| 1046 | * as the PCM volume, in preparation for powering down the entire part. | ||
| 1047 | */ | ||
| 1048 | cs4281_read_ac97(s, BA0_AC97_MASTER_VOLUME, &s->pm.u32AC97_master_volume); | ||
| 1049 | cs4281_read_ac97(s, BA0_AC97_HEADPHONE_VOLUME, &s->pm.u32AC97_headphone_volume); | ||
| 1050 | cs4281_read_ac97(s, BA0_AC97_MASTER_VOLUME_MONO, &s->pm.u32AC97_master_volume_mono); | ||
| 1051 | cs4281_read_ac97(s, BA0_AC97_PCM_OUT_VOLUME, &s->pm.u32AC97_pcm_out_volume); | ||
| 1052 | |||
| 1053 | cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME, 0x8000); | ||
| 1054 | cs4281_write_ac97(s, BA0_AC97_HEADPHONE_VOLUME, 0x8000); | ||
| 1055 | cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME_MONO, 0x8000); | ||
| 1056 | cs4281_write_ac97(s, BA0_AC97_PCM_OUT_VOLUME, 0x8000); | ||
| 1057 | |||
| 1058 | cs4281_read_ac97(s, BA0_AC97_POWERDOWN, &s->pm.u32AC97_powerdown); | ||
| 1059 | cs4281_read_ac97(s, BA0_AC97_GENERAL_PURPOSE, &s->pm.u32AC97_general_purpose); | ||
| 1060 | |||
| 1061 | /* | ||
| 1062 | * And power down everything on the AC97 codec. | ||
| 1063 | */ | ||
| 1064 | cs4281_write_ac97(s, BA0_AC97_POWERDOWN, 0xff00); | ||
| 1065 | CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_suspend()-\n")); | ||
| 1066 | } | ||
| 1067 | |||
| 1068 | /**************************************************************************** | ||
| 1069 | * | ||
| 1070 | * Resume - power up the part and restore its registers.. | ||
| 1071 | * | ||
| 1072 | ****************************************************************************/ | ||
| 1073 | static void cs4281_ac97_resume(struct cs4281_state *s) | ||
| 1074 | { | ||
| 1075 | int Count,i; | ||
| 1076 | |||
| 1077 | CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_resume()+\n")); | ||
| 1078 | |||
| 1079 | /* do not save the power state registers at this time | ||
| 1080 | // | ||
| 1081 | // If we saved away the power control registers, write them into the | ||
| 1082 | // shadows so those saved values get restored instead of the current | ||
| 1083 | // shadowed value. | ||
| 1084 | // | ||
| 1085 | if( bPowerStateSaved ) | ||
| 1086 | { | ||
| 1087 | PokeShadow( 0x26, ulSaveReg0x26 ); | ||
| 1088 | bPowerStateSaved = FALSE; | ||
| 1089 | } | ||
| 1090 | */ | ||
| 1091 | |||
| 1092 | // | ||
| 1093 | // First, we restore the state of the general purpose register. This | ||
| 1094 | // contains the mic select (mic1 or mic2) and if we restore this after | ||
| 1095 | // we restore the mic volume/boost state and mic2 was selected at | ||
| 1096 | // suspend time, we will end up with a brief period of time where mic1 | ||
| 1097 | // is selected with the volume/boost settings for mic2, causing | ||
| 1098 | // acoustic feedback. So we restore the general purpose register | ||
| 1099 | // first, thereby getting the correct mic selected before we restore | ||
| 1100 | // the mic volume/boost. | ||
| 1101 | // | ||
| 1102 | cs4281_write_ac97(s, BA0_AC97_GENERAL_PURPOSE, s->pm.u32AC97_general_purpose); | ||
| 1103 | |||
| 1104 | // | ||
| 1105 | // Now, while the outputs are still muted, restore the state of power | ||
| 1106 | // on the AC97 part. | ||
| 1107 | // | ||
| 1108 | cs4281_write_ac97(s, BA0_AC97_POWERDOWN, s->pm.u32AC97_powerdown); | ||
| 1109 | |||
| 1110 | /* | ||
| 1111 | * Restore just the first set of registers, from register number | ||
| 1112 | * 0x02 to the register number that ulHighestRegToRestore specifies. | ||
| 1113 | */ | ||
| 1114 | for( Count = 0x2, i=0; | ||
| 1115 | (Count <= CS4281_AC97_HIGHESTREGTORESTORE) | ||
| 1116 | && (i < CS4281_AC97_NUMBER_RESTORE_REGS); | ||
| 1117 | Count += 2, i++) | ||
| 1118 | { | ||
| 1119 | cs4281_write_ac97(s, BA0_AC97_RESET + Count, s->pm.ac97[i]); | ||
| 1120 | } | ||
| 1121 | CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_resume()-\n")); | ||
| 1122 | } | ||
| 1123 | |||
| 1124 | /* do not save the power state registers at this time | ||
| 1125 | **************************************************************************** | ||
| 1126 | * | ||
| 1127 | * SavePowerState - Save the power registers away. | ||
| 1128 | * | ||
| 1129 | **************************************************************************** | ||
| 1130 | void | ||
| 1131 | HWAC97codec::SavePowerState(void) | ||
| 1132 | { | ||
| 1133 | ENTRY(TM_OBJECTCALLS, "HWAC97codec::SavePowerState()\r\n"); | ||
| 1134 | |||
| 1135 | ulSaveReg0x26 = PeekShadow(0x26); | ||
| 1136 | |||
| 1137 | // | ||
| 1138 | // Note that we have saved registers that need to be restored during a | ||
| 1139 | // resume instead of ulAC97Regs[]. | ||
| 1140 | // | ||
| 1141 | bPowerStateSaved = TRUE; | ||
| 1142 | |||
| 1143 | } // SavePowerState | ||
| 1144 | */ | ||
| 1145 | |||
| 1146 | static void cs4281_SuspendFIFO(struct cs4281_state *s, struct cs4281_pipeline *pl) | ||
| 1147 | { | ||
| 1148 | /* | ||
| 1149 | * We need to save the contents of the BASIC FIFO Registers. | ||
| 1150 | */ | ||
| 1151 | pl->u32FCRn_Save = readl(s->pBA0 + pl->u32FCRnAddress); | ||
| 1152 | pl->u32FSICn_Save = readl(s->pBA0 + pl->u32FSICnAddress); | ||
| 1153 | } | ||
| 1154 | static void cs4281_ResumeFIFO(struct cs4281_state *s, struct cs4281_pipeline *pl) | ||
| 1155 | { | ||
| 1156 | /* | ||
| 1157 | * We need to restore the contents of the BASIC FIFO Registers. | ||
| 1158 | */ | ||
| 1159 | writel(pl->u32FCRn_Save,s->pBA0 + pl->u32FCRnAddress); | ||
| 1160 | writel(pl->u32FSICn_Save,s->pBA0 + pl->u32FSICnAddress); | ||
| 1161 | } | ||
| 1162 | static void cs4281_SuspendDMAengine(struct cs4281_state *s, struct cs4281_pipeline *pl) | ||
| 1163 | { | ||
| 1164 | // | ||
| 1165 | // We need to save the contents of the BASIC DMA Registers. | ||
| 1166 | // | ||
| 1167 | pl->u32DBAn_Save = readl(s->pBA0 + pl->u32DBAnAddress); | ||
| 1168 | pl->u32DBCn_Save = readl(s->pBA0 + pl->u32DBCnAddress); | ||
| 1169 | pl->u32DMRn_Save = readl(s->pBA0 + pl->u32DMRnAddress); | ||
| 1170 | pl->u32DCRn_Save = readl(s->pBA0 + pl->u32DCRnAddress); | ||
| 1171 | pl->u32DCCn_Save = readl(s->pBA0 + pl->u32DCCnAddress); | ||
| 1172 | pl->u32DCAn_Save = readl(s->pBA0 + pl->u32DCAnAddress); | ||
| 1173 | } | ||
| 1174 | static void cs4281_ResumeDMAengine(struct cs4281_state *s, struct cs4281_pipeline *pl) | ||
| 1175 | { | ||
| 1176 | // | ||
| 1177 | // We need to save the contents of the BASIC DMA Registers. | ||
| 1178 | // | ||
| 1179 | writel( pl->u32DBAn_Save, s->pBA0 + pl->u32DBAnAddress); | ||
| 1180 | writel( pl->u32DBCn_Save, s->pBA0 + pl->u32DBCnAddress); | ||
| 1181 | writel( pl->u32DMRn_Save, s->pBA0 + pl->u32DMRnAddress); | ||
| 1182 | writel( pl->u32DCRn_Save, s->pBA0 + pl->u32DCRnAddress); | ||
| 1183 | writel( pl->u32DCCn_Save, s->pBA0 + pl->u32DCCnAddress); | ||
| 1184 | writel( pl->u32DCAn_Save, s->pBA0 + pl->u32DCAnAddress); | ||
| 1185 | } | ||
| 1186 | |||
| 1187 | static int cs4281_suspend(struct cs4281_state *s) | ||
| 1188 | { | ||
| 1189 | int i; | ||
| 1190 | u32 u32CLKCR1; | ||
| 1191 | struct cs4281_pm *pm = &s->pm; | ||
| 1192 | CS_DBGOUT(CS_PM | CS_FUNCTION, 9, | ||
| 1193 | printk("cs4281: cs4281_suspend()+ flags=%d\n", | ||
| 1194 | (unsigned)s->pm.flags)); | ||
| 1195 | /* | ||
| 1196 | * check the current state, only suspend if IDLE | ||
| 1197 | */ | ||
| 1198 | if(!(s->pm.flags & CS4281_PM_IDLE)) | ||
| 1199 | { | ||
| 1200 | CS_DBGOUT(CS_PM | CS_ERROR, 2, | ||
| 1201 | printk("cs4281: cs4281_suspend() unable to suspend, not IDLE\n")); | ||
| 1202 | return 1; | ||
| 1203 | } | ||
| 1204 | s->pm.flags &= ~CS4281_PM_IDLE; | ||
| 1205 | s->pm.flags |= CS4281_PM_SUSPENDING; | ||
| 1206 | |||
| 1207 | // | ||
| 1208 | // Gershwin CLKRUN - Set CKRA | ||
| 1209 | // | ||
| 1210 | u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1); | ||
| 1211 | |||
| 1212 | pm->u32CLKCR1_SAVE = u32CLKCR1; | ||
| 1213 | if(!(u32CLKCR1 & 0x00010000 ) ) | ||
| 1214 | writel(u32CLKCR1 | 0x00010000, s->pBA0 + BA0_CLKCR1); | ||
| 1215 | |||
| 1216 | // | ||
| 1217 | // First, turn on the clocks (yikes) to the devices, so that they will | ||
| 1218 | // respond when we try to save their state. | ||
| 1219 | // | ||
| 1220 | if(!(u32CLKCR1 & CLKCR1_SWCE)) | ||
| 1221 | { | ||
| 1222 | writel(u32CLKCR1 | CLKCR1_SWCE , s->pBA0 + BA0_CLKCR1); | ||
| 1223 | } | ||
| 1224 | |||
| 1225 | // | ||
| 1226 | // Save the power state | ||
| 1227 | // | ||
| 1228 | pm->u32SSPMValue = readl(s->pBA0 + BA0_SSPM); | ||
| 1229 | |||
| 1230 | // | ||
| 1231 | // Disable interrupts. | ||
| 1232 | // | ||
| 1233 | writel(HICR_CHGM, s->pBA0 + BA0_HICR); | ||
| 1234 | |||
| 1235 | // | ||
| 1236 | // Save the PCM Playback Left and Right Volume Control. | ||
| 1237 | // | ||
| 1238 | pm->u32PPLVCvalue = readl(s->pBA0 + BA0_PPLVC); | ||
| 1239 | pm->u32PPRVCvalue = readl(s->pBA0 + BA0_PPRVC); | ||
| 1240 | |||
| 1241 | // | ||
| 1242 | // Save the FM Synthesis Left and Right Volume Control. | ||
| 1243 | // | ||
| 1244 | pm->u32FMLVCvalue = readl(s->pBA0 + BA0_FMLVC); | ||
| 1245 | pm->u32FMRVCvalue = readl(s->pBA0 + BA0_FMRVC); | ||
| 1246 | |||
| 1247 | // | ||
| 1248 | // Save the GPIOR value. | ||
| 1249 | // | ||
| 1250 | pm->u32GPIORvalue = readl(s->pBA0 + BA0_GPIOR); | ||
| 1251 | |||
| 1252 | // | ||
| 1253 | // Save the JSCTL value. | ||
| 1254 | // | ||
| 1255 | pm->u32JSCTLvalue = readl(s->pBA0 + BA0_GPIOR); | ||
| 1256 | |||
| 1257 | // | ||
| 1258 | // Save Sound System Control Register | ||
| 1259 | // | ||
| 1260 | pm->u32SSCR = readl(s->pBA0 + BA0_SSCR); | ||
| 1261 | |||
| 1262 | // | ||
| 1263 | // Save SRC Slot Assinment register | ||
| 1264 | // | ||
| 1265 | pm->u32SRCSA = readl(s->pBA0 + BA0_SRCSA); | ||
| 1266 | |||
| 1267 | // | ||
| 1268 | // Save sample rate | ||
| 1269 | // | ||
| 1270 | pm->u32DacASR = readl(s->pBA0 + BA0_PASR); | ||
| 1271 | pm->u32AdcASR = readl(s->pBA0 + BA0_CASR); | ||
| 1272 | pm->u32DacSR = readl(s->pBA0 + BA0_DACSR); | ||
| 1273 | pm->u32AdcSR = readl(s->pBA0 + BA0_ADCSR); | ||
| 1274 | |||
| 1275 | // | ||
| 1276 | // Loop through all of the PipeLines | ||
| 1277 | // | ||
| 1278 | for(i = 0; i < CS4281_NUMBER_OF_PIPELINES; i++) | ||
| 1279 | { | ||
| 1280 | if(s->pl[i].flags & CS4281_PIPELINE_VALID) | ||
| 1281 | { | ||
| 1282 | // | ||
| 1283 | // Ask the DMAengines and FIFOs to Suspend. | ||
| 1284 | // | ||
| 1285 | cs4281_SuspendDMAengine(s,&s->pl[i]); | ||
| 1286 | cs4281_SuspendFIFO(s,&s->pl[i]); | ||
| 1287 | } | ||
| 1288 | } | ||
| 1289 | // | ||
| 1290 | // We need to save the contents of the Midi Control Register. | ||
| 1291 | // | ||
| 1292 | pm->u32MIDCR_Save = readl(s->pBA0 + BA0_MIDCR); | ||
| 1293 | /* | ||
| 1294 | * save off the AC97 part information | ||
| 1295 | */ | ||
| 1296 | cs4281_ac97_suspend(s); | ||
| 1297 | |||
| 1298 | // | ||
| 1299 | // Turn off the serial ports. | ||
| 1300 | // | ||
| 1301 | writel(0, s->pBA0 + BA0_SERMC); | ||
| 1302 | |||
| 1303 | // | ||
| 1304 | // Power off FM, Joystick, AC link, | ||
| 1305 | // | ||
| 1306 | writel(0, s->pBA0 + BA0_SSPM); | ||
| 1307 | |||
| 1308 | // | ||
| 1309 | // DLL off. | ||
| 1310 | // | ||
| 1311 | writel(0, s->pBA0 + BA0_CLKCR1); | ||
| 1312 | |||
| 1313 | // | ||
| 1314 | // AC link off. | ||
| 1315 | // | ||
| 1316 | writel(0, s->pBA0 + BA0_SPMC); | ||
| 1317 | |||
| 1318 | // | ||
| 1319 | // Put the chip into D3(hot) state. | ||
| 1320 | // | ||
| 1321 | // PokeBA0(BA0_PMCS, 0x00000003); | ||
| 1322 | |||
| 1323 | // | ||
| 1324 | // Gershwin CLKRUN - Clear CKRA | ||
| 1325 | // | ||
| 1326 | u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1); | ||
| 1327 | writel(u32CLKCR1 & 0xFFFEFFFF, s->pBA0 + BA0_CLKCR1); | ||
| 1328 | |||
| 1329 | #ifdef CSDEBUG | ||
| 1330 | printpm(s); | ||
| 1331 | printpipelines(s); | ||
| 1332 | #endif | ||
| 1333 | |||
| 1334 | s->pm.flags &= ~CS4281_PM_SUSPENDING; | ||
| 1335 | s->pm.flags |= CS4281_PM_SUSPENDED; | ||
| 1336 | |||
| 1337 | CS_DBGOUT(CS_PM | CS_FUNCTION, 9, | ||
| 1338 | printk("cs4281: cs4281_suspend()- flags=%d\n", | ||
| 1339 | (unsigned)s->pm.flags)); | ||
| 1340 | return 0; | ||
| 1341 | } | ||
| 1342 | |||
| 1343 | static int cs4281_resume(struct cs4281_state *s) | ||
| 1344 | { | ||
| 1345 | int i; | ||
| 1346 | unsigned temp1; | ||
| 1347 | u32 u32CLKCR1; | ||
| 1348 | struct cs4281_pm *pm = &s->pm; | ||
| 1349 | CS_DBGOUT(CS_PM | CS_FUNCTION, 4, | ||
| 1350 | printk( "cs4281: cs4281_resume()+ flags=%d\n", | ||
| 1351 | (unsigned)s->pm.flags)); | ||
| 1352 | if(!(s->pm.flags & CS4281_PM_SUSPENDED)) | ||
| 1353 | { | ||
| 1354 | CS_DBGOUT(CS_PM | CS_ERROR, 2, | ||
| 1355 | printk("cs4281: cs4281_resume() unable to resume, not SUSPENDED\n")); | ||
| 1356 | return 1; | ||
| 1357 | } | ||
| 1358 | s->pm.flags &= ~CS4281_PM_SUSPENDED; | ||
| 1359 | s->pm.flags |= CS4281_PM_RESUMING; | ||
| 1360 | |||
| 1361 | // | ||
| 1362 | // Gershwin CLKRUN - Set CKRA | ||
| 1363 | // | ||
| 1364 | u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1); | ||
| 1365 | writel(u32CLKCR1 | 0x00010000, s->pBA0 + BA0_CLKCR1); | ||
| 1366 | |||
| 1367 | // | ||
| 1368 | // set the power state. | ||
| 1369 | // | ||
| 1370 | //old PokeBA0(BA0_PMCS, 0); | ||
| 1371 | |||
| 1372 | // | ||
| 1373 | // Program the clock circuit and serial ports. | ||
| 1374 | // | ||
| 1375 | temp1 = cs4281_hw_init(s); | ||
| 1376 | if (temp1) { | ||
| 1377 | CS_DBGOUT(CS_ERROR | CS_INIT, 1, | ||
| 1378 | printk(KERN_ERR | ||
| 1379 | "cs4281: resume cs4281_hw_init() error.\n")); | ||
| 1380 | return -1; | ||
| 1381 | } | ||
| 1382 | |||
| 1383 | // | ||
| 1384 | // restore the Power state | ||
| 1385 | // | ||
| 1386 | writel(pm->u32SSPMValue, s->pBA0 + BA0_SSPM); | ||
| 1387 | |||
| 1388 | // | ||
| 1389 | // Set post SRC mix setting (FM or ALT48K) | ||
| 1390 | // | ||
| 1391 | writel(pm->u32SSPM_BITS, s->pBA0 + BA0_SSPM); | ||
| 1392 | |||
| 1393 | // | ||
| 1394 | // Loop through all of the PipeLines | ||
| 1395 | // | ||
| 1396 | for(i = 0; i < CS4281_NUMBER_OF_PIPELINES; i++) | ||
| 1397 | { | ||
| 1398 | if(s->pl[i].flags & CS4281_PIPELINE_VALID) | ||
| 1399 | { | ||
| 1400 | // | ||
| 1401 | // Ask the DMAengines and FIFOs to Resume. | ||
| 1402 | // | ||
| 1403 | cs4281_ResumeDMAengine(s,&s->pl[i]); | ||
| 1404 | cs4281_ResumeFIFO(s,&s->pl[i]); | ||
| 1405 | } | ||
| 1406 | } | ||
| 1407 | // | ||
| 1408 | // We need to restore the contents of the Midi Control Register. | ||
| 1409 | // | ||
| 1410 | writel(pm->u32MIDCR_Save, s->pBA0 + BA0_MIDCR); | ||
| 1411 | |||
| 1412 | cs4281_ac97_resume(s); | ||
| 1413 | // | ||
| 1414 | // Restore the PCM Playback Left and Right Volume Control. | ||
| 1415 | // | ||
| 1416 | writel(pm->u32PPLVCvalue, s->pBA0 + BA0_PPLVC); | ||
| 1417 | writel(pm->u32PPRVCvalue, s->pBA0 + BA0_PPRVC); | ||
| 1418 | |||
| 1419 | // | ||
| 1420 | // Restore the FM Synthesis Left and Right Volume Control. | ||
| 1421 | // | ||
| 1422 | writel(pm->u32FMLVCvalue, s->pBA0 + BA0_FMLVC); | ||
| 1423 | writel(pm->u32FMRVCvalue, s->pBA0 + BA0_FMRVC); | ||
| 1424 | |||
| 1425 | // | ||
| 1426 | // Restore the JSCTL value. | ||
| 1427 | // | ||
| 1428 | writel(pm->u32JSCTLvalue, s->pBA0 + BA0_JSCTL); | ||
| 1429 | |||
| 1430 | // | ||
| 1431 | // Restore the GPIOR register value. | ||
| 1432 | // | ||
| 1433 | writel(pm->u32GPIORvalue, s->pBA0 + BA0_GPIOR); | ||
| 1434 | |||
| 1435 | // | ||
| 1436 | // Restore Sound System Control Register | ||
| 1437 | // | ||
| 1438 | writel(pm->u32SSCR, s->pBA0 + BA0_SSCR); | ||
| 1439 | |||
| 1440 | // | ||
| 1441 | // Restore SRC Slot Assignment register | ||
| 1442 | // | ||
| 1443 | writel(pm->u32SRCSA, s->pBA0 + BA0_SRCSA); | ||
| 1444 | |||
| 1445 | // | ||
| 1446 | // Restore sample rate | ||
| 1447 | // | ||
| 1448 | writel(pm->u32DacASR, s->pBA0 + BA0_PASR); | ||
| 1449 | writel(pm->u32AdcASR, s->pBA0 + BA0_CASR); | ||
| 1450 | writel(pm->u32DacSR, s->pBA0 + BA0_DACSR); | ||
| 1451 | writel(pm->u32AdcSR, s->pBA0 + BA0_ADCSR); | ||
| 1452 | |||
| 1453 | // | ||
| 1454 | // Restore CFL1/2 registers we saved to compensate for OEM bugs. | ||
| 1455 | // | ||
| 1456 | // PokeBA0(BA0_CFLR, ulConfig); | ||
| 1457 | |||
| 1458 | // | ||
| 1459 | // Gershwin CLKRUN - Clear CKRA | ||
| 1460 | // | ||
| 1461 | writel(pm->u32CLKCR1_SAVE, s->pBA0 + BA0_CLKCR1); | ||
| 1462 | |||
| 1463 | // | ||
| 1464 | // Enable interrupts on the part. | ||
| 1465 | // | ||
| 1466 | writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); | ||
| 1467 | |||
| 1468 | #ifdef CSDEBUG | ||
| 1469 | printpm(s); | ||
| 1470 | printpipelines(s); | ||
| 1471 | #endif | ||
| 1472 | /* | ||
| 1473 | * change the state, restore the current hwptrs, then stop the dac/adc | ||
| 1474 | */ | ||
| 1475 | s->pm.flags |= CS4281_PM_IDLE; | ||
| 1476 | s->pm.flags &= ~(CS4281_PM_SUSPENDING | CS4281_PM_SUSPENDED | ||
| 1477 | | CS4281_PM_RESUMING | CS4281_PM_RESUMED); | ||
| 1478 | |||
| 1479 | writel(s->pm.u32hwptr_playback, s->pBA0 + BA0_DCA0); | ||
| 1480 | writel(s->pm.u32hwptr_capture, s->pBA0 + BA0_DCA1); | ||
| 1481 | start_dac(s); | ||
| 1482 | start_adc(s); | ||
| 1483 | |||
| 1484 | CS_DBGOUT(CS_PM | CS_FUNCTION, 9, printk("cs4281: cs4281_resume()- flags=%d\n", | ||
| 1485 | (unsigned)s->pm.flags)); | ||
| 1486 | return 0; | ||
| 1487 | } | ||
| 1488 | |||
| 1489 | #endif | ||
| 1490 | |||
| 1491 | //****************************************************************************** | ||
| 1492 | // "cs4281_play_rate()" -- | ||
| 1493 | //****************************************************************************** | ||
| 1494 | static void cs4281_play_rate(struct cs4281_state *card, u32 playrate) | ||
| 1495 | { | ||
| 1496 | u32 DACSRvalue = 1; | ||
| 1497 | |||
| 1498 | // Based on the sample rate, program the DACSR register. | ||
| 1499 | if (playrate == 8000) | ||
| 1500 | DACSRvalue = 5; | ||
| 1501 | if (playrate == 11025) | ||
| 1502 | DACSRvalue = 4; | ||
| 1503 | else if (playrate == 22050) | ||
| 1504 | DACSRvalue = 2; | ||
| 1505 | else if (playrate == 44100) | ||
| 1506 | DACSRvalue = 1; | ||
| 1507 | else if ((playrate <= 48000) && (playrate >= 6023)) | ||
| 1508 | DACSRvalue = 24576000 / (playrate * 16); | ||
| 1509 | else if (playrate < 6023) | ||
| 1510 | // Not allowed by open. | ||
| 1511 | return; | ||
| 1512 | else if (playrate > 48000) | ||
| 1513 | // Not allowed by open. | ||
| 1514 | return; | ||
| 1515 | CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 2, printk(KERN_INFO | ||
| 1516 | "cs4281: cs4281_play_rate(): DACSRvalue=0x%.8x playrate=%d\n", | ||
| 1517 | DACSRvalue, playrate)); | ||
| 1518 | // Write the 'sample rate select code' | ||
| 1519 | // to the 'DAC Sample Rate' register. | ||
| 1520 | writel(DACSRvalue, card->pBA0 + BA0_DACSR); // (744h) | ||
| 1521 | } | ||
| 1522 | |||
| 1523 | //****************************************************************************** | ||
| 1524 | // "cs4281_record_rate()" -- Initialize the record sample rate converter. | ||
| 1525 | //****************************************************************************** | ||
| 1526 | static void cs4281_record_rate(struct cs4281_state *card, u32 outrate) | ||
| 1527 | { | ||
| 1528 | u32 ADCSRvalue = 1; | ||
| 1529 | |||
| 1530 | // | ||
| 1531 | // Based on the sample rate, program the ADCSR register | ||
| 1532 | // | ||
| 1533 | if (outrate == 8000) | ||
| 1534 | ADCSRvalue = 5; | ||
| 1535 | if (outrate == 11025) | ||
| 1536 | ADCSRvalue = 4; | ||
| 1537 | else if (outrate == 22050) | ||
| 1538 | ADCSRvalue = 2; | ||
| 1539 | else if (outrate == 44100) | ||
| 1540 | ADCSRvalue = 1; | ||
| 1541 | else if ((outrate <= 48000) && (outrate >= 6023)) | ||
| 1542 | ADCSRvalue = 24576000 / (outrate * 16); | ||
| 1543 | else if (outrate < 6023) { | ||
| 1544 | // Not allowed by open. | ||
| 1545 | return; | ||
| 1546 | } else if (outrate > 48000) { | ||
| 1547 | // Not allowed by open. | ||
| 1548 | return; | ||
| 1549 | } | ||
| 1550 | CS_DBGOUT(CS_WAVE_READ | CS_PARMS, 2, printk(KERN_INFO | ||
| 1551 | "cs4281: cs4281_record_rate(): ADCSRvalue=0x%.8x outrate=%d\n", | ||
| 1552 | ADCSRvalue, outrate)); | ||
| 1553 | // Write the 'sample rate select code | ||
| 1554 | // to the 'ADC Sample Rate' register. | ||
| 1555 | writel(ADCSRvalue, card->pBA0 + BA0_ADCSR); // (748h) | ||
| 1556 | } | ||
| 1557 | |||
| 1558 | |||
| 1559 | |||
| 1560 | static void stop_dac(struct cs4281_state *s) | ||
| 1561 | { | ||
| 1562 | unsigned long flags; | ||
| 1563 | unsigned temp1; | ||
| 1564 | |||
| 1565 | CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4281: stop_dac():\n")); | ||
| 1566 | spin_lock_irqsave(&s->lock, flags); | ||
| 1567 | s->ena &= ~FMODE_WRITE; | ||
| 1568 | temp1 = readl(s->pBA0 + BA0_DCR0) | DCRn_MSK; | ||
| 1569 | writel(temp1, s->pBA0 + BA0_DCR0); | ||
| 1570 | |||
| 1571 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 1572 | } | ||
| 1573 | |||
| 1574 | |||
| 1575 | static void start_dac(struct cs4281_state *s) | ||
| 1576 | { | ||
| 1577 | unsigned long flags; | ||
| 1578 | unsigned temp1; | ||
| 1579 | |||
| 1580 | CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4281: start_dac()+\n")); | ||
| 1581 | spin_lock_irqsave(&s->lock, flags); | ||
| 1582 | if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped || | ||
| 1583 | (s->dma_dac.count > 0 | ||
| 1584 | && s->dma_dac.ready)) | ||
| 1585 | #ifndef NOT_CS4281_PM | ||
| 1586 | && (s->pm.flags & CS4281_PM_IDLE)) | ||
| 1587 | #else | ||
| 1588 | ) | ||
| 1589 | #endif | ||
| 1590 | { | ||
| 1591 | s->ena |= FMODE_WRITE; | ||
| 1592 | temp1 = readl(s->pBA0 + BA0_DCR0) & ~DCRn_MSK; // Clear DMA0 channel mask. | ||
| 1593 | writel(temp1, s->pBA0 + BA0_DCR0); // Start DMA'ing. | ||
| 1594 | writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Enable interrupts. | ||
| 1595 | |||
| 1596 | writel(7, s->pBA0 + BA0_PPRVC); | ||
| 1597 | writel(7, s->pBA0 + BA0_PPLVC); | ||
| 1598 | CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO | ||
| 1599 | "cs4281: start_dac(): writel 0x%x start dma\n", temp1)); | ||
| 1600 | |||
| 1601 | } | ||
| 1602 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 1603 | CS_DBGOUT(CS_FUNCTION, 3, | ||
| 1604 | printk(KERN_INFO "cs4281: start_dac()-\n")); | ||
| 1605 | } | ||
| 1606 | |||
| 1607 | |||
| 1608 | static void stop_adc(struct cs4281_state *s) | ||
| 1609 | { | ||
| 1610 | unsigned long flags; | ||
| 1611 | unsigned temp1; | ||
| 1612 | |||
| 1613 | CS_DBGOUT(CS_FUNCTION, 3, | ||
| 1614 | printk(KERN_INFO "cs4281: stop_adc()+\n")); | ||
| 1615 | |||
| 1616 | spin_lock_irqsave(&s->lock, flags); | ||
| 1617 | s->ena &= ~FMODE_READ; | ||
| 1618 | |||
| 1619 | if (s->conversion == 1) { | ||
| 1620 | s->conversion = 0; | ||
| 1621 | s->prop_adc.fmt = s->prop_adc.fmt_original; | ||
| 1622 | } | ||
| 1623 | temp1 = readl(s->pBA0 + BA0_DCR1) | DCRn_MSK; | ||
| 1624 | writel(temp1, s->pBA0 + BA0_DCR1); | ||
| 1625 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 1626 | CS_DBGOUT(CS_FUNCTION, 3, | ||
| 1627 | printk(KERN_INFO "cs4281: stop_adc()-\n")); | ||
| 1628 | } | ||
| 1629 | |||
| 1630 | |||
| 1631 | static void start_adc(struct cs4281_state *s) | ||
| 1632 | { | ||
| 1633 | unsigned long flags; | ||
| 1634 | unsigned temp1; | ||
| 1635 | |||
| 1636 | CS_DBGOUT(CS_FUNCTION, 2, | ||
| 1637 | printk(KERN_INFO "cs4281: start_adc()+\n")); | ||
| 1638 | |||
| 1639 | if (!(s->ena & FMODE_READ) && | ||
| 1640 | (s->dma_adc.mapped || s->dma_adc.count <= | ||
| 1641 | (signed) (s->dma_adc.dmasize - 2 * s->dma_adc.fragsize)) | ||
| 1642 | && s->dma_adc.ready | ||
| 1643 | #ifndef NOT_CS4281_PM | ||
| 1644 | && (s->pm.flags & CS4281_PM_IDLE)) | ||
| 1645 | #else | ||
| 1646 | ) | ||
| 1647 | #endif | ||
| 1648 | { | ||
| 1649 | if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) { | ||
| 1650 | // | ||
| 1651 | // now only use 16 bit capture, due to truncation issue | ||
| 1652 | // in the chip, noticable distortion occurs. | ||
| 1653 | // allocate buffer and then convert from 16 bit to | ||
| 1654 | // 8 bit for the user buffer. | ||
| 1655 | // | ||
| 1656 | s->prop_adc.fmt_original = s->prop_adc.fmt; | ||
| 1657 | if (s->prop_adc.fmt & AFMT_S8) { | ||
| 1658 | s->prop_adc.fmt &= ~AFMT_S8; | ||
| 1659 | s->prop_adc.fmt |= AFMT_S16_LE; | ||
| 1660 | } | ||
| 1661 | if (s->prop_adc.fmt & AFMT_U8) { | ||
| 1662 | s->prop_adc.fmt &= ~AFMT_U8; | ||
| 1663 | s->prop_adc.fmt |= AFMT_U16_LE; | ||
| 1664 | } | ||
| 1665 | // | ||
| 1666 | // prog_dmabuf_adc performs a stop_adc() but that is | ||
| 1667 | // ok since we really haven't started the DMA yet. | ||
| 1668 | // | ||
| 1669 | prog_codec(s, CS_TYPE_ADC); | ||
| 1670 | |||
| 1671 | if (prog_dmabuf_adc(s) != 0) { | ||
| 1672 | CS_DBGOUT(CS_ERROR, 2, printk(KERN_INFO | ||
| 1673 | "cs4281: start_adc(): error in prog_dmabuf_adc\n")); | ||
| 1674 | } | ||
| 1675 | s->conversion = 1; | ||
| 1676 | } | ||
| 1677 | spin_lock_irqsave(&s->lock, flags); | ||
| 1678 | s->ena |= FMODE_READ; | ||
| 1679 | temp1 = readl(s->pBA0 + BA0_DCR1) & ~DCRn_MSK; // Clear DMA1 channel mask bit. | ||
| 1680 | writel(temp1, s->pBA0 + BA0_DCR1); // Start recording | ||
| 1681 | writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Enable interrupts. | ||
| 1682 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 1683 | |||
| 1684 | CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO | ||
| 1685 | "cs4281: start_adc(): writel 0x%x \n", temp1)); | ||
| 1686 | } | ||
| 1687 | CS_DBGOUT(CS_FUNCTION, 2, | ||
| 1688 | printk(KERN_INFO "cs4281: start_adc()-\n")); | ||
| 1689 | |||
| 1690 | } | ||
| 1691 | |||
| 1692 | |||
| 1693 | // --------------------------------------------------------------------- | ||
| 1694 | |||
| 1695 | #define DMABUF_MINORDER 1 // ==> min buffer size = 8K. | ||
| 1696 | |||
| 1697 | |||
| 1698 | static void dealloc_dmabuf(struct cs4281_state *s, struct dmabuf *db) | ||
| 1699 | { | ||
| 1700 | struct page *map, *mapend; | ||
| 1701 | |||
| 1702 | if (db->rawbuf) { | ||
| 1703 | // Undo prog_dmabuf()'s marking the pages as reserved | ||
| 1704 | mapend = | ||
| 1705 | virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - | ||
| 1706 | 1); | ||
| 1707 | for (map = virt_to_page(db->rawbuf); map <= mapend; map++) | ||
| 1708 | ClearPageReserved(map); | ||
| 1709 | free_dmabuf(s, db); | ||
| 1710 | } | ||
| 1711 | if (s->tmpbuff && (db->type == CS_TYPE_ADC)) { | ||
| 1712 | // Undo prog_dmabuf()'s marking the pages as reserved | ||
| 1713 | mapend = | ||
| 1714 | virt_to_page(s->tmpbuff + | ||
| 1715 | (PAGE_SIZE << s->buforder_tmpbuff) - 1); | ||
| 1716 | for (map = virt_to_page(s->tmpbuff); map <= mapend; map++) | ||
| 1717 | ClearPageReserved(map); | ||
| 1718 | free_dmabuf2(s, db); | ||
| 1719 | } | ||
| 1720 | s->tmpbuff = NULL; | ||
| 1721 | db->rawbuf = NULL; | ||
| 1722 | db->mapped = db->ready = 0; | ||
| 1723 | } | ||
| 1724 | |||
| 1725 | static int prog_dmabuf(struct cs4281_state *s, struct dmabuf *db) | ||
| 1726 | { | ||
| 1727 | int order; | ||
| 1728 | unsigned bytespersec, temp1; | ||
| 1729 | unsigned bufs, sample_shift = 0; | ||
| 1730 | struct page *map, *mapend; | ||
| 1731 | unsigned long df; | ||
| 1732 | |||
| 1733 | CS_DBGOUT(CS_FUNCTION, 2, | ||
| 1734 | printk(KERN_INFO "cs4281: prog_dmabuf()+\n")); | ||
| 1735 | db->hwptr = db->swptr = db->total_bytes = db->count = db->error = | ||
| 1736 | db->endcleared = db->blocks = db->wakeup = db->underrun = 0; | ||
| 1737 | /* | ||
| 1738 | * check for order within limits, but do not overwrite value, check | ||
| 1739 | * later for a fractional defaultorder (i.e. 100+). | ||
| 1740 | */ | ||
| 1741 | if((defaultorder > 0) && (defaultorder < 12)) | ||
| 1742 | df = defaultorder; | ||
| 1743 | else | ||
| 1744 | df = 1; | ||
| 1745 | |||
| 1746 | if (!db->rawbuf) { | ||
| 1747 | db->ready = db->mapped = 0; | ||
| 1748 | for (order = df; order >= DMABUF_MINORDER; order--) | ||
| 1749 | if ( (db->rawbuf = (void *) pci_alloc_consistent( | ||
| 1750 | s->pcidev, PAGE_SIZE << order, &db-> dmaaddr))) | ||
| 1751 | break; | ||
| 1752 | if (!db->rawbuf) { | ||
| 1753 | CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR | ||
| 1754 | "cs4281: prog_dmabuf(): unable to allocate rawbuf\n")); | ||
| 1755 | return -ENOMEM; | ||
| 1756 | } | ||
| 1757 | db->buforder = order; | ||
| 1758 | // Now mark the pages as reserved; otherwise the | ||
| 1759 | // remap_pfn_range() in cs4281_mmap doesn't work. | ||
| 1760 | // 1. get index to last page in mem_map array for rawbuf. | ||
| 1761 | mapend = virt_to_page(db->rawbuf + | ||
| 1762 | (PAGE_SIZE << db->buforder) - 1); | ||
| 1763 | |||
| 1764 | // 2. mark each physical page in range as 'reserved'. | ||
| 1765 | for (map = virt_to_page(db->rawbuf); map <= mapend; map++) | ||
| 1766 | SetPageReserved(map); | ||
| 1767 | } | ||
| 1768 | if (!s->tmpbuff && (db->type == CS_TYPE_ADC)) { | ||
| 1769 | for (order = df; order >= DMABUF_MINORDER; | ||
| 1770 | order--) | ||
| 1771 | if ( (s->tmpbuff = (void *) pci_alloc_consistent( | ||
| 1772 | s->pcidev, PAGE_SIZE << order, | ||
| 1773 | &s->dmaaddr_tmpbuff))) | ||
| 1774 | break; | ||
| 1775 | if (!s->tmpbuff) { | ||
| 1776 | CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR | ||
| 1777 | "cs4281: prog_dmabuf(): unable to allocate tmpbuff\n")); | ||
| 1778 | return -ENOMEM; | ||
| 1779 | } | ||
| 1780 | s->buforder_tmpbuff = order; | ||
| 1781 | // Now mark the pages as reserved; otherwise the | ||
| 1782 | // remap_pfn_range() in cs4281_mmap doesn't work. | ||
| 1783 | // 1. get index to last page in mem_map array for rawbuf. | ||
| 1784 | mapend = virt_to_page(s->tmpbuff + | ||
| 1785 | (PAGE_SIZE << s->buforder_tmpbuff) - 1); | ||
| 1786 | |||
| 1787 | // 2. mark each physical page in range as 'reserved'. | ||
| 1788 | for (map = virt_to_page(s->tmpbuff); map <= mapend; map++) | ||
| 1789 | SetPageReserved(map); | ||
| 1790 | } | ||
| 1791 | if (db->type == CS_TYPE_DAC) { | ||
| 1792 | if (s->prop_dac.fmt & (AFMT_S16_LE | AFMT_U16_LE)) | ||
| 1793 | sample_shift++; | ||
| 1794 | if (s->prop_dac.channels > 1) | ||
| 1795 | sample_shift++; | ||
| 1796 | bytespersec = s->prop_dac.rate << sample_shift; | ||
| 1797 | } else // CS_TYPE_ADC | ||
| 1798 | { | ||
| 1799 | if (s->prop_adc.fmt & (AFMT_S16_LE | AFMT_U16_LE)) | ||
| 1800 | sample_shift++; | ||
| 1801 | if (s->prop_adc.channels > 1) | ||
| 1802 | sample_shift++; | ||
| 1803 | bytespersec = s->prop_adc.rate << sample_shift; | ||
| 1804 | } | ||
| 1805 | bufs = PAGE_SIZE << db->buforder; | ||
| 1806 | |||
| 1807 | /* | ||
| 1808 | * added fractional "defaultorder" inputs. if >100 then use | ||
| 1809 | * defaultorder-100 as power of 2 for the buffer size. example: | ||
| 1810 | * 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size. | ||
| 1811 | */ | ||
| 1812 | if(defaultorder >= 100) | ||
| 1813 | { | ||
| 1814 | bufs = 1 << (defaultorder-100); | ||
| 1815 | } | ||
| 1816 | |||
| 1817 | #define INTERRUPT_RATE_MS 100 // Interrupt rate in milliseconds. | ||
| 1818 | db->numfrag = 2; | ||
| 1819 | /* | ||
| 1820 | * Nominal frag size(bytes/interrupt) | ||
| 1821 | */ | ||
| 1822 | temp1 = bytespersec / (1000 / INTERRUPT_RATE_MS); | ||
| 1823 | db->fragshift = 8; // Min 256 bytes. | ||
| 1824 | while (1 << db->fragshift < temp1) // Calc power of 2 frag size. | ||
| 1825 | db->fragshift += 1; | ||
| 1826 | db->fragsize = 1 << db->fragshift; | ||
| 1827 | db->dmasize = db->fragsize * 2; | ||
| 1828 | db->fragsamples = db->fragsize >> sample_shift; // # samples/fragment. | ||
| 1829 | |||
| 1830 | // If the calculated size is larger than the allocated | ||
| 1831 | // buffer, divide the allocated buffer into 2 fragments. | ||
| 1832 | if (db->dmasize > bufs) { | ||
| 1833 | |||
| 1834 | db->numfrag = 2; // Two fragments. | ||
| 1835 | db->fragsize = bufs >> 1; // Each 1/2 the alloc'ed buffer. | ||
| 1836 | db->fragsamples = db->fragsize >> sample_shift; // # samples/fragment. | ||
| 1837 | db->dmasize = bufs; // Use all the alloc'ed buffer. | ||
| 1838 | |||
| 1839 | db->fragshift = 0; // Calculate 'fragshift'. | ||
| 1840 | temp1 = db->fragsize; // update_ptr() uses it | ||
| 1841 | while ((temp1 >>= 1) > 1) // to calc 'total-bytes' | ||
| 1842 | db->fragshift += 1; // returned in DSP_GETI/OPTR. | ||
| 1843 | } | ||
| 1844 | CS_DBGOUT(CS_PARMS, 3, printk(KERN_INFO | ||
| 1845 | "cs4281: prog_dmabuf(): numfrag=%d fragsize=%d fragsamples=%d fragshift=%d bufs=%d fmt=0x%x ch=%d\n", | ||
| 1846 | db->numfrag, db->fragsize, db->fragsamples, | ||
| 1847 | db->fragshift, bufs, | ||
| 1848 | (db->type == CS_TYPE_DAC) ? s->prop_dac.fmt : | ||
| 1849 | s->prop_adc.fmt, | ||
| 1850 | (db->type == CS_TYPE_DAC) ? s->prop_dac.channels : | ||
| 1851 | s->prop_adc.channels)); | ||
| 1852 | CS_DBGOUT(CS_FUNCTION, 2, | ||
| 1853 | printk(KERN_INFO "cs4281: prog_dmabuf()-\n")); | ||
| 1854 | return 0; | ||
| 1855 | } | ||
| 1856 | |||
| 1857 | |||
| 1858 | static int prog_dmabuf_adc(struct cs4281_state *s) | ||
| 1859 | { | ||
| 1860 | unsigned long va; | ||
| 1861 | unsigned count; | ||
| 1862 | int c; | ||
| 1863 | stop_adc(s); | ||
| 1864 | s->dma_adc.type = CS_TYPE_ADC; | ||
| 1865 | if ((c = prog_dmabuf(s, &s->dma_adc))) | ||
| 1866 | return c; | ||
| 1867 | |||
| 1868 | if (s->dma_adc.rawbuf) { | ||
| 1869 | memset(s->dma_adc.rawbuf, | ||
| 1870 | (s->prop_adc. | ||
| 1871 | fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0, | ||
| 1872 | s->dma_adc.dmasize); | ||
| 1873 | } | ||
| 1874 | if (s->tmpbuff) { | ||
| 1875 | memset(s->tmpbuff, | ||
| 1876 | (s->prop_adc. | ||
| 1877 | fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0, | ||
| 1878 | PAGE_SIZE << s->buforder_tmpbuff); | ||
| 1879 | } | ||
| 1880 | |||
| 1881 | va = virt_to_bus(s->dma_adc.rawbuf); | ||
| 1882 | |||
| 1883 | count = s->dma_adc.dmasize; | ||
| 1884 | |||
| 1885 | if (s->prop_adc. | ||
| 1886 | fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) | ||
| 1887 | count /= 2; // 16-bit. | ||
| 1888 | |||
| 1889 | if (s->prop_adc.channels > 1) | ||
| 1890 | count /= 2; // Assume stereo. | ||
| 1891 | |||
| 1892 | CS_DBGOUT(CS_WAVE_READ, 3, printk(KERN_INFO | ||
| 1893 | "cs4281: prog_dmabuf_adc(): count=%d va=0x%.8x\n", | ||
| 1894 | count, (unsigned) va)); | ||
| 1895 | |||
| 1896 | writel(va, s->pBA0 + BA0_DBA1); // Set buffer start address. | ||
| 1897 | writel(count - 1, s->pBA0 + BA0_DBC1); // Set count. | ||
| 1898 | s->dma_adc.ready = 1; | ||
| 1899 | return 0; | ||
| 1900 | } | ||
| 1901 | |||
| 1902 | |||
| 1903 | static int prog_dmabuf_dac(struct cs4281_state *s) | ||
| 1904 | { | ||
| 1905 | unsigned long va; | ||
| 1906 | unsigned count; | ||
| 1907 | int c; | ||
| 1908 | stop_dac(s); | ||
| 1909 | s->dma_dac.type = CS_TYPE_DAC; | ||
| 1910 | if ((c = prog_dmabuf(s, &s->dma_dac))) | ||
| 1911 | return c; | ||
| 1912 | memset(s->dma_dac.rawbuf, | ||
| 1913 | (s->prop_dac.fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0, | ||
| 1914 | s->dma_dac.dmasize); | ||
| 1915 | |||
| 1916 | va = virt_to_bus(s->dma_dac.rawbuf); | ||
| 1917 | |||
| 1918 | count = s->dma_dac.dmasize; | ||
| 1919 | if (s->prop_dac. | ||
| 1920 | fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) | ||
| 1921 | count /= 2; // 16-bit. | ||
| 1922 | |||
| 1923 | if (s->prop_dac.channels > 1) | ||
| 1924 | count /= 2; // Assume stereo. | ||
| 1925 | |||
| 1926 | writel(va, s->pBA0 + BA0_DBA0); // Set buffer start address. | ||
| 1927 | writel(count - 1, s->pBA0 + BA0_DBC0); // Set count. | ||
| 1928 | |||
| 1929 | CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO | ||
| 1930 | "cs4281: prog_dmabuf_dac(): count=%d va=0x%.8x\n", | ||
| 1931 | count, (unsigned) va)); | ||
| 1932 | |||
| 1933 | s->dma_dac.ready = 1; | ||
| 1934 | return 0; | ||
| 1935 | } | ||
| 1936 | |||
| 1937 | |||
| 1938 | static void clear_advance(void *buf, unsigned bsize, unsigned bptr, | ||
| 1939 | unsigned len, unsigned char c) | ||
| 1940 | { | ||
| 1941 | if (bptr + len > bsize) { | ||
| 1942 | unsigned x = bsize - bptr; | ||
| 1943 | memset(((char *) buf) + bptr, c, x); | ||
| 1944 | bptr = 0; | ||
| 1945 | len -= x; | ||
| 1946 | } | ||
| 1947 | CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO | ||
| 1948 | "cs4281: clear_advance(): memset %d at %p for %d size \n", | ||
| 1949 | (unsigned)c, ((char *) buf) + bptr, len)); | ||
| 1950 | memset(((char *) buf) + bptr, c, len); | ||
| 1951 | } | ||
| 1952 | |||
| 1953 | |||
| 1954 | |||
| 1955 | // call with spinlock held! | ||
| 1956 | static void cs4281_update_ptr(struct cs4281_state *s, int intflag) | ||
| 1957 | { | ||
| 1958 | int diff; | ||
| 1959 | unsigned hwptr, va; | ||
| 1960 | |||
| 1961 | // update ADC pointer | ||
| 1962 | if (s->ena & FMODE_READ) { | ||
| 1963 | hwptr = readl(s->pBA0 + BA0_DCA1); // Read capture DMA address. | ||
| 1964 | va = virt_to_bus(s->dma_adc.rawbuf); | ||
| 1965 | hwptr -= (unsigned) va; | ||
| 1966 | diff = | ||
| 1967 | (s->dma_adc.dmasize + hwptr - | ||
| 1968 | s->dma_adc.hwptr) % s->dma_adc.dmasize; | ||
| 1969 | s->dma_adc.hwptr = hwptr; | ||
| 1970 | s->dma_adc.total_bytes += diff; | ||
| 1971 | s->dma_adc.count += diff; | ||
| 1972 | if (s->dma_adc.count > s->dma_adc.dmasize) | ||
| 1973 | s->dma_adc.count = s->dma_adc.dmasize; | ||
| 1974 | if (s->dma_adc.mapped) { | ||
| 1975 | if (s->dma_adc.count >= | ||
| 1976 | (signed) s->dma_adc.fragsize) wake_up(&s-> | ||
| 1977 | dma_adc. | ||
| 1978 | wait); | ||
| 1979 | } else { | ||
| 1980 | if (s->dma_adc.count > 0) | ||
| 1981 | wake_up(&s->dma_adc.wait); | ||
| 1982 | } | ||
| 1983 | CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO | ||
| 1984 | "cs4281: cs4281_update_ptr(): s=%p hwptr=%d total_bytes=%d count=%d \n", | ||
| 1985 | s, s->dma_adc.hwptr, s->dma_adc.total_bytes, s->dma_adc.count)); | ||
| 1986 | } | ||
| 1987 | // update DAC pointer | ||
| 1988 | // | ||
| 1989 | // check for end of buffer, means that we are going to wait for another interrupt | ||
| 1990 | // to allow silence to fill the fifos on the part, to keep pops down to a minimum. | ||
| 1991 | // | ||
| 1992 | if (s->ena & FMODE_WRITE) { | ||
| 1993 | hwptr = readl(s->pBA0 + BA0_DCA0); // Read play DMA address. | ||
| 1994 | va = virt_to_bus(s->dma_dac.rawbuf); | ||
| 1995 | hwptr -= (unsigned) va; | ||
| 1996 | diff = (s->dma_dac.dmasize + hwptr - | ||
| 1997 | s->dma_dac.hwptr) % s->dma_dac.dmasize; | ||
| 1998 | s->dma_dac.hwptr = hwptr; | ||
| 1999 | s->dma_dac.total_bytes += diff; | ||
| 2000 | if (s->dma_dac.mapped) { | ||
| 2001 | s->dma_dac.count += diff; | ||
| 2002 | if (s->dma_dac.count >= s->dma_dac.fragsize) { | ||
| 2003 | s->dma_dac.wakeup = 1; | ||
| 2004 | wake_up(&s->dma_dac.wait); | ||
| 2005 | if (s->dma_dac.count > s->dma_dac.dmasize) | ||
| 2006 | s->dma_dac.count &= | ||
| 2007 | s->dma_dac.dmasize - 1; | ||
| 2008 | } | ||
| 2009 | } else { | ||
| 2010 | s->dma_dac.count -= diff; | ||
| 2011 | if (s->dma_dac.count <= 0) { | ||
| 2012 | // | ||
| 2013 | // fill with silence, and do not shut down the DAC. | ||
| 2014 | // Continue to play silence until the _release. | ||
| 2015 | // | ||
| 2016 | CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO | ||
| 2017 | "cs4281: cs4281_update_ptr(): memset %d at %p for %d size \n", | ||
| 2018 | (unsigned)(s->prop_dac.fmt & | ||
| 2019 | (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0, | ||
| 2020 | s->dma_dac.rawbuf, s->dma_dac.dmasize)); | ||
| 2021 | memset(s->dma_dac.rawbuf, | ||
| 2022 | (s->prop_dac. | ||
| 2023 | fmt & (AFMT_U8 | AFMT_U16_LE)) ? | ||
| 2024 | 0x80 : 0, s->dma_dac.dmasize); | ||
| 2025 | if (s->dma_dac.count < 0) { | ||
| 2026 | s->dma_dac.underrun = 1; | ||
| 2027 | s->dma_dac.count = 0; | ||
| 2028 | CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO | ||
| 2029 | "cs4281: cs4281_update_ptr(): underrun\n")); | ||
| 2030 | } | ||
| 2031 | } else if (s->dma_dac.count <= | ||
| 2032 | (signed) s->dma_dac.fragsize | ||
| 2033 | && !s->dma_dac.endcleared) { | ||
| 2034 | clear_advance(s->dma_dac.rawbuf, | ||
| 2035 | s->dma_dac.dmasize, | ||
| 2036 | s->dma_dac.swptr, | ||
| 2037 | s->dma_dac.fragsize, | ||
| 2038 | (s->prop_dac. | ||
| 2039 | fmt & (AFMT_U8 | | ||
| 2040 | AFMT_U16_LE)) ? 0x80 | ||
| 2041 | : 0); | ||
| 2042 | s->dma_dac.endcleared = 1; | ||
| 2043 | } | ||
| 2044 | if ( (s->dma_dac.count <= (signed) s->dma_dac.dmasize/2) || | ||
| 2045 | intflag) | ||
| 2046 | { | ||
| 2047 | wake_up(&s->dma_dac.wait); | ||
| 2048 | } | ||
| 2049 | } | ||
| 2050 | CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO | ||
| 2051 | "cs4281: cs4281_update_ptr(): s=%p hwptr=%d total_bytes=%d count=%d \n", | ||
| 2052 | s, s->dma_dac.hwptr, s->dma_dac.total_bytes, s->dma_dac.count)); | ||
| 2053 | } | ||
| 2054 | } | ||
| 2055 | |||
| 2056 | |||
| 2057 | // --------------------------------------------------------------------- | ||
| 2058 | |||
| 2059 | static void prog_codec(struct cs4281_state *s, unsigned type) | ||
| 2060 | { | ||
| 2061 | unsigned long flags; | ||
| 2062 | unsigned temp1, format; | ||
| 2063 | |||
| 2064 | CS_DBGOUT(CS_FUNCTION, 2, | ||
| 2065 | printk(KERN_INFO "cs4281: prog_codec()+ \n")); | ||
| 2066 | |||
| 2067 | spin_lock_irqsave(&s->lock, flags); | ||
| 2068 | if (type == CS_TYPE_ADC) { | ||
| 2069 | temp1 = readl(s->pBA0 + BA0_DCR1); | ||
| 2070 | writel(temp1 | DCRn_MSK, s->pBA0 + BA0_DCR1); // Stop capture DMA, if active. | ||
| 2071 | |||
| 2072 | // program sampling rates | ||
| 2073 | // Note, for CS4281, capture & play rates can be set independently. | ||
| 2074 | cs4281_record_rate(s, s->prop_adc.rate); | ||
| 2075 | |||
| 2076 | // program ADC parameters | ||
| 2077 | format = DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE; | ||
| 2078 | if (s->prop_adc. | ||
| 2079 | fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) { // 16-bit | ||
| 2080 | if (s->prop_adc.fmt & (AFMT_S16_BE | AFMT_U16_BE)) // Big-endian? | ||
| 2081 | format |= DMRn_BEND; | ||
| 2082 | if (s->prop_adc.fmt & (AFMT_U16_LE | AFMT_U16_BE)) | ||
| 2083 | format |= DMRn_USIGN; // Unsigned. | ||
| 2084 | } else | ||
| 2085 | format |= DMRn_SIZE8 | DMRn_USIGN; // 8-bit, unsigned | ||
| 2086 | if (s->prop_adc.channels < 2) | ||
| 2087 | format |= DMRn_MONO; | ||
| 2088 | |||
| 2089 | writel(format, s->pBA0 + BA0_DMR1); | ||
| 2090 | |||
| 2091 | CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO | ||
| 2092 | "cs4281: prog_codec(): adc %s %s %s rate=%d DMR0 format=0x%.8x\n", | ||
| 2093 | (format & DMRn_SIZE8) ? "8" : "16", | ||
| 2094 | (format & DMRn_USIGN) ? "Unsigned" : "Signed", | ||
| 2095 | (format & DMRn_MONO) ? "Mono" : "Stereo", | ||
| 2096 | s->prop_adc.rate, format)); | ||
| 2097 | |||
| 2098 | s->ena &= ~FMODE_READ; // not capturing data yet | ||
| 2099 | } | ||
| 2100 | |||
| 2101 | |||
| 2102 | if (type == CS_TYPE_DAC) { | ||
| 2103 | temp1 = readl(s->pBA0 + BA0_DCR0); | ||
| 2104 | writel(temp1 | DCRn_MSK, s->pBA0 + BA0_DCR0); // Stop play DMA, if active. | ||
| 2105 | |||
| 2106 | // program sampling rates | ||
| 2107 | // Note, for CS4281, capture & play rates can be set independently. | ||
| 2108 | cs4281_play_rate(s, s->prop_dac.rate); | ||
| 2109 | |||
| 2110 | // program DAC parameters | ||
| 2111 | format = DMRn_DMA | DMRn_AUTO | DMRn_TR_READ; | ||
| 2112 | if (s->prop_dac. | ||
| 2113 | fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) { // 16-bit | ||
| 2114 | if (s->prop_dac.fmt & (AFMT_S16_BE | AFMT_U16_BE)) | ||
| 2115 | format |= DMRn_BEND; // Big Endian. | ||
| 2116 | if (s->prop_dac.fmt & (AFMT_U16_LE | AFMT_U16_BE)) | ||
| 2117 | format |= DMRn_USIGN; // Unsigned. | ||
| 2118 | } else | ||
| 2119 | format |= DMRn_SIZE8 | DMRn_USIGN; // 8-bit, unsigned | ||
| 2120 | |||
| 2121 | if (s->prop_dac.channels < 2) | ||
| 2122 | format |= DMRn_MONO; | ||
| 2123 | |||
| 2124 | writel(format, s->pBA0 + BA0_DMR0); | ||
| 2125 | |||
| 2126 | |||
| 2127 | CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO | ||
| 2128 | "cs4281: prog_codec(): dac %s %s %s rate=%d DMR0 format=0x%.8x\n", | ||
| 2129 | (format & DMRn_SIZE8) ? "8" : "16", | ||
| 2130 | (format & DMRn_USIGN) ? "Unsigned" : "Signed", | ||
| 2131 | (format & DMRn_MONO) ? "Mono" : "Stereo", | ||
| 2132 | s->prop_dac.rate, format)); | ||
| 2133 | |||
| 2134 | s->ena &= ~FMODE_WRITE; // not capturing data yet | ||
| 2135 | |||
| 2136 | } | ||
| 2137 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 2138 | CS_DBGOUT(CS_FUNCTION, 2, | ||
| 2139 | printk(KERN_INFO "cs4281: prog_codec()- \n")); | ||
| 2140 | } | ||
| 2141 | |||
| 2142 | |||
| 2143 | static int mixer_ioctl(struct cs4281_state *s, unsigned int cmd, | ||
| 2144 | unsigned long arg) | ||
| 2145 | { | ||
| 2146 | // Index to mixer_src[] is value of AC97 Input Mux Select Reg. | ||
| 2147 | // Value of array member is recording source Device ID Mask. | ||
| 2148 | static const unsigned int mixer_src[8] = { | ||
| 2149 | SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1, | ||
| 2150 | SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0 | ||
| 2151 | }; | ||
| 2152 | void __user *argp = (void __user *)arg; | ||
| 2153 | |||
| 2154 | // Index of mixtable1[] member is Device ID | ||
| 2155 | // and must be <= SOUND_MIXER_NRDEVICES. | ||
| 2156 | // Value of array member is index into s->mix.vol[] | ||
| 2157 | static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = { | ||
| 2158 | [SOUND_MIXER_PCM] = 1, // voice | ||
| 2159 | [SOUND_MIXER_LINE1] = 2, // AUX | ||
| 2160 | [SOUND_MIXER_CD] = 3, // CD | ||
| 2161 | [SOUND_MIXER_LINE] = 4, // Line | ||
| 2162 | [SOUND_MIXER_SYNTH] = 5, // FM | ||
| 2163 | [SOUND_MIXER_MIC] = 6, // Mic | ||
| 2164 | [SOUND_MIXER_SPEAKER] = 7, // Speaker | ||
| 2165 | [SOUND_MIXER_RECLEV] = 8, // Recording level | ||
| 2166 | [SOUND_MIXER_VOLUME] = 9 // Master Volume | ||
| 2167 | }; | ||
| 2168 | |||
| 2169 | |||
| 2170 | static const unsigned mixreg[] = { | ||
| 2171 | BA0_AC97_PCM_OUT_VOLUME, | ||
| 2172 | BA0_AC97_AUX_VOLUME, | ||
| 2173 | BA0_AC97_CD_VOLUME, | ||
| 2174 | BA0_AC97_LINE_IN_VOLUME | ||
| 2175 | }; | ||
| 2176 | unsigned char l, r, rl, rr, vidx; | ||
| 2177 | unsigned char attentbl[11] = | ||
| 2178 | { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 }; | ||
| 2179 | unsigned temp1; | ||
| 2180 | int i, val; | ||
| 2181 | |||
| 2182 | VALIDATE_STATE(s); | ||
| 2183 | CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO | ||
| 2184 | "cs4281: mixer_ioctl(): s=%p cmd=0x%.8x\n", s, cmd)); | ||
| 2185 | #if CSDEBUG | ||
| 2186 | cs_printioctl(cmd); | ||
| 2187 | #endif | ||
| 2188 | #if CSDEBUG_INTERFACE | ||
| 2189 | |||
| 2190 | if ((cmd == SOUND_MIXER_CS_GETDBGMASK) || | ||
| 2191 | (cmd == SOUND_MIXER_CS_SETDBGMASK) || | ||
| 2192 | (cmd == SOUND_MIXER_CS_GETDBGLEVEL) || | ||
| 2193 | (cmd == SOUND_MIXER_CS_SETDBGLEVEL) || | ||
| 2194 | (cmd == SOUND_MIXER_CS_APM)) | ||
| 2195 | { | ||
| 2196 | switch (cmd) { | ||
| 2197 | |||
| 2198 | case SOUND_MIXER_CS_GETDBGMASK: | ||
| 2199 | return put_user(cs_debugmask, | ||
| 2200 | (unsigned long __user *) argp); | ||
| 2201 | |||
| 2202 | case SOUND_MIXER_CS_GETDBGLEVEL: | ||
| 2203 | return put_user(cs_debuglevel, | ||
| 2204 | (unsigned long __user *) argp); | ||
| 2205 | |||
| 2206 | case SOUND_MIXER_CS_SETDBGMASK: | ||
| 2207 | if (get_user(val, (unsigned long __user *) argp)) | ||
| 2208 | return -EFAULT; | ||
| 2209 | cs_debugmask = val; | ||
| 2210 | return 0; | ||
| 2211 | |||
| 2212 | case SOUND_MIXER_CS_SETDBGLEVEL: | ||
| 2213 | if (get_user(val, (unsigned long __user *) argp)) | ||
| 2214 | return -EFAULT; | ||
| 2215 | cs_debuglevel = val; | ||
| 2216 | return 0; | ||
| 2217 | #ifndef NOT_CS4281_PM | ||
| 2218 | case SOUND_MIXER_CS_APM: | ||
| 2219 | if (get_user(val, (unsigned long __user *) argp)) | ||
| 2220 | return -EFAULT; | ||
| 2221 | if(val == CS_IOCTL_CMD_SUSPEND) | ||
| 2222 | cs4281_suspend(s); | ||
| 2223 | else if(val == CS_IOCTL_CMD_RESUME) | ||
| 2224 | cs4281_resume(s); | ||
| 2225 | else | ||
| 2226 | { | ||
| 2227 | CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO | ||
| 2228 | "cs4281: mixer_ioctl(): invalid APM cmd (%d)\n", | ||
| 2229 | val)); | ||
| 2230 | } | ||
| 2231 | return 0; | ||
| 2232 | #endif | ||
| 2233 | default: | ||
| 2234 | CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO | ||
| 2235 | "cs4281: mixer_ioctl(): ERROR unknown debug cmd\n")); | ||
| 2236 | return 0; | ||
| 2237 | } | ||
| 2238 | } | ||
| 2239 | #endif | ||
| 2240 | |||
| 2241 | if (cmd == SOUND_MIXER_PRIVATE1) { | ||
| 2242 | // enable/disable/query mixer preamp | ||
| 2243 | if (get_user(val, (int __user *) argp)) | ||
| 2244 | return -EFAULT; | ||
| 2245 | if (val != -1) { | ||
| 2246 | cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1); | ||
| 2247 | temp1 = val ? (temp1 | 0x40) : (temp1 & 0xffbf); | ||
| 2248 | cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1); | ||
| 2249 | } | ||
| 2250 | cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1); | ||
| 2251 | val = (temp1 & 0x40) ? 1 : 0; | ||
| 2252 | return put_user(val, (int __user *) argp); | ||
| 2253 | } | ||
| 2254 | if (cmd == SOUND_MIXER_PRIVATE2) { | ||
| 2255 | // enable/disable/query spatializer | ||
| 2256 | if (get_user(val, (int __user *)argp)) | ||
| 2257 | return -EFAULT; | ||
| 2258 | if (val != -1) { | ||
| 2259 | temp1 = (val & 0x3f) >> 2; | ||
| 2260 | cs4281_write_ac97(s, BA0_AC97_3D_CONTROL, temp1); | ||
| 2261 | cs4281_read_ac97(s, BA0_AC97_GENERAL_PURPOSE, | ||
| 2262 | &temp1); | ||
| 2263 | cs4281_write_ac97(s, BA0_AC97_GENERAL_PURPOSE, | ||
| 2264 | temp1 | 0x2000); | ||
| 2265 | } | ||
| 2266 | cs4281_read_ac97(s, BA0_AC97_3D_CONTROL, &temp1); | ||
| 2267 | return put_user((temp1 << 2) | 3, (int __user *)argp); | ||
| 2268 | } | ||
| 2269 | if (cmd == SOUND_MIXER_INFO) { | ||
| 2270 | mixer_info info; | ||
| 2271 | strlcpy(info.id, "CS4281", sizeof(info.id)); | ||
| 2272 | strlcpy(info.name, "Crystal CS4281", sizeof(info.name)); | ||
| 2273 | info.modify_counter = s->mix.modcnt; | ||
| 2274 | if (copy_to_user(argp, &info, sizeof(info))) | ||
| 2275 | return -EFAULT; | ||
| 2276 | return 0; | ||
| 2277 | } | ||
| 2278 | if (cmd == SOUND_OLD_MIXER_INFO) { | ||
| 2279 | _old_mixer_info info; | ||
| 2280 | strlcpy(info.id, "CS4281", sizeof(info.id)); | ||
| 2281 | strlcpy(info.name, "Crystal CS4281", sizeof(info.name)); | ||
| 2282 | if (copy_to_user(argp, &info, sizeof(info))) | ||
| 2283 | return -EFAULT; | ||
| 2284 | return 0; | ||
| 2285 | } | ||
| 2286 | if (cmd == OSS_GETVERSION) | ||
| 2287 | return put_user(SOUND_VERSION, (int __user *) argp); | ||
| 2288 | |||
| 2289 | if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int)) | ||
| 2290 | return -EINVAL; | ||
| 2291 | |||
| 2292 | // If ioctl has only the SIOC_READ bit(bit 31) | ||
| 2293 | // on, process the only-read commands. | ||
| 2294 | if (_SIOC_DIR(cmd) == _SIOC_READ) { | ||
| 2295 | switch (_IOC_NR(cmd)) { | ||
| 2296 | case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source | ||
| 2297 | cs4281_read_ac97(s, BA0_AC97_RECORD_SELECT, &temp1); | ||
| 2298 | return put_user(mixer_src[temp1&7], (int __user *)argp); | ||
| 2299 | |||
| 2300 | case SOUND_MIXER_DEVMASK: // Arg contains a bit for each supported device | ||
| 2301 | return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH | | ||
| 2302 | SOUND_MASK_CD | SOUND_MASK_LINE | | ||
| 2303 | SOUND_MASK_LINE1 | SOUND_MASK_MIC | | ||
| 2304 | SOUND_MASK_VOLUME | | ||
| 2305 | SOUND_MASK_RECLEV | | ||
| 2306 | SOUND_MASK_SPEAKER, (int __user *)argp); | ||
| 2307 | |||
| 2308 | case SOUND_MIXER_RECMASK: // Arg contains a bit for each supported recording source | ||
| 2309 | return put_user(SOUND_MASK_LINE | SOUND_MASK_MIC | | ||
| 2310 | SOUND_MASK_CD | SOUND_MASK_VOLUME | | ||
| 2311 | SOUND_MASK_LINE1, (int __user *) argp); | ||
| 2312 | |||
| 2313 | case SOUND_MIXER_STEREODEVS: // Mixer channels supporting stereo | ||
| 2314 | return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH | | ||
| 2315 | SOUND_MASK_CD | SOUND_MASK_LINE | | ||
| 2316 | SOUND_MASK_LINE1 | SOUND_MASK_MIC | | ||
| 2317 | SOUND_MASK_VOLUME | | ||
| 2318 | SOUND_MASK_RECLEV, (int __user *)argp); | ||
| 2319 | |||
| 2320 | case SOUND_MIXER_CAPS: | ||
| 2321 | return put_user(SOUND_CAP_EXCL_INPUT, (int __user *)argp); | ||
| 2322 | |||
| 2323 | default: | ||
| 2324 | i = _IOC_NR(cmd); | ||
| 2325 | if (i >= SOUND_MIXER_NRDEVICES | ||
| 2326 | || !(vidx = mixtable1[i])) | ||
| 2327 | return -EINVAL; | ||
| 2328 | return put_user(s->mix.vol[vidx - 1], (int __user *)argp); | ||
| 2329 | } | ||
| 2330 | } | ||
| 2331 | // If ioctl doesn't have both the SIOC_READ and | ||
| 2332 | // the SIOC_WRITE bit set, return invalid. | ||
| 2333 | if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE)) | ||
| 2334 | return -EINVAL; | ||
| 2335 | |||
| 2336 | // Increment the count of volume writes. | ||
| 2337 | s->mix.modcnt++; | ||
| 2338 | |||
| 2339 | // Isolate the command; it must be a write. | ||
| 2340 | switch (_IOC_NR(cmd)) { | ||
| 2341 | |||
| 2342 | case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source | ||
| 2343 | if (get_user(val, (int __user *)argp)) | ||
| 2344 | return -EFAULT; | ||
| 2345 | i = hweight32(val); // i = # bits on in val. | ||
| 2346 | if (i != 1) // One & only 1 bit must be on. | ||
| 2347 | return 0; | ||
| 2348 | for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) { | ||
| 2349 | if (val == mixer_src[i]) { | ||
| 2350 | temp1 = (i << 8) | i; | ||
| 2351 | cs4281_write_ac97(s, | ||
| 2352 | BA0_AC97_RECORD_SELECT, | ||
| 2353 | temp1); | ||
| 2354 | return 0; | ||
| 2355 | } | ||
| 2356 | } | ||
| 2357 | return 0; | ||
| 2358 | |||
| 2359 | case SOUND_MIXER_VOLUME: | ||
| 2360 | if (get_user(val, (int __user *)argp)) | ||
| 2361 | return -EFAULT; | ||
| 2362 | l = val & 0xff; | ||
| 2363 | if (l > 100) | ||
| 2364 | l = 100; // Max soundcard.h vol is 100. | ||
| 2365 | if (l < 6) { | ||
| 2366 | rl = 63; | ||
| 2367 | l = 0; | ||
| 2368 | } else | ||
| 2369 | rl = attentbl[(10 * l) / 100]; // Convert 0-100 vol to 63-0 atten. | ||
| 2370 | |||
| 2371 | r = (val >> 8) & 0xff; | ||
| 2372 | if (r > 100) | ||
| 2373 | r = 100; // Max right volume is 100, too | ||
| 2374 | if (r < 6) { | ||
| 2375 | rr = 63; | ||
| 2376 | r = 0; | ||
| 2377 | } else | ||
| 2378 | rr = attentbl[(10 * r) / 100]; // Convert volume to attenuation. | ||
| 2379 | |||
| 2380 | if ((rl > 60) && (rr > 60)) // If both l & r are 'low', | ||
| 2381 | temp1 = 0x8000; // turn on the mute bit. | ||
| 2382 | else | ||
| 2383 | temp1 = 0; | ||
| 2384 | |||
| 2385 | temp1 |= (rl << 8) | rr; | ||
| 2386 | |||
| 2387 | cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME, temp1); | ||
| 2388 | cs4281_write_ac97(s, BA0_AC97_HEADPHONE_VOLUME, temp1); | ||
| 2389 | |||
| 2390 | #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS | ||
| 2391 | s->mix.vol[8] = ((unsigned int) r << 8) | l; | ||
| 2392 | #else | ||
| 2393 | s->mix.vol[8] = val; | ||
| 2394 | #endif | ||
| 2395 | return put_user(s->mix.vol[8], (int __user *)argp); | ||
| 2396 | |||
| 2397 | case SOUND_MIXER_SPEAKER: | ||
| 2398 | if (get_user(val, (int __user *)argp)) | ||
| 2399 | return -EFAULT; | ||
| 2400 | l = val & 0xff; | ||
| 2401 | if (l > 100) | ||
| 2402 | l = 100; | ||
| 2403 | if (l < 3) { | ||
| 2404 | rl = 0; | ||
| 2405 | l = 0; | ||
| 2406 | } else { | ||
| 2407 | rl = (l * 2 - 5) / 13; // Convert 0-100 range to 0-15. | ||
| 2408 | l = (rl * 13 + 5) / 2; | ||
| 2409 | } | ||
| 2410 | |||
| 2411 | if (rl < 3) { | ||
| 2412 | temp1 = 0x8000; | ||
| 2413 | rl = 0; | ||
| 2414 | } else | ||
| 2415 | temp1 = 0; | ||
| 2416 | rl = 15 - rl; // Convert volume to attenuation. | ||
| 2417 | temp1 |= rl << 1; | ||
| 2418 | cs4281_write_ac97(s, BA0_AC97_PC_BEEP_VOLUME, temp1); | ||
| 2419 | |||
| 2420 | #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS | ||
| 2421 | s->mix.vol[6] = l << 8; | ||
| 2422 | #else | ||
| 2423 | s->mix.vol[6] = val; | ||
| 2424 | #endif | ||
| 2425 | return put_user(s->mix.vol[6], (int __user *)argp); | ||
| 2426 | |||
| 2427 | case SOUND_MIXER_RECLEV: | ||
| 2428 | if (get_user(val, (int __user *)argp)) | ||
| 2429 | return -EFAULT; | ||
| 2430 | l = val & 0xff; | ||
| 2431 | if (l > 100) | ||
| 2432 | l = 100; | ||
| 2433 | r = (val >> 8) & 0xff; | ||
| 2434 | if (r > 100) | ||
| 2435 | r = 100; | ||
| 2436 | rl = (l * 2 - 5) / 13; // Convert 0-100 scale to 0-15. | ||
| 2437 | rr = (r * 2 - 5) / 13; | ||
| 2438 | if (rl < 3 && rr < 3) | ||
| 2439 | temp1 = 0x8000; | ||
| 2440 | else | ||
| 2441 | temp1 = 0; | ||
| 2442 | |||
| 2443 | temp1 = temp1 | (rl << 8) | rr; | ||
| 2444 | cs4281_write_ac97(s, BA0_AC97_RECORD_GAIN, temp1); | ||
| 2445 | |||
| 2446 | #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS | ||
| 2447 | s->mix.vol[7] = ((unsigned int) r << 8) | l; | ||
| 2448 | #else | ||
| 2449 | s->mix.vol[7] = val; | ||
| 2450 | #endif | ||
| 2451 | return put_user(s->mix.vol[7], (int __user *)argp); | ||
| 2452 | |||
| 2453 | case SOUND_MIXER_MIC: | ||
| 2454 | if (get_user(val, (int __user *)argp)) | ||
| 2455 | return -EFAULT; | ||
| 2456 | l = val & 0xff; | ||
| 2457 | if (l > 100) | ||
| 2458 | l = 100; | ||
| 2459 | if (l < 1) { | ||
| 2460 | l = 0; | ||
| 2461 | rl = 0; | ||
| 2462 | } else { | ||
| 2463 | rl = ((unsigned) l * 5 - 4) / 16; // Convert 0-100 range to 0-31. | ||
| 2464 | l = (rl * 16 + 4) / 5; | ||
| 2465 | } | ||
| 2466 | cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1); | ||
| 2467 | temp1 &= 0x40; // Isolate 20db gain bit. | ||
| 2468 | if (rl < 3) { | ||
| 2469 | temp1 |= 0x8000; | ||
| 2470 | rl = 0; | ||
| 2471 | } | ||
| 2472 | rl = 31 - rl; // Convert volume to attenuation. | ||
| 2473 | temp1 |= rl; | ||
| 2474 | cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1); | ||
| 2475 | |||
| 2476 | #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS | ||
| 2477 | s->mix.vol[5] = val << 8; | ||
| 2478 | #else | ||
| 2479 | s->mix.vol[5] = val; | ||
| 2480 | #endif | ||
| 2481 | return put_user(s->mix.vol[5], (int __user *)argp); | ||
| 2482 | |||
| 2483 | |||
| 2484 | case SOUND_MIXER_SYNTH: | ||
| 2485 | if (get_user(val, (int __user *)argp)) | ||
| 2486 | return -EFAULT; | ||
| 2487 | l = val & 0xff; | ||
| 2488 | if (l > 100) | ||
| 2489 | l = 100; | ||
| 2490 | if (get_user(val, (int __user *)argp)) | ||
| 2491 | return -EFAULT; | ||
| 2492 | r = (val >> 8) & 0xff; | ||
| 2493 | if (r > 100) | ||
| 2494 | r = 100; | ||
| 2495 | rl = (l * 2 - 11) / 3; // Convert 0-100 range to 0-63. | ||
| 2496 | rr = (r * 2 - 11) / 3; | ||
| 2497 | if (rl < 3) // If l is low, turn on | ||
| 2498 | temp1 = 0x0080; // the mute bit. | ||
| 2499 | else | ||
| 2500 | temp1 = 0; | ||
| 2501 | |||
| 2502 | rl = 63 - rl; // Convert vol to attenuation. | ||
| 2503 | writel(temp1 | rl, s->pBA0 + BA0_FMLVC); | ||
| 2504 | if (rr < 3) // If rr is low, turn on | ||
| 2505 | temp1 = 0x0080; // the mute bit. | ||
| 2506 | else | ||
| 2507 | temp1 = 0; | ||
| 2508 | rr = 63 - rr; // Convert vol to attenuation. | ||
| 2509 | writel(temp1 | rr, s->pBA0 + BA0_FMRVC); | ||
| 2510 | |||
| 2511 | #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS | ||
| 2512 | s->mix.vol[4] = (r << 8) | l; | ||
| 2513 | #else | ||
| 2514 | s->mix.vol[4] = val; | ||
| 2515 | #endif | ||
| 2516 | return put_user(s->mix.vol[4], (int __user *)argp); | ||
| 2517 | |||
| 2518 | |||
| 2519 | default: | ||
| 2520 | CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO | ||
| 2521 | "cs4281: mixer_ioctl(): default\n")); | ||
| 2522 | |||
| 2523 | i = _IOC_NR(cmd); | ||
| 2524 | if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i])) | ||
| 2525 | return -EINVAL; | ||
| 2526 | if (get_user(val, (int __user *)argp)) | ||
| 2527 | return -EFAULT; | ||
| 2528 | l = val & 0xff; | ||
| 2529 | if (l > 100) | ||
| 2530 | l = 100; | ||
| 2531 | if (l < 1) { | ||
| 2532 | l = 0; | ||
| 2533 | rl = 31; | ||
| 2534 | } else | ||
| 2535 | rl = (attentbl[(l * 10) / 100]) >> 1; | ||
| 2536 | |||
| 2537 | r = (val >> 8) & 0xff; | ||
| 2538 | if (r > 100) | ||
| 2539 | r = 100; | ||
| 2540 | if (r < 1) { | ||
| 2541 | r = 0; | ||
| 2542 | rr = 31; | ||
| 2543 | } else | ||
| 2544 | rr = (attentbl[(r * 10) / 100]) >> 1; | ||
| 2545 | if ((rl > 30) && (rr > 30)) | ||
| 2546 | temp1 = 0x8000; | ||
| 2547 | else | ||
| 2548 | temp1 = 0; | ||
| 2549 | temp1 = temp1 | (rl << 8) | rr; | ||
| 2550 | cs4281_write_ac97(s, mixreg[vidx - 1], temp1); | ||
| 2551 | |||
| 2552 | #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS | ||
| 2553 | s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l; | ||
| 2554 | #else | ||
| 2555 | s->mix.vol[vidx - 1] = val; | ||
| 2556 | #endif | ||
| 2557 | #ifndef NOT_CS4281_PM | ||
| 2558 | CS_DBGOUT(CS_PM, 9, printk(KERN_INFO | ||
| 2559 | "write ac97 mixreg[%d]=0x%x mix.vol[]=0x%x\n", | ||
| 2560 | vidx-1,temp1,s->mix.vol[vidx-1])); | ||
| 2561 | #endif | ||
| 2562 | return put_user(s->mix.vol[vidx - 1], (int __user *)argp); | ||
| 2563 | } | ||
| 2564 | } | ||
| 2565 | |||
| 2566 | |||
| 2567 | // --------------------------------------------------------------------- | ||
| 2568 | |||
| 2569 | static int cs4281_open_mixdev(struct inode *inode, struct file *file) | ||
| 2570 | { | ||
| 2571 | unsigned int minor = iminor(inode); | ||
| 2572 | struct cs4281_state *s=NULL; | ||
| 2573 | struct list_head *entry; | ||
| 2574 | |||
| 2575 | CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4, | ||
| 2576 | printk(KERN_INFO "cs4281: cs4281_open_mixdev()+\n")); | ||
| 2577 | |||
| 2578 | list_for_each(entry, &cs4281_devs) | ||
| 2579 | { | ||
| 2580 | s = list_entry(entry, struct cs4281_state, list); | ||
| 2581 | if(s->dev_mixer == minor) | ||
| 2582 | break; | ||
| 2583 | } | ||
| 2584 | if (!s) | ||
| 2585 | { | ||
| 2586 | CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, | ||
| 2587 | printk(KERN_INFO "cs4281: cs4281_open_mixdev()- -ENODEV\n")); | ||
| 2588 | return -ENODEV; | ||
| 2589 | } | ||
| 2590 | VALIDATE_STATE(s); | ||
| 2591 | file->private_data = s; | ||
| 2592 | |||
| 2593 | CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4, | ||
| 2594 | printk(KERN_INFO "cs4281: cs4281_open_mixdev()- 0\n")); | ||
| 2595 | |||
| 2596 | return nonseekable_open(inode, file); | ||
| 2597 | } | ||
| 2598 | |||
| 2599 | |||
| 2600 | static int cs4281_release_mixdev(struct inode *inode, struct file *file) | ||
| 2601 | { | ||
| 2602 | struct cs4281_state *s = | ||
| 2603 | (struct cs4281_state *) file->private_data; | ||
| 2604 | |||
| 2605 | VALIDATE_STATE(s); | ||
| 2606 | return 0; | ||
| 2607 | } | ||
| 2608 | |||
| 2609 | |||
| 2610 | static int cs4281_ioctl_mixdev(struct inode *inode, struct file *file, | ||
| 2611 | unsigned int cmd, unsigned long arg) | ||
| 2612 | { | ||
| 2613 | return mixer_ioctl((struct cs4281_state *) file->private_data, cmd, | ||
| 2614 | arg); | ||
| 2615 | } | ||
| 2616 | |||
| 2617 | |||
| 2618 | // ****************************************************************************************** | ||
| 2619 | // Mixer file operations struct. | ||
| 2620 | // ****************************************************************************************** | ||
| 2621 | static /*const */ struct file_operations cs4281_mixer_fops = { | ||
| 2622 | .owner = THIS_MODULE, | ||
| 2623 | .llseek = no_llseek, | ||
| 2624 | .ioctl = cs4281_ioctl_mixdev, | ||
| 2625 | .open = cs4281_open_mixdev, | ||
| 2626 | .release = cs4281_release_mixdev, | ||
| 2627 | }; | ||
| 2628 | |||
| 2629 | // --------------------------------------------------------------------- | ||
| 2630 | |||
| 2631 | |||
| 2632 | static int drain_adc(struct cs4281_state *s, int nonblock) | ||
| 2633 | { | ||
| 2634 | DECLARE_WAITQUEUE(wait, current); | ||
| 2635 | unsigned long flags; | ||
| 2636 | int count; | ||
| 2637 | unsigned tmo; | ||
| 2638 | |||
| 2639 | if (s->dma_adc.mapped) | ||
| 2640 | return 0; | ||
| 2641 | add_wait_queue(&s->dma_adc.wait, &wait); | ||
| 2642 | for (;;) { | ||
| 2643 | set_current_state(TASK_INTERRUPTIBLE); | ||
| 2644 | spin_lock_irqsave(&s->lock, flags); | ||
| 2645 | count = s->dma_adc.count; | ||
| 2646 | CS_DBGOUT(CS_FUNCTION, 2, | ||
| 2647 | printk(KERN_INFO "cs4281: drain_adc() %d\n", count)); | ||
| 2648 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 2649 | if (count <= 0) { | ||
| 2650 | CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_INFO | ||
| 2651 | "cs4281: drain_adc() count<0\n")); | ||
| 2652 | break; | ||
| 2653 | } | ||
| 2654 | if (signal_pending(current)) | ||
| 2655 | break; | ||
| 2656 | if (nonblock) { | ||
| 2657 | remove_wait_queue(&s->dma_adc.wait, &wait); | ||
| 2658 | current->state = TASK_RUNNING; | ||
| 2659 | return -EBUSY; | ||
| 2660 | } | ||
| 2661 | tmo = | ||
| 2662 | 3 * HZ * (count + | ||
| 2663 | s->dma_adc.fragsize) / 2 / s->prop_adc.rate; | ||
| 2664 | if (s->prop_adc.fmt & (AFMT_S16_LE | AFMT_U16_LE)) | ||
| 2665 | tmo >>= 1; | ||
| 2666 | if (s->prop_adc.channels > 1) | ||
| 2667 | tmo >>= 1; | ||
| 2668 | if (!schedule_timeout(tmo + 1)) | ||
| 2669 | printk(KERN_DEBUG "cs4281: dma timed out??\n"); | ||
| 2670 | } | ||
| 2671 | remove_wait_queue(&s->dma_adc.wait, &wait); | ||
| 2672 | current->state = TASK_RUNNING; | ||
| 2673 | if (signal_pending(current)) | ||
| 2674 | return -ERESTARTSYS; | ||
| 2675 | return 0; | ||
| 2676 | } | ||
| 2677 | |||
| 2678 | static int drain_dac(struct cs4281_state *s, int nonblock) | ||
| 2679 | { | ||
| 2680 | DECLARE_WAITQUEUE(wait, current); | ||
| 2681 | unsigned long flags; | ||
| 2682 | int count; | ||
| 2683 | unsigned tmo; | ||
| 2684 | |||
| 2685 | if (s->dma_dac.mapped) | ||
| 2686 | return 0; | ||
| 2687 | add_wait_queue(&s->dma_dac.wait, &wait); | ||
| 2688 | for (;;) { | ||
| 2689 | set_current_state(TASK_INTERRUPTIBLE); | ||
| 2690 | spin_lock_irqsave(&s->lock, flags); | ||
| 2691 | count = s->dma_dac.count; | ||
| 2692 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 2693 | if (count <= 0) | ||
| 2694 | break; | ||
| 2695 | if (signal_pending(current)) | ||
| 2696 | break; | ||
| 2697 | if (nonblock) { | ||
| 2698 | remove_wait_queue(&s->dma_dac.wait, &wait); | ||
| 2699 | current->state = TASK_RUNNING; | ||
| 2700 | return -EBUSY; | ||
| 2701 | } | ||
| 2702 | tmo = | ||
| 2703 | 3 * HZ * (count + | ||
| 2704 | s->dma_dac.fragsize) / 2 / s->prop_dac.rate; | ||
| 2705 | if (s->prop_dac.fmt & (AFMT_S16_LE | AFMT_U16_LE)) | ||
| 2706 | tmo >>= 1; | ||
| 2707 | if (s->prop_dac.channels > 1) | ||
| 2708 | tmo >>= 1; | ||
| 2709 | if (!schedule_timeout(tmo + 1)) | ||
| 2710 | printk(KERN_DEBUG "cs4281: dma timed out??\n"); | ||
| 2711 | } | ||
| 2712 | remove_wait_queue(&s->dma_dac.wait, &wait); | ||
| 2713 | current->state = TASK_RUNNING; | ||
| 2714 | if (signal_pending(current)) | ||
| 2715 | return -ERESTARTSYS; | ||
| 2716 | return 0; | ||
| 2717 | } | ||
| 2718 | |||
| 2719 | //**************************************************************************** | ||
| 2720 | // | ||
| 2721 | // CopySamples copies 16-bit stereo samples from the source to the | ||
| 2722 | // destination, possibly converting down to either 8-bit or mono or both. | ||
| 2723 | // count specifies the number of output bytes to write. | ||
| 2724 | // | ||
| 2725 | // Arguments: | ||
| 2726 | // | ||
| 2727 | // dst - Pointer to a destination buffer. | ||
| 2728 | // src - Pointer to a source buffer | ||
| 2729 | // count - The number of bytes to copy into the destination buffer. | ||
| 2730 | // iChannels - Stereo - 2 | ||
| 2731 | // Mono - 1 | ||
| 2732 | // fmt - AFMT_xxx (soundcard.h formats) | ||
| 2733 | // | ||
| 2734 | // NOTES: only call this routine for conversion to 8bit from 16bit | ||
| 2735 | // | ||
| 2736 | //**************************************************************************** | ||
| 2737 | static void CopySamples(char *dst, char *src, int count, int iChannels, | ||
| 2738 | unsigned fmt) | ||
| 2739 | { | ||
| 2740 | |||
| 2741 | unsigned short *psSrc; | ||
| 2742 | long lAudioSample; | ||
| 2743 | |||
| 2744 | CS_DBGOUT(CS_FUNCTION, 2, | ||
| 2745 | printk(KERN_INFO "cs4281: CopySamples()+ ")); | ||
| 2746 | CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO | ||
| 2747 | " dst=%p src=%p count=%d iChannels=%d fmt=0x%x\n", | ||
| 2748 | dst, src, (unsigned) count, (unsigned) iChannels, (unsigned) fmt)); | ||
| 2749 | |||
| 2750 | // Gershwin does format conversion in hardware so normally | ||
| 2751 | // we don't do any host based coversion. The data formatter | ||
| 2752 | // truncates 16 bit data to 8 bit and that causes some hiss. | ||
| 2753 | // We have already forced the HW to do 16 bit sampling and | ||
| 2754 | // 2 channel so that we can use software to round instead | ||
| 2755 | // of truncate | ||
| 2756 | |||
| 2757 | // | ||
| 2758 | // See if the data should be output as 8-bit unsigned stereo. | ||
| 2759 | // or if the data should be output at 8-bit unsigned mono. | ||
| 2760 | // | ||
| 2761 | if ( ((iChannels == 2) && (fmt & AFMT_U8)) || | ||
| 2762 | ((iChannels == 1) && (fmt & AFMT_U8)) ) { | ||
| 2763 | // | ||
| 2764 | // Convert each 16-bit unsigned stereo sample to 8-bit unsigned | ||
| 2765 | // stereo using rounding. | ||
| 2766 | // | ||
| 2767 | psSrc = (unsigned short *) src; | ||
| 2768 | count = count / 2; | ||
| 2769 | while (count--) { | ||
| 2770 | lAudioSample = (long) psSrc[count] + (long) 0x80; | ||
| 2771 | if (lAudioSample > 0xffff) { | ||
| 2772 | lAudioSample = 0xffff; | ||
| 2773 | } | ||
| 2774 | dst[count] = (char) (lAudioSample >> 8); | ||
| 2775 | } | ||
| 2776 | } | ||
| 2777 | // | ||
| 2778 | // check for 8-bit signed stereo. | ||
| 2779 | // | ||
| 2780 | else if ((iChannels == 2) && (fmt & AFMT_S8)) { | ||
| 2781 | // | ||
| 2782 | // Convert each 16-bit stereo sample to 8-bit stereo using rounding. | ||
| 2783 | // | ||
| 2784 | psSrc = (short *) src; | ||
| 2785 | while (count--) { | ||
| 2786 | lAudioSample = | ||
| 2787 | (((long) psSrc[0] + (long) psSrc[1]) / 2); | ||
| 2788 | psSrc += 2; | ||
| 2789 | *dst++ = (char) ((short) lAudioSample >> 8); | ||
| 2790 | } | ||
| 2791 | } | ||
| 2792 | // | ||
| 2793 | // Otherwise, the data should be output as 8-bit signed mono. | ||
| 2794 | // | ||
| 2795 | else if ((iChannels == 1) && (fmt & AFMT_S8)) { | ||
| 2796 | // | ||
| 2797 | // Convert each 16-bit signed mono sample to 8-bit signed mono | ||
| 2798 | // using rounding. | ||
| 2799 | // | ||
| 2800 | psSrc = (short *) src; | ||
| 2801 | count = count / 2; | ||
| 2802 | while (count--) { | ||
| 2803 | lAudioSample = | ||
| 2804 | (((long) psSrc[0] + (long) psSrc[1]) / 2); | ||
| 2805 | if (lAudioSample > 0x7fff) { | ||
| 2806 | lAudioSample = 0x7fff; | ||
| 2807 | } | ||
| 2808 | psSrc += 2; | ||
| 2809 | *dst++ = (char) ((short) lAudioSample >> 8); | ||
| 2810 | } | ||
| 2811 | } | ||
| 2812 | } | ||
| 2813 | |||
| 2814 | // | ||
| 2815 | // cs_copy_to_user() | ||
| 2816 | // replacement for the standard copy_to_user, to allow for a conversion from | ||
| 2817 | // 16 bit to 8 bit if the record conversion is active. the cs4281 has some | ||
| 2818 | // issues with 8 bit capture, so the driver always captures data in 16 bit | ||
| 2819 | // and then if the user requested 8 bit, converts from 16 to 8 bit. | ||
| 2820 | // | ||
| 2821 | static unsigned cs_copy_to_user(struct cs4281_state *s, void __user *dest, | ||
| 2822 | unsigned *hwsrc, unsigned cnt, | ||
| 2823 | unsigned *copied) | ||
| 2824 | { | ||
| 2825 | void *src = hwsrc; //default to the standard destination buffer addr | ||
| 2826 | |||
| 2827 | CS_DBGOUT(CS_FUNCTION, 6, printk(KERN_INFO | ||
| 2828 | "cs_copy_to_user()+ fmt=0x%x fmt_o=0x%x cnt=%d dest=%p\n", | ||
| 2829 | s->prop_adc.fmt, s->prop_adc.fmt_original, | ||
| 2830 | (unsigned) cnt, dest)); | ||
| 2831 | |||
| 2832 | if (cnt > s->dma_adc.dmasize) { | ||
| 2833 | cnt = s->dma_adc.dmasize; | ||
| 2834 | } | ||
| 2835 | if (!cnt) { | ||
| 2836 | *copied = 0; | ||
| 2837 | return 0; | ||
| 2838 | } | ||
| 2839 | if (s->conversion) { | ||
| 2840 | if (!s->tmpbuff) { | ||
| 2841 | *copied = cnt / 2; | ||
| 2842 | return 0; | ||
| 2843 | } | ||
| 2844 | CopySamples(s->tmpbuff, (void *) hwsrc, cnt, | ||
| 2845 | (unsigned) s->prop_adc.channels, | ||
| 2846 | s->prop_adc.fmt_original); | ||
| 2847 | src = s->tmpbuff; | ||
| 2848 | cnt = cnt / 2; | ||
| 2849 | } | ||
| 2850 | |||
| 2851 | if (copy_to_user(dest, src, cnt)) { | ||
| 2852 | *copied = 0; | ||
| 2853 | return -EFAULT; | ||
| 2854 | } | ||
| 2855 | *copied = cnt; | ||
| 2856 | CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_INFO | ||
| 2857 | "cs4281: cs_copy_to_user()- copied bytes is %d \n", cnt)); | ||
| 2858 | return 0; | ||
| 2859 | } | ||
| 2860 | |||
| 2861 | // --------------------------------------------------------------------- | ||
| 2862 | |||
| 2863 | static ssize_t cs4281_read(struct file *file, char __user *buffer, size_t count, | ||
| 2864 | loff_t * ppos) | ||
| 2865 | { | ||
| 2866 | struct cs4281_state *s = | ||
| 2867 | (struct cs4281_state *) file->private_data; | ||
| 2868 | ssize_t ret; | ||
| 2869 | unsigned long flags; | ||
| 2870 | unsigned swptr; | ||
| 2871 | int cnt; | ||
| 2872 | unsigned copied = 0; | ||
| 2873 | |||
| 2874 | CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2, | ||
| 2875 | printk(KERN_INFO "cs4281: cs4281_read()+ %Zu \n", count)); | ||
| 2876 | |||
| 2877 | VALIDATE_STATE(s); | ||
| 2878 | if (s->dma_adc.mapped) | ||
| 2879 | return -ENXIO; | ||
| 2880 | if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s))) | ||
| 2881 | return ret; | ||
| 2882 | if (!access_ok(VERIFY_WRITE, buffer, count)) | ||
| 2883 | return -EFAULT; | ||
| 2884 | ret = 0; | ||
| 2885 | // | ||
| 2886 | // "count" is the amount of bytes to read (from app), is decremented each loop | ||
| 2887 | // by the amount of bytes that have been returned to the user buffer. | ||
| 2888 | // "cnt" is the running total of each read from the buffer (changes each loop) | ||
| 2889 | // "buffer" points to the app's buffer | ||
| 2890 | // "ret" keeps a running total of the amount of bytes that have been copied | ||
| 2891 | // to the user buffer. | ||
| 2892 | // "copied" is the total bytes copied into the user buffer for each loop. | ||
| 2893 | // | ||
| 2894 | while (count > 0) { | ||
| 2895 | CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO | ||
| 2896 | "_read() count>0 count=%Zu .count=%d .swptr=%d .hwptr=%d \n", | ||
| 2897 | count, s->dma_adc.count, | ||
| 2898 | s->dma_adc.swptr, s->dma_adc.hwptr)); | ||
| 2899 | spin_lock_irqsave(&s->lock, flags); | ||
| 2900 | |||
| 2901 | // get the current copy point of the sw buffer | ||
| 2902 | swptr = s->dma_adc.swptr; | ||
| 2903 | |||
| 2904 | // cnt is the amount of unread bytes from the end of the | ||
| 2905 | // hw buffer to the current sw pointer | ||
| 2906 | cnt = s->dma_adc.dmasize - swptr; | ||
| 2907 | |||
| 2908 | // dma_adc.count is the current total bytes that have not been read. | ||
| 2909 | // if the amount of unread bytes from the current sw pointer to the | ||
| 2910 | // end of the buffer is greater than the current total bytes that | ||
| 2911 | // have not been read, then set the "cnt" (unread bytes) to the | ||
| 2912 | // amount of unread bytes. | ||
| 2913 | |||
| 2914 | if (s->dma_adc.count < cnt) | ||
| 2915 | cnt = s->dma_adc.count; | ||
| 2916 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 2917 | // | ||
| 2918 | // if we are converting from 8/16 then we need to copy | ||
| 2919 | // twice the number of 16 bit bytes then 8 bit bytes. | ||
| 2920 | // | ||
| 2921 | if (s->conversion) { | ||
| 2922 | if (cnt > (count * 2)) | ||
| 2923 | cnt = (count * 2); | ||
| 2924 | } else { | ||
| 2925 | if (cnt > count) | ||
| 2926 | cnt = count; | ||
| 2927 | } | ||
| 2928 | // | ||
| 2929 | // "cnt" NOW is the smaller of the amount that will be read, | ||
| 2930 | // and the amount that is requested in this read (or partial). | ||
| 2931 | // if there are no bytes in the buffer to read, then start the | ||
| 2932 | // ADC and wait for the interrupt handler to wake us up. | ||
| 2933 | // | ||
| 2934 | if (cnt <= 0) { | ||
| 2935 | |||
| 2936 | // start up the dma engine and then continue back to the top of | ||
| 2937 | // the loop when wake up occurs. | ||
| 2938 | start_adc(s); | ||
| 2939 | if (file->f_flags & O_NONBLOCK) | ||
| 2940 | return ret ? ret : -EAGAIN; | ||
| 2941 | interruptible_sleep_on(&s->dma_adc.wait); | ||
| 2942 | if (signal_pending(current)) | ||
| 2943 | return ret ? ret : -ERESTARTSYS; | ||
| 2944 | continue; | ||
| 2945 | } | ||
| 2946 | // there are bytes in the buffer to read. | ||
| 2947 | // copy from the hw buffer over to the user buffer. | ||
| 2948 | // user buffer is designated by "buffer" | ||
| 2949 | // virtual address to copy from is rawbuf+swptr | ||
| 2950 | // the "cnt" is the number of bytes to read. | ||
| 2951 | |||
| 2952 | CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO | ||
| 2953 | "_read() copy_to cnt=%d count=%Zu ", cnt, count)); | ||
| 2954 | CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO | ||
| 2955 | " .dmasize=%d .count=%d buffer=%p ret=%Zd\n", | ||
| 2956 | s->dma_adc.dmasize, s->dma_adc.count, buffer, ret)); | ||
| 2957 | |||
| 2958 | if (cs_copy_to_user | ||
| 2959 | (s, buffer, s->dma_adc.rawbuf + swptr, cnt, &copied)) | ||
| 2960 | return ret ? ret : -EFAULT; | ||
| 2961 | swptr = (swptr + cnt) % s->dma_adc.dmasize; | ||
| 2962 | spin_lock_irqsave(&s->lock, flags); | ||
| 2963 | s->dma_adc.swptr = swptr; | ||
| 2964 | s->dma_adc.count -= cnt; | ||
| 2965 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 2966 | count -= copied; | ||
| 2967 | buffer += copied; | ||
| 2968 | ret += copied; | ||
| 2969 | start_adc(s); | ||
| 2970 | } | ||
| 2971 | CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2, | ||
| 2972 | printk(KERN_INFO "cs4281: cs4281_read()- %Zd\n", ret)); | ||
| 2973 | return ret; | ||
| 2974 | } | ||
| 2975 | |||
| 2976 | |||
| 2977 | static ssize_t cs4281_write(struct file *file, const char __user *buffer, | ||
| 2978 | size_t count, loff_t * ppos) | ||
| 2979 | { | ||
| 2980 | struct cs4281_state *s = | ||
| 2981 | (struct cs4281_state *) file->private_data; | ||
| 2982 | ssize_t ret; | ||
| 2983 | unsigned long flags; | ||
| 2984 | unsigned swptr, hwptr, busaddr; | ||
| 2985 | int cnt; | ||
| 2986 | |||
| 2987 | CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2, | ||
| 2988 | printk(KERN_INFO "cs4281: cs4281_write()+ count=%Zu\n", | ||
| 2989 | count)); | ||
| 2990 | VALIDATE_STATE(s); | ||
| 2991 | |||
| 2992 | if (s->dma_dac.mapped) | ||
| 2993 | return -ENXIO; | ||
| 2994 | if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s))) | ||
| 2995 | return ret; | ||
| 2996 | if (!access_ok(VERIFY_READ, buffer, count)) | ||
| 2997 | return -EFAULT; | ||
| 2998 | ret = 0; | ||
| 2999 | while (count > 0) { | ||
| 3000 | spin_lock_irqsave(&s->lock, flags); | ||
| 3001 | if (s->dma_dac.count < 0) { | ||
| 3002 | s->dma_dac.count = 0; | ||
| 3003 | s->dma_dac.swptr = s->dma_dac.hwptr; | ||
| 3004 | } | ||
| 3005 | if (s->dma_dac.underrun) { | ||
| 3006 | s->dma_dac.underrun = 0; | ||
| 3007 | hwptr = readl(s->pBA0 + BA0_DCA0); | ||
| 3008 | busaddr = virt_to_bus(s->dma_dac.rawbuf); | ||
| 3009 | hwptr -= (unsigned) busaddr; | ||
| 3010 | s->dma_dac.swptr = s->dma_dac.hwptr = hwptr; | ||
| 3011 | } | ||
| 3012 | swptr = s->dma_dac.swptr; | ||
| 3013 | cnt = s->dma_dac.dmasize - swptr; | ||
| 3014 | if (s->dma_dac.count + cnt > s->dma_dac.dmasize) | ||
| 3015 | cnt = s->dma_dac.dmasize - s->dma_dac.count; | ||
| 3016 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 3017 | if (cnt > count) | ||
| 3018 | cnt = count; | ||
| 3019 | if (cnt <= 0) { | ||
| 3020 | start_dac(s); | ||
| 3021 | if (file->f_flags & O_NONBLOCK) | ||
| 3022 | return ret ? ret : -EAGAIN; | ||
| 3023 | interruptible_sleep_on(&s->dma_dac.wait); | ||
| 3024 | if (signal_pending(current)) | ||
| 3025 | return ret ? ret : -ERESTARTSYS; | ||
| 3026 | continue; | ||
| 3027 | } | ||
| 3028 | if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) | ||
| 3029 | return ret ? ret : -EFAULT; | ||
| 3030 | swptr = (swptr + cnt) % s->dma_dac.dmasize; | ||
| 3031 | spin_lock_irqsave(&s->lock, flags); | ||
| 3032 | s->dma_dac.swptr = swptr; | ||
| 3033 | s->dma_dac.count += cnt; | ||
| 3034 | s->dma_dac.endcleared = 0; | ||
| 3035 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 3036 | count -= cnt; | ||
| 3037 | buffer += cnt; | ||
| 3038 | ret += cnt; | ||
| 3039 | start_dac(s); | ||
| 3040 | } | ||
| 3041 | CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2, | ||
| 3042 | printk(KERN_INFO "cs4281: cs4281_write()- %Zd\n", ret)); | ||
| 3043 | return ret; | ||
| 3044 | } | ||
| 3045 | |||
| 3046 | |||
| 3047 | static unsigned int cs4281_poll(struct file *file, | ||
| 3048 | struct poll_table_struct *wait) | ||
| 3049 | { | ||
| 3050 | struct cs4281_state *s = | ||
| 3051 | (struct cs4281_state *) file->private_data; | ||
| 3052 | unsigned long flags; | ||
| 3053 | unsigned int mask = 0; | ||
| 3054 | |||
| 3055 | CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4, | ||
| 3056 | printk(KERN_INFO "cs4281: cs4281_poll()+\n")); | ||
| 3057 | VALIDATE_STATE(s); | ||
| 3058 | if (file->f_mode & FMODE_WRITE) { | ||
| 3059 | CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4, | ||
| 3060 | printk(KERN_INFO | ||
| 3061 | "cs4281: cs4281_poll() wait on FMODE_WRITE\n")); | ||
| 3062 | if(!s->dma_dac.ready && prog_dmabuf_dac(s)) | ||
| 3063 | return 0; | ||
| 3064 | poll_wait(file, &s->dma_dac.wait, wait); | ||
| 3065 | } | ||
| 3066 | if (file->f_mode & FMODE_READ) { | ||
| 3067 | CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4, | ||
| 3068 | printk(KERN_INFO | ||
| 3069 | "cs4281: cs4281_poll() wait on FMODE_READ\n")); | ||
| 3070 | if(!s->dma_dac.ready && prog_dmabuf_adc(s)) | ||
| 3071 | return 0; | ||
| 3072 | poll_wait(file, &s->dma_adc.wait, wait); | ||
| 3073 | } | ||
| 3074 | spin_lock_irqsave(&s->lock, flags); | ||
| 3075 | cs4281_update_ptr(s,CS_FALSE); | ||
| 3076 | if (file->f_mode & FMODE_WRITE) { | ||
| 3077 | if (s->dma_dac.mapped) { | ||
| 3078 | if (s->dma_dac.count >= | ||
| 3079 | (signed) s->dma_dac.fragsize) { | ||
| 3080 | if (s->dma_dac.wakeup) | ||
| 3081 | mask |= POLLOUT | POLLWRNORM; | ||
| 3082 | else | ||
| 3083 | mask = 0; | ||
| 3084 | s->dma_dac.wakeup = 0; | ||
| 3085 | } | ||
| 3086 | } else { | ||
| 3087 | if ((signed) (s->dma_dac.dmasize/2) >= s->dma_dac.count) | ||
| 3088 | mask |= POLLOUT | POLLWRNORM; | ||
| 3089 | } | ||
| 3090 | } else if (file->f_mode & FMODE_READ) { | ||
| 3091 | if (s->dma_adc.mapped) { | ||
| 3092 | if (s->dma_adc.count >= (signed) s->dma_adc.fragsize) | ||
| 3093 | mask |= POLLIN | POLLRDNORM; | ||
| 3094 | } else { | ||
| 3095 | if (s->dma_adc.count > 0) | ||
| 3096 | mask |= POLLIN | POLLRDNORM; | ||
| 3097 | } | ||
| 3098 | } | ||
| 3099 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 3100 | CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4, | ||
| 3101 | printk(KERN_INFO "cs4281: cs4281_poll()- 0x%.8x\n", | ||
| 3102 | mask)); | ||
| 3103 | return mask; | ||
| 3104 | } | ||
| 3105 | |||
| 3106 | |||
| 3107 | static int cs4281_mmap(struct file *file, struct vm_area_struct *vma) | ||
| 3108 | { | ||
| 3109 | struct cs4281_state *s = | ||
| 3110 | (struct cs4281_state *) file->private_data; | ||
| 3111 | struct dmabuf *db; | ||
| 3112 | int ret; | ||
| 3113 | unsigned long size; | ||
| 3114 | |||
| 3115 | CS_DBGOUT(CS_FUNCTION | CS_PARMS | CS_OPEN, 4, | ||
| 3116 | printk(KERN_INFO "cs4281: cs4281_mmap()+\n")); | ||
| 3117 | |||
| 3118 | VALIDATE_STATE(s); | ||
| 3119 | if (vma->vm_flags & VM_WRITE) { | ||
| 3120 | if ((ret = prog_dmabuf_dac(s)) != 0) | ||
| 3121 | return ret; | ||
| 3122 | db = &s->dma_dac; | ||
| 3123 | } else if (vma->vm_flags & VM_READ) { | ||
| 3124 | if ((ret = prog_dmabuf_adc(s)) != 0) | ||
| 3125 | return ret; | ||
| 3126 | db = &s->dma_adc; | ||
| 3127 | } else | ||
| 3128 | return -EINVAL; | ||
| 3129 | // | ||
| 3130 | // only support PLAYBACK for now | ||
| 3131 | // | ||
| 3132 | db = &s->dma_dac; | ||
| 3133 | |||
| 3134 | if (cs4x_pgoff(vma) != 0) | ||
| 3135 | return -EINVAL; | ||
| 3136 | size = vma->vm_end - vma->vm_start; | ||
| 3137 | if (size > (PAGE_SIZE << db->buforder)) | ||
| 3138 | return -EINVAL; | ||
| 3139 | if (remap_pfn_range(vma, vma->vm_start, | ||
| 3140 | virt_to_phys(db->rawbuf) >> PAGE_SHIFT, | ||
| 3141 | size, vma->vm_page_prot)) | ||
| 3142 | return -EAGAIN; | ||
| 3143 | db->mapped = 1; | ||
| 3144 | |||
| 3145 | CS_DBGOUT(CS_FUNCTION | CS_PARMS | CS_OPEN, 4, | ||
| 3146 | printk(KERN_INFO "cs4281: cs4281_mmap()- 0 size=%d\n", | ||
| 3147 | (unsigned) size)); | ||
| 3148 | |||
| 3149 | return 0; | ||
| 3150 | } | ||
| 3151 | |||
| 3152 | |||
| 3153 | static int cs4281_ioctl(struct inode *inode, struct file *file, | ||
| 3154 | unsigned int cmd, unsigned long arg) | ||
| 3155 | { | ||
| 3156 | struct cs4281_state *s = | ||
| 3157 | (struct cs4281_state *) file->private_data; | ||
| 3158 | unsigned long flags; | ||
| 3159 | audio_buf_info abinfo; | ||
| 3160 | count_info cinfo; | ||
| 3161 | int val, mapped, ret; | ||
| 3162 | int __user *p = (int __user *)arg; | ||
| 3163 | |||
| 3164 | CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO | ||
| 3165 | "cs4281: cs4281_ioctl(): file=%p cmd=0x%.8x\n", file, cmd)); | ||
| 3166 | #if CSDEBUG | ||
| 3167 | cs_printioctl(cmd); | ||
| 3168 | #endif | ||
| 3169 | VALIDATE_STATE(s); | ||
| 3170 | mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) || | ||
| 3171 | ((file->f_mode & FMODE_READ) && s->dma_adc.mapped); | ||
| 3172 | switch (cmd) { | ||
| 3173 | case OSS_GETVERSION: | ||
| 3174 | CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO | ||
| 3175 | "cs4281: cs4281_ioctl(): SOUND_VERSION=0x%.8x\n", | ||
| 3176 | SOUND_VERSION)); | ||
| 3177 | return put_user(SOUND_VERSION, p); | ||
| 3178 | |||
| 3179 | case SNDCTL_DSP_SYNC: | ||
| 3180 | CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO | ||
| 3181 | "cs4281: cs4281_ioctl(): DSP_SYNC\n")); | ||
| 3182 | if (file->f_mode & FMODE_WRITE) | ||
| 3183 | return drain_dac(s, | ||
| 3184 | 0 /*file->f_flags & O_NONBLOCK */ | ||
| 3185 | ); | ||
| 3186 | return 0; | ||
| 3187 | |||
| 3188 | case SNDCTL_DSP_SETDUPLEX: | ||
| 3189 | return 0; | ||
| 3190 | |||
| 3191 | case SNDCTL_DSP_GETCAPS: | ||
| 3192 | return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | | ||
| 3193 | DSP_CAP_TRIGGER | DSP_CAP_MMAP, | ||
| 3194 | p); | ||
| 3195 | |||
| 3196 | case SNDCTL_DSP_RESET: | ||
| 3197 | CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO | ||
| 3198 | "cs4281: cs4281_ioctl(): DSP_RESET\n")); | ||
| 3199 | if (file->f_mode & FMODE_WRITE) { | ||
| 3200 | stop_dac(s); | ||
| 3201 | synchronize_irq(s->irq); | ||
| 3202 | s->dma_dac.swptr = s->dma_dac.hwptr = | ||
| 3203 | s->dma_dac.count = s->dma_dac.total_bytes = | ||
| 3204 | s->dma_dac.blocks = s->dma_dac.wakeup = 0; | ||
| 3205 | prog_codec(s, CS_TYPE_DAC); | ||
| 3206 | } | ||
| 3207 | if (file->f_mode & FMODE_READ) { | ||
| 3208 | stop_adc(s); | ||
| 3209 | synchronize_irq(s->irq); | ||
| 3210 | s->dma_adc.swptr = s->dma_adc.hwptr = | ||
| 3211 | s->dma_adc.count = s->dma_adc.total_bytes = | ||
| 3212 | s->dma_adc.blocks = s->dma_dac.wakeup = 0; | ||
| 3213 | prog_codec(s, CS_TYPE_ADC); | ||
| 3214 | } | ||
| 3215 | return 0; | ||
| 3216 | |||
| 3217 | case SNDCTL_DSP_SPEED: | ||
| 3218 | if (get_user(val, p)) | ||
| 3219 | return -EFAULT; | ||
| 3220 | CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO | ||
| 3221 | "cs4281: cs4281_ioctl(): DSP_SPEED val=%d\n", val)); | ||
| 3222 | // | ||
| 3223 | // support independent capture and playback channels | ||
| 3224 | // assume that the file mode bit determines the | ||
| 3225 | // direction of the data flow. | ||
| 3226 | // | ||
| 3227 | if (file->f_mode & FMODE_READ) { | ||
| 3228 | if (val >= 0) { | ||
| 3229 | stop_adc(s); | ||
| 3230 | s->dma_adc.ready = 0; | ||
| 3231 | // program sampling rates | ||
| 3232 | if (val > 48000) | ||
| 3233 | val = 48000; | ||
| 3234 | if (val < 6300) | ||
| 3235 | val = 6300; | ||
| 3236 | s->prop_adc.rate = val; | ||
| 3237 | prog_codec(s, CS_TYPE_ADC); | ||
| 3238 | } | ||
| 3239 | } | ||
| 3240 | if (file->f_mode & FMODE_WRITE) { | ||
| 3241 | if (val >= 0) { | ||
| 3242 | stop_dac(s); | ||
| 3243 | s->dma_dac.ready = 0; | ||
| 3244 | // program sampling rates | ||
| 3245 | if (val > 48000) | ||
| 3246 | val = 48000; | ||
| 3247 | if (val < 6300) | ||
| 3248 | val = 6300; | ||
| 3249 | s->prop_dac.rate = val; | ||
| 3250 | prog_codec(s, CS_TYPE_DAC); | ||
| 3251 | } | ||
| 3252 | } | ||
| 3253 | |||
| 3254 | if (file->f_mode & FMODE_WRITE) | ||
| 3255 | val = s->prop_dac.rate; | ||
| 3256 | else if (file->f_mode & FMODE_READ) | ||
| 3257 | val = s->prop_adc.rate; | ||
| 3258 | |||
| 3259 | return put_user(val, p); | ||
| 3260 | |||
| 3261 | case SNDCTL_DSP_STEREO: | ||
| 3262 | if (get_user(val, p)) | ||
| 3263 | return -EFAULT; | ||
| 3264 | CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO | ||
| 3265 | "cs4281: cs4281_ioctl(): DSP_STEREO val=%d\n", val)); | ||
| 3266 | if (file->f_mode & FMODE_READ) { | ||
| 3267 | stop_adc(s); | ||
| 3268 | s->dma_adc.ready = 0; | ||
| 3269 | s->prop_adc.channels = val ? 2 : 1; | ||
| 3270 | prog_codec(s, CS_TYPE_ADC); | ||
| 3271 | } | ||
| 3272 | if (file->f_mode & FMODE_WRITE) { | ||
| 3273 | stop_dac(s); | ||
| 3274 | s->dma_dac.ready = 0; | ||
| 3275 | s->prop_dac.channels = val ? 2 : 1; | ||
| 3276 | prog_codec(s, CS_TYPE_DAC); | ||
| 3277 | } | ||
| 3278 | return 0; | ||
| 3279 | |||
| 3280 | case SNDCTL_DSP_CHANNELS: | ||
| 3281 | if (get_user(val, p)) | ||
| 3282 | return -EFAULT; | ||
| 3283 | CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO | ||
| 3284 | "cs4281: cs4281_ioctl(): DSP_CHANNELS val=%d\n", | ||
| 3285 | val)); | ||
| 3286 | if (val != 0) { | ||
| 3287 | if (file->f_mode & FMODE_READ) { | ||
| 3288 | stop_adc(s); | ||
| 3289 | s->dma_adc.ready = 0; | ||
| 3290 | if (val >= 2) | ||
| 3291 | s->prop_adc.channels = 2; | ||
| 3292 | else | ||
| 3293 | s->prop_adc.channels = 1; | ||
| 3294 | prog_codec(s, CS_TYPE_ADC); | ||
| 3295 | } | ||
| 3296 | if (file->f_mode & FMODE_WRITE) { | ||
| 3297 | stop_dac(s); | ||
| 3298 | s->dma_dac.ready = 0; | ||
| 3299 | if (val >= 2) | ||
| 3300 | s->prop_dac.channels = 2; | ||
| 3301 | else | ||
| 3302 | s->prop_dac.channels = 1; | ||
| 3303 | prog_codec(s, CS_TYPE_DAC); | ||
| 3304 | } | ||
| 3305 | } | ||
| 3306 | |||
| 3307 | if (file->f_mode & FMODE_WRITE) | ||
| 3308 | val = s->prop_dac.channels; | ||
| 3309 | else if (file->f_mode & FMODE_READ) | ||
| 3310 | val = s->prop_adc.channels; | ||
| 3311 | |||
| 3312 | return put_user(val, p); | ||
| 3313 | |||
| 3314 | case SNDCTL_DSP_GETFMTS: // Returns a mask | ||
| 3315 | CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO | ||
| 3316 | "cs4281: cs4281_ioctl(): DSP_GETFMT val=0x%.8x\n", | ||
| 3317 | AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 | | ||
| 3318 | AFMT_U8)); | ||
| 3319 | return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 | | ||
| 3320 | AFMT_U8, p); | ||
| 3321 | |||
| 3322 | case SNDCTL_DSP_SETFMT: | ||
| 3323 | if (get_user(val, p)) | ||
| 3324 | return -EFAULT; | ||
| 3325 | CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO | ||
| 3326 | "cs4281: cs4281_ioctl(): DSP_SETFMT val=0x%.8x\n", | ||
| 3327 | val)); | ||
| 3328 | if (val != AFMT_QUERY) { | ||
| 3329 | if (file->f_mode & FMODE_READ) { | ||
| 3330 | stop_adc(s); | ||
| 3331 | s->dma_adc.ready = 0; | ||
| 3332 | if (val != AFMT_S16_LE | ||
| 3333 | && val != AFMT_U16_LE && val != AFMT_S8 | ||
| 3334 | && val != AFMT_U8) | ||
| 3335 | val = AFMT_U8; | ||
| 3336 | s->prop_adc.fmt = val; | ||
| 3337 | s->prop_adc.fmt_original = s->prop_adc.fmt; | ||
| 3338 | prog_codec(s, CS_TYPE_ADC); | ||
| 3339 | } | ||
| 3340 | if (file->f_mode & FMODE_WRITE) { | ||
| 3341 | stop_dac(s); | ||
| 3342 | s->dma_dac.ready = 0; | ||
| 3343 | if (val != AFMT_S16_LE | ||
| 3344 | && val != AFMT_U16_LE && val != AFMT_S8 | ||
| 3345 | && val != AFMT_U8) | ||
| 3346 | val = AFMT_U8; | ||
| 3347 | s->prop_dac.fmt = val; | ||
| 3348 | s->prop_dac.fmt_original = s->prop_dac.fmt; | ||
| 3349 | prog_codec(s, CS_TYPE_DAC); | ||
| 3350 | } | ||
| 3351 | } else { | ||
| 3352 | if (file->f_mode & FMODE_WRITE) | ||
| 3353 | val = s->prop_dac.fmt_original; | ||
| 3354 | else if (file->f_mode & FMODE_READ) | ||
| 3355 | val = s->prop_adc.fmt_original; | ||
| 3356 | } | ||
| 3357 | CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO | ||
| 3358 | "cs4281: cs4281_ioctl(): DSP_SETFMT return val=0x%.8x\n", | ||
| 3359 | val)); | ||
| 3360 | return put_user(val, p); | ||
| 3361 | |||
| 3362 | case SNDCTL_DSP_POST: | ||
| 3363 | CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO | ||
| 3364 | "cs4281: cs4281_ioctl(): DSP_POST\n")); | ||
| 3365 | return 0; | ||
| 3366 | |||
| 3367 | case SNDCTL_DSP_GETTRIGGER: | ||
| 3368 | val = 0; | ||
| 3369 | if (file->f_mode & s->ena & FMODE_READ) | ||
| 3370 | val |= PCM_ENABLE_INPUT; | ||
| 3371 | if (file->f_mode & s->ena & FMODE_WRITE) | ||
| 3372 | val |= PCM_ENABLE_OUTPUT; | ||
| 3373 | return put_user(val, p); | ||
| 3374 | |||
| 3375 | case SNDCTL_DSP_SETTRIGGER: | ||
| 3376 | if (get_user(val, p)) | ||
| 3377 | return -EFAULT; | ||
| 3378 | if (file->f_mode & FMODE_READ) { | ||
| 3379 | if (val & PCM_ENABLE_INPUT) { | ||
| 3380 | if (!s->dma_adc.ready | ||
| 3381 | && (ret = prog_dmabuf_adc(s))) | ||
| 3382 | return ret; | ||
| 3383 | start_adc(s); | ||
| 3384 | } else | ||
| 3385 | stop_adc(s); | ||
| 3386 | } | ||
| 3387 | if (file->f_mode & FMODE_WRITE) { | ||
| 3388 | if (val & PCM_ENABLE_OUTPUT) { | ||
| 3389 | if (!s->dma_dac.ready | ||
| 3390 | && (ret = prog_dmabuf_dac(s))) | ||
| 3391 | return ret; | ||
| 3392 | start_dac(s); | ||
| 3393 | } else | ||
| 3394 | stop_dac(s); | ||
| 3395 | } | ||
| 3396 | return 0; | ||
| 3397 | |||
| 3398 | case SNDCTL_DSP_GETOSPACE: | ||
| 3399 | if (!(file->f_mode & FMODE_WRITE)) | ||
| 3400 | return -EINVAL; | ||
| 3401 | if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s))) | ||
| 3402 | return val; | ||
| 3403 | spin_lock_irqsave(&s->lock, flags); | ||
| 3404 | cs4281_update_ptr(s,CS_FALSE); | ||
| 3405 | abinfo.fragsize = s->dma_dac.fragsize; | ||
| 3406 | if (s->dma_dac.mapped) | ||
| 3407 | abinfo.bytes = s->dma_dac.dmasize; | ||
| 3408 | else | ||
| 3409 | abinfo.bytes = | ||
| 3410 | s->dma_dac.dmasize - s->dma_dac.count; | ||
| 3411 | abinfo.fragstotal = s->dma_dac.numfrag; | ||
| 3412 | abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift; | ||
| 3413 | CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO | ||
| 3414 | "cs4281: cs4281_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n", | ||
| 3415 | abinfo.fragsize,abinfo.bytes,abinfo.fragstotal, | ||
| 3416 | abinfo.fragments)); | ||
| 3417 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 3418 | return copy_to_user(p, &abinfo, | ||
| 3419 | sizeof(abinfo)) ? -EFAULT : 0; | ||
| 3420 | |||
| 3421 | case SNDCTL_DSP_GETISPACE: | ||
| 3422 | if (!(file->f_mode & FMODE_READ)) | ||
| 3423 | return -EINVAL; | ||
| 3424 | if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s))) | ||
| 3425 | return val; | ||
| 3426 | spin_lock_irqsave(&s->lock, flags); | ||
| 3427 | cs4281_update_ptr(s,CS_FALSE); | ||
| 3428 | if (s->conversion) { | ||
| 3429 | abinfo.fragsize = s->dma_adc.fragsize / 2; | ||
| 3430 | abinfo.bytes = s->dma_adc.count / 2; | ||
| 3431 | abinfo.fragstotal = s->dma_adc.numfrag; | ||
| 3432 | abinfo.fragments = | ||
| 3433 | abinfo.bytes >> (s->dma_adc.fragshift - 1); | ||
| 3434 | } else { | ||
| 3435 | abinfo.fragsize = s->dma_adc.fragsize; | ||
| 3436 | abinfo.bytes = s->dma_adc.count; | ||
| 3437 | abinfo.fragstotal = s->dma_adc.numfrag; | ||
| 3438 | abinfo.fragments = | ||
| 3439 | abinfo.bytes >> s->dma_adc.fragshift; | ||
| 3440 | } | ||
| 3441 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 3442 | return copy_to_user(p, &abinfo, | ||
| 3443 | sizeof(abinfo)) ? -EFAULT : 0; | ||
| 3444 | |||
| 3445 | case SNDCTL_DSP_NONBLOCK: | ||
| 3446 | file->f_flags |= O_NONBLOCK; | ||
| 3447 | return 0; | ||
| 3448 | |||
| 3449 | case SNDCTL_DSP_GETODELAY: | ||
| 3450 | if (!(file->f_mode & FMODE_WRITE)) | ||
| 3451 | return -EINVAL; | ||
| 3452 | if(!s->dma_dac.ready && prog_dmabuf_dac(s)) | ||
| 3453 | return 0; | ||
| 3454 | spin_lock_irqsave(&s->lock, flags); | ||
| 3455 | cs4281_update_ptr(s,CS_FALSE); | ||
| 3456 | val = s->dma_dac.count; | ||
| 3457 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 3458 | return put_user(val, p); | ||
| 3459 | |||
| 3460 | case SNDCTL_DSP_GETIPTR: | ||
| 3461 | if (!(file->f_mode & FMODE_READ)) | ||
| 3462 | return -EINVAL; | ||
| 3463 | if(!s->dma_adc.ready && prog_dmabuf_adc(s)) | ||
| 3464 | return 0; | ||
| 3465 | spin_lock_irqsave(&s->lock, flags); | ||
| 3466 | cs4281_update_ptr(s,CS_FALSE); | ||
| 3467 | cinfo.bytes = s->dma_adc.total_bytes; | ||
| 3468 | if (s->dma_adc.mapped) { | ||
| 3469 | cinfo.blocks = | ||
| 3470 | (cinfo.bytes >> s->dma_adc.fragshift) - | ||
| 3471 | s->dma_adc.blocks; | ||
| 3472 | s->dma_adc.blocks = | ||
| 3473 | cinfo.bytes >> s->dma_adc.fragshift; | ||
| 3474 | } else { | ||
| 3475 | if (s->conversion) { | ||
| 3476 | cinfo.blocks = | ||
| 3477 | s->dma_adc.count / | ||
| 3478 | 2 >> (s->dma_adc.fragshift - 1); | ||
| 3479 | } else | ||
| 3480 | cinfo.blocks = | ||
| 3481 | s->dma_adc.count >> s->dma_adc. | ||
| 3482 | fragshift; | ||
| 3483 | } | ||
| 3484 | if (s->conversion) | ||
| 3485 | cinfo.ptr = s->dma_adc.hwptr / 2; | ||
| 3486 | else | ||
| 3487 | cinfo.ptr = s->dma_adc.hwptr; | ||
| 3488 | if (s->dma_adc.mapped) | ||
| 3489 | s->dma_adc.count &= s->dma_adc.fragsize - 1; | ||
| 3490 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 3491 | if (copy_to_user(p, &cinfo, sizeof(cinfo))) | ||
| 3492 | return -EFAULT; | ||
| 3493 | return 0; | ||
| 3494 | |||
| 3495 | case SNDCTL_DSP_GETOPTR: | ||
| 3496 | if (!(file->f_mode & FMODE_WRITE)) | ||
| 3497 | return -EINVAL; | ||
| 3498 | if(!s->dma_dac.ready && prog_dmabuf_dac(s)) | ||
| 3499 | return 0; | ||
| 3500 | spin_lock_irqsave(&s->lock, flags); | ||
| 3501 | cs4281_update_ptr(s,CS_FALSE); | ||
| 3502 | cinfo.bytes = s->dma_dac.total_bytes; | ||
| 3503 | if (s->dma_dac.mapped) { | ||
| 3504 | cinfo.blocks = | ||
| 3505 | (cinfo.bytes >> s->dma_dac.fragshift) - | ||
| 3506 | s->dma_dac.blocks; | ||
| 3507 | s->dma_dac.blocks = | ||
| 3508 | cinfo.bytes >> s->dma_dac.fragshift; | ||
| 3509 | } else { | ||
| 3510 | cinfo.blocks = | ||
| 3511 | s->dma_dac.count >> s->dma_dac.fragshift; | ||
| 3512 | } | ||
| 3513 | cinfo.ptr = s->dma_dac.hwptr; | ||
| 3514 | if (s->dma_dac.mapped) | ||
| 3515 | s->dma_dac.count &= s->dma_dac.fragsize - 1; | ||
| 3516 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 3517 | if (copy_to_user(p, &cinfo, sizeof(cinfo))) | ||
| 3518 | return -EFAULT; | ||
| 3519 | return 0; | ||
| 3520 | |||
| 3521 | case SNDCTL_DSP_GETBLKSIZE: | ||
| 3522 | if (file->f_mode & FMODE_WRITE) { | ||
| 3523 | if ((val = prog_dmabuf_dac(s))) | ||
| 3524 | return val; | ||
| 3525 | return put_user(s->dma_dac.fragsize, p); | ||
| 3526 | } | ||
| 3527 | if ((val = prog_dmabuf_adc(s))) | ||
| 3528 | return val; | ||
| 3529 | if (s->conversion) | ||
| 3530 | return put_user(s->dma_adc.fragsize / 2, p); | ||
| 3531 | else | ||
| 3532 | return put_user(s->dma_adc.fragsize, p); | ||
| 3533 | |||
| 3534 | case SNDCTL_DSP_SETFRAGMENT: | ||
| 3535 | if (get_user(val, p)) | ||
| 3536 | return -EFAULT; | ||
| 3537 | return 0; // Say OK, but do nothing. | ||
| 3538 | |||
| 3539 | case SNDCTL_DSP_SUBDIVIDE: | ||
| 3540 | if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) | ||
| 3541 | || (file->f_mode & FMODE_WRITE | ||
| 3542 | && s->dma_dac.subdivision)) return -EINVAL; | ||
| 3543 | if (get_user(val, p)) | ||
| 3544 | return -EFAULT; | ||
| 3545 | if (val != 1 && val != 2 && val != 4) | ||
| 3546 | return -EINVAL; | ||
| 3547 | if (file->f_mode & FMODE_READ) | ||
| 3548 | s->dma_adc.subdivision = val; | ||
| 3549 | else if (file->f_mode & FMODE_WRITE) | ||
| 3550 | s->dma_dac.subdivision = val; | ||
| 3551 | return 0; | ||
| 3552 | |||
| 3553 | case SOUND_PCM_READ_RATE: | ||
| 3554 | if (file->f_mode & FMODE_READ) | ||
| 3555 | return put_user(s->prop_adc.rate, p); | ||
| 3556 | else if (file->f_mode & FMODE_WRITE) | ||
| 3557 | return put_user(s->prop_dac.rate, p); | ||
| 3558 | |||
| 3559 | case SOUND_PCM_READ_CHANNELS: | ||
| 3560 | if (file->f_mode & FMODE_READ) | ||
| 3561 | return put_user(s->prop_adc.channels, p); | ||
| 3562 | else if (file->f_mode & FMODE_WRITE) | ||
| 3563 | return put_user(s->prop_dac.channels, p); | ||
| 3564 | |||
| 3565 | case SOUND_PCM_READ_BITS: | ||
| 3566 | if (file->f_mode & FMODE_READ) | ||
| 3567 | return | ||
| 3568 | put_user( | ||
| 3569 | (s->prop_adc. | ||
| 3570 | fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16, | ||
| 3571 | p); | ||
| 3572 | else if (file->f_mode & FMODE_WRITE) | ||
| 3573 | return | ||
| 3574 | put_user( | ||
| 3575 | (s->prop_dac. | ||
| 3576 | fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16, | ||
| 3577 | p); | ||
| 3578 | |||
| 3579 | case SOUND_PCM_WRITE_FILTER: | ||
| 3580 | case SNDCTL_DSP_SETSYNCRO: | ||
| 3581 | case SOUND_PCM_READ_FILTER: | ||
| 3582 | return -EINVAL; | ||
| 3583 | } | ||
| 3584 | return mixer_ioctl(s, cmd, arg); | ||
| 3585 | } | ||
| 3586 | |||
| 3587 | |||
| 3588 | static int cs4281_release(struct inode *inode, struct file *file) | ||
| 3589 | { | ||
| 3590 | struct cs4281_state *s = | ||
| 3591 | (struct cs4281_state *) file->private_data; | ||
| 3592 | |||
| 3593 | CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO | ||
| 3594 | "cs4281: cs4281_release(): inode=%p file=%p f_mode=%d\n", | ||
| 3595 | inode, file, file->f_mode)); | ||
| 3596 | |||
| 3597 | VALIDATE_STATE(s); | ||
| 3598 | |||
| 3599 | if (file->f_mode & FMODE_WRITE) { | ||
| 3600 | drain_dac(s, file->f_flags & O_NONBLOCK); | ||
| 3601 | down(&s->open_sem_dac); | ||
| 3602 | stop_dac(s); | ||
| 3603 | dealloc_dmabuf(s, &s->dma_dac); | ||
| 3604 | s->open_mode &= ~FMODE_WRITE; | ||
| 3605 | up(&s->open_sem_dac); | ||
| 3606 | wake_up(&s->open_wait_dac); | ||
| 3607 | } | ||
| 3608 | if (file->f_mode & FMODE_READ) { | ||
| 3609 | drain_adc(s, file->f_flags & O_NONBLOCK); | ||
| 3610 | down(&s->open_sem_adc); | ||
| 3611 | stop_adc(s); | ||
| 3612 | dealloc_dmabuf(s, &s->dma_adc); | ||
| 3613 | s->open_mode &= ~FMODE_READ; | ||
| 3614 | up(&s->open_sem_adc); | ||
| 3615 | wake_up(&s->open_wait_adc); | ||
| 3616 | } | ||
| 3617 | return 0; | ||
| 3618 | } | ||
| 3619 | |||
| 3620 | static int cs4281_open(struct inode *inode, struct file *file) | ||
| 3621 | { | ||
| 3622 | unsigned int minor = iminor(inode); | ||
| 3623 | struct cs4281_state *s=NULL; | ||
| 3624 | struct list_head *entry; | ||
| 3625 | |||
| 3626 | CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO | ||
| 3627 | "cs4281: cs4281_open(): inode=%p file=%p f_mode=0x%x\n", | ||
| 3628 | inode, file, file->f_mode)); | ||
| 3629 | |||
| 3630 | list_for_each(entry, &cs4281_devs) | ||
| 3631 | { | ||
| 3632 | s = list_entry(entry, struct cs4281_state, list); | ||
| 3633 | |||
| 3634 | if (!((s->dev_audio ^ minor) & ~0xf)) | ||
| 3635 | break; | ||
| 3636 | } | ||
| 3637 | if (entry == &cs4281_devs) | ||
| 3638 | return -ENODEV; | ||
| 3639 | if (!s) { | ||
| 3640 | CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO | ||
| 3641 | "cs4281: cs4281_open(): Error - unable to find audio state struct\n")); | ||
| 3642 | return -ENODEV; | ||
| 3643 | } | ||
| 3644 | VALIDATE_STATE(s); | ||
| 3645 | file->private_data = s; | ||
| 3646 | |||
| 3647 | // wait for device to become free | ||
| 3648 | if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) { | ||
| 3649 | CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO | ||
| 3650 | "cs4281: cs4281_open(): Error - must open READ and/or WRITE\n")); | ||
| 3651 | return -ENODEV; | ||
| 3652 | } | ||
| 3653 | if (file->f_mode & FMODE_WRITE) { | ||
| 3654 | down(&s->open_sem_dac); | ||
| 3655 | while (s->open_mode & FMODE_WRITE) { | ||
| 3656 | if (file->f_flags & O_NONBLOCK) { | ||
| 3657 | up(&s->open_sem_dac); | ||
| 3658 | return -EBUSY; | ||
| 3659 | } | ||
| 3660 | up(&s->open_sem_dac); | ||
| 3661 | interruptible_sleep_on(&s->open_wait_dac); | ||
| 3662 | |||
| 3663 | if (signal_pending(current)) | ||
| 3664 | return -ERESTARTSYS; | ||
| 3665 | down(&s->open_sem_dac); | ||
| 3666 | } | ||
| 3667 | } | ||
| 3668 | if (file->f_mode & FMODE_READ) { | ||
| 3669 | down(&s->open_sem_adc); | ||
| 3670 | while (s->open_mode & FMODE_READ) { | ||
| 3671 | if (file->f_flags & O_NONBLOCK) { | ||
| 3672 | up(&s->open_sem_adc); | ||
| 3673 | return -EBUSY; | ||
| 3674 | } | ||
| 3675 | up(&s->open_sem_adc); | ||
| 3676 | interruptible_sleep_on(&s->open_wait_adc); | ||
| 3677 | |||
| 3678 | if (signal_pending(current)) | ||
| 3679 | return -ERESTARTSYS; | ||
| 3680 | down(&s->open_sem_adc); | ||
| 3681 | } | ||
| 3682 | } | ||
| 3683 | s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE); | ||
| 3684 | if (file->f_mode & FMODE_READ) { | ||
| 3685 | s->prop_adc.fmt = AFMT_U8; | ||
| 3686 | s->prop_adc.fmt_original = s->prop_adc.fmt; | ||
| 3687 | s->prop_adc.channels = 1; | ||
| 3688 | s->prop_adc.rate = 8000; | ||
| 3689 | s->prop_adc.clkdiv = 96 | 0x80; | ||
| 3690 | s->conversion = 0; | ||
| 3691 | s->ena &= ~FMODE_READ; | ||
| 3692 | s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = | ||
| 3693 | s->dma_adc.subdivision = 0; | ||
| 3694 | up(&s->open_sem_adc); | ||
| 3695 | |||
| 3696 | if (prog_dmabuf_adc(s)) { | ||
| 3697 | CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR | ||
| 3698 | "cs4281: adc Program dmabufs failed.\n")); | ||
| 3699 | cs4281_release(inode, file); | ||
| 3700 | return -ENOMEM; | ||
| 3701 | } | ||
| 3702 | prog_codec(s, CS_TYPE_ADC); | ||
| 3703 | } | ||
| 3704 | if (file->f_mode & FMODE_WRITE) { | ||
| 3705 | s->prop_dac.fmt = AFMT_U8; | ||
| 3706 | s->prop_dac.fmt_original = s->prop_dac.fmt; | ||
| 3707 | s->prop_dac.channels = 1; | ||
| 3708 | s->prop_dac.rate = 8000; | ||
| 3709 | s->prop_dac.clkdiv = 96 | 0x80; | ||
| 3710 | s->conversion = 0; | ||
| 3711 | s->ena &= ~FMODE_WRITE; | ||
| 3712 | s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = | ||
| 3713 | s->dma_dac.subdivision = 0; | ||
| 3714 | up(&s->open_sem_dac); | ||
| 3715 | |||
| 3716 | if (prog_dmabuf_dac(s)) { | ||
| 3717 | CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR | ||
| 3718 | "cs4281: dac Program dmabufs failed.\n")); | ||
| 3719 | cs4281_release(inode, file); | ||
| 3720 | return -ENOMEM; | ||
| 3721 | } | ||
| 3722 | prog_codec(s, CS_TYPE_DAC); | ||
| 3723 | } | ||
| 3724 | CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, | ||
| 3725 | printk(KERN_INFO "cs4281: cs4281_open()- 0\n")); | ||
| 3726 | return nonseekable_open(inode, file); | ||
| 3727 | } | ||
| 3728 | |||
| 3729 | |||
| 3730 | // ****************************************************************************************** | ||
| 3731 | // Wave (audio) file operations struct. | ||
| 3732 | // ****************************************************************************************** | ||
| 3733 | static /*const */ struct file_operations cs4281_audio_fops = { | ||
| 3734 | .owner = THIS_MODULE, | ||
| 3735 | .llseek = no_llseek, | ||
| 3736 | .read = cs4281_read, | ||
| 3737 | .write = cs4281_write, | ||
| 3738 | .poll = cs4281_poll, | ||
| 3739 | .ioctl = cs4281_ioctl, | ||
| 3740 | .mmap = cs4281_mmap, | ||
| 3741 | .open = cs4281_open, | ||
| 3742 | .release = cs4281_release, | ||
| 3743 | }; | ||
| 3744 | |||
| 3745 | // --------------------------------------------------------------------- | ||
| 3746 | |||
| 3747 | // hold spinlock for the following! | ||
| 3748 | static void cs4281_handle_midi(struct cs4281_state *s) | ||
| 3749 | { | ||
| 3750 | unsigned char ch; | ||
| 3751 | int wake; | ||
| 3752 | unsigned temp1; | ||
| 3753 | |||
| 3754 | wake = 0; | ||
| 3755 | while (!(readl(s->pBA0 + BA0_MIDSR) & 0x80)) { | ||
| 3756 | ch = readl(s->pBA0 + BA0_MIDRP); | ||
| 3757 | if (s->midi.icnt < MIDIINBUF) { | ||
| 3758 | s->midi.ibuf[s->midi.iwr] = ch; | ||
| 3759 | s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF; | ||
| 3760 | s->midi.icnt++; | ||
| 3761 | } | ||
| 3762 | wake = 1; | ||
| 3763 | } | ||
| 3764 | if (wake) | ||
| 3765 | wake_up(&s->midi.iwait); | ||
| 3766 | wake = 0; | ||
| 3767 | while (!(readl(s->pBA0 + BA0_MIDSR) & 0x40) && s->midi.ocnt > 0) { | ||
| 3768 | temp1 = (s->midi.obuf[s->midi.ord]) & 0x000000ff; | ||
| 3769 | writel(temp1, s->pBA0 + BA0_MIDWP); | ||
| 3770 | s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF; | ||
| 3771 | s->midi.ocnt--; | ||
| 3772 | if (s->midi.ocnt < MIDIOUTBUF - 16) | ||
| 3773 | wake = 1; | ||
| 3774 | } | ||
| 3775 | if (wake) | ||
| 3776 | wake_up(&s->midi.owait); | ||
| 3777 | } | ||
| 3778 | |||
| 3779 | |||
| 3780 | |||
| 3781 | static irqreturn_t cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs) | ||
| 3782 | { | ||
| 3783 | struct cs4281_state *s = (struct cs4281_state *) dev_id; | ||
| 3784 | unsigned int temp1; | ||
| 3785 | |||
| 3786 | // fastpath out, to ease interrupt sharing | ||
| 3787 | temp1 = readl(s->pBA0 + BA0_HISR); // Get Int Status reg. | ||
| 3788 | |||
| 3789 | CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO | ||
| 3790 | "cs4281: cs4281_interrupt() BA0_HISR=0x%.8x\n", temp1)); | ||
| 3791 | /* | ||
| 3792 | * If not DMA or MIDI interrupt, then just return. | ||
| 3793 | */ | ||
| 3794 | if (!(temp1 & (HISR_DMA0 | HISR_DMA1 | HISR_MIDI))) { | ||
| 3795 | writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); | ||
| 3796 | CS_DBGOUT(CS_INTERRUPT, 9, printk(KERN_INFO | ||
| 3797 | "cs4281: cs4281_interrupt(): returning not cs4281 interrupt.\n")); | ||
| 3798 | return IRQ_NONE; | ||
| 3799 | } | ||
| 3800 | |||
| 3801 | if (temp1 & HISR_DMA0) // If play interrupt, | ||
| 3802 | readl(s->pBA0 + BA0_HDSR0); // clear the source. | ||
| 3803 | |||
| 3804 | if (temp1 & HISR_DMA1) // Same for play. | ||
| 3805 | readl(s->pBA0 + BA0_HDSR1); | ||
| 3806 | writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Local EOI | ||
| 3807 | |||
| 3808 | spin_lock(&s->lock); | ||
| 3809 | cs4281_update_ptr(s,CS_TRUE); | ||
| 3810 | cs4281_handle_midi(s); | ||
| 3811 | spin_unlock(&s->lock); | ||
| 3812 | return IRQ_HANDLED; | ||
| 3813 | } | ||
| 3814 | |||
| 3815 | // ************************************************************************** | ||
| 3816 | |||
| 3817 | static void cs4281_midi_timer(unsigned long data) | ||
| 3818 | { | ||
| 3819 | struct cs4281_state *s = (struct cs4281_state *) data; | ||
| 3820 | unsigned long flags; | ||
| 3821 | |||
| 3822 | spin_lock_irqsave(&s->lock, flags); | ||
| 3823 | cs4281_handle_midi(s); | ||
| 3824 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 3825 | s->midi.timer.expires = jiffies + 1; | ||
| 3826 | add_timer(&s->midi.timer); | ||
| 3827 | } | ||
| 3828 | |||
| 3829 | |||
| 3830 | // --------------------------------------------------------------------- | ||
| 3831 | |||
| 3832 | static ssize_t cs4281_midi_read(struct file *file, char __user *buffer, | ||
| 3833 | size_t count, loff_t * ppos) | ||
| 3834 | { | ||
| 3835 | struct cs4281_state *s = | ||
| 3836 | (struct cs4281_state *) file->private_data; | ||
| 3837 | ssize_t ret; | ||
| 3838 | unsigned long flags; | ||
| 3839 | unsigned ptr; | ||
| 3840 | int cnt; | ||
| 3841 | |||
| 3842 | VALIDATE_STATE(s); | ||
| 3843 | if (!access_ok(VERIFY_WRITE, buffer, count)) | ||
| 3844 | return -EFAULT; | ||
| 3845 | ret = 0; | ||
| 3846 | while (count > 0) { | ||
| 3847 | spin_lock_irqsave(&s->lock, flags); | ||
| 3848 | ptr = s->midi.ird; | ||
| 3849 | cnt = MIDIINBUF - ptr; | ||
| 3850 | if (s->midi.icnt < cnt) | ||
| 3851 | cnt = s->midi.icnt; | ||
| 3852 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 3853 | if (cnt > count) | ||
| 3854 | cnt = count; | ||
| 3855 | if (cnt <= 0) { | ||
| 3856 | if (file->f_flags & O_NONBLOCK) | ||
| 3857 | return ret ? ret : -EAGAIN; | ||
| 3858 | interruptible_sleep_on(&s->midi.iwait); | ||
| 3859 | if (signal_pending(current)) | ||
| 3860 | return ret ? ret : -ERESTARTSYS; | ||
| 3861 | continue; | ||
| 3862 | } | ||
| 3863 | if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) | ||
| 3864 | return ret ? ret : -EFAULT; | ||
| 3865 | ptr = (ptr + cnt) % MIDIINBUF; | ||
| 3866 | spin_lock_irqsave(&s->lock, flags); | ||
| 3867 | s->midi.ird = ptr; | ||
| 3868 | s->midi.icnt -= cnt; | ||
| 3869 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 3870 | count -= cnt; | ||
| 3871 | buffer += cnt; | ||
| 3872 | ret += cnt; | ||
| 3873 | } | ||
| 3874 | return ret; | ||
| 3875 | } | ||
| 3876 | |||
| 3877 | |||
| 3878 | static ssize_t cs4281_midi_write(struct file *file, const char __user *buffer, | ||
| 3879 | size_t count, loff_t * ppos) | ||
| 3880 | { | ||
| 3881 | struct cs4281_state *s = | ||
| 3882 | (struct cs4281_state *) file->private_data; | ||
| 3883 | ssize_t ret; | ||
| 3884 | unsigned long flags; | ||
| 3885 | unsigned ptr; | ||
| 3886 | int cnt; | ||
| 3887 | |||
| 3888 | VALIDATE_STATE(s); | ||
| 3889 | if (!access_ok(VERIFY_READ, buffer, count)) | ||
| 3890 | return -EFAULT; | ||
| 3891 | ret = 0; | ||
| 3892 | while (count > 0) { | ||
| 3893 | spin_lock_irqsave(&s->lock, flags); | ||
| 3894 | ptr = s->midi.owr; | ||
| 3895 | cnt = MIDIOUTBUF - ptr; | ||
| 3896 | if (s->midi.ocnt + cnt > MIDIOUTBUF) | ||
| 3897 | cnt = MIDIOUTBUF - s->midi.ocnt; | ||
| 3898 | if (cnt <= 0) | ||
| 3899 | cs4281_handle_midi(s); | ||
| 3900 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 3901 | if (cnt > count) | ||
| 3902 | cnt = count; | ||
| 3903 | if (cnt <= 0) { | ||
| 3904 | if (file->f_flags & O_NONBLOCK) | ||
| 3905 | return ret ? ret : -EAGAIN; | ||
| 3906 | interruptible_sleep_on(&s->midi.owait); | ||
| 3907 | if (signal_pending(current)) | ||
| 3908 | return ret ? ret : -ERESTARTSYS; | ||
| 3909 | continue; | ||
| 3910 | } | ||
| 3911 | if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) | ||
| 3912 | return ret ? ret : -EFAULT; | ||
| 3913 | ptr = (ptr + cnt) % MIDIOUTBUF; | ||
| 3914 | spin_lock_irqsave(&s->lock, flags); | ||
| 3915 | s->midi.owr = ptr; | ||
| 3916 | s->midi.ocnt += cnt; | ||
| 3917 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 3918 | count -= cnt; | ||
| 3919 | buffer += cnt; | ||
| 3920 | ret += cnt; | ||
| 3921 | spin_lock_irqsave(&s->lock, flags); | ||
| 3922 | cs4281_handle_midi(s); | ||
| 3923 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 3924 | } | ||
| 3925 | return ret; | ||
| 3926 | } | ||
| 3927 | |||
| 3928 | |||
| 3929 | static unsigned int cs4281_midi_poll(struct file *file, | ||
| 3930 | struct poll_table_struct *wait) | ||
| 3931 | { | ||
| 3932 | struct cs4281_state *s = | ||
| 3933 | (struct cs4281_state *) file->private_data; | ||
| 3934 | unsigned long flags; | ||
| 3935 | unsigned int mask = 0; | ||
| 3936 | |||
| 3937 | VALIDATE_STATE(s); | ||
| 3938 | if (file->f_flags & FMODE_WRITE) | ||
| 3939 | poll_wait(file, &s->midi.owait, wait); | ||
| 3940 | if (file->f_flags & FMODE_READ) | ||
| 3941 | poll_wait(file, &s->midi.iwait, wait); | ||
| 3942 | spin_lock_irqsave(&s->lock, flags); | ||
| 3943 | if (file->f_flags & FMODE_READ) { | ||
| 3944 | if (s->midi.icnt > 0) | ||
| 3945 | mask |= POLLIN | POLLRDNORM; | ||
| 3946 | } | ||
| 3947 | if (file->f_flags & FMODE_WRITE) { | ||
| 3948 | if (s->midi.ocnt < MIDIOUTBUF) | ||
| 3949 | mask |= POLLOUT | POLLWRNORM; | ||
| 3950 | } | ||
| 3951 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 3952 | return mask; | ||
| 3953 | } | ||
| 3954 | |||
| 3955 | |||
| 3956 | static int cs4281_midi_open(struct inode *inode, struct file *file) | ||
| 3957 | { | ||
| 3958 | unsigned long flags, temp1; | ||
| 3959 | unsigned int minor = iminor(inode); | ||
| 3960 | struct cs4281_state *s=NULL; | ||
| 3961 | struct list_head *entry; | ||
| 3962 | list_for_each(entry, &cs4281_devs) | ||
| 3963 | { | ||
| 3964 | s = list_entry(entry, struct cs4281_state, list); | ||
| 3965 | |||
| 3966 | if (s->dev_midi == minor) | ||
| 3967 | break; | ||
| 3968 | } | ||
| 3969 | |||
| 3970 | if (entry == &cs4281_devs) | ||
| 3971 | return -ENODEV; | ||
| 3972 | if (!s) | ||
| 3973 | { | ||
| 3974 | CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO | ||
| 3975 | "cs4281: cs4281_open(): Error - unable to find audio state struct\n")); | ||
| 3976 | return -ENODEV; | ||
| 3977 | } | ||
| 3978 | VALIDATE_STATE(s); | ||
| 3979 | file->private_data = s; | ||
| 3980 | // wait for device to become free | ||
| 3981 | down(&s->open_sem); | ||
| 3982 | while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) { | ||
| 3983 | if (file->f_flags & O_NONBLOCK) { | ||
| 3984 | up(&s->open_sem); | ||
| 3985 | return -EBUSY; | ||
| 3986 | } | ||
| 3987 | up(&s->open_sem); | ||
| 3988 | interruptible_sleep_on(&s->open_wait); | ||
| 3989 | if (signal_pending(current)) | ||
| 3990 | return -ERESTARTSYS; | ||
| 3991 | down(&s->open_sem); | ||
| 3992 | } | ||
| 3993 | spin_lock_irqsave(&s->lock, flags); | ||
| 3994 | if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) { | ||
| 3995 | s->midi.ird = s->midi.iwr = s->midi.icnt = 0; | ||
| 3996 | s->midi.ord = s->midi.owr = s->midi.ocnt = 0; | ||
| 3997 | writel(1, s->pBA0 + BA0_MIDCR); // Reset the interface. | ||
| 3998 | writel(0, s->pBA0 + BA0_MIDCR); // Return to normal mode. | ||
| 3999 | s->midi.ird = s->midi.iwr = s->midi.icnt = 0; | ||
| 4000 | writel(0x0000000f, s->pBA0 + BA0_MIDCR); // Enable transmit, record, ints. | ||
| 4001 | temp1 = readl(s->pBA0 + BA0_HIMR); | ||
| 4002 | writel(temp1 & 0xffbfffff, s->pBA0 + BA0_HIMR); // Enable midi int. recognition. | ||
| 4003 | writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Enable interrupts | ||
| 4004 | init_timer(&s->midi.timer); | ||
| 4005 | s->midi.timer.expires = jiffies + 1; | ||
| 4006 | s->midi.timer.data = (unsigned long) s; | ||
| 4007 | s->midi.timer.function = cs4281_midi_timer; | ||
| 4008 | add_timer(&s->midi.timer); | ||
| 4009 | } | ||
| 4010 | if (file->f_mode & FMODE_READ) { | ||
| 4011 | s->midi.ird = s->midi.iwr = s->midi.icnt = 0; | ||
| 4012 | } | ||
| 4013 | if (file->f_mode & FMODE_WRITE) { | ||
| 4014 | s->midi.ord = s->midi.owr = s->midi.ocnt = 0; | ||
| 4015 | } | ||
| 4016 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 4017 | s->open_mode |= | ||
| 4018 | (file-> | ||
| 4019 | f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | | ||
| 4020 | FMODE_MIDI_WRITE); | ||
| 4021 | up(&s->open_sem); | ||
| 4022 | return nonseekable_open(inode, file); | ||
| 4023 | } | ||
| 4024 | |||
| 4025 | |||
| 4026 | static int cs4281_midi_release(struct inode *inode, struct file *file) | ||
| 4027 | { | ||
| 4028 | struct cs4281_state *s = | ||
| 4029 | (struct cs4281_state *) file->private_data; | ||
| 4030 | DECLARE_WAITQUEUE(wait, current); | ||
| 4031 | unsigned long flags; | ||
| 4032 | unsigned count, tmo; | ||
| 4033 | |||
| 4034 | VALIDATE_STATE(s); | ||
| 4035 | |||
| 4036 | if (file->f_mode & FMODE_WRITE) { | ||
| 4037 | add_wait_queue(&s->midi.owait, &wait); | ||
| 4038 | for (;;) { | ||
| 4039 | set_current_state(TASK_INTERRUPTIBLE); | ||
| 4040 | spin_lock_irqsave(&s->lock, flags); | ||
| 4041 | count = s->midi.ocnt; | ||
| 4042 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 4043 | if (count <= 0) | ||
| 4044 | break; | ||
| 4045 | if (signal_pending(current)) | ||
| 4046 | break; | ||
| 4047 | if (file->f_flags & O_NONBLOCK) { | ||
| 4048 | remove_wait_queue(&s->midi.owait, &wait); | ||
| 4049 | current->state = TASK_RUNNING; | ||
| 4050 | return -EBUSY; | ||
| 4051 | } | ||
| 4052 | tmo = (count * HZ) / 3100; | ||
| 4053 | if (!schedule_timeout(tmo ? : 1) && tmo) | ||
| 4054 | printk(KERN_DEBUG | ||
| 4055 | "cs4281: midi timed out??\n"); | ||
| 4056 | } | ||
| 4057 | remove_wait_queue(&s->midi.owait, &wait); | ||
| 4058 | current->state = TASK_RUNNING; | ||
| 4059 | } | ||
| 4060 | down(&s->open_sem); | ||
| 4061 | s->open_mode &= | ||
| 4062 | (~(file->f_mode << FMODE_MIDI_SHIFT)) & (FMODE_MIDI_READ | | ||
| 4063 | FMODE_MIDI_WRITE); | ||
| 4064 | spin_lock_irqsave(&s->lock, flags); | ||
| 4065 | if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) { | ||
| 4066 | writel(0, s->pBA0 + BA0_MIDCR); // Disable Midi interrupts. | ||
| 4067 | del_timer(&s->midi.timer); | ||
| 4068 | } | ||
| 4069 | spin_unlock_irqrestore(&s->lock, flags); | ||
| 4070 | up(&s->open_sem); | ||
| 4071 | wake_up(&s->open_wait); | ||
| 4072 | return 0; | ||
| 4073 | } | ||
| 4074 | |||
| 4075 | // ****************************************************************************************** | ||
| 4076 | // Midi file operations struct. | ||
| 4077 | // ****************************************************************************************** | ||
| 4078 | static /*const */ struct file_operations cs4281_midi_fops = { | ||
| 4079 | .owner = THIS_MODULE, | ||
| 4080 | .llseek = no_llseek, | ||
| 4081 | .read = cs4281_midi_read, | ||
| 4082 | .write = cs4281_midi_write, | ||
| 4083 | .poll = cs4281_midi_poll, | ||
| 4084 | .open = cs4281_midi_open, | ||
| 4085 | .release = cs4281_midi_release, | ||
| 4086 | }; | ||
| 4087 | |||
| 4088 | |||
| 4089 | // --------------------------------------------------------------------- | ||
| 4090 | |||
| 4091 | // maximum number of devices | ||
| 4092 | #define NR_DEVICE 8 // Only eight devices supported currently. | ||
| 4093 | |||
| 4094 | // --------------------------------------------------------------------- | ||
| 4095 | |||
| 4096 | static struct initvol { | ||
| 4097 | int mixch; | ||
| 4098 | int vol; | ||
| 4099 | } initvol[] __devinitdata = { | ||
| 4100 | |||
| 4101 | { | ||
| 4102 | SOUND_MIXER_WRITE_VOLUME, 0x4040}, { | ||
| 4103 | SOUND_MIXER_WRITE_PCM, 0x4040}, { | ||
| 4104 | SOUND_MIXER_WRITE_SYNTH, 0x4040}, { | ||
| 4105 | SOUND_MIXER_WRITE_CD, 0x4040}, { | ||
| 4106 | SOUND_MIXER_WRITE_LINE, 0x4040}, { | ||
| 4107 | SOUND_MIXER_WRITE_LINE1, 0x4040}, { | ||
| 4108 | SOUND_MIXER_WRITE_RECLEV, 0x0000}, { | ||
| 4109 | SOUND_MIXER_WRITE_SPEAKER, 0x4040}, { | ||
| 4110 | SOUND_MIXER_WRITE_MIC, 0x0000} | ||
| 4111 | }; | ||
| 4112 | |||
| 4113 | |||
| 4114 | #ifndef NOT_CS4281_PM | ||
| 4115 | static void __devinit cs4281_BuildFIFO( | ||
| 4116 | struct cs4281_pipeline *p, | ||
| 4117 | struct cs4281_state *s) | ||
| 4118 | { | ||
| 4119 | switch(p->number) | ||
| 4120 | { | ||
| 4121 | case 0: /* playback */ | ||
| 4122 | { | ||
| 4123 | p->u32FCRnAddress = BA0_FCR0; | ||
| 4124 | p->u32FSICnAddress = BA0_FSIC0; | ||
| 4125 | p->u32FPDRnAddress = BA0_FPDR0; | ||
| 4126 | break; | ||
| 4127 | } | ||
| 4128 | case 1: /* capture */ | ||
| 4129 | { | ||
| 4130 | p->u32FCRnAddress = BA0_FCR1; | ||
| 4131 | p->u32FSICnAddress = BA0_FSIC1; | ||
| 4132 | p->u32FPDRnAddress = BA0_FPDR1; | ||
| 4133 | break; | ||
| 4134 | } | ||
| 4135 | |||
| 4136 | case 2: | ||
| 4137 | { | ||
| 4138 | p->u32FCRnAddress = BA0_FCR2; | ||
| 4139 | p->u32FSICnAddress = BA0_FSIC2; | ||
| 4140 | p->u32FPDRnAddress = BA0_FPDR2; | ||
| 4141 | break; | ||
| 4142 | } | ||
| 4143 | case 3: | ||
| 4144 | { | ||
| 4145 | p->u32FCRnAddress = BA0_FCR3; | ||
| 4146 | p->u32FSICnAddress = BA0_FSIC3; | ||
| 4147 | p->u32FPDRnAddress = BA0_FPDR3; | ||
| 4148 | break; | ||
| 4149 | } | ||
| 4150 | default: | ||
| 4151 | break; | ||
| 4152 | } | ||
| 4153 | // | ||
| 4154 | // first read the hardware to initialize the member variables | ||
| 4155 | // | ||
| 4156 | p->u32FCRnValue = readl(s->pBA0 + p->u32FCRnAddress); | ||
| 4157 | p->u32FSICnValue = readl(s->pBA0 + p->u32FSICnAddress); | ||
| 4158 | p->u32FPDRnValue = readl(s->pBA0 + p->u32FPDRnAddress); | ||
| 4159 | |||
| 4160 | } | ||
| 4161 | |||
| 4162 | static void __devinit cs4281_BuildDMAengine( | ||
| 4163 | struct cs4281_pipeline *p, | ||
| 4164 | struct cs4281_state *s) | ||
| 4165 | { | ||
| 4166 | /* | ||
| 4167 | * initialize all the addresses of this pipeline dma info. | ||
| 4168 | */ | ||
| 4169 | switch(p->number) | ||
| 4170 | { | ||
| 4171 | case 0: /* playback */ | ||
| 4172 | { | ||
| 4173 | p->u32DBAnAddress = BA0_DBA0; | ||
| 4174 | p->u32DCAnAddress = BA0_DCA0; | ||
| 4175 | p->u32DBCnAddress = BA0_DBC0; | ||
| 4176 | p->u32DCCnAddress = BA0_DCC0; | ||
| 4177 | p->u32DMRnAddress = BA0_DMR0; | ||
| 4178 | p->u32DCRnAddress = BA0_DCR0; | ||
| 4179 | p->u32HDSRnAddress = BA0_HDSR0; | ||
| 4180 | break; | ||
| 4181 | } | ||
| 4182 | |||
| 4183 | case 1: /* capture */ | ||
| 4184 | { | ||
| 4185 | p->u32DBAnAddress = BA0_DBA1; | ||
| 4186 | p->u32DCAnAddress = BA0_DCA1; | ||
| 4187 | p->u32DBCnAddress = BA0_DBC1; | ||
| 4188 | p->u32DCCnAddress = BA0_DCC1; | ||
| 4189 | p->u32DMRnAddress = BA0_DMR1; | ||
| 4190 | p->u32DCRnAddress = BA0_DCR1; | ||
| 4191 | p->u32HDSRnAddress = BA0_HDSR1; | ||
| 4192 | break; | ||
| 4193 | } | ||
| 4194 | |||
| 4195 | case 2: | ||
| 4196 | { | ||
| 4197 | p->u32DBAnAddress = BA0_DBA2; | ||
| 4198 | p->u32DCAnAddress = BA0_DCA2; | ||
| 4199 | p->u32DBCnAddress = BA0_DBC2; | ||
| 4200 | p->u32DCCnAddress = BA0_DCC2; | ||
| 4201 | p->u32DMRnAddress = BA0_DMR2; | ||
| 4202 | p->u32DCRnAddress = BA0_DCR2; | ||
| 4203 | p->u32HDSRnAddress = BA0_HDSR2; | ||
| 4204 | break; | ||
| 4205 | } | ||
| 4206 | |||
| 4207 | case 3: | ||
| 4208 | { | ||
| 4209 | p->u32DBAnAddress = BA0_DBA3; | ||
| 4210 | p->u32DCAnAddress = BA0_DCA3; | ||
| 4211 | p->u32DBCnAddress = BA0_DBC3; | ||
| 4212 | p->u32DCCnAddress = BA0_DCC3; | ||
| 4213 | p->u32DMRnAddress = BA0_DMR3; | ||
| 4214 | p->u32DCRnAddress = BA0_DCR3; | ||
| 4215 | p->u32HDSRnAddress = BA0_HDSR3; | ||
| 4216 | break; | ||
| 4217 | } | ||
| 4218 | default: | ||
| 4219 | break; | ||
| 4220 | } | ||
| 4221 | |||
| 4222 | // | ||
| 4223 | // Initialize the dma values for this pipeline | ||
| 4224 | // | ||
| 4225 | p->u32DBAnValue = readl(s->pBA0 + p->u32DBAnAddress); | ||
| 4226 | p->u32DBCnValue = readl(s->pBA0 + p->u32DBCnAddress); | ||
| 4227 | p->u32DMRnValue = readl(s->pBA0 + p->u32DMRnAddress); | ||
| 4228 | p->u32DCRnValue = readl(s->pBA0 + p->u32DCRnAddress); | ||
| 4229 | |||
| 4230 | } | ||
| 4231 | |||
| 4232 | static void __devinit cs4281_InitPM(struct cs4281_state *s) | ||
| 4233 | { | ||
| 4234 | int i; | ||
| 4235 | struct cs4281_pipeline *p; | ||
| 4236 | |||
| 4237 | for(i=0;i<CS4281_NUMBER_OF_PIPELINES;i++) | ||
| 4238 | { | ||
| 4239 | p = &s->pl[i]; | ||
| 4240 | p->number = i; | ||
| 4241 | cs4281_BuildDMAengine(p,s); | ||
| 4242 | cs4281_BuildFIFO(p,s); | ||
| 4243 | /* | ||
| 4244 | * currently only 2 pipelines are used | ||
| 4245 | * so, only set the valid bit on the playback and capture. | ||
| 4246 | */ | ||
| 4247 | if( (i == CS4281_PLAYBACK_PIPELINE_NUMBER) || | ||
| 4248 | (i == CS4281_CAPTURE_PIPELINE_NUMBER)) | ||
| 4249 | p->flags |= CS4281_PIPELINE_VALID; | ||
| 4250 | } | ||
| 4251 | s->pm.u32SSPM_BITS = 0x7e; /* rev c, use 0x7c for rev a or b */ | ||
| 4252 | } | ||
| 4253 | #endif | ||
| 4254 | |||
| 4255 | static int __devinit cs4281_probe(struct pci_dev *pcidev, | ||
| 4256 | const struct pci_device_id *pciid) | ||
| 4257 | { | ||
| 4258 | #ifndef NOT_CS4281_PM | ||
| 4259 | struct pm_dev *pmdev; | ||
| 4260 | #endif | ||
| 4261 | struct cs4281_state *s; | ||
| 4262 | dma_addr_t dma_mask; | ||
| 4263 | mm_segment_t fs; | ||
| 4264 | int i, val; | ||
| 4265 | unsigned int temp1, temp2; | ||
| 4266 | |||
| 4267 | CS_DBGOUT(CS_FUNCTION | CS_INIT, 2, | ||
| 4268 | printk(KERN_INFO "cs4281: probe()+\n")); | ||
| 4269 | |||
| 4270 | if (pci_enable_device(pcidev)) { | ||
| 4271 | CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR | ||
| 4272 | "cs4281: pci_enable_device() failed\n")); | ||
| 4273 | return -1; | ||
| 4274 | } | ||
| 4275 | if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_MEM) || | ||
| 4276 | !(pci_resource_flags(pcidev, 1) & IORESOURCE_MEM)) { | ||
| 4277 | CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR | ||
| 4278 | "cs4281: probe()- Memory region not assigned\n")); | ||
| 4279 | return -ENODEV; | ||
| 4280 | } | ||
| 4281 | if (pcidev->irq == 0) { | ||
| 4282 | CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR | ||
| 4283 | "cs4281: probe() IRQ not assigned\n")); | ||
| 4284 | return -ENODEV; | ||
| 4285 | } | ||
| 4286 | dma_mask = 0xffffffff; /* this enables playback and recording */ | ||
| 4287 | i = pci_set_dma_mask(pcidev, dma_mask); | ||
| 4288 | if (i) { | ||
| 4289 | CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR | ||
| 4290 | "cs4281: probe() architecture does not support 32bit PCI busmaster DMA\n")); | ||
| 4291 | return i; | ||
| 4292 | } | ||
| 4293 | if (!(s = kmalloc(sizeof(struct cs4281_state), GFP_KERNEL))) { | ||
| 4294 | CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR | ||
| 4295 | "cs4281: probe() no memory for state struct.\n")); | ||
| 4296 | return -1; | ||
| 4297 | } | ||
| 4298 | memset(s, 0, sizeof(struct cs4281_state)); | ||
| 4299 | init_waitqueue_head(&s->dma_adc.wait); | ||
| 4300 | init_waitqueue_head(&s->dma_dac.wait); | ||
| 4301 | init_waitqueue_head(&s->open_wait); | ||
| 4302 | init_waitqueue_head(&s->open_wait_adc); | ||
| 4303 | init_waitqueue_head(&s->open_wait_dac); | ||
| 4304 | init_waitqueue_head(&s->midi.iwait); | ||
| 4305 | init_waitqueue_head(&s->midi.owait); | ||
| 4306 | init_MUTEX(&s->open_sem); | ||
| 4307 | init_MUTEX(&s->open_sem_adc); | ||
| 4308 | init_MUTEX(&s->open_sem_dac); | ||
| 4309 | spin_lock_init(&s->lock); | ||
| 4310 | s->pBA0phys = pci_resource_start(pcidev, 0); | ||
| 4311 | s->pBA1phys = pci_resource_start(pcidev, 1); | ||
| 4312 | |||
| 4313 | /* Convert phys to linear. */ | ||
| 4314 | s->pBA0 = ioremap_nocache(s->pBA0phys, 4096); | ||
| 4315 | if (!s->pBA0) { | ||
| 4316 | CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR | ||
| 4317 | "cs4281: BA0 I/O mapping failed. Skipping part.\n")); | ||
| 4318 | goto err_free; | ||
| 4319 | } | ||
| 4320 | s->pBA1 = ioremap_nocache(s->pBA1phys, 65536); | ||
| 4321 | if (!s->pBA1) { | ||
| 4322 | CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR | ||
| 4323 | "cs4281: BA1 I/O mapping failed. Skipping part.\n")); | ||
| 4324 | goto err_unmap; | ||
| 4325 | } | ||
| 4326 | |||
| 4327 | temp1 = readl(s->pBA0 + BA0_PCICFG00); | ||
| 4328 | temp2 = readl(s->pBA0 + BA0_PCICFG04); | ||
| 4329 | |||
| 4330 | CS_DBGOUT(CS_INIT, 2, | ||
| 4331 | printk(KERN_INFO | ||
| 4332 | "cs4281: probe() BA0=0x%.8x BA1=0x%.8x pBA0=%p pBA1=%p \n", | ||
| 4333 | (unsigned) temp1, (unsigned) temp2, s->pBA0, s->pBA1)); | ||
| 4334 | CS_DBGOUT(CS_INIT, 2, | ||
| 4335 | printk(KERN_INFO | ||
| 4336 | "cs4281: probe() pBA0phys=0x%.8x pBA1phys=0x%.8x\n", | ||
| 4337 | (unsigned) s->pBA0phys, (unsigned) s->pBA1phys)); | ||
| 4338 | |||
| 4339 | #ifndef NOT_CS4281_PM | ||
| 4340 | s->pm.flags = CS4281_PM_IDLE; | ||
| 4341 | #endif | ||
| 4342 | temp1 = cs4281_hw_init(s); | ||
| 4343 | if (temp1) { | ||
| 4344 | CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR | ||
| 4345 | "cs4281: cs4281_hw_init() failed. Skipping part.\n")); | ||
| 4346 | goto err_irq; | ||
| 4347 | } | ||
| 4348 | s->magic = CS4281_MAGIC; | ||
| 4349 | s->pcidev = pcidev; | ||
| 4350 | s->irq = pcidev->irq; | ||
| 4351 | if (request_irq | ||
| 4352 | (s->irq, cs4281_interrupt, SA_SHIRQ, "Crystal CS4281", s)) { | ||
| 4353 | CS_DBGOUT(CS_INIT | CS_ERROR, 1, | ||
| 4354 | printk(KERN_ERR "cs4281: irq %u in use\n", s->irq)); | ||
| 4355 | goto err_irq; | ||
| 4356 | } | ||
| 4357 | if ((s->dev_audio = register_sound_dsp(&cs4281_audio_fops, -1)) < | ||
| 4358 | 0) { | ||
| 4359 | CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR | ||
| 4360 | "cs4281: probe() register_sound_dsp() failed.\n")); | ||
| 4361 | goto err_dev1; | ||
| 4362 | } | ||
| 4363 | if ((s->dev_mixer = register_sound_mixer(&cs4281_mixer_fops, -1)) < | ||
| 4364 | 0) { | ||
| 4365 | CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR | ||
| 4366 | "cs4281: probe() register_sound_mixer() failed.\n")); | ||
| 4367 | goto err_dev2; | ||
| 4368 | } | ||
| 4369 | if ((s->dev_midi = register_sound_midi(&cs4281_midi_fops, -1)) < 0) { | ||
| 4370 | CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR | ||
| 4371 | "cs4281: probe() register_sound_midi() failed.\n")); | ||
| 4372 | goto err_dev3; | ||
| 4373 | } | ||
| 4374 | #ifndef NOT_CS4281_PM | ||
| 4375 | cs4281_InitPM(s); | ||
| 4376 | pmdev = cs_pm_register(PM_PCI_DEV, PM_PCI_ID(pcidev), cs4281_pm_callback); | ||
| 4377 | if (pmdev) | ||
| 4378 | { | ||
| 4379 | CS_DBGOUT(CS_INIT | CS_PM, 4, printk(KERN_INFO | ||
| 4380 | "cs4281: probe() pm_register() succeeded (%p).\n", pmdev)); | ||
| 4381 | pmdev->data = s; | ||
| 4382 | } | ||
| 4383 | else | ||
| 4384 | { | ||
| 4385 | CS_DBGOUT(CS_INIT | CS_PM | CS_ERROR, 0, printk(KERN_INFO | ||
| 4386 | "cs4281: probe() pm_register() failed (%p).\n", pmdev)); | ||
| 4387 | s->pm.flags |= CS4281_PM_NOT_REGISTERED; | ||
| 4388 | } | ||
| 4389 | #endif | ||
| 4390 | |||
| 4391 | pci_set_master(pcidev); // enable bus mastering | ||
| 4392 | |||
| 4393 | fs = get_fs(); | ||
| 4394 | set_fs(KERNEL_DS); | ||
| 4395 | val = SOUND_MASK_LINE; | ||
| 4396 | mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val); | ||
| 4397 | for (i = 0; i < sizeof(initvol) / sizeof(initvol[0]); i++) { | ||
| 4398 | val = initvol[i].vol; | ||
| 4399 | mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val); | ||
| 4400 | } | ||
| 4401 | val = 1; // enable mic preamp | ||
| 4402 | mixer_ioctl(s, SOUND_MIXER_PRIVATE1, (unsigned long) &val); | ||
| 4403 | set_fs(fs); | ||
| 4404 | |||
| 4405 | pci_set_drvdata(pcidev, s); | ||
| 4406 | list_add(&s->list, &cs4281_devs); | ||
| 4407 | CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO | ||
| 4408 | "cs4281: probe()- device allocated successfully\n")); | ||
| 4409 | return 0; | ||
| 4410 | |||
| 4411 | err_dev3: | ||
| 4412 | unregister_sound_mixer(s->dev_mixer); | ||
| 4413 | err_dev2: | ||
| 4414 | unregister_sound_dsp(s->dev_audio); | ||
| 4415 | err_dev1: | ||
| 4416 | free_irq(s->irq, s); | ||
| 4417 | err_irq: | ||
| 4418 | iounmap(s->pBA1); | ||
| 4419 | err_unmap: | ||
| 4420 | iounmap(s->pBA0); | ||
| 4421 | err_free: | ||
| 4422 | kfree(s); | ||
| 4423 | |||
| 4424 | CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO | ||
| 4425 | "cs4281: probe()- no device allocated\n")); | ||
| 4426 | return -ENODEV; | ||
| 4427 | } // probe_cs4281 | ||
| 4428 | |||
| 4429 | |||
| 4430 | // --------------------------------------------------------------------- | ||
| 4431 | |||
| 4432 | static void __devexit cs4281_remove(struct pci_dev *pci_dev) | ||
| 4433 | { | ||
| 4434 | struct cs4281_state *s = pci_get_drvdata(pci_dev); | ||
| 4435 | // stop DMA controller | ||
| 4436 | synchronize_irq(s->irq); | ||
| 4437 | free_irq(s->irq, s); | ||
| 4438 | unregister_sound_dsp(s->dev_audio); | ||
| 4439 | unregister_sound_mixer(s->dev_mixer); | ||
| 4440 | unregister_sound_midi(s->dev_midi); | ||
| 4441 | iounmap(s->pBA1); | ||
| 4442 | iounmap(s->pBA0); | ||
| 4443 | pci_set_drvdata(pci_dev,NULL); | ||
| 4444 | list_del(&s->list); | ||
| 4445 | kfree(s); | ||
| 4446 | CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO | ||
| 4447 | "cs4281: cs4281_remove()-: remove successful\n")); | ||
| 4448 | } | ||
| 4449 | |||
| 4450 | static struct pci_device_id cs4281_pci_tbl[] = { | ||
| 4451 | { | ||
| 4452 | .vendor = PCI_VENDOR_ID_CIRRUS, | ||
| 4453 | .device = PCI_DEVICE_ID_CRYSTAL_CS4281, | ||
| 4454 | .subvendor = PCI_ANY_ID, | ||
| 4455 | .subdevice = PCI_ANY_ID, | ||
| 4456 | }, | ||
| 4457 | { 0, }, | ||
| 4458 | }; | ||
| 4459 | |||
| 4460 | MODULE_DEVICE_TABLE(pci, cs4281_pci_tbl); | ||
| 4461 | |||
| 4462 | static struct pci_driver cs4281_pci_driver = { | ||
| 4463 | .name = "cs4281", | ||
| 4464 | .id_table = cs4281_pci_tbl, | ||
| 4465 | .probe = cs4281_probe, | ||
| 4466 | .remove = __devexit_p(cs4281_remove), | ||
| 4467 | .suspend = CS4281_SUSPEND_TBL, | ||
| 4468 | .resume = CS4281_RESUME_TBL, | ||
| 4469 | }; | ||
| 4470 | |||
| 4471 | static int __init cs4281_init_module(void) | ||
| 4472 | { | ||
| 4473 | int rtn = 0; | ||
| 4474 | CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO | ||
| 4475 | "cs4281: cs4281_init_module()+ \n")); | ||
| 4476 | printk(KERN_INFO "cs4281: version v%d.%02d.%d time " __TIME__ " " | ||
| 4477 | __DATE__ "\n", CS4281_MAJOR_VERSION, CS4281_MINOR_VERSION, | ||
| 4478 | CS4281_ARCH); | ||
| 4479 | rtn = pci_module_init(&cs4281_pci_driver); | ||
| 4480 | |||
| 4481 | CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, | ||
| 4482 | printk(KERN_INFO "cs4281: cs4281_init_module()- (%d)\n",rtn)); | ||
| 4483 | return rtn; | ||
| 4484 | } | ||
| 4485 | |||
| 4486 | static void __exit cs4281_cleanup_module(void) | ||
| 4487 | { | ||
| 4488 | pci_unregister_driver(&cs4281_pci_driver); | ||
| 4489 | #ifndef NOT_CS4281_PM | ||
| 4490 | cs_pm_unregister_all(cs4281_pm_callback); | ||
| 4491 | #endif | ||
| 4492 | CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, | ||
| 4493 | printk(KERN_INFO "cs4281: cleanup_cs4281() finished\n")); | ||
| 4494 | } | ||
| 4495 | // --------------------------------------------------------------------- | ||
| 4496 | |||
| 4497 | MODULE_AUTHOR("gw boynton, audio@crystal.cirrus.com"); | ||
| 4498 | MODULE_DESCRIPTION("Cirrus Logic CS4281 Driver"); | ||
| 4499 | MODULE_LICENSE("GPL"); | ||
| 4500 | |||
| 4501 | // --------------------------------------------------------------------- | ||
| 4502 | |||
| 4503 | module_init(cs4281_init_module); | ||
| 4504 | module_exit(cs4281_cleanup_module); | ||
| 4505 | |||
diff --git a/sound/oss/cs4281/cs4281pm-24.c b/sound/oss/cs4281/cs4281pm-24.c new file mode 100644 index 000000000000..d2a453aff0aa --- /dev/null +++ b/sound/oss/cs4281/cs4281pm-24.c | |||
| @@ -0,0 +1,84 @@ | |||
| 1 | /******************************************************************************* | ||
| 2 | * | ||
| 3 | * "cs4281pm.c" -- Cirrus Logic-Crystal CS4281 linux audio driver. | ||
| 4 | * | ||
| 5 | * Copyright (C) 2000,2001 Cirrus Logic Corp. | ||
| 6 | * -- tom woller (twoller@crystal.cirrus.com) or | ||
| 7 | * (audio@crystal.cirrus.com). | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this program; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 22 | * | ||
| 23 | * 12/22/00 trw - new file. | ||
| 24 | * | ||
| 25 | *******************************************************************************/ | ||
| 26 | |||
| 27 | #ifndef NOT_CS4281_PM | ||
| 28 | #include <linux/pm.h> | ||
| 29 | |||
| 30 | #define cs_pm_register(a, b, c) pm_register((a), (b), (c)); | ||
| 31 | #define cs_pm_unregister_all(a) pm_unregister_all((a)); | ||
| 32 | |||
| 33 | static int cs4281_suspend(struct cs4281_state *s); | ||
| 34 | static int cs4281_resume(struct cs4281_state *s); | ||
| 35 | /* | ||
| 36 | * for now (12/22/00) only enable the pm_register PM support. | ||
| 37 | * allow these table entries to be null. | ||
| 38 | #define CS4281_SUSPEND_TBL cs4281_suspend_tbl | ||
| 39 | #define CS4281_RESUME_TBL cs4281_resume_tbl | ||
| 40 | */ | ||
| 41 | #define CS4281_SUSPEND_TBL cs4281_suspend_null | ||
| 42 | #define CS4281_RESUME_TBL cs4281_resume_null | ||
| 43 | |||
| 44 | static int cs4281_pm_callback(struct pm_dev *dev, pm_request_t rqst, void *data) | ||
| 45 | { | ||
| 46 | struct cs4281_state *state; | ||
| 47 | |||
| 48 | CS_DBGOUT(CS_PM, 2, printk(KERN_INFO | ||
| 49 | "cs4281: cs4281_pm_callback dev=%p rqst=0x%x state=%p\n", | ||
| 50 | dev,(unsigned)rqst,data)); | ||
| 51 | state = (struct cs4281_state *) dev->data; | ||
| 52 | if (state) { | ||
| 53 | switch(rqst) { | ||
| 54 | case PM_SUSPEND: | ||
| 55 | CS_DBGOUT(CS_PM, 2, printk(KERN_INFO | ||
| 56 | "cs4281: PM suspend request\n")); | ||
| 57 | if(cs4281_suspend(state)) | ||
| 58 | { | ||
| 59 | CS_DBGOUT(CS_ERROR, 2, printk(KERN_INFO | ||
| 60 | "cs4281: PM suspend request refused\n")); | ||
| 61 | return 1; | ||
| 62 | } | ||
| 63 | break; | ||
| 64 | case PM_RESUME: | ||
| 65 | CS_DBGOUT(CS_PM, 2, printk(KERN_INFO | ||
| 66 | "cs4281: PM resume request\n")); | ||
| 67 | if(cs4281_resume(state)) | ||
| 68 | { | ||
| 69 | CS_DBGOUT(CS_ERROR, 2, printk(KERN_INFO | ||
| 70 | "cs4281: PM resume request refused\n")); | ||
| 71 | return 1; | ||
| 72 | } | ||
| 73 | break; | ||
| 74 | } | ||
| 75 | } | ||
| 76 | |||
| 77 | return 0; | ||
| 78 | } | ||
| 79 | |||
| 80 | #else /* CS4281_PM */ | ||
| 81 | #define CS4281_SUSPEND_TBL cs4281_suspend_null | ||
| 82 | #define CS4281_RESUME_TBL cs4281_resume_null | ||
| 83 | #endif /* CS4281_PM */ | ||
| 84 | |||
diff --git a/sound/oss/cs4281/cs4281pm.h b/sound/oss/cs4281/cs4281pm.h new file mode 100644 index 000000000000..b44fdc9ce002 --- /dev/null +++ b/sound/oss/cs4281/cs4281pm.h | |||
| @@ -0,0 +1,74 @@ | |||
| 1 | #ifndef NOT_CS4281_PM | ||
| 2 | /******************************************************************************* | ||
| 3 | * | ||
| 4 | * "cs4281pm.h" -- Cirrus Logic-Crystal CS4281 linux audio driver. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2000,2001 Cirrus Logic Corp. | ||
| 7 | * -- tom woller (twoller@crystal.cirrus.com) or | ||
| 8 | * (audio@crystal.cirrus.com). | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | * | ||
| 15 | * This program is distributed in the hope that it will be useful, | ||
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 18 | * GNU General Public License for more details. | ||
| 19 | * | ||
| 20 | * You should have received a copy of the GNU General Public License | ||
| 21 | * along with this program; if not, write to the Free Software | ||
| 22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 23 | * | ||
| 24 | * 12/22/00 trw - new file. | ||
| 25 | * | ||
| 26 | *******************************************************************************/ | ||
| 27 | /* general pm definitions */ | ||
| 28 | #define CS4281_AC97_HIGHESTREGTORESTORE 0x26 | ||
| 29 | #define CS4281_AC97_NUMBER_RESTORE_REGS (CS4281_AC97_HIGHESTREGTORESTORE/2-1) | ||
| 30 | |||
| 31 | /* pipeline definitions */ | ||
| 32 | #define CS4281_NUMBER_OF_PIPELINES 4 | ||
| 33 | #define CS4281_PIPELINE_VALID 0x0001 | ||
| 34 | #define CS4281_PLAYBACK_PIPELINE_NUMBER 0x0000 | ||
| 35 | #define CS4281_CAPTURE_PIPELINE_NUMBER 0x0001 | ||
| 36 | |||
| 37 | /* PM state defintions */ | ||
| 38 | #define CS4281_PM_NOT_REGISTERED 0x1000 | ||
| 39 | #define CS4281_PM_IDLE 0x0001 | ||
| 40 | #define CS4281_PM_SUSPENDING 0x0002 | ||
| 41 | #define CS4281_PM_SUSPENDED 0x0004 | ||
| 42 | #define CS4281_PM_RESUMING 0x0008 | ||
| 43 | #define CS4281_PM_RESUMED 0x0010 | ||
| 44 | |||
| 45 | struct cs4281_pm { | ||
| 46 | unsigned long flags; | ||
| 47 | u32 u32CLKCR1_SAVE,u32SSPMValue,u32PPLVCvalue,u32PPRVCvalue; | ||
| 48 | u32 u32FMLVCvalue,u32FMRVCvalue,u32GPIORvalue,u32JSCTLvalue,u32SSCR; | ||
| 49 | u32 u32SRCSA,u32DacASR,u32AdcASR,u32DacSR,u32AdcSR,u32MIDCR_Save; | ||
| 50 | u32 u32SSPM_BITS; | ||
| 51 | u32 ac97[CS4281_AC97_NUMBER_RESTORE_REGS]; | ||
| 52 | u32 u32AC97_master_volume, u32AC97_headphone_volume, u32AC97_master_volume_mono; | ||
| 53 | u32 u32AC97_pcm_out_volume, u32AC97_powerdown, u32AC97_general_purpose; | ||
| 54 | u32 u32hwptr_playback,u32hwptr_capture; | ||
| 55 | }; | ||
| 56 | |||
| 57 | struct cs4281_pipeline { | ||
| 58 | unsigned flags; | ||
| 59 | unsigned number; | ||
| 60 | u32 u32DBAnValue,u32DBCnValue,u32DMRnValue,u32DCRnValue; | ||
| 61 | u32 u32DBAnAddress,u32DCAnAddress,u32DBCnAddress,u32DCCnAddress; | ||
| 62 | u32 u32DMRnAddress,u32DCRnAddress,u32HDSRnAddress; | ||
| 63 | u32 u32DBAn_Save,u32DBCn_Save,u32DMRn_Save,u32DCRn_Save; | ||
| 64 | u32 u32DCCn_Save,u32DCAn_Save; | ||
| 65 | /* | ||
| 66 | * technically, these are fifo variables, but just map the | ||
| 67 | * first fifo with the first pipeline and then use the fifo | ||
| 68 | * variables inside of the pipeline struct. | ||
| 69 | */ | ||
| 70 | u32 u32FCRn_Save,u32FSICn_Save; | ||
| 71 | u32 u32FCRnValue,u32FCRnAddress,u32FSICnValue,u32FSICnAddress; | ||
| 72 | u32 u32FPDRnValue,u32FPDRnAddress; | ||
| 73 | }; | ||
| 74 | #endif | ||