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authorKrzysztof Helt <krzysztof.h1@wp.pl>2009-01-09 17:10:52 -0500
committerTakashi Iwai <tiwai@suse.de>2009-01-11 07:09:05 -0500
commit199f7978730a4bbd88038fd84212b30759579f1a (patch)
treeee3deea40e2db5a38967fce16cb55a3b6103d154 /sound/isa/wss/wss_lib.c
parentc59765042f53a79a7a65585042ff463b69cb248c (diff)
ALSA: wss-lib: move AD1845 frequency setting into wss-lib
This is required to allow the sscape driver to autodetect installed codec. Also, do not create a timer if detected codec has no hardware timer (e.g. AD1848). Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Cc: Rene Herman Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/isa/wss/wss_lib.c')
-rw-r--r--sound/isa/wss/wss_lib.c40
1 files changed, 40 insertions, 0 deletions
diff --git a/sound/isa/wss/wss_lib.c b/sound/isa/wss/wss_lib.c
index 3d6c5f2838af..13299aebd077 100644
--- a/sound/isa/wss/wss_lib.c
+++ b/sound/isa/wss/wss_lib.c
@@ -646,6 +646,24 @@ static void snd_wss_playback_format(struct snd_wss *chip,
646 full_calib = 0; 646 full_calib = 0;
647 } 647 }
648 spin_unlock_irqrestore(&chip->reg_lock, flags); 648 spin_unlock_irqrestore(&chip->reg_lock, flags);
649 } else if (chip->hardware == WSS_HW_AD1845) {
650 unsigned rate = params_rate(params);
651
652 /*
653 * Program the AD1845 correctly for the playback stream.
654 * Note that we do NOT need to toggle the MCE bit because
655 * the PLAYBACK_ENABLE bit of the Interface Configuration
656 * register is set.
657 *
658 * NOTE: We seem to need to write to the MSB before the LSB
659 * to get the correct sample frequency.
660 */
661 spin_lock_irqsave(&chip->reg_lock, flags);
662 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, (pdfr & 0xf0));
663 snd_wss_out(chip, AD1845_UPR_FREQ_SEL, (rate >> 8) & 0xff);
664 snd_wss_out(chip, AD1845_LWR_FREQ_SEL, rate & 0xff);
665 full_calib = 0;
666 spin_unlock_irqrestore(&chip->reg_lock, flags);
649 } 667 }
650 if (full_calib) { 668 if (full_calib) {
651 snd_wss_mce_up(chip); 669 snd_wss_mce_up(chip);
@@ -690,6 +708,24 @@ static void snd_wss_capture_format(struct snd_wss *chip,
690 full_calib = 0; 708 full_calib = 0;
691 } 709 }
692 spin_unlock_irqrestore(&chip->reg_lock, flags); 710 spin_unlock_irqrestore(&chip->reg_lock, flags);
711 } else if (chip->hardware == WSS_HW_AD1845) {
712 unsigned rate = params_rate(params);
713
714 /*
715 * Program the AD1845 correctly for the capture stream.
716 * Note that we do NOT need to toggle the MCE bit because
717 * the PLAYBACK_ENABLE bit of the Interface Configuration
718 * register is set.
719 *
720 * NOTE: We seem to need to write to the MSB before the LSB
721 * to get the correct sample frequency.
722 */
723 spin_lock_irqsave(&chip->reg_lock, flags);
724 snd_wss_out(chip, CS4231_REC_FORMAT, (cdfr & 0xf0));
725 snd_wss_out(chip, AD1845_UPR_FREQ_SEL, (rate >> 8) & 0xff);
726 snd_wss_out(chip, AD1845_LWR_FREQ_SEL, rate & 0xff);
727 full_calib = 0;
728 spin_unlock_irqrestore(&chip->reg_lock, flags);
693 } 729 }
694 if (full_calib) { 730 if (full_calib) {
695 snd_wss_mce_up(chip); 731 snd_wss_mce_up(chip);
@@ -1314,6 +1350,10 @@ static int snd_wss_probe(struct snd_wss *chip)
1314 chip->image[CS4231_ALT_FEATURE_2] = 1350 chip->image[CS4231_ALT_FEATURE_2] =
1315 chip->hardware == WSS_HW_INTERWAVE ? 0xc2 : 0x01; 1351 chip->hardware == WSS_HW_INTERWAVE ? 0xc2 : 0x01;
1316 } 1352 }
1353 /* enable fine grained frequency selection */
1354 if (chip->hardware == WSS_HW_AD1845)
1355 chip->image[AD1845_PWR_DOWN] = 8;
1356
1317 ptr = (unsigned char *) &chip->image; 1357 ptr = (unsigned char *) &chip->image;
1318 regnum = (chip->hardware & WSS_HW_AD1848_MASK) ? 16 : 32; 1358 regnum = (chip->hardware & WSS_HW_AD1848_MASK) ? 16 : 32;
1319 snd_wss_mce_down(chip); 1359 snd_wss_mce_down(chip);