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authorTakashi Iwai <tiwai@suse.de>2013-10-22 04:02:57 -0400
committerTakashi Iwai <tiwai@suse.de>2013-10-22 04:02:57 -0400
commit861e66d3418a90f57b31a50110fc70b23569c551 (patch)
treeffa0d5bf8dc3e4b82b88d8942390a11d827423f9 /sound/firewire
parentb55447a7301b12d509df4b2909ed38d125ad83d4 (diff)
parentb20be8de1b3972ccf9af72850b045214faa8d830 (diff)
Merge branch 'dice-driver-playback-only' of git://git.alsa-project.org/alsa-kprivate into for-next
Diffstat (limited to 'sound/firewire')
-rw-r--r--sound/firewire/Kconfig15
-rw-r--r--sound/firewire/Makefile2
-rw-r--r--sound/firewire/amdtp.c209
-rw-r--r--sound/firewire/amdtp.h46
-rw-r--r--sound/firewire/cmp.c50
-rw-r--r--sound/firewire/dice-interface.h371
-rw-r--r--sound/firewire/dice.c1494
-rw-r--r--sound/firewire/fcp.c2
-rw-r--r--sound/firewire/isight.c43
-rw-r--r--sound/firewire/lib.c24
-rw-r--r--sound/firewire/lib.h7
-rw-r--r--sound/firewire/scs1x.c8
-rw-r--r--sound/firewire/speakers.c16
13 files changed, 2137 insertions, 150 deletions
diff --git a/sound/firewire/Kconfig b/sound/firewire/Kconfig
index ea063e1f8722..b3e274fe4a77 100644
--- a/sound/firewire/Kconfig
+++ b/sound/firewire/Kconfig
@@ -11,6 +11,21 @@ config SND_FIREWIRE_LIB
11 tristate 11 tristate
12 depends on SND_PCM 12 depends on SND_PCM
13 13
14config SND_DICE
15 tristate "DICE-based DACs (EXPERIMENTAL)"
16 select SND_HWDEP
17 select SND_PCM
18 select SND_FIREWIRE_LIB
19 help
20 Say Y here to include support for many DACs based on the DICE
21 chip family (DICE-II/Jr/Mini) from TC Applied Technologies.
22
23 At the moment, this driver supports playback only. If you
24 want to use devices that support capturing, use FFADO instead.
25
26 To compile this driver as a module, choose M here: the module
27 will be called snd-dice.
28
14config SND_FIREWIRE_SPEAKERS 29config SND_FIREWIRE_SPEAKERS
15 tristate "FireWire speakers" 30 tristate "FireWire speakers"
16 select SND_PCM 31 select SND_PCM
diff --git a/sound/firewire/Makefile b/sound/firewire/Makefile
index 460179df5bb5..509955061d30 100644
--- a/sound/firewire/Makefile
+++ b/sound/firewire/Makefile
@@ -1,10 +1,12 @@
1snd-firewire-lib-objs := lib.o iso-resources.o packets-buffer.o \ 1snd-firewire-lib-objs := lib.o iso-resources.o packets-buffer.o \
2 fcp.o cmp.o amdtp.o 2 fcp.o cmp.o amdtp.o
3snd-dice-objs := dice.o
3snd-firewire-speakers-objs := speakers.o 4snd-firewire-speakers-objs := speakers.o
4snd-isight-objs := isight.o 5snd-isight-objs := isight.o
5snd-scs1x-objs := scs1x.o 6snd-scs1x-objs := scs1x.o
6 7
7obj-$(CONFIG_SND_FIREWIRE_LIB) += snd-firewire-lib.o 8obj-$(CONFIG_SND_FIREWIRE_LIB) += snd-firewire-lib.o
9obj-$(CONFIG_SND_DICE) += snd-dice.o
8obj-$(CONFIG_SND_FIREWIRE_SPEAKERS) += snd-firewire-speakers.o 10obj-$(CONFIG_SND_FIREWIRE_SPEAKERS) += snd-firewire-speakers.o
9obj-$(CONFIG_SND_ISIGHT) += snd-isight.o 11obj-$(CONFIG_SND_ISIGHT) += snd-isight.o
10obj-$(CONFIG_SND_SCS1X) += snd-scs1x.o 12obj-$(CONFIG_SND_SCS1X) += snd-scs1x.o
diff --git a/sound/firewire/amdtp.c b/sound/firewire/amdtp.c
index 4b08b25a4db8..d3226892ad6b 100644
--- a/sound/firewire/amdtp.c
+++ b/sound/firewire/amdtp.c
@@ -42,9 +42,6 @@ static void pcm_period_tasklet(unsigned long data);
42int amdtp_out_stream_init(struct amdtp_out_stream *s, struct fw_unit *unit, 42int amdtp_out_stream_init(struct amdtp_out_stream *s, struct fw_unit *unit,
43 enum cip_out_flags flags) 43 enum cip_out_flags flags)
44{ 44{
45 if (flags != CIP_NONBLOCKING)
46 return -EINVAL;
47
48 s->unit = fw_unit_get(unit); 45 s->unit = fw_unit_get(unit);
49 s->flags = flags; 46 s->flags = flags;
50 s->context = ERR_PTR(-1); 47 s->context = ERR_PTR(-1);
@@ -62,73 +59,91 @@ EXPORT_SYMBOL(amdtp_out_stream_init);
62 */ 59 */
63void amdtp_out_stream_destroy(struct amdtp_out_stream *s) 60void amdtp_out_stream_destroy(struct amdtp_out_stream *s)
64{ 61{
65 WARN_ON(!IS_ERR(s->context)); 62 WARN_ON(amdtp_out_stream_running(s));
66 mutex_destroy(&s->mutex); 63 mutex_destroy(&s->mutex);
67 fw_unit_put(s->unit); 64 fw_unit_put(s->unit);
68} 65}
69EXPORT_SYMBOL(amdtp_out_stream_destroy); 66EXPORT_SYMBOL(amdtp_out_stream_destroy);
70 67
68const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = {
69 [CIP_SFC_32000] = 8,
70 [CIP_SFC_44100] = 8,
71 [CIP_SFC_48000] = 8,
72 [CIP_SFC_88200] = 16,
73 [CIP_SFC_96000] = 16,
74 [CIP_SFC_176400] = 32,
75 [CIP_SFC_192000] = 32,
76};
77EXPORT_SYMBOL(amdtp_syt_intervals);
78
71/** 79/**
72 * amdtp_out_stream_set_rate - set the sample rate 80 * amdtp_out_stream_set_parameters - set stream parameters
73 * @s: the AMDTP output stream to configure 81 * @s: the AMDTP output stream to configure
74 * @rate: the sample rate 82 * @rate: the sample rate
83 * @pcm_channels: the number of PCM samples in each data block, to be encoded
84 * as AM824 multi-bit linear audio
85 * @midi_ports: the number of MIDI ports (i.e., MPX-MIDI Data Channels)
75 * 86 *
76 * The sample rate must be set before the stream is started, and must not be 87 * The parameters must be set before the stream is started, and must not be
77 * changed while the stream is running. 88 * changed while the stream is running.
78 */ 89 */
79void amdtp_out_stream_set_rate(struct amdtp_out_stream *s, unsigned int rate) 90void amdtp_out_stream_set_parameters(struct amdtp_out_stream *s,
91 unsigned int rate,
92 unsigned int pcm_channels,
93 unsigned int midi_ports)
80{ 94{
81 static const struct { 95 static const unsigned int rates[] = {
82 unsigned int rate; 96 [CIP_SFC_32000] = 32000,
83 unsigned int syt_interval; 97 [CIP_SFC_44100] = 44100,
84 } rate_info[] = { 98 [CIP_SFC_48000] = 48000,
85 [CIP_SFC_32000] = { 32000, 8, }, 99 [CIP_SFC_88200] = 88200,
86 [CIP_SFC_44100] = { 44100, 8, }, 100 [CIP_SFC_96000] = 96000,
87 [CIP_SFC_48000] = { 48000, 8, }, 101 [CIP_SFC_176400] = 176400,
88 [CIP_SFC_88200] = { 88200, 16, }, 102 [CIP_SFC_192000] = 192000,
89 [CIP_SFC_96000] = { 96000, 16, },
90 [CIP_SFC_176400] = { 176400, 32, },
91 [CIP_SFC_192000] = { 192000, 32, },
92 }; 103 };
93 unsigned int sfc; 104 unsigned int sfc;
94 105
95 if (WARN_ON(!IS_ERR(s->context))) 106 if (WARN_ON(amdtp_out_stream_running(s)))
96 return; 107 return;
97 108
98 for (sfc = 0; sfc < ARRAY_SIZE(rate_info); ++sfc) 109 for (sfc = 0; sfc < CIP_SFC_COUNT; ++sfc)
99 if (rate_info[sfc].rate == rate) { 110 if (rates[sfc] == rate)
100 s->sfc = sfc; 111 goto sfc_found;
101 s->syt_interval = rate_info[sfc].syt_interval;
102 return;
103 }
104 WARN_ON(1); 112 WARN_ON(1);
113 return;
114
115sfc_found:
116 s->dual_wire = (s->flags & CIP_HI_DUALWIRE) && sfc > CIP_SFC_96000;
117 if (s->dual_wire) {
118 sfc -= 2;
119 rate /= 2;
120 pcm_channels *= 2;
121 }
122 s->sfc = sfc;
123 s->data_block_quadlets = pcm_channels + DIV_ROUND_UP(midi_ports, 8);
124 s->pcm_channels = pcm_channels;
125 s->midi_ports = midi_ports;
126
127 s->syt_interval = amdtp_syt_intervals[sfc];
128
129 /* default buffering in the device */
130 s->transfer_delay = TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE;
131 if (s->flags & CIP_BLOCKING)
132 /* additional buffering needed to adjust for no-data packets */
133 s->transfer_delay += TICKS_PER_SECOND * s->syt_interval / rate;
105} 134}
106EXPORT_SYMBOL(amdtp_out_stream_set_rate); 135EXPORT_SYMBOL(amdtp_out_stream_set_parameters);
107 136
108/** 137/**
109 * amdtp_out_stream_get_max_payload - get the stream's packet size 138 * amdtp_out_stream_get_max_payload - get the stream's packet size
110 * @s: the AMDTP output stream 139 * @s: the AMDTP output stream
111 * 140 *
112 * This function must not be called before the stream has been configured 141 * This function must not be called before the stream has been configured
113 * with amdtp_out_stream_set_hw_params(), amdtp_out_stream_set_pcm(), and 142 * with amdtp_out_stream_set_parameters().
114 * amdtp_out_stream_set_midi().
115 */ 143 */
116unsigned int amdtp_out_stream_get_max_payload(struct amdtp_out_stream *s) 144unsigned int amdtp_out_stream_get_max_payload(struct amdtp_out_stream *s)
117{ 145{
118 static const unsigned int max_data_blocks[] = { 146 return 8 + s->syt_interval * s->data_block_quadlets * 4;
119 [CIP_SFC_32000] = 4,
120 [CIP_SFC_44100] = 6,
121 [CIP_SFC_48000] = 6,
122 [CIP_SFC_88200] = 12,
123 [CIP_SFC_96000] = 12,
124 [CIP_SFC_176400] = 23,
125 [CIP_SFC_192000] = 24,
126 };
127
128 s->data_block_quadlets = s->pcm_channels;
129 s->data_block_quadlets += DIV_ROUND_UP(s->midi_ports, 8);
130
131 return 8 + max_data_blocks[s->sfc] * 4 * s->data_block_quadlets;
132} 147}
133EXPORT_SYMBOL(amdtp_out_stream_get_max_payload); 148EXPORT_SYMBOL(amdtp_out_stream_get_max_payload);
134 149
@@ -138,19 +153,26 @@ static void amdtp_write_s16(struct amdtp_out_stream *s,
138static void amdtp_write_s32(struct amdtp_out_stream *s, 153static void amdtp_write_s32(struct amdtp_out_stream *s,
139 struct snd_pcm_substream *pcm, 154 struct snd_pcm_substream *pcm,
140 __be32 *buffer, unsigned int frames); 155 __be32 *buffer, unsigned int frames);
156static void amdtp_write_s16_dualwire(struct amdtp_out_stream *s,
157 struct snd_pcm_substream *pcm,
158 __be32 *buffer, unsigned int frames);
159static void amdtp_write_s32_dualwire(struct amdtp_out_stream *s,
160 struct snd_pcm_substream *pcm,
161 __be32 *buffer, unsigned int frames);
141 162
142/** 163/**
143 * amdtp_out_stream_set_pcm_format - set the PCM format 164 * amdtp_out_stream_set_pcm_format - set the PCM format
144 * @s: the AMDTP output stream to configure 165 * @s: the AMDTP output stream to configure
145 * @format: the format of the ALSA PCM device 166 * @format: the format of the ALSA PCM device
146 * 167 *
147 * The sample format must be set before the stream is started, and must not be 168 * The sample format must be set after the other paramters (rate/PCM channels/
148 * changed while the stream is running. 169 * MIDI) and before the stream is started, and must not be changed while the
170 * stream is running.
149 */ 171 */
150void amdtp_out_stream_set_pcm_format(struct amdtp_out_stream *s, 172void amdtp_out_stream_set_pcm_format(struct amdtp_out_stream *s,
151 snd_pcm_format_t format) 173 snd_pcm_format_t format)
152{ 174{
153 if (WARN_ON(!IS_ERR(s->context))) 175 if (WARN_ON(amdtp_out_stream_running(s)))
154 return; 176 return;
155 177
156 switch (format) { 178 switch (format) {
@@ -158,10 +180,16 @@ void amdtp_out_stream_set_pcm_format(struct amdtp_out_stream *s,
158 WARN_ON(1); 180 WARN_ON(1);
159 /* fall through */ 181 /* fall through */
160 case SNDRV_PCM_FORMAT_S16: 182 case SNDRV_PCM_FORMAT_S16:
161 s->transfer_samples = amdtp_write_s16; 183 if (s->dual_wire)
184 s->transfer_samples = amdtp_write_s16_dualwire;
185 else
186 s->transfer_samples = amdtp_write_s16;
162 break; 187 break;
163 case SNDRV_PCM_FORMAT_S32: 188 case SNDRV_PCM_FORMAT_S32:
164 s->transfer_samples = amdtp_write_s32; 189 if (s->dual_wire)
190 s->transfer_samples = amdtp_write_s32_dualwire;
191 else
192 s->transfer_samples = amdtp_write_s32;
165 break; 193 break;
166 } 194 }
167} 195}
@@ -248,7 +276,7 @@ static unsigned int calculate_syt(struct amdtp_out_stream *s,
248 s->last_syt_offset = syt_offset; 276 s->last_syt_offset = syt_offset;
249 277
250 if (syt_offset < TICKS_PER_CYCLE) { 278 if (syt_offset < TICKS_PER_CYCLE) {
251 syt_offset += TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE; 279 syt_offset += s->transfer_delay;
252 syt = (cycle + syt_offset / TICKS_PER_CYCLE) << 12; 280 syt = (cycle + syt_offset / TICKS_PER_CYCLE) << 12;
253 syt += syt_offset % TICKS_PER_CYCLE; 281 syt += syt_offset % TICKS_PER_CYCLE;
254 282
@@ -310,6 +338,68 @@ static void amdtp_write_s16(struct amdtp_out_stream *s,
310 } 338 }
311} 339}
312 340
341static void amdtp_write_s32_dualwire(struct amdtp_out_stream *s,
342 struct snd_pcm_substream *pcm,
343 __be32 *buffer, unsigned int frames)
344{
345 struct snd_pcm_runtime *runtime = pcm->runtime;
346 unsigned int channels, frame_adjust_1, frame_adjust_2, i, c;
347 const u32 *src;
348
349 channels = s->pcm_channels;
350 src = (void *)runtime->dma_area +
351 s->pcm_buffer_pointer * (runtime->frame_bits / 8);
352 frame_adjust_1 = channels - 1;
353 frame_adjust_2 = 1 - (s->data_block_quadlets - channels);
354
355 channels /= 2;
356 for (i = 0; i < frames; ++i) {
357 for (c = 0; c < channels; ++c) {
358 *buffer = cpu_to_be32((*src >> 8) | 0x40000000);
359 src++;
360 buffer += 2;
361 }
362 buffer -= frame_adjust_1;
363 for (c = 0; c < channels; ++c) {
364 *buffer = cpu_to_be32((*src >> 8) | 0x40000000);
365 src++;
366 buffer += 2;
367 }
368 buffer -= frame_adjust_2;
369 }
370}
371
372static void amdtp_write_s16_dualwire(struct amdtp_out_stream *s,
373 struct snd_pcm_substream *pcm,
374 __be32 *buffer, unsigned int frames)
375{
376 struct snd_pcm_runtime *runtime = pcm->runtime;
377 unsigned int channels, frame_adjust_1, frame_adjust_2, i, c;
378 const u16 *src;
379
380 channels = s->pcm_channels;
381 src = (void *)runtime->dma_area +
382 s->pcm_buffer_pointer * (runtime->frame_bits / 8);
383 frame_adjust_1 = channels - 1;
384 frame_adjust_2 = 1 - (s->data_block_quadlets - channels);
385
386 channels /= 2;
387 for (i = 0; i < frames; ++i) {
388 for (c = 0; c < channels; ++c) {
389 *buffer = cpu_to_be32((*src << 8) | 0x40000000);
390 src++;
391 buffer += 2;
392 }
393 buffer -= frame_adjust_1;
394 for (c = 0; c < channels; ++c) {
395 *buffer = cpu_to_be32((*src << 8) | 0x40000000);
396 src++;
397 buffer += 2;
398 }
399 buffer -= frame_adjust_2;
400 }
401}
402
313static void amdtp_fill_pcm_silence(struct amdtp_out_stream *s, 403static void amdtp_fill_pcm_silence(struct amdtp_out_stream *s,
314 __be32 *buffer, unsigned int frames) 404 __be32 *buffer, unsigned int frames)
315{ 405{
@@ -344,8 +434,17 @@ static void queue_out_packet(struct amdtp_out_stream *s, unsigned int cycle)
344 return; 434 return;
345 index = s->packet_index; 435 index = s->packet_index;
346 436
347 data_blocks = calculate_data_blocks(s);
348 syt = calculate_syt(s, cycle); 437 syt = calculate_syt(s, cycle);
438 if (!(s->flags & CIP_BLOCKING)) {
439 data_blocks = calculate_data_blocks(s);
440 } else {
441 if (syt != 0xffff) {
442 data_blocks = s->syt_interval;
443 } else {
444 data_blocks = 0;
445 syt = 0xffffff;
446 }
447 }
349 448
350 buffer = s->buffer.packets[index].buffer; 449 buffer = s->buffer.packets[index].buffer;
351 buffer[0] = cpu_to_be32(ACCESS_ONCE(s->source_node_id_field) | 450 buffer[0] = cpu_to_be32(ACCESS_ONCE(s->source_node_id_field) |
@@ -386,6 +485,9 @@ static void queue_out_packet(struct amdtp_out_stream *s, unsigned int cycle)
386 s->packet_index = index; 485 s->packet_index = index;
387 486
388 if (pcm) { 487 if (pcm) {
488 if (s->dual_wire)
489 data_blocks *= 2;
490
389 ptr = s->pcm_buffer_pointer + data_blocks; 491 ptr = s->pcm_buffer_pointer + data_blocks;
390 if (ptr >= pcm->runtime->buffer_size) 492 if (ptr >= pcm->runtime->buffer_size)
391 ptr -= pcm->runtime->buffer_size; 493 ptr -= pcm->runtime->buffer_size;
@@ -455,9 +557,8 @@ static int queue_initial_skip_packets(struct amdtp_out_stream *s)
455 * @speed: firewire speed code 557 * @speed: firewire speed code
456 * 558 *
457 * The stream cannot be started until it has been configured with 559 * The stream cannot be started until it has been configured with
458 * amdtp_out_stream_set_hw_params(), amdtp_out_stream_set_pcm(), and 560 * amdtp_out_stream_set_parameters() and amdtp_out_stream_set_pcm_format(),
459 * amdtp_out_stream_set_midi(); and it must be started before any 561 * and it must be started before any PCM or MIDI device can be started.
460 * PCM or MIDI device can be started.
461 */ 562 */
462int amdtp_out_stream_start(struct amdtp_out_stream *s, int channel, int speed) 563int amdtp_out_stream_start(struct amdtp_out_stream *s, int channel, int speed)
463{ 564{
@@ -477,7 +578,7 @@ int amdtp_out_stream_start(struct amdtp_out_stream *s, int channel, int speed)
477 578
478 mutex_lock(&s->mutex); 579 mutex_lock(&s->mutex);
479 580
480 if (WARN_ON(!IS_ERR(s->context) || 581 if (WARN_ON(amdtp_out_stream_running(s) ||
481 (!s->pcm_channels && !s->midi_ports))) { 582 (!s->pcm_channels && !s->midi_ports))) {
482 err = -EBADFD; 583 err = -EBADFD;
483 goto err_unlock; 584 goto err_unlock;
@@ -573,7 +674,7 @@ void amdtp_out_stream_stop(struct amdtp_out_stream *s)
573{ 674{
574 mutex_lock(&s->mutex); 675 mutex_lock(&s->mutex);
575 676
576 if (IS_ERR(s->context)) { 677 if (!amdtp_out_stream_running(s)) {
577 mutex_unlock(&s->mutex); 678 mutex_unlock(&s->mutex);
578 return; 679 return;
579 } 680 }
diff --git a/sound/firewire/amdtp.h b/sound/firewire/amdtp.h
index f6103d68c4b1..839ebf812d79 100644
--- a/sound/firewire/amdtp.h
+++ b/sound/firewire/amdtp.h
@@ -1,6 +1,7 @@
1#ifndef SOUND_FIREWIRE_AMDTP_H_INCLUDED 1#ifndef SOUND_FIREWIRE_AMDTP_H_INCLUDED
2#define SOUND_FIREWIRE_AMDTP_H_INCLUDED 2#define SOUND_FIREWIRE_AMDTP_H_INCLUDED
3 3
4#include <linux/err.h>
4#include <linux/interrupt.h> 5#include <linux/interrupt.h>
5#include <linux/mutex.h> 6#include <linux/mutex.h>
6#include "packets-buffer.h" 7#include "packets-buffer.h"
@@ -11,9 +12,18 @@
11 * sample_rate/8000 samples, with rounding up or down to adjust 12 * sample_rate/8000 samples, with rounding up or down to adjust
12 * for clock skew and left-over fractional samples. This should 13 * for clock skew and left-over fractional samples. This should
13 * be used if supported by the device. 14 * be used if supported by the device.
15 * @CIP_BLOCKING: In blocking mode, each packet contains either zero or
16 * SYT_INTERVAL samples, with these two types alternating so that
17 * the overall sample rate comes out right.
18 * @CIP_HI_DUALWIRE: At rates above 96 kHz, pretend that the stream runs
19 * at half the actual sample rate with twice the number of channels;
20 * two samples of a channel are stored consecutively in the packet.
21 * Requires blocking mode and SYT_INTERVAL-aligned PCM buffer size.
14 */ 22 */
15enum cip_out_flags { 23enum cip_out_flags {
16 CIP_NONBLOCKING = 0, 24 CIP_NONBLOCKING = 0x00,
25 CIP_BLOCKING = 0x01,
26 CIP_HI_DUALWIRE = 0x02,
17}; 27};
18 28
19/** 29/**
@@ -27,6 +37,7 @@ enum cip_sfc {
27 CIP_SFC_96000 = 4, 37 CIP_SFC_96000 = 4,
28 CIP_SFC_176400 = 5, 38 CIP_SFC_176400 = 5,
29 CIP_SFC_192000 = 6, 39 CIP_SFC_192000 = 6,
40 CIP_SFC_COUNT
30}; 41};
31 42
32#define AMDTP_OUT_PCM_FORMAT_BITS (SNDRV_PCM_FMTBIT_S16 | \ 43#define AMDTP_OUT_PCM_FORMAT_BITS (SNDRV_PCM_FMTBIT_S16 | \
@@ -43,6 +54,7 @@ struct amdtp_out_stream {
43 struct mutex mutex; 54 struct mutex mutex;
44 55
45 enum cip_sfc sfc; 56 enum cip_sfc sfc;
57 bool dual_wire;
46 unsigned int data_block_quadlets; 58 unsigned int data_block_quadlets;
47 unsigned int pcm_channels; 59 unsigned int pcm_channels;
48 unsigned int midi_ports; 60 unsigned int midi_ports;
@@ -51,6 +63,7 @@ struct amdtp_out_stream {
51 __be32 *buffer, unsigned int frames); 63 __be32 *buffer, unsigned int frames);
52 64
53 unsigned int syt_interval; 65 unsigned int syt_interval;
66 unsigned int transfer_delay;
54 unsigned int source_node_id_field; 67 unsigned int source_node_id_field;
55 struct iso_packets_buffer buffer; 68 struct iso_packets_buffer buffer;
56 69
@@ -74,7 +87,10 @@ int amdtp_out_stream_init(struct amdtp_out_stream *s, struct fw_unit *unit,
74 enum cip_out_flags flags); 87 enum cip_out_flags flags);
75void amdtp_out_stream_destroy(struct amdtp_out_stream *s); 88void amdtp_out_stream_destroy(struct amdtp_out_stream *s);
76 89
77void amdtp_out_stream_set_rate(struct amdtp_out_stream *s, unsigned int rate); 90void amdtp_out_stream_set_parameters(struct amdtp_out_stream *s,
91 unsigned int rate,
92 unsigned int pcm_channels,
93 unsigned int midi_ports);
78unsigned int amdtp_out_stream_get_max_payload(struct amdtp_out_stream *s); 94unsigned int amdtp_out_stream_get_max_payload(struct amdtp_out_stream *s);
79 95
80int amdtp_out_stream_start(struct amdtp_out_stream *s, int channel, int speed); 96int amdtp_out_stream_start(struct amdtp_out_stream *s, int channel, int speed);
@@ -87,31 +103,11 @@ void amdtp_out_stream_pcm_prepare(struct amdtp_out_stream *s);
87unsigned long amdtp_out_stream_pcm_pointer(struct amdtp_out_stream *s); 103unsigned long amdtp_out_stream_pcm_pointer(struct amdtp_out_stream *s);
88void amdtp_out_stream_pcm_abort(struct amdtp_out_stream *s); 104void amdtp_out_stream_pcm_abort(struct amdtp_out_stream *s);
89 105
90/** 106extern const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT];
91 * amdtp_out_stream_set_pcm - configure format of PCM samples
92 * @s: the AMDTP output stream to be configured
93 * @pcm_channels: the number of PCM samples in each data block, to be encoded
94 * as AM824 multi-bit linear audio
95 *
96 * This function must not be called while the stream is running.
97 */
98static inline void amdtp_out_stream_set_pcm(struct amdtp_out_stream *s,
99 unsigned int pcm_channels)
100{
101 s->pcm_channels = pcm_channels;
102}
103 107
104/** 108static inline bool amdtp_out_stream_running(struct amdtp_out_stream *s)
105 * amdtp_out_stream_set_midi - configure format of MIDI data
106 * @s: the AMDTP output stream to be configured
107 * @midi_ports: the number of MIDI ports (i.e., MPX-MIDI Data Channels)
108 *
109 * This function must not be called while the stream is running.
110 */
111static inline void amdtp_out_stream_set_midi(struct amdtp_out_stream *s,
112 unsigned int midi_ports)
113{ 109{
114 s->midi_ports = midi_ports; 110 return !IS_ERR(s->context);
115} 111}
116 112
117/** 113/**
diff --git a/sound/firewire/cmp.c b/sound/firewire/cmp.c
index 645cb0ba4293..efdbf585e404 100644
--- a/sound/firewire/cmp.c
+++ b/sound/firewire/cmp.c
@@ -48,9 +48,6 @@ static int pcr_modify(struct cmp_connection *c,
48 int (*check)(struct cmp_connection *c, __be32 pcr), 48 int (*check)(struct cmp_connection *c, __be32 pcr),
49 enum bus_reset_handling bus_reset_handling) 49 enum bus_reset_handling bus_reset_handling)
50{ 50{
51 struct fw_device *device = fw_parent_device(c->resources.unit);
52 int generation = c->resources.generation;
53 int rcode, errors = 0;
54 __be32 old_arg, buffer[2]; 51 __be32 old_arg, buffer[2];
55 int err; 52 int err;
56 53
@@ -59,36 +56,31 @@ static int pcr_modify(struct cmp_connection *c,
59 old_arg = buffer[0]; 56 old_arg = buffer[0];
60 buffer[1] = modify(c, buffer[0]); 57 buffer[1] = modify(c, buffer[0]);
61 58
62 rcode = fw_run_transaction( 59 err = snd_fw_transaction(
63 device->card, TCODE_LOCK_COMPARE_SWAP, 60 c->resources.unit, TCODE_LOCK_COMPARE_SWAP,
64 device->node_id, generation, device->max_speed,
65 CSR_REGISTER_BASE + CSR_IPCR(c->pcr_index), 61 CSR_REGISTER_BASE + CSR_IPCR(c->pcr_index),
66 buffer, 8); 62 buffer, 8,
67 63 FW_FIXED_GENERATION | c->resources.generation);
68 if (rcode == RCODE_COMPLETE) { 64
69 if (buffer[0] == old_arg) /* success? */ 65 if (err < 0) {
70 break; 66 if (err == -EAGAIN &&
71 67 bus_reset_handling == SUCCEED_ON_BUS_RESET)
72 if (check) { 68 err = 0;
73 err = check(c, buffer[0]); 69 return err;
74 if (err < 0) 70 }
75 return err; 71
76 } 72 if (buffer[0] == old_arg) /* success? */
77 } else if (rcode == RCODE_GENERATION) 73 break;
78 goto bus_reset; 74
79 else if (rcode_is_permanent_error(rcode) || ++errors >= 3) 75 if (check) {
80 goto io_error; 76 err = check(c, buffer[0]);
77 if (err < 0)
78 return err;
79 }
81 } 80 }
82 c->last_pcr_value = buffer[1]; 81 c->last_pcr_value = buffer[1];
83 82
84 return 0; 83 return 0;
85
86io_error:
87 cmp_error(c, "transaction failed: %s\n", fw_rcode_string(rcode));
88 return -EIO;
89
90bus_reset:
91 return bus_reset_handling == ABORT_ON_BUS_RESET ? -EAGAIN : 0;
92} 84}
93 85
94 86
@@ -108,7 +100,7 @@ int cmp_connection_init(struct cmp_connection *c,
108 100
109 err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST, 101 err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
110 CSR_REGISTER_BASE + CSR_IMPR, 102 CSR_REGISTER_BASE + CSR_IMPR,
111 &impr_be, 4); 103 &impr_be, 4, 0);
112 if (err < 0) 104 if (err < 0)
113 return err; 105 return err;
114 impr = be32_to_cpu(impr_be); 106 impr = be32_to_cpu(impr_be);
diff --git a/sound/firewire/dice-interface.h b/sound/firewire/dice-interface.h
new file mode 100644
index 000000000000..27b044f84c81
--- /dev/null
+++ b/sound/firewire/dice-interface.h
@@ -0,0 +1,371 @@
1#ifndef SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED
2#define SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED
3
4/*
5 * DICE device interface definitions
6 */
7
8/*
9 * Generally, all registers can be read like memory, i.e., with quadlet read or
10 * block read transactions with at least quadlet-aligned offset and length.
11 * Writes are not allowed except where noted; quadlet-sized registers must be
12 * written with a quadlet write transaction.
13 *
14 * All values are in big endian. The DICE firmware runs on a little-endian CPU
15 * and just byte-swaps _all_ quadlets on the bus, so values without endianness
16 * (e.g. strings) get scrambled and must be byte-swapped again by the driver.
17 */
18
19/*
20 * Streaming is handled by the "DICE driver" interface. Its registers are
21 * located in this private address space.
22 */
23#define DICE_PRIVATE_SPACE 0xffffe0000000uLL
24
25/*
26 * The registers are organized in several sections, which are organized
27 * separately to allow them to be extended individually. Whether a register is
28 * supported can be detected by checking its offset against its section's size.
29 *
30 * The section offset values are relative to DICE_PRIVATE_SPACE; the offset/
31 * size values are measured in quadlets. Read-only.
32 */
33#define DICE_GLOBAL_OFFSET 0x00
34#define DICE_GLOBAL_SIZE 0x04
35#define DICE_TX_OFFSET 0x08
36#define DICE_TX_SIZE 0x0c
37#define DICE_RX_OFFSET 0x10
38#define DICE_RX_SIZE 0x14
39#define DICE_EXT_SYNC_OFFSET 0x18
40#define DICE_EXT_SYNC_SIZE 0x1c
41#define DICE_UNUSED2_OFFSET 0x20
42#define DICE_UNUSED2_SIZE 0x24
43
44/*
45 * Global settings.
46 */
47
48/*
49 * Stores the full 64-bit address (node ID and offset in the node's address
50 * space) where the device will send notifications. Must be changed with
51 * a compare/swap transaction by the owner. This register is automatically
52 * cleared on a bus reset.
53 */
54#define GLOBAL_OWNER 0x000
55#define OWNER_NO_OWNER 0xffff000000000000uLL
56#define OWNER_NODE_SHIFT 48
57
58/*
59 * A bitmask with asynchronous events; read-only. When any event(s) happen,
60 * the bits of previous events are cleared, and the value of this register is
61 * also written to the address stored in the owner register.
62 */
63#define GLOBAL_NOTIFICATION 0x008
64/* Some registers in the Rx/Tx sections may have changed. */
65#define NOTIFY_RX_CFG_CHG 0x00000001
66#define NOTIFY_TX_CFG_CHG 0x00000002
67/* Lock status of the current clock source may have changed. */
68#define NOTIFY_LOCK_CHG 0x00000010
69/* Write to the clock select register has been finished. */
70#define NOTIFY_CLOCK_ACCEPTED 0x00000020
71/* Lock status of some clock source has changed. */
72#define NOTIFY_EXT_STATUS 0x00000040
73/* Other bits may be used for device-specific events. */
74
75/*
76 * A name that can be customized for each device; read/write. Padded with zero
77 * bytes. Quadlets are byte-swapped. The encoding is whatever the host driver
78 * happens to be using.
79 */
80#define GLOBAL_NICK_NAME 0x00c
81#define NICK_NAME_SIZE 64
82
83/*
84 * The current sample rate and clock source; read/write. Whether a clock
85 * source or sample rate is supported is device-specific; the internal clock
86 * source is always available. Low/mid/high = up to 48/96/192 kHz. This
87 * register can be changed even while streams are running.
88 */
89#define GLOBAL_CLOCK_SELECT 0x04c
90#define CLOCK_SOURCE_MASK 0x000000ff
91#define CLOCK_SOURCE_AES1 0x00000000
92#define CLOCK_SOURCE_AES2 0x00000001
93#define CLOCK_SOURCE_AES3 0x00000002
94#define CLOCK_SOURCE_AES4 0x00000003
95#define CLOCK_SOURCE_AES_ANY 0x00000004
96#define CLOCK_SOURCE_ADAT 0x00000005
97#define CLOCK_SOURCE_TDIF 0x00000006
98#define CLOCK_SOURCE_WC 0x00000007
99#define CLOCK_SOURCE_ARX1 0x00000008
100#define CLOCK_SOURCE_ARX2 0x00000009
101#define CLOCK_SOURCE_ARX3 0x0000000a
102#define CLOCK_SOURCE_ARX4 0x0000000b
103#define CLOCK_SOURCE_INTERNAL 0x0000000c
104#define CLOCK_RATE_MASK 0x0000ff00
105#define CLOCK_RATE_32000 0x00000000
106#define CLOCK_RATE_44100 0x00000100
107#define CLOCK_RATE_48000 0x00000200
108#define CLOCK_RATE_88200 0x00000300
109#define CLOCK_RATE_96000 0x00000400
110#define CLOCK_RATE_176400 0x00000500
111#define CLOCK_RATE_192000 0x00000600
112#define CLOCK_RATE_ANY_LOW 0x00000700
113#define CLOCK_RATE_ANY_MID 0x00000800
114#define CLOCK_RATE_ANY_HIGH 0x00000900
115#define CLOCK_RATE_NONE 0x00000a00
116#define CLOCK_RATE_SHIFT 8
117
118/*
119 * Enable streaming; read/write. Writing a non-zero value (re)starts all
120 * streams that have a valid iso channel set; zero stops all streams. The
121 * streams' parameters must be configured before starting. This register is
122 * automatically cleared on a bus reset.
123 */
124#define GLOBAL_ENABLE 0x050
125
126/*
127 * Status of the sample clock; read-only.
128 */
129#define GLOBAL_STATUS 0x054
130/* The current clock source is locked. */
131#define STATUS_SOURCE_LOCKED 0x00000001
132/* The actual sample rate; CLOCK_RATE_32000-_192000 or _NONE. */
133#define STATUS_NOMINAL_RATE_MASK 0x0000ff00
134
135/*
136 * Status of all clock sources; read-only.
137 */
138#define GLOBAL_EXTENDED_STATUS 0x058
139/*
140 * The _LOCKED bits always show the current status; any change generates
141 * a notification.
142 */
143#define EXT_STATUS_AES1_LOCKED 0x00000001
144#define EXT_STATUS_AES2_LOCKED 0x00000002
145#define EXT_STATUS_AES3_LOCKED 0x00000004
146#define EXT_STATUS_AES4_LOCKED 0x00000008
147#define EXT_STATUS_ADAT_LOCKED 0x00000010
148#define EXT_STATUS_TDIF_LOCKED 0x00000020
149#define EXT_STATUS_ARX1_LOCKED 0x00000040
150#define EXT_STATUS_ARX2_LOCKED 0x00000080
151#define EXT_STATUS_ARX3_LOCKED 0x00000100
152#define EXT_STATUS_ARX4_LOCKED 0x00000200
153#define EXT_STATUS_WC_LOCKED 0x00000400
154/*
155 * The _SLIP bits do not generate notifications; a set bit indicates that an
156 * error occurred since the last time when this register was read with
157 * a quadlet read transaction.
158 */
159#define EXT_STATUS_AES1_SLIP 0x00010000
160#define EXT_STATUS_AES2_SLIP 0x00020000
161#define EXT_STATUS_AES3_SLIP 0x00040000
162#define EXT_STATUS_AES4_SLIP 0x00080000
163#define EXT_STATUS_ADAT_SLIP 0x00100000
164#define EXT_STATUS_TDIF_SLIP 0x00200000
165#define EXT_STATUS_ARX1_SLIP 0x00400000
166#define EXT_STATUS_ARX2_SLIP 0x00800000
167#define EXT_STATUS_ARX3_SLIP 0x01000000
168#define EXT_STATUS_ARX4_SLIP 0x02000000
169#define EXT_STATUS_WC_SLIP 0x04000000
170
171/*
172 * The measured rate of the current clock source, in Hz; read-only.
173 */
174#define GLOBAL_SAMPLE_RATE 0x05c
175
176/*
177 * The version of the DICE driver specification that this device conforms to;
178 * read-only.
179 */
180#define GLOBAL_VERSION 0x060
181
182/* Some old firmware versions do not have the following global registers: */
183
184/*
185 * Supported sample rates and clock sources; read-only.
186 */
187#define GLOBAL_CLOCK_CAPABILITIES 0x064
188#define CLOCK_CAP_RATE_32000 0x00000001
189#define CLOCK_CAP_RATE_44100 0x00000002
190#define CLOCK_CAP_RATE_48000 0x00000004
191#define CLOCK_CAP_RATE_88200 0x00000008
192#define CLOCK_CAP_RATE_96000 0x00000010
193#define CLOCK_CAP_RATE_176400 0x00000020
194#define CLOCK_CAP_RATE_192000 0x00000040
195#define CLOCK_CAP_SOURCE_AES1 0x00010000
196#define CLOCK_CAP_SOURCE_AES2 0x00020000
197#define CLOCK_CAP_SOURCE_AES3 0x00040000
198#define CLOCK_CAP_SOURCE_AES4 0x00080000
199#define CLOCK_CAP_SOURCE_AES_ANY 0x00100000
200#define CLOCK_CAP_SOURCE_ADAT 0x00200000
201#define CLOCK_CAP_SOURCE_TDIF 0x00400000
202#define CLOCK_CAP_SOURCE_WC 0x00800000
203#define CLOCK_CAP_SOURCE_ARX1 0x01000000
204#define CLOCK_CAP_SOURCE_ARX2 0x02000000
205#define CLOCK_CAP_SOURCE_ARX3 0x04000000
206#define CLOCK_CAP_SOURCE_ARX4 0x08000000
207#define CLOCK_CAP_SOURCE_INTERNAL 0x10000000
208
209/*
210 * Names of all clock sources; read-only. Quadlets are byte-swapped. Names
211 * are separated with one backslash, the list is terminated with two
212 * backslashes. Unused clock sources are included.
213 */
214#define GLOBAL_CLOCK_SOURCE_NAMES 0x068
215#define CLOCK_SOURCE_NAMES_SIZE 256
216
217/*
218 * Capture stream settings. This section includes the number/size registers
219 * and the registers of all streams.
220 */
221
222/*
223 * The number of supported capture streams; read-only.
224 */
225#define TX_NUMBER 0x000
226
227/*
228 * The size of one stream's register block, in quadlets; read-only. The
229 * registers of the first stream follow immediately afterwards; the registers
230 * of the following streams are offset by this register's value.
231 */
232#define TX_SIZE 0x004
233
234/*
235 * The isochronous channel number on which packets are sent, or -1 if the
236 * stream is not to be used; read/write.
237 */
238#define TX_ISOCHRONOUS 0x008
239
240/*
241 * The number of audio channels; read-only. There will be one quadlet per
242 * channel; the first channel is the first quadlet in a data block.
243 */
244#define TX_NUMBER_AUDIO 0x00c
245
246/*
247 * The number of MIDI ports, 0-8; read-only. If > 0, there will be one
248 * additional quadlet in each data block, following the audio quadlets.
249 */
250#define TX_NUMBER_MIDI 0x010
251
252/*
253 * The speed at which the packets are sent, SCODE_100-_400; read/write.
254 */
255#define TX_SPEED 0x014
256
257/*
258 * Names of all audio channels; read-only. Quadlets are byte-swapped. Names
259 * are separated with one backslash, the list is terminated with two
260 * backslashes.
261 */
262#define TX_NAMES 0x018
263#define TX_NAMES_SIZE 256
264
265/*
266 * Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio
267 * channel.
268 */
269#define TX_AC3_CAPABILITIES 0x118
270
271/*
272 * Send audio data with IEC60958 label; read/write. Bitmask with one bit per
273 * audio channel. This register can be changed even while the stream is
274 * running.
275 */
276#define TX_AC3_ENABLE 0x11c
277
278/*
279 * Playback stream settings. This section includes the number/size registers
280 * and the registers of all streams.
281 */
282
283/*
284 * The number of supported playback streams; read-only.
285 */
286#define RX_NUMBER 0x000
287
288/*
289 * The size of one stream's register block, in quadlets; read-only. The
290 * registers of the first stream follow immediately afterwards; the registers
291 * of the following streams are offset by this register's value.
292 */
293#define RX_SIZE 0x004
294
295/*
296 * The isochronous channel number on which packets are received, or -1 if the
297 * stream is not to be used; read/write.
298 */
299#define RX_ISOCHRONOUS 0x008
300
301/*
302 * Index of first quadlet to be interpreted; read/write. If > 0, that many
303 * quadlets at the beginning of each data block will be ignored, and all the
304 * audio and MIDI quadlets will follow.
305 */
306#define RX_SEQ_START 0x00c
307
308/*
309 * The number of audio channels; read-only. There will be one quadlet per
310 * channel.
311 */
312#define RX_NUMBER_AUDIO 0x010
313
314/*
315 * The number of MIDI ports, 0-8; read-only. If > 0, there will be one
316 * additional quadlet in each data block, following the audio quadlets.
317 */
318#define RX_NUMBER_MIDI 0x014
319
320/*
321 * Names of all audio channels; read-only. Quadlets are byte-swapped. Names
322 * are separated with one backslash, the list is terminated with two
323 * backslashes.
324 */
325#define RX_NAMES 0x018
326#define RX_NAMES_SIZE 256
327
328/*
329 * Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio
330 * channel.
331 */
332#define RX_AC3_CAPABILITIES 0x118
333
334/*
335 * Receive audio data with IEC60958 label; read/write. Bitmask with one bit
336 * per audio channel. This register can be changed even while the stream is
337 * running.
338 */
339#define RX_AC3_ENABLE 0x11c
340
341/*
342 * Extended synchronization information.
343 * This section can be read completely with a block read request.
344 */
345
346/*
347 * Current clock source; read-only.
348 */
349#define EXT_SYNC_CLOCK_SOURCE 0x000
350
351/*
352 * Clock source is locked (boolean); read-only.
353 */
354#define EXT_SYNC_LOCKED 0x004
355
356/*
357 * Current sample rate (CLOCK_RATE_* >> CLOCK_RATE_SHIFT), _32000-_192000 or
358 * _NONE; read-only.
359 */
360#define EXT_SYNC_RATE 0x008
361
362/*
363 * ADAT user data bits; read-only.
364 */
365#define EXT_SYNC_ADAT_USER_DATA 0x00c
366/* The data bits, if available. */
367#define ADAT_USER_DATA_MASK 0x0f
368/* The data bits are not available. */
369#define ADAT_USER_DATA_NO_DATA 0x10
370
371#endif
diff --git a/sound/firewire/dice.c b/sound/firewire/dice.c
new file mode 100644
index 000000000000..6feee6614193
--- /dev/null
+++ b/sound/firewire/dice.c
@@ -0,0 +1,1494 @@
1/*
2 * TC Applied Technologies Digital Interface Communications Engine driver
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 * Licensed under the terms of the GNU General Public License, version 2.
6 */
7
8#include <linux/compat.h>
9#include <linux/completion.h>
10#include <linux/delay.h>
11#include <linux/device.h>
12#include <linux/firewire.h>
13#include <linux/firewire-constants.h>
14#include <linux/jiffies.h>
15#include <linux/module.h>
16#include <linux/mod_devicetable.h>
17#include <linux/mutex.h>
18#include <linux/slab.h>
19#include <linux/spinlock.h>
20#include <linux/wait.h>
21#include <sound/control.h>
22#include <sound/core.h>
23#include <sound/firewire.h>
24#include <sound/hwdep.h>
25#include <sound/info.h>
26#include <sound/initval.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include "amdtp.h"
30#include "iso-resources.h"
31#include "lib.h"
32#include "dice-interface.h"
33
34
35struct dice {
36 struct snd_card *card;
37 struct fw_unit *unit;
38 spinlock_t lock;
39 struct mutex mutex;
40 unsigned int global_offset;
41 unsigned int rx_offset;
42 unsigned int clock_caps;
43 unsigned int rx_channels[3];
44 unsigned int rx_midi_ports[3];
45 struct fw_address_handler notification_handler;
46 int owner_generation;
47 int dev_lock_count; /* > 0 driver, < 0 userspace */
48 bool dev_lock_changed;
49 bool global_enabled;
50 struct completion clock_accepted;
51 wait_queue_head_t hwdep_wait;
52 u32 notification_bits;
53 struct fw_iso_resources resources;
54 struct amdtp_out_stream stream;
55};
56
57MODULE_DESCRIPTION("DICE driver");
58MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
59MODULE_LICENSE("GPL v2");
60
61static const unsigned int dice_rates[] = {
62 /* mode 0 */
63 [0] = 32000,
64 [1] = 44100,
65 [2] = 48000,
66 /* mode 1 */
67 [3] = 88200,
68 [4] = 96000,
69 /* mode 2 */
70 [5] = 176400,
71 [6] = 192000,
72};
73
74static unsigned int rate_to_index(unsigned int rate)
75{
76 unsigned int i;
77
78 for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
79 if (dice_rates[i] == rate)
80 return i;
81
82 return 0;
83}
84
85static unsigned int rate_index_to_mode(unsigned int rate_index)
86{
87 return ((int)rate_index - 1) / 2;
88}
89
90static void dice_lock_changed(struct dice *dice)
91{
92 dice->dev_lock_changed = true;
93 wake_up(&dice->hwdep_wait);
94}
95
96static int dice_try_lock(struct dice *dice)
97{
98 int err;
99
100 spin_lock_irq(&dice->lock);
101
102 if (dice->dev_lock_count < 0) {
103 err = -EBUSY;
104 goto out;
105 }
106
107 if (dice->dev_lock_count++ == 0)
108 dice_lock_changed(dice);
109 err = 0;
110
111out:
112 spin_unlock_irq(&dice->lock);
113
114 return err;
115}
116
117static void dice_unlock(struct dice *dice)
118{
119 spin_lock_irq(&dice->lock);
120
121 if (WARN_ON(dice->dev_lock_count <= 0))
122 goto out;
123
124 if (--dice->dev_lock_count == 0)
125 dice_lock_changed(dice);
126
127out:
128 spin_unlock_irq(&dice->lock);
129}
130
131static inline u64 global_address(struct dice *dice, unsigned int offset)
132{
133 return DICE_PRIVATE_SPACE + dice->global_offset + offset;
134}
135
136// TODO: rx index
137static inline u64 rx_address(struct dice *dice, unsigned int offset)
138{
139 return DICE_PRIVATE_SPACE + dice->rx_offset + offset;
140}
141
142static int dice_owner_set(struct dice *dice)
143{
144 struct fw_device *device = fw_parent_device(dice->unit);
145 __be64 *buffer;
146 int err, errors = 0;
147
148 buffer = kmalloc(2 * 8, GFP_KERNEL);
149 if (!buffer)
150 return -ENOMEM;
151
152 for (;;) {
153 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
154 buffer[1] = cpu_to_be64(
155 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
156 dice->notification_handler.offset);
157
158 dice->owner_generation = device->generation;
159 smp_rmb(); /* node_id vs. generation */
160 err = snd_fw_transaction(dice->unit,
161 TCODE_LOCK_COMPARE_SWAP,
162 global_address(dice, GLOBAL_OWNER),
163 buffer, 2 * 8,
164 FW_FIXED_GENERATION |
165 dice->owner_generation);
166
167 if (err == 0) {
168 if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
169 dev_err(&dice->unit->device,
170 "device is already in use\n");
171 err = -EBUSY;
172 }
173 break;
174 }
175 if (err != -EAGAIN || ++errors >= 3)
176 break;
177
178 msleep(20);
179 }
180
181 kfree(buffer);
182
183 return err;
184}
185
186static int dice_owner_update(struct dice *dice)
187{
188 struct fw_device *device = fw_parent_device(dice->unit);
189 __be64 *buffer;
190 int err;
191
192 if (dice->owner_generation == -1)
193 return 0;
194
195 buffer = kmalloc(2 * 8, GFP_KERNEL);
196 if (!buffer)
197 return -ENOMEM;
198
199 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
200 buffer[1] = cpu_to_be64(
201 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
202 dice->notification_handler.offset);
203
204 dice->owner_generation = device->generation;
205 smp_rmb(); /* node_id vs. generation */
206 err = snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
207 global_address(dice, GLOBAL_OWNER),
208 buffer, 2 * 8,
209 FW_FIXED_GENERATION | dice->owner_generation);
210
211 if (err == 0) {
212 if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
213 dev_err(&dice->unit->device,
214 "device is already in use\n");
215 err = -EBUSY;
216 }
217 } else if (err == -EAGAIN) {
218 err = 0; /* try again later */
219 }
220
221 kfree(buffer);
222
223 if (err < 0)
224 dice->owner_generation = -1;
225
226 return err;
227}
228
229static void dice_owner_clear(struct dice *dice)
230{
231 struct fw_device *device = fw_parent_device(dice->unit);
232 __be64 *buffer;
233
234 buffer = kmalloc(2 * 8, GFP_KERNEL);
235 if (!buffer)
236 return;
237
238 buffer[0] = cpu_to_be64(
239 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
240 dice->notification_handler.offset);
241 buffer[1] = cpu_to_be64(OWNER_NO_OWNER);
242 snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
243 global_address(dice, GLOBAL_OWNER),
244 buffer, 2 * 8, FW_QUIET |
245 FW_FIXED_GENERATION | dice->owner_generation);
246
247 kfree(buffer);
248
249 dice->owner_generation = -1;
250}
251
252static int dice_enable_set(struct dice *dice)
253{
254 __be32 value;
255 int err;
256
257 value = cpu_to_be32(1);
258 err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
259 global_address(dice, GLOBAL_ENABLE),
260 &value, 4,
261 FW_FIXED_GENERATION | dice->owner_generation);
262 if (err < 0)
263 return err;
264
265 dice->global_enabled = true;
266
267 return 0;
268}
269
270static void dice_enable_clear(struct dice *dice)
271{
272 __be32 value;
273
274 if (!dice->global_enabled)
275 return;
276
277 value = 0;
278 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
279 global_address(dice, GLOBAL_ENABLE),
280 &value, 4, FW_QUIET |
281 FW_FIXED_GENERATION | dice->owner_generation);
282
283 dice->global_enabled = false;
284}
285
286static void dice_notification(struct fw_card *card, struct fw_request *request,
287 int tcode, int destination, int source,
288 int generation, unsigned long long offset,
289 void *data, size_t length, void *callback_data)
290{
291 struct dice *dice = callback_data;
292 u32 bits;
293 unsigned long flags;
294
295 if (tcode != TCODE_WRITE_QUADLET_REQUEST) {
296 fw_send_response(card, request, RCODE_TYPE_ERROR);
297 return;
298 }
299 if ((offset & 3) != 0) {
300 fw_send_response(card, request, RCODE_ADDRESS_ERROR);
301 return;
302 }
303
304 bits = be32_to_cpup(data);
305
306 spin_lock_irqsave(&dice->lock, flags);
307 dice->notification_bits |= bits;
308 spin_unlock_irqrestore(&dice->lock, flags);
309
310 fw_send_response(card, request, RCODE_COMPLETE);
311
312 if (bits & NOTIFY_CLOCK_ACCEPTED)
313 complete(&dice->clock_accepted);
314 wake_up(&dice->hwdep_wait);
315}
316
317static int dice_rate_constraint(struct snd_pcm_hw_params *params,
318 struct snd_pcm_hw_rule *rule)
319{
320 struct dice *dice = rule->private;
321 const struct snd_interval *channels =
322 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_CHANNELS);
323 struct snd_interval *rate =
324 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
325 struct snd_interval allowed_rates = {
326 .min = UINT_MAX, .max = 0, .integer = 1
327 };
328 unsigned int i, mode;
329
330 for (i = 0; i < ARRAY_SIZE(dice_rates); ++i) {
331 mode = rate_index_to_mode(i);
332 if ((dice->clock_caps & (1 << i)) &&
333 snd_interval_test(channels, dice->rx_channels[mode])) {
334 allowed_rates.min = min(allowed_rates.min,
335 dice_rates[i]);
336 allowed_rates.max = max(allowed_rates.max,
337 dice_rates[i]);
338 }
339 }
340
341 return snd_interval_refine(rate, &allowed_rates);
342}
343
344static int dice_channels_constraint(struct snd_pcm_hw_params *params,
345 struct snd_pcm_hw_rule *rule)
346{
347 struct dice *dice = rule->private;
348 const struct snd_interval *rate =
349 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE);
350 struct snd_interval *channels =
351 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
352 struct snd_interval allowed_channels = {
353 .min = UINT_MAX, .max = 0, .integer = 1
354 };
355 unsigned int i, mode;
356
357 for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
358 if ((dice->clock_caps & (1 << i)) &&
359 snd_interval_test(rate, dice_rates[i])) {
360 mode = rate_index_to_mode(i);
361 allowed_channels.min = min(allowed_channels.min,
362 dice->rx_channels[mode]);
363 allowed_channels.max = max(allowed_channels.max,
364 dice->rx_channels[mode]);
365 }
366
367 return snd_interval_refine(channels, &allowed_channels);
368}
369
370static int dice_open(struct snd_pcm_substream *substream)
371{
372 static const struct snd_pcm_hardware hardware = {
373 .info = SNDRV_PCM_INFO_MMAP |
374 SNDRV_PCM_INFO_MMAP_VALID |
375 SNDRV_PCM_INFO_BATCH |
376 SNDRV_PCM_INFO_INTERLEAVED |
377 SNDRV_PCM_INFO_BLOCK_TRANSFER,
378 .formats = AMDTP_OUT_PCM_FORMAT_BITS,
379 .channels_min = UINT_MAX,
380 .channels_max = 0,
381 .buffer_bytes_max = 16 * 1024 * 1024,
382 .period_bytes_min = 1,
383 .period_bytes_max = UINT_MAX,
384 .periods_min = 1,
385 .periods_max = UINT_MAX,
386 };
387 struct dice *dice = substream->private_data;
388 struct snd_pcm_runtime *runtime = substream->runtime;
389 unsigned int i;
390 int err;
391
392 err = dice_try_lock(dice);
393 if (err < 0)
394 goto error;
395
396 runtime->hw = hardware;
397
398 for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
399 if (dice->clock_caps & (1 << i))
400 runtime->hw.rates |=
401 snd_pcm_rate_to_rate_bit(dice_rates[i]);
402 snd_pcm_limit_hw_rates(runtime);
403
404 for (i = 0; i < 3; ++i)
405 if (dice->rx_channels[i]) {
406 runtime->hw.channels_min = min(runtime->hw.channels_min,
407 dice->rx_channels[i]);
408 runtime->hw.channels_max = max(runtime->hw.channels_max,
409 dice->rx_channels[i]);
410 }
411
412 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
413 dice_rate_constraint, dice,
414 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
415 if (err < 0)
416 goto err_lock;
417 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
418 dice_channels_constraint, dice,
419 SNDRV_PCM_HW_PARAM_RATE, -1);
420 if (err < 0)
421 goto err_lock;
422
423 err = snd_pcm_hw_constraint_step(runtime, 0,
424 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 32);
425 if (err < 0)
426 goto err_lock;
427 err = snd_pcm_hw_constraint_step(runtime, 0,
428 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32);
429 if (err < 0)
430 goto err_lock;
431
432 err = snd_pcm_hw_constraint_minmax(runtime,
433 SNDRV_PCM_HW_PARAM_PERIOD_TIME,
434 5000, UINT_MAX);
435 if (err < 0)
436 goto err_lock;
437
438 err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
439 if (err < 0)
440 goto err_lock;
441
442 return 0;
443
444err_lock:
445 dice_unlock(dice);
446error:
447 return err;
448}
449
450static int dice_close(struct snd_pcm_substream *substream)
451{
452 struct dice *dice = substream->private_data;
453
454 dice_unlock(dice);
455
456 return 0;
457}
458
459static int dice_stream_start_packets(struct dice *dice)
460{
461 int err;
462
463 if (amdtp_out_stream_running(&dice->stream))
464 return 0;
465
466 err = amdtp_out_stream_start(&dice->stream, dice->resources.channel,
467 fw_parent_device(dice->unit)->max_speed);
468 if (err < 0)
469 return err;
470
471 err = dice_enable_set(dice);
472 if (err < 0) {
473 amdtp_out_stream_stop(&dice->stream);
474 return err;
475 }
476
477 return 0;
478}
479
480static int dice_stream_start(struct dice *dice)
481{
482 __be32 channel;
483 int err;
484
485 if (!dice->resources.allocated) {
486 err = fw_iso_resources_allocate(&dice->resources,
487 amdtp_out_stream_get_max_payload(&dice->stream),
488 fw_parent_device(dice->unit)->max_speed);
489 if (err < 0)
490 goto error;
491
492 channel = cpu_to_be32(dice->resources.channel);
493 err = snd_fw_transaction(dice->unit,
494 TCODE_WRITE_QUADLET_REQUEST,
495 rx_address(dice, RX_ISOCHRONOUS),
496 &channel, 4, 0);
497 if (err < 0)
498 goto err_resources;
499 }
500
501 err = dice_stream_start_packets(dice);
502 if (err < 0)
503 goto err_rx_channel;
504
505 return 0;
506
507err_rx_channel:
508 channel = cpu_to_be32((u32)-1);
509 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
510 rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
511err_resources:
512 fw_iso_resources_free(&dice->resources);
513error:
514 return err;
515}
516
517static void dice_stream_stop_packets(struct dice *dice)
518{
519 if (amdtp_out_stream_running(&dice->stream)) {
520 dice_enable_clear(dice);
521 amdtp_out_stream_stop(&dice->stream);
522 }
523}
524
525static void dice_stream_stop(struct dice *dice)
526{
527 __be32 channel;
528
529 dice_stream_stop_packets(dice);
530
531 if (!dice->resources.allocated)
532 return;
533
534 channel = cpu_to_be32((u32)-1);
535 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
536 rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
537
538 fw_iso_resources_free(&dice->resources);
539}
540
541static int dice_change_rate(struct dice *dice, unsigned int clock_rate)
542{
543 __be32 value;
544 int err;
545
546 INIT_COMPLETION(dice->clock_accepted);
547
548 value = cpu_to_be32(clock_rate | CLOCK_SOURCE_ARX1);
549 err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
550 global_address(dice, GLOBAL_CLOCK_SELECT),
551 &value, 4, 0);
552 if (err < 0)
553 return err;
554
555 if (!wait_for_completion_timeout(&dice->clock_accepted,
556 msecs_to_jiffies(100)))
557 dev_warn(&dice->unit->device, "clock change timed out\n");
558
559 return 0;
560}
561
562static int dice_hw_params(struct snd_pcm_substream *substream,
563 struct snd_pcm_hw_params *hw_params)
564{
565 struct dice *dice = substream->private_data;
566 unsigned int rate_index, mode;
567 int err;
568
569 mutex_lock(&dice->mutex);
570 dice_stream_stop(dice);
571 mutex_unlock(&dice->mutex);
572
573 err = snd_pcm_lib_alloc_vmalloc_buffer(substream,
574 params_buffer_bytes(hw_params));
575 if (err < 0)
576 return err;
577
578 rate_index = rate_to_index(params_rate(hw_params));
579 err = dice_change_rate(dice, rate_index << CLOCK_RATE_SHIFT);
580 if (err < 0)
581 return err;
582
583 mode = rate_index_to_mode(rate_index);
584 amdtp_out_stream_set_parameters(&dice->stream,
585 params_rate(hw_params),
586 params_channels(hw_params),
587 dice->rx_midi_ports[mode]);
588 amdtp_out_stream_set_pcm_format(&dice->stream,
589 params_format(hw_params));
590
591 return 0;
592}
593
594static int dice_hw_free(struct snd_pcm_substream *substream)
595{
596 struct dice *dice = substream->private_data;
597
598 mutex_lock(&dice->mutex);
599 dice_stream_stop(dice);
600 mutex_unlock(&dice->mutex);
601
602 return snd_pcm_lib_free_vmalloc_buffer(substream);
603}
604
605static int dice_prepare(struct snd_pcm_substream *substream)
606{
607 struct dice *dice = substream->private_data;
608 int err;
609
610 mutex_lock(&dice->mutex);
611
612 if (amdtp_out_streaming_error(&dice->stream))
613 dice_stream_stop_packets(dice);
614
615 err = dice_stream_start(dice);
616 if (err < 0) {
617 mutex_unlock(&dice->mutex);
618 return err;
619 }
620
621 mutex_unlock(&dice->mutex);
622
623 amdtp_out_stream_pcm_prepare(&dice->stream);
624
625 return 0;
626}
627
628static int dice_trigger(struct snd_pcm_substream *substream, int cmd)
629{
630 struct dice *dice = substream->private_data;
631 struct snd_pcm_substream *pcm;
632
633 switch (cmd) {
634 case SNDRV_PCM_TRIGGER_START:
635 pcm = substream;
636 break;
637 case SNDRV_PCM_TRIGGER_STOP:
638 pcm = NULL;
639 break;
640 default:
641 return -EINVAL;
642 }
643 amdtp_out_stream_pcm_trigger(&dice->stream, pcm);
644
645 return 0;
646}
647
648static snd_pcm_uframes_t dice_pointer(struct snd_pcm_substream *substream)
649{
650 struct dice *dice = substream->private_data;
651
652 return amdtp_out_stream_pcm_pointer(&dice->stream);
653}
654
655static int dice_create_pcm(struct dice *dice)
656{
657 static struct snd_pcm_ops ops = {
658 .open = dice_open,
659 .close = dice_close,
660 .ioctl = snd_pcm_lib_ioctl,
661 .hw_params = dice_hw_params,
662 .hw_free = dice_hw_free,
663 .prepare = dice_prepare,
664 .trigger = dice_trigger,
665 .pointer = dice_pointer,
666 .page = snd_pcm_lib_get_vmalloc_page,
667 .mmap = snd_pcm_lib_mmap_vmalloc,
668 };
669 struct snd_pcm *pcm;
670 int err;
671
672 err = snd_pcm_new(dice->card, "DICE", 0, 1, 0, &pcm);
673 if (err < 0)
674 return err;
675 pcm->private_data = dice;
676 strcpy(pcm->name, dice->card->shortname);
677 pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->ops = &ops;
678
679 return 0;
680}
681
682static long dice_hwdep_read(struct snd_hwdep *hwdep, char __user *buf,
683 long count, loff_t *offset)
684{
685 struct dice *dice = hwdep->private_data;
686 DEFINE_WAIT(wait);
687 union snd_firewire_event event;
688
689 spin_lock_irq(&dice->lock);
690
691 while (!dice->dev_lock_changed && dice->notification_bits == 0) {
692 prepare_to_wait(&dice->hwdep_wait, &wait, TASK_INTERRUPTIBLE);
693 spin_unlock_irq(&dice->lock);
694 schedule();
695 finish_wait(&dice->hwdep_wait, &wait);
696 if (signal_pending(current))
697 return -ERESTARTSYS;
698 spin_lock_irq(&dice->lock);
699 }
700
701 memset(&event, 0, sizeof(event));
702 if (dice->dev_lock_changed) {
703 event.lock_status.type = SNDRV_FIREWIRE_EVENT_LOCK_STATUS;
704 event.lock_status.status = dice->dev_lock_count > 0;
705 dice->dev_lock_changed = false;
706
707 count = min(count, (long)sizeof(event.lock_status));
708 } else {
709 event.dice_notification.type = SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION;
710 event.dice_notification.notification = dice->notification_bits;
711 dice->notification_bits = 0;
712
713 count = min(count, (long)sizeof(event.dice_notification));
714 }
715
716 spin_unlock_irq(&dice->lock);
717
718 if (copy_to_user(buf, &event, count))
719 return -EFAULT;
720
721 return count;
722}
723
724static unsigned int dice_hwdep_poll(struct snd_hwdep *hwdep, struct file *file,
725 poll_table *wait)
726{
727 struct dice *dice = hwdep->private_data;
728 unsigned int events;
729
730 poll_wait(file, &dice->hwdep_wait, wait);
731
732 spin_lock_irq(&dice->lock);
733 if (dice->dev_lock_changed || dice->notification_bits != 0)
734 events = POLLIN | POLLRDNORM;
735 else
736 events = 0;
737 spin_unlock_irq(&dice->lock);
738
739 return events;
740}
741
742static int dice_hwdep_get_info(struct dice *dice, void __user *arg)
743{
744 struct fw_device *dev = fw_parent_device(dice->unit);
745 struct snd_firewire_get_info info;
746
747 memset(&info, 0, sizeof(info));
748 info.type = SNDRV_FIREWIRE_TYPE_DICE;
749 info.card = dev->card->index;
750 *(__be32 *)&info.guid[0] = cpu_to_be32(dev->config_rom[3]);
751 *(__be32 *)&info.guid[4] = cpu_to_be32(dev->config_rom[4]);
752 strlcpy(info.device_name, dev_name(&dev->device),
753 sizeof(info.device_name));
754
755 if (copy_to_user(arg, &info, sizeof(info)))
756 return -EFAULT;
757
758 return 0;
759}
760
761static int dice_hwdep_lock(struct dice *dice)
762{
763 int err;
764
765 spin_lock_irq(&dice->lock);
766
767 if (dice->dev_lock_count == 0) {
768 dice->dev_lock_count = -1;
769 err = 0;
770 } else {
771 err = -EBUSY;
772 }
773
774 spin_unlock_irq(&dice->lock);
775
776 return err;
777}
778
779static int dice_hwdep_unlock(struct dice *dice)
780{
781 int err;
782
783 spin_lock_irq(&dice->lock);
784
785 if (dice->dev_lock_count == -1) {
786 dice->dev_lock_count = 0;
787 err = 0;
788 } else {
789 err = -EBADFD;
790 }
791
792 spin_unlock_irq(&dice->lock);
793
794 return err;
795}
796
797static int dice_hwdep_release(struct snd_hwdep *hwdep, struct file *file)
798{
799 struct dice *dice = hwdep->private_data;
800
801 spin_lock_irq(&dice->lock);
802 if (dice->dev_lock_count == -1)
803 dice->dev_lock_count = 0;
804 spin_unlock_irq(&dice->lock);
805
806 return 0;
807}
808
809static int dice_hwdep_ioctl(struct snd_hwdep *hwdep, struct file *file,
810 unsigned int cmd, unsigned long arg)
811{
812 struct dice *dice = hwdep->private_data;
813
814 switch (cmd) {
815 case SNDRV_FIREWIRE_IOCTL_GET_INFO:
816 return dice_hwdep_get_info(dice, (void __user *)arg);
817 case SNDRV_FIREWIRE_IOCTL_LOCK:
818 return dice_hwdep_lock(dice);
819 case SNDRV_FIREWIRE_IOCTL_UNLOCK:
820 return dice_hwdep_unlock(dice);
821 default:
822 return -ENOIOCTLCMD;
823 }
824}
825
826#ifdef CONFIG_COMPAT
827static int dice_hwdep_compat_ioctl(struct snd_hwdep *hwdep, struct file *file,
828 unsigned int cmd, unsigned long arg)
829{
830 return dice_hwdep_ioctl(hwdep, file, cmd,
831 (unsigned long)compat_ptr(arg));
832}
833#else
834#define dice_hwdep_compat_ioctl NULL
835#endif
836
837static int dice_create_hwdep(struct dice *dice)
838{
839 static const struct snd_hwdep_ops ops = {
840 .read = dice_hwdep_read,
841 .release = dice_hwdep_release,
842 .poll = dice_hwdep_poll,
843 .ioctl = dice_hwdep_ioctl,
844 .ioctl_compat = dice_hwdep_compat_ioctl,
845 };
846 struct snd_hwdep *hwdep;
847 int err;
848
849 err = snd_hwdep_new(dice->card, "DICE", 0, &hwdep);
850 if (err < 0)
851 return err;
852 strcpy(hwdep->name, "DICE");
853 hwdep->iface = SNDRV_HWDEP_IFACE_FW_DICE;
854 hwdep->ops = ops;
855 hwdep->private_data = dice;
856 hwdep->exclusive = true;
857
858 return 0;
859}
860
861static int dice_proc_read_mem(struct dice *dice, void *buffer,
862 unsigned int offset_q, unsigned int quadlets)
863{
864 unsigned int i;
865 int err;
866
867 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
868 DICE_PRIVATE_SPACE + 4 * offset_q,
869 buffer, 4 * quadlets, 0);
870 if (err < 0)
871 return err;
872
873 for (i = 0; i < quadlets; ++i)
874 be32_to_cpus(&((u32 *)buffer)[i]);
875
876 return 0;
877}
878
879static const char *str_from_array(const char *const strs[], unsigned int count,
880 unsigned int i)
881{
882 if (i < count)
883 return strs[i];
884 else
885 return "(unknown)";
886}
887
888static void dice_proc_fixup_string(char *s, unsigned int size)
889{
890 unsigned int i;
891
892 for (i = 0; i < size; i += 4)
893 cpu_to_le32s((u32 *)(s + i));
894
895 for (i = 0; i < size - 2; ++i) {
896 if (s[i] == '\0')
897 return;
898 if (s[i] == '\\' && s[i + 1] == '\\') {
899 s[i + 2] = '\0';
900 return;
901 }
902 }
903 s[size - 1] = '\0';
904}
905
906static void dice_proc_read(struct snd_info_entry *entry,
907 struct snd_info_buffer *buffer)
908{
909 static const char *const section_names[5] = {
910 "global", "tx", "rx", "ext_sync", "unused2"
911 };
912 static const char *const clock_sources[] = {
913 "aes1", "aes2", "aes3", "aes4", "aes", "adat", "tdif",
914 "wc", "arx1", "arx2", "arx3", "arx4", "internal"
915 };
916 static const char *const rates[] = {
917 "32000", "44100", "48000", "88200", "96000", "176400", "192000",
918 "any low", "any mid", "any high", "none"
919 };
920 struct dice *dice = entry->private_data;
921 u32 sections[ARRAY_SIZE(section_names) * 2];
922 struct {
923 u32 number;
924 u32 size;
925 } tx_rx_header;
926 union {
927 struct {
928 u32 owner_hi, owner_lo;
929 u32 notification;
930 char nick_name[NICK_NAME_SIZE];
931 u32 clock_select;
932 u32 enable;
933 u32 status;
934 u32 extended_status;
935 u32 sample_rate;
936 u32 version;
937 u32 clock_caps;
938 char clock_source_names[CLOCK_SOURCE_NAMES_SIZE];
939 } global;
940 struct {
941 u32 iso;
942 u32 number_audio;
943 u32 number_midi;
944 u32 speed;
945 char names[TX_NAMES_SIZE];
946 u32 ac3_caps;
947 u32 ac3_enable;
948 } tx;
949 struct {
950 u32 iso;
951 u32 seq_start;
952 u32 number_audio;
953 u32 number_midi;
954 char names[RX_NAMES_SIZE];
955 u32 ac3_caps;
956 u32 ac3_enable;
957 } rx;
958 struct {
959 u32 clock_source;
960 u32 locked;
961 u32 rate;
962 u32 adat_user_data;
963 } ext_sync;
964 } buf;
965 unsigned int quadlets, stream, i;
966
967 if (dice_proc_read_mem(dice, sections, 0, ARRAY_SIZE(sections)) < 0)
968 return;
969 snd_iprintf(buffer, "sections:\n");
970 for (i = 0; i < ARRAY_SIZE(section_names); ++i)
971 snd_iprintf(buffer, " %s: offset %u, size %u\n",
972 section_names[i],
973 sections[i * 2], sections[i * 2 + 1]);
974
975 quadlets = min_t(u32, sections[1], sizeof(buf.global) / 4);
976 if (dice_proc_read_mem(dice, &buf.global, sections[0], quadlets) < 0)
977 return;
978 snd_iprintf(buffer, "global:\n");
979 snd_iprintf(buffer, " owner: %04x:%04x%08x\n",
980 buf.global.owner_hi >> 16,
981 buf.global.owner_hi & 0xffff, buf.global.owner_lo);
982 snd_iprintf(buffer, " notification: %08x\n", buf.global.notification);
983 dice_proc_fixup_string(buf.global.nick_name, NICK_NAME_SIZE);
984 snd_iprintf(buffer, " nick name: %s\n", buf.global.nick_name);
985 snd_iprintf(buffer, " clock select: %s %s\n",
986 str_from_array(clock_sources, ARRAY_SIZE(clock_sources),
987 buf.global.clock_select & CLOCK_SOURCE_MASK),
988 str_from_array(rates, ARRAY_SIZE(rates),
989 (buf.global.clock_select & CLOCK_RATE_MASK)
990 >> CLOCK_RATE_SHIFT));
991 snd_iprintf(buffer, " enable: %u\n", buf.global.enable);
992 snd_iprintf(buffer, " status: %slocked %s\n",
993 buf.global.status & STATUS_SOURCE_LOCKED ? "" : "un",
994 str_from_array(rates, ARRAY_SIZE(rates),
995 (buf.global.status &
996 STATUS_NOMINAL_RATE_MASK)
997 >> CLOCK_RATE_SHIFT));
998 snd_iprintf(buffer, " ext status: %08x\n", buf.global.extended_status);
999 snd_iprintf(buffer, " sample rate: %u\n", buf.global.sample_rate);
1000 snd_iprintf(buffer, " version: %u.%u.%u.%u\n",
1001 (buf.global.version >> 24) & 0xff,
1002 (buf.global.version >> 16) & 0xff,
1003 (buf.global.version >> 8) & 0xff,
1004 (buf.global.version >> 0) & 0xff);
1005 if (quadlets >= 90) {
1006 snd_iprintf(buffer, " clock caps:");
1007 for (i = 0; i <= 6; ++i)
1008 if (buf.global.clock_caps & (1 << i))
1009 snd_iprintf(buffer, " %s", rates[i]);
1010 for (i = 0; i <= 12; ++i)
1011 if (buf.global.clock_caps & (1 << (16 + i)))
1012 snd_iprintf(buffer, " %s", clock_sources[i]);
1013 snd_iprintf(buffer, "\n");
1014 dice_proc_fixup_string(buf.global.clock_source_names,
1015 CLOCK_SOURCE_NAMES_SIZE);
1016 snd_iprintf(buffer, " clock source names: %s\n",
1017 buf.global.clock_source_names);
1018 }
1019
1020 if (dice_proc_read_mem(dice, &tx_rx_header, sections[2], 2) < 0)
1021 return;
1022 quadlets = min_t(u32, tx_rx_header.size, sizeof(buf.tx));
1023 for (stream = 0; stream < tx_rx_header.number; ++stream) {
1024 if (dice_proc_read_mem(dice, &buf.tx, sections[2] + 2 +
1025 stream * tx_rx_header.size,
1026 quadlets) < 0)
1027 break;
1028 snd_iprintf(buffer, "tx %u:\n", stream);
1029 snd_iprintf(buffer, " iso channel: %d\n", (int)buf.tx.iso);
1030 snd_iprintf(buffer, " audio channels: %u\n",
1031 buf.tx.number_audio);
1032 snd_iprintf(buffer, " midi ports: %u\n", buf.tx.number_midi);
1033 snd_iprintf(buffer, " speed: S%u\n", 100u << buf.tx.speed);
1034 if (quadlets >= 68) {
1035 dice_proc_fixup_string(buf.tx.names, TX_NAMES_SIZE);
1036 snd_iprintf(buffer, " names: %s\n", buf.tx.names);
1037 }
1038 if (quadlets >= 70) {
1039 snd_iprintf(buffer, " ac3 caps: %08x\n",
1040 buf.tx.ac3_caps);
1041 snd_iprintf(buffer, " ac3 enable: %08x\n",
1042 buf.tx.ac3_enable);
1043 }
1044 }
1045
1046 if (dice_proc_read_mem(dice, &tx_rx_header, sections[4], 2) < 0)
1047 return;
1048 quadlets = min_t(u32, tx_rx_header.size, sizeof(buf.rx));
1049 for (stream = 0; stream < tx_rx_header.number; ++stream) {
1050 if (dice_proc_read_mem(dice, &buf.rx, sections[4] + 2 +
1051 stream * tx_rx_header.size,
1052 quadlets) < 0)
1053 break;
1054 snd_iprintf(buffer, "rx %u:\n", stream);
1055 snd_iprintf(buffer, " iso channel: %d\n", (int)buf.rx.iso);
1056 snd_iprintf(buffer, " sequence start: %u\n", buf.rx.seq_start);
1057 snd_iprintf(buffer, " audio channels: %u\n",
1058 buf.rx.number_audio);
1059 snd_iprintf(buffer, " midi ports: %u\n", buf.rx.number_midi);
1060 if (quadlets >= 68) {
1061 dice_proc_fixup_string(buf.rx.names, RX_NAMES_SIZE);
1062 snd_iprintf(buffer, " names: %s\n", buf.rx.names);
1063 }
1064 if (quadlets >= 70) {
1065 snd_iprintf(buffer, " ac3 caps: %08x\n",
1066 buf.rx.ac3_caps);
1067 snd_iprintf(buffer, " ac3 enable: %08x\n",
1068 buf.rx.ac3_enable);
1069 }
1070 }
1071
1072 quadlets = min_t(u32, sections[7], sizeof(buf.ext_sync) / 4);
1073 if (quadlets >= 4) {
1074 if (dice_proc_read_mem(dice, &buf.ext_sync,
1075 sections[6], 4) < 0)
1076 return;
1077 snd_iprintf(buffer, "ext status:\n");
1078 snd_iprintf(buffer, " clock source: %s\n",
1079 str_from_array(clock_sources,
1080 ARRAY_SIZE(clock_sources),
1081 buf.ext_sync.clock_source));
1082 snd_iprintf(buffer, " locked: %u\n", buf.ext_sync.locked);
1083 snd_iprintf(buffer, " rate: %s\n",
1084 str_from_array(rates, ARRAY_SIZE(rates),
1085 buf.ext_sync.rate));
1086 snd_iprintf(buffer, " adat user data: ");
1087 if (buf.ext_sync.adat_user_data & ADAT_USER_DATA_NO_DATA)
1088 snd_iprintf(buffer, "-\n");
1089 else
1090 snd_iprintf(buffer, "%x\n",
1091 buf.ext_sync.adat_user_data);
1092 }
1093}
1094
1095static void dice_create_proc(struct dice *dice)
1096{
1097 struct snd_info_entry *entry;
1098
1099 if (!snd_card_proc_new(dice->card, "dice", &entry))
1100 snd_info_set_text_ops(entry, dice, dice_proc_read);
1101}
1102
1103static void dice_card_free(struct snd_card *card)
1104{
1105 struct dice *dice = card->private_data;
1106
1107 amdtp_out_stream_destroy(&dice->stream);
1108 fw_core_remove_address_handler(&dice->notification_handler);
1109 mutex_destroy(&dice->mutex);
1110}
1111
1112#define OUI_WEISS 0x001c6a
1113
1114#define DICE_CATEGORY_ID 0x04
1115#define WEISS_CATEGORY_ID 0x00
1116
1117static int dice_interface_check(struct fw_unit *unit)
1118{
1119 static const int min_values[10] = {
1120 10, 0x64 / 4,
1121 10, 0x18 / 4,
1122 10, 0x18 / 4,
1123 0, 0,
1124 0, 0,
1125 };
1126 struct fw_device *device = fw_parent_device(unit);
1127 struct fw_csr_iterator it;
1128 int key, value, vendor = -1, model = -1, err;
1129 unsigned int category, i;
1130 __be32 pointers[ARRAY_SIZE(min_values)];
1131 __be32 tx_data[4];
1132 __be32 version;
1133
1134 /*
1135 * Check that GUID and unit directory are constructed according to DICE
1136 * rules, i.e., that the specifier ID is the GUID's OUI, and that the
1137 * GUID chip ID consists of the 8-bit category ID, the 10-bit product
1138 * ID, and a 22-bit serial number.
1139 */
1140 fw_csr_iterator_init(&it, unit->directory);
1141 while (fw_csr_iterator_next(&it, &key, &value)) {
1142 switch (key) {
1143 case CSR_SPECIFIER_ID:
1144 vendor = value;
1145 break;
1146 case CSR_MODEL:
1147 model = value;
1148 break;
1149 }
1150 }
1151 if (vendor == OUI_WEISS)
1152 category = WEISS_CATEGORY_ID;
1153 else
1154 category = DICE_CATEGORY_ID;
1155 if (device->config_rom[3] != ((vendor << 8) | category) ||
1156 device->config_rom[4] >> 22 != model)
1157 return -ENODEV;
1158
1159 /*
1160 * Check that the sub address spaces exist and are located inside the
1161 * private address space. The minimum values are chosen so that all
1162 * minimally required registers are included.
1163 */
1164 err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
1165 DICE_PRIVATE_SPACE,
1166 pointers, sizeof(pointers), 0);
1167 if (err < 0)
1168 return -ENODEV;
1169 for (i = 0; i < ARRAY_SIZE(pointers); ++i) {
1170 value = be32_to_cpu(pointers[i]);
1171 if (value < min_values[i] || value >= 0x40000)
1172 return -ENODEV;
1173 }
1174
1175 /* We support playback only. Let capture devices be handled by FFADO. */
1176 err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
1177 DICE_PRIVATE_SPACE +
1178 be32_to_cpu(pointers[2]) * 4,
1179 tx_data, sizeof(tx_data), 0);
1180 if (err < 0 || (tx_data[0] && tx_data[3]))
1181 return -ENODEV;
1182
1183 /*
1184 * Check that the implemented DICE driver specification major version
1185 * number matches.
1186 */
1187 err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
1188 DICE_PRIVATE_SPACE +
1189 be32_to_cpu(pointers[0]) * 4 + GLOBAL_VERSION,
1190 &version, 4, 0);
1191 if (err < 0)
1192 return -ENODEV;
1193 if ((version & cpu_to_be32(0xff000000)) != cpu_to_be32(0x01000000)) {
1194 dev_err(&unit->device,
1195 "unknown DICE version: 0x%08x\n", be32_to_cpu(version));
1196 return -ENODEV;
1197 }
1198
1199 return 0;
1200}
1201
1202static int highest_supported_mode_rate(struct dice *dice, unsigned int mode)
1203{
1204 int i;
1205
1206 for (i = ARRAY_SIZE(dice_rates) - 1; i >= 0; --i)
1207 if ((dice->clock_caps & (1 << i)) &&
1208 rate_index_to_mode(i) == mode)
1209 return i;
1210
1211 return -1;
1212}
1213
1214static int dice_read_mode_params(struct dice *dice, unsigned int mode)
1215{
1216 __be32 values[2];
1217 int rate_index, err;
1218
1219 rate_index = highest_supported_mode_rate(dice, mode);
1220 if (rate_index < 0) {
1221 dice->rx_channels[mode] = 0;
1222 dice->rx_midi_ports[mode] = 0;
1223 return 0;
1224 }
1225
1226 err = dice_change_rate(dice, rate_index << CLOCK_RATE_SHIFT);
1227 if (err < 0)
1228 return err;
1229
1230 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1231 rx_address(dice, RX_NUMBER_AUDIO),
1232 values, 2 * 4, 0);
1233 if (err < 0)
1234 return err;
1235
1236 dice->rx_channels[mode] = be32_to_cpu(values[0]);
1237 dice->rx_midi_ports[mode] = be32_to_cpu(values[1]);
1238
1239 return 0;
1240}
1241
1242static int dice_read_params(struct dice *dice)
1243{
1244 __be32 pointers[6];
1245 __be32 value;
1246 int mode, err;
1247
1248 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1249 DICE_PRIVATE_SPACE,
1250 pointers, sizeof(pointers), 0);
1251 if (err < 0)
1252 return err;
1253
1254 dice->global_offset = be32_to_cpu(pointers[0]) * 4;
1255 dice->rx_offset = be32_to_cpu(pointers[4]) * 4;
1256
1257 /* some very old firmwares don't tell about their clock support */
1258 if (be32_to_cpu(pointers[1]) * 4 >= GLOBAL_CLOCK_CAPABILITIES + 4) {
1259 err = snd_fw_transaction(
1260 dice->unit, TCODE_READ_QUADLET_REQUEST,
1261 global_address(dice, GLOBAL_CLOCK_CAPABILITIES),
1262 &value, 4, 0);
1263 if (err < 0)
1264 return err;
1265 dice->clock_caps = be32_to_cpu(value);
1266 } else {
1267 /* this should be supported by any device */
1268 dice->clock_caps = CLOCK_CAP_RATE_44100 |
1269 CLOCK_CAP_RATE_48000 |
1270 CLOCK_CAP_SOURCE_ARX1 |
1271 CLOCK_CAP_SOURCE_INTERNAL;
1272 }
1273
1274 for (mode = 2; mode >= 0; --mode) {
1275 err = dice_read_mode_params(dice, mode);
1276 if (err < 0)
1277 return err;
1278 }
1279
1280 return 0;
1281}
1282
1283static void dice_card_strings(struct dice *dice)
1284{
1285 struct snd_card *card = dice->card;
1286 struct fw_device *dev = fw_parent_device(dice->unit);
1287 char vendor[32], model[32];
1288 unsigned int i;
1289 int err;
1290
1291 strcpy(card->driver, "DICE");
1292
1293 strcpy(card->shortname, "DICE");
1294 BUILD_BUG_ON(NICK_NAME_SIZE < sizeof(card->shortname));
1295 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1296 global_address(dice, GLOBAL_NICK_NAME),
1297 card->shortname, sizeof(card->shortname), 0);
1298 if (err >= 0) {
1299 /* DICE strings are returned in "always-wrong" endianness */
1300 BUILD_BUG_ON(sizeof(card->shortname) % 4 != 0);
1301 for (i = 0; i < sizeof(card->shortname); i += 4)
1302 swab32s((u32 *)&card->shortname[i]);
1303 card->shortname[sizeof(card->shortname) - 1] = '\0';
1304 }
1305
1306 strcpy(vendor, "?");
1307 fw_csr_string(dev->config_rom + 5, CSR_VENDOR, vendor, sizeof(vendor));
1308 strcpy(model, "?");
1309 fw_csr_string(dice->unit->directory, CSR_MODEL, model, sizeof(model));
1310 snprintf(card->longname, sizeof(card->longname),
1311 "%s %s (serial %u) at %s, S%d",
1312 vendor, model, dev->config_rom[4] & 0x3fffff,
1313 dev_name(&dice->unit->device), 100 << dev->max_speed);
1314
1315 strcpy(card->mixername, "DICE");
1316}
1317
1318static int dice_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
1319{
1320 struct snd_card *card;
1321 struct dice *dice;
1322 __be32 clock_sel;
1323 int err;
1324
1325 err = dice_interface_check(unit);
1326 if (err < 0)
1327 return err;
1328
1329 err = snd_card_create(-1, NULL, THIS_MODULE, sizeof(*dice), &card);
1330 if (err < 0)
1331 return err;
1332 snd_card_set_dev(card, &unit->device);
1333
1334 dice = card->private_data;
1335 dice->card = card;
1336 spin_lock_init(&dice->lock);
1337 mutex_init(&dice->mutex);
1338 dice->unit = unit;
1339 init_completion(&dice->clock_accepted);
1340 init_waitqueue_head(&dice->hwdep_wait);
1341
1342 dice->notification_handler.length = 4;
1343 dice->notification_handler.address_callback = dice_notification;
1344 dice->notification_handler.callback_data = dice;
1345 err = fw_core_add_address_handler(&dice->notification_handler,
1346 &fw_high_memory_region);
1347 if (err < 0)
1348 goto err_mutex;
1349
1350 err = dice_owner_set(dice);
1351 if (err < 0)
1352 goto err_notification_handler;
1353
1354 err = dice_read_params(dice);
1355 if (err < 0)
1356 goto err_owner;
1357
1358 err = fw_iso_resources_init(&dice->resources, unit);
1359 if (err < 0)
1360 goto err_owner;
1361 dice->resources.channels_mask = 0x00000000ffffffffuLL;
1362
1363 err = amdtp_out_stream_init(&dice->stream, unit,
1364 CIP_BLOCKING | CIP_HI_DUALWIRE);
1365 if (err < 0)
1366 goto err_resources;
1367
1368 card->private_free = dice_card_free;
1369
1370 dice_card_strings(dice);
1371
1372 err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
1373 global_address(dice, GLOBAL_CLOCK_SELECT),
1374 &clock_sel, 4, 0);
1375 if (err < 0)
1376 goto error;
1377 clock_sel &= cpu_to_be32(~CLOCK_SOURCE_MASK);
1378 clock_sel |= cpu_to_be32(CLOCK_SOURCE_ARX1);
1379 err = snd_fw_transaction(unit, TCODE_WRITE_QUADLET_REQUEST,
1380 global_address(dice, GLOBAL_CLOCK_SELECT),
1381 &clock_sel, 4, 0);
1382 if (err < 0)
1383 goto error;
1384
1385 err = dice_create_pcm(dice);
1386 if (err < 0)
1387 goto error;
1388
1389 err = dice_create_hwdep(dice);
1390 if (err < 0)
1391 goto error;
1392
1393 dice_create_proc(dice);
1394
1395 err = snd_card_register(card);
1396 if (err < 0)
1397 goto error;
1398
1399 dev_set_drvdata(&unit->device, dice);
1400
1401 return 0;
1402
1403err_resources:
1404 fw_iso_resources_destroy(&dice->resources);
1405err_owner:
1406 dice_owner_clear(dice);
1407err_notification_handler:
1408 fw_core_remove_address_handler(&dice->notification_handler);
1409err_mutex:
1410 mutex_destroy(&dice->mutex);
1411error:
1412 snd_card_free(card);
1413 return err;
1414}
1415
1416static void dice_remove(struct fw_unit *unit)
1417{
1418 struct dice *dice = dev_get_drvdata(&unit->device);
1419
1420 amdtp_out_stream_pcm_abort(&dice->stream);
1421
1422 snd_card_disconnect(dice->card);
1423
1424 mutex_lock(&dice->mutex);
1425
1426 dice_stream_stop(dice);
1427 dice_owner_clear(dice);
1428
1429 mutex_unlock(&dice->mutex);
1430
1431 snd_card_free_when_closed(dice->card);
1432}
1433
1434static void dice_bus_reset(struct fw_unit *unit)
1435{
1436 struct dice *dice = dev_get_drvdata(&unit->device);
1437
1438 /*
1439 * On a bus reset, the DICE firmware disables streaming and then goes
1440 * off contemplating its own navel for hundreds of milliseconds before
1441 * it can react to any of our attempts to reenable streaming. This
1442 * means that we lose synchronization anyway, so we force our streams
1443 * to stop so that the application can restart them in an orderly
1444 * manner.
1445 */
1446 amdtp_out_stream_pcm_abort(&dice->stream);
1447
1448 mutex_lock(&dice->mutex);
1449
1450 dice->global_enabled = false;
1451 dice_stream_stop_packets(dice);
1452
1453 dice_owner_update(dice);
1454
1455 fw_iso_resources_update(&dice->resources);
1456
1457 mutex_unlock(&dice->mutex);
1458}
1459
1460#define DICE_INTERFACE 0x000001
1461
1462static const struct ieee1394_device_id dice_id_table[] = {
1463 {
1464 .match_flags = IEEE1394_MATCH_VERSION,
1465 .version = DICE_INTERFACE,
1466 },
1467 { }
1468};
1469MODULE_DEVICE_TABLE(ieee1394, dice_id_table);
1470
1471static struct fw_driver dice_driver = {
1472 .driver = {
1473 .owner = THIS_MODULE,
1474 .name = KBUILD_MODNAME,
1475 .bus = &fw_bus_type,
1476 },
1477 .probe = dice_probe,
1478 .update = dice_bus_reset,
1479 .remove = dice_remove,
1480 .id_table = dice_id_table,
1481};
1482
1483static int __init alsa_dice_init(void)
1484{
1485 return driver_register(&dice_driver.driver);
1486}
1487
1488static void __exit alsa_dice_exit(void)
1489{
1490 driver_unregister(&dice_driver.driver);
1491}
1492
1493module_init(alsa_dice_init);
1494module_exit(alsa_dice_exit);
diff --git a/sound/firewire/fcp.c b/sound/firewire/fcp.c
index ec578b5ad8da..860c08073c59 100644
--- a/sound/firewire/fcp.c
+++ b/sound/firewire/fcp.c
@@ -90,7 +90,7 @@ int fcp_avc_transaction(struct fw_unit *unit,
90 : TCODE_WRITE_BLOCK_REQUEST; 90 : TCODE_WRITE_BLOCK_REQUEST;
91 ret = snd_fw_transaction(t.unit, tcode, 91 ret = snd_fw_transaction(t.unit, tcode,
92 CSR_REGISTER_BASE + CSR_FCP_COMMAND, 92 CSR_REGISTER_BASE + CSR_FCP_COMMAND,
93 (void *)command, command_size); 93 (void *)command, command_size, 0);
94 if (ret < 0) 94 if (ret < 0)
95 break; 95 break;
96 96
diff --git a/sound/firewire/isight.c b/sound/firewire/isight.c
index 58a5afefdc69..fd42e6b315e6 100644
--- a/sound/firewire/isight.c
+++ b/sound/firewire/isight.c
@@ -217,7 +217,7 @@ static void isight_packet(struct fw_iso_context *context, u32 cycle,
217 217
218static int isight_connect(struct isight *isight) 218static int isight_connect(struct isight *isight)
219{ 219{
220 int ch, err, rcode, errors = 0; 220 int ch, err;
221 __be32 value; 221 __be32 value;
222 222
223retry_after_bus_reset: 223retry_after_bus_reset:
@@ -230,27 +230,19 @@ retry_after_bus_reset:
230 } 230 }
231 231
232 value = cpu_to_be32(ch | (isight->device->max_speed << SPEED_SHIFT)); 232 value = cpu_to_be32(ch | (isight->device->max_speed << SPEED_SHIFT));
233 for (;;) { 233 err = snd_fw_transaction(isight->unit, TCODE_WRITE_QUADLET_REQUEST,
234 rcode = fw_run_transaction( 234 isight->audio_base + REG_ISO_TX_CONFIG,
235 isight->device->card, 235 &value, 4, FW_FIXED_GENERATION |
236 TCODE_WRITE_QUADLET_REQUEST, 236 isight->resources.generation);
237 isight->device->node_id, 237 if (err == -EAGAIN) {
238 isight->resources.generation, 238 fw_iso_resources_free(&isight->resources);
239 isight->device->max_speed, 239 goto retry_after_bus_reset;
240 isight->audio_base + REG_ISO_TX_CONFIG, 240 } else if (err < 0) {
241 &value, 4); 241 goto err_resources;
242 if (rcode == RCODE_COMPLETE) {
243 return 0;
244 } else if (rcode == RCODE_GENERATION) {
245 fw_iso_resources_free(&isight->resources);
246 goto retry_after_bus_reset;
247 } else if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
248 err = -EIO;
249 goto err_resources;
250 }
251 msleep(5);
252 } 242 }
253 243
244 return 0;
245
254err_resources: 246err_resources:
255 fw_iso_resources_free(&isight->resources); 247 fw_iso_resources_free(&isight->resources);
256error: 248error:
@@ -315,17 +307,19 @@ static int isight_hw_params(struct snd_pcm_substream *substream,
315static int reg_read(struct isight *isight, int offset, __be32 *value) 307static int reg_read(struct isight *isight, int offset, __be32 *value)
316{ 308{
317 return snd_fw_transaction(isight->unit, TCODE_READ_QUADLET_REQUEST, 309 return snd_fw_transaction(isight->unit, TCODE_READ_QUADLET_REQUEST,
318 isight->audio_base + offset, value, 4); 310 isight->audio_base + offset, value, 4, 0);
319} 311}
320 312
321static int reg_write(struct isight *isight, int offset, __be32 value) 313static int reg_write(struct isight *isight, int offset, __be32 value)
322{ 314{
323 return snd_fw_transaction(isight->unit, TCODE_WRITE_QUADLET_REQUEST, 315 return snd_fw_transaction(isight->unit, TCODE_WRITE_QUADLET_REQUEST,
324 isight->audio_base + offset, &value, 4); 316 isight->audio_base + offset, &value, 4, 0);
325} 317}
326 318
327static void isight_stop_streaming(struct isight *isight) 319static void isight_stop_streaming(struct isight *isight)
328{ 320{
321 __be32 value;
322
329 if (!isight->context) 323 if (!isight->context)
330 return; 324 return;
331 325
@@ -333,7 +327,10 @@ static void isight_stop_streaming(struct isight *isight)
333 fw_iso_context_destroy(isight->context); 327 fw_iso_context_destroy(isight->context);
334 isight->context = NULL; 328 isight->context = NULL;
335 fw_iso_resources_free(&isight->resources); 329 fw_iso_resources_free(&isight->resources);
336 reg_write(isight, REG_AUDIO_ENABLE, 0); 330 value = 0;
331 snd_fw_transaction(isight->unit, TCODE_WRITE_QUADLET_REQUEST,
332 isight->audio_base + REG_AUDIO_ENABLE,
333 &value, 4, FW_QUIET);
337} 334}
338 335
339static int isight_hw_free(struct snd_pcm_substream *substream) 336static int isight_hw_free(struct snd_pcm_substream *substream)
diff --git a/sound/firewire/lib.c b/sound/firewire/lib.c
index 14eb41498372..7409edba9f06 100644
--- a/sound/firewire/lib.c
+++ b/sound/firewire/lib.c
@@ -11,7 +11,7 @@
11#include <linux/module.h> 11#include <linux/module.h>
12#include "lib.h" 12#include "lib.h"
13 13
14#define ERROR_RETRY_DELAY_MS 5 14#define ERROR_RETRY_DELAY_MS 20
15 15
16/** 16/**
17 * snd_fw_transaction - send a request and wait for its completion 17 * snd_fw_transaction - send a request and wait for its completion
@@ -20,6 +20,9 @@
20 * @offset: the address in the target's address space 20 * @offset: the address in the target's address space
21 * @buffer: input/output data 21 * @buffer: input/output data
22 * @length: length of @buffer 22 * @length: length of @buffer
23 * @flags: use %FW_FIXED_GENERATION and add the generation value to attempt the
24 * request only in that generation; use %FW_QUIET to suppress error
25 * messages
23 * 26 *
24 * Submits an asynchronous request to the target device, and waits for the 27 * Submits an asynchronous request to the target device, and waits for the
25 * response. The node ID and the current generation are derived from @unit. 28 * response. The node ID and the current generation are derived from @unit.
@@ -27,14 +30,18 @@
27 * Returns zero on success, or a negative error code. 30 * Returns zero on success, or a negative error code.
28 */ 31 */
29int snd_fw_transaction(struct fw_unit *unit, int tcode, 32int snd_fw_transaction(struct fw_unit *unit, int tcode,
30 u64 offset, void *buffer, size_t length) 33 u64 offset, void *buffer, size_t length,
34 unsigned int flags)
31{ 35{
32 struct fw_device *device = fw_parent_device(unit); 36 struct fw_device *device = fw_parent_device(unit);
33 int generation, rcode, tries = 0; 37 int generation, rcode, tries = 0;
34 38
39 generation = flags & FW_GENERATION_MASK;
35 for (;;) { 40 for (;;) {
36 generation = device->generation; 41 if (!(flags & FW_FIXED_GENERATION)) {
37 smp_rmb(); /* node_id vs. generation */ 42 generation = device->generation;
43 smp_rmb(); /* node_id vs. generation */
44 }
38 rcode = fw_run_transaction(device->card, tcode, 45 rcode = fw_run_transaction(device->card, tcode,
39 device->node_id, generation, 46 device->node_id, generation,
40 device->max_speed, offset, 47 device->max_speed, offset,
@@ -43,9 +50,14 @@ int snd_fw_transaction(struct fw_unit *unit, int tcode,
43 if (rcode == RCODE_COMPLETE) 50 if (rcode == RCODE_COMPLETE)
44 return 0; 51 return 0;
45 52
53 if (rcode == RCODE_GENERATION && (flags & FW_FIXED_GENERATION))
54 return -EAGAIN;
55
46 if (rcode_is_permanent_error(rcode) || ++tries >= 3) { 56 if (rcode_is_permanent_error(rcode) || ++tries >= 3) {
47 dev_err(&unit->device, "transaction failed: %s\n", 57 if (!(flags & FW_QUIET))
48 fw_rcode_string(rcode)); 58 dev_err(&unit->device,
59 "transaction failed: %s\n",
60 fw_rcode_string(rcode));
49 return -EIO; 61 return -EIO;
50 } 62 }
51 63
diff --git a/sound/firewire/lib.h b/sound/firewire/lib.h
index aef301476ea9..02cfabc9c3c4 100644
--- a/sound/firewire/lib.h
+++ b/sound/firewire/lib.h
@@ -6,8 +6,13 @@
6 6
7struct fw_unit; 7struct fw_unit;
8 8
9#define FW_GENERATION_MASK 0x00ff
10#define FW_FIXED_GENERATION 0x0100
11#define FW_QUIET 0x0200
12
9int snd_fw_transaction(struct fw_unit *unit, int tcode, 13int snd_fw_transaction(struct fw_unit *unit, int tcode,
10 u64 offset, void *buffer, size_t length); 14 u64 offset, void *buffer, size_t length,
15 unsigned int flags);
11 16
12/* returns true if retrying the transaction would not make sense */ 17/* returns true if retrying the transaction would not make sense */
13static inline bool rcode_is_permanent_error(int rcode) 18static inline bool rcode_is_permanent_error(int rcode)
diff --git a/sound/firewire/scs1x.c b/sound/firewire/scs1x.c
index 505fc8123199..858023cf4298 100644
--- a/sound/firewire/scs1x.c
+++ b/sound/firewire/scs1x.c
@@ -369,7 +369,7 @@ static int scs_init_hss_address(struct scs *scs)
369 data = cpu_to_be64(((u64)HSS1394_TAG_CHANGE_ADDRESS << 56) | 369 data = cpu_to_be64(((u64)HSS1394_TAG_CHANGE_ADDRESS << 56) |
370 scs->hss_handler.offset); 370 scs->hss_handler.offset);
371 err = snd_fw_transaction(scs->unit, TCODE_WRITE_BLOCK_REQUEST, 371 err = snd_fw_transaction(scs->unit, TCODE_WRITE_BLOCK_REQUEST,
372 HSS1394_ADDRESS, &data, 8); 372 HSS1394_ADDRESS, &data, 8, 0);
373 if (err < 0) 373 if (err < 0)
374 dev_err(&scs->unit->device, "HSS1394 communication failed\n"); 374 dev_err(&scs->unit->device, "HSS1394 communication failed\n");
375 375
@@ -455,12 +455,16 @@ err_card:
455static void scs_update(struct fw_unit *unit) 455static void scs_update(struct fw_unit *unit)
456{ 456{
457 struct scs *scs = dev_get_drvdata(&unit->device); 457 struct scs *scs = dev_get_drvdata(&unit->device);
458 int generation;
458 __be64 data; 459 __be64 data;
459 460
460 data = cpu_to_be64(((u64)HSS1394_TAG_CHANGE_ADDRESS << 56) | 461 data = cpu_to_be64(((u64)HSS1394_TAG_CHANGE_ADDRESS << 56) |
461 scs->hss_handler.offset); 462 scs->hss_handler.offset);
463 generation = fw_parent_device(unit)->generation;
464 smp_rmb(); /* node_id vs. generation */
462 snd_fw_transaction(scs->unit, TCODE_WRITE_BLOCK_REQUEST, 465 snd_fw_transaction(scs->unit, TCODE_WRITE_BLOCK_REQUEST,
463 HSS1394_ADDRESS, &data, 8); 466 HSS1394_ADDRESS, &data, 8,
467 FW_FIXED_GENERATION | generation);
464} 468}
465 469
466static void scs_remove(struct fw_unit *unit) 470static void scs_remove(struct fw_unit *unit)
diff --git a/sound/firewire/speakers.c b/sound/firewire/speakers.c
index fe9e6e2f2c5b..cc8bc3a51bc1 100644
--- a/sound/firewire/speakers.c
+++ b/sound/firewire/speakers.c
@@ -52,7 +52,6 @@ struct fwspk {
52 struct mutex mutex; 52 struct mutex mutex;
53 struct cmp_connection connection; 53 struct cmp_connection connection;
54 struct amdtp_out_stream stream; 54 struct amdtp_out_stream stream;
55 bool stream_running;
56 bool mute; 55 bool mute;
57 s16 volume[6]; 56 s16 volume[6];
58 s16 volume_min; 57 s16 volume_min;
@@ -188,10 +187,9 @@ static int fwspk_close(struct snd_pcm_substream *substream)
188 187
189static void fwspk_stop_stream(struct fwspk *fwspk) 188static void fwspk_stop_stream(struct fwspk *fwspk)
190{ 189{
191 if (fwspk->stream_running) { 190 if (amdtp_out_stream_running(&fwspk->stream)) {
192 amdtp_out_stream_stop(&fwspk->stream); 191 amdtp_out_stream_stop(&fwspk->stream);
193 cmp_connection_break(&fwspk->connection); 192 cmp_connection_break(&fwspk->connection);
194 fwspk->stream_running = false;
195 } 193 }
196} 194}
197 195
@@ -246,8 +244,10 @@ static int fwspk_hw_params(struct snd_pcm_substream *substream,
246 if (err < 0) 244 if (err < 0)
247 goto error; 245 goto error;
248 246
249 amdtp_out_stream_set_rate(&fwspk->stream, params_rate(hw_params)); 247 amdtp_out_stream_set_parameters(&fwspk->stream,
250 amdtp_out_stream_set_pcm(&fwspk->stream, params_channels(hw_params)); 248 params_rate(hw_params),
249 params_channels(hw_params),
250 0);
251 251
252 amdtp_out_stream_set_pcm_format(&fwspk->stream, 252 amdtp_out_stream_set_pcm_format(&fwspk->stream,
253 params_format(hw_params)); 253 params_format(hw_params));
@@ -285,7 +285,7 @@ static int fwspk_prepare(struct snd_pcm_substream *substream)
285 if (amdtp_out_streaming_error(&fwspk->stream)) 285 if (amdtp_out_streaming_error(&fwspk->stream))
286 fwspk_stop_stream(fwspk); 286 fwspk_stop_stream(fwspk);
287 287
288 if (!fwspk->stream_running) { 288 if (!amdtp_out_stream_running(&fwspk->stream)) {
289 err = cmp_connection_establish(&fwspk->connection, 289 err = cmp_connection_establish(&fwspk->connection,
290 amdtp_out_stream_get_max_payload(&fwspk->stream)); 290 amdtp_out_stream_get_max_payload(&fwspk->stream));
291 if (err < 0) 291 if (err < 0)
@@ -296,8 +296,6 @@ static int fwspk_prepare(struct snd_pcm_substream *substream)
296 fwspk->connection.speed); 296 fwspk->connection.speed);
297 if (err < 0) 297 if (err < 0)
298 goto err_connection; 298 goto err_connection;
299
300 fwspk->stream_running = true;
301 } 299 }
302 300
303 mutex_unlock(&fwspk->mutex); 301 mutex_unlock(&fwspk->mutex);
@@ -647,7 +645,7 @@ static u32 fwspk_read_firmware_version(struct fw_unit *unit)
647 int err; 645 int err;
648 646
649 err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST, 647 err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
650 OXFORD_FIRMWARE_ID_ADDRESS, &data, 4); 648 OXFORD_FIRMWARE_ID_ADDRESS, &data, 4, 0);
651 return err >= 0 ? be32_to_cpu(data) : 0; 649 return err >= 0 ? be32_to_cpu(data) : 0;
652} 650}
653 651
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 11:49:53 -0500