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| author | Andy Fleming <afleming@freescale.com> | 2008-03-24 11:53:28 -0400 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2008-03-26 00:44:47 -0400 |
| commit | 2f4489112896770d66dc2960f71174d69ee23004 (patch) | |
| tree | d91605f48735267a9c827ad1b7c1cc1324c2992d /scripts/checkstack.pl | |
| parent | 99da5003a5b085c12d996da1010e276e9b88672f (diff) | |
gianfar: Fix Rx/Tx HW interrupt coalescing counter reset procedure.
- Fix Rx/Tx HW interrupt coalescing counter reset logic. Disabling
is required before resetting the counter.
- Update the Default both Rx and Tx coalescing timer
threshold. Formerly 4 is set which is equal to 1.5 frame at the line
rate of 1GbE interface, and it doesn't match to the coalescing frame
count which is set to 16. Threashold 21 is matched to frame count 16.
Signed-off-by: Dai Haruki <dai.haruki@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'scripts/checkstack.pl')
0 files changed, 0 insertions, 0 deletions