litmus-rt.git - The LITMUS^RT kernel.

The LITMUS^RT kernel.

Bjoern Brandenburg

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author	Josef Bacik <jbacik@redhat.com>	2008-04-09 09:33:41 -0400
committer	Steven Whitehouse <swhiteho@redhat.com>	2008-04-10 04:55:26 -0400
commit	16c5f06f15ad4e5a5d6e90b78ffb1ac14319e445 (patch)
tree	84204e44e0246e9a3f4db23223a5209105fde368 /net/lapb/lapb_timer.c
parent	773adff8e983cba1f5844c3be3be224ca6645f26 (diff)

[GFS2] fix GFP_KERNEL misuses

There are several places where GFP_KERNEL allocations happen under a glock, which will result in hangs if we're under memory pressure and go to re-enter the fs in order to flush stuff out. This patch changes the culprits to GFS_NOFS to keep this problem from happening. Thank you, Signed-off-by: Josef Bacik <jbacik@redhat.com> Signed-off-by: Steven Whitehouse <swhiteho@redhat.com>

Diffstat (limited to 'net/lapb/lapb_timer.c')

0 files changed, 0 insertions, 0 deletions

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/* niu.h: Definitions for Neptune ethernet driver.
 *
 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
 */

#ifndef _NIU_H
#define _NIU_H

#define PIO			0x000000UL
#define FZC_PIO			0x080000UL
#define FZC_MAC			0x180000UL
#define FZC_IPP			0x280000UL
#define FFLP			0x300000UL
#define FZC_FFLP		0x380000UL
#define PIO_VADDR		0x400000UL
#define ZCP			0x500000UL
#define FZC_ZCP			0x580000UL
#define DMC			0x600000UL
#define FZC_DMC			0x680000UL
#define TXC			0x700000UL
#define FZC_TXC			0x780000UL
#define PIO_LDSV		0x800000UL
#define PIO_PIO_LDGIM		0x900000UL
#define PIO_IMASK0		0xa00000UL
#define PIO_IMASK1		0xb00000UL
#define FZC_PROM		0xc80000UL
#define FZC_PIM			0xd80000UL

#define LDSV0(LDG)		(PIO_LDSV + 0x00000UL + (LDG) * 0x2000UL)
#define LDSV1(LDG)		(PIO_LDSV + 0x00008UL + (LDG) * 0x2000UL)
#define LDSV2(LDG)		(PIO_LDSV + 0x00010UL + (LDG) * 0x2000UL)

#define LDG_IMGMT(LDG)		(PIO_LDSV + 0x00018UL + (LDG) * 0x2000UL)
#define  LDG_IMGMT_ARM		0x0000000080000000ULL
#define  LDG_IMGMT_TIMER	0x000000000000003fULL

#define LD_IM0(IDX)		(PIO_IMASK0 + 0x00000UL + (IDX) * 0x2000UL)
#define  LD_IM0_MASK		0x0000000000000003ULL

#define LD_IM1(IDX)		(PIO_IMASK1 + 0x00000UL + (IDX) * 0x2000UL)
#define  LD_IM1_MASK		0x0000000000000003ULL

#define LDG_TIMER_RES		(FZC_PIO + 0x00008UL)
#define  LDG_TIMER_RES_VAL	0x00000000000fffffULL

#define DIRTY_TID_CTL		(FZC_PIO + 0x00010UL)
#define  DIRTY_TID_CTL_NPTHRED	0x00000000003f0000ULL
#define  DIRTY_TID_CTL_RDTHRED	0x00000000000003f0ULL
#define  DIRTY_TID_CTL_DTIDCLR	0x0000000000000002ULL
#define  DIRTY_TID_CTL_DTIDENAB	0x0000000000000001ULL

#define DIRTY_TID_STAT		(FZC_PIO + 0x00018UL)
#define  DIRTY_TID_STAT_NPWSTAT	0x0000000000003f00ULL
#define  DIRTY_TID_STAT_RDSTAT	0x000000000000003fULL

#define RST_CTL			(FZC_PIO + 0x00038UL)
#define  RST_CTL_MAC_RST3	0x0000000000400000ULL
#define  RST_CTL_MAC_RST2	0x0000000000200000ULL
#define  RST_CTL_MAC_RST1	0x0000000000100000ULL
#define  RST_CTL_MAC_RST0	0x0000000000080000ULL
#define  RST_CTL_ACK_TO_EN	0x0000000000000800ULL
#define  RST_CTL_ACK_TO_VAL	0x00000000000007feULL

#define SMX_CFIG_DAT		(FZC_PIO + 0x00040UL)
#define  SMX_CFIG_DAT_RAS_DET	0x0000000080000000ULL
#define  SMX_CFIG_DAT_RAS_INJ	0x0000000040000000ULL
#define  SMX_CFIG_DAT_XACT_TO	0x000000000fffffffULL

#define SMX_INT_STAT		(FZC_PIO + 0x00048UL)
#define  SMX_INT_STAT_STAT	0x00000000ffffffffULL

#define SMX_CTL			(FZC_PIO + 0x00050UL)
#define  SMX_CTL_CTL		0x00000000ffffffffULL

#define SMX_DBG_VEC		(FZC_PIO + 0x00058UL)
#define  SMX_DBG_VEC_VEC	0x00000000ffffffffULL

#define PIO_DBG_SEL		(FZC_PIO + 0x00060UL)
#define  PIO_DBG_SEL_SEL	0x000000000000003fULL

#define PIO_TRAIN_VEC		(FZC_PIO + 0x00068UL)
#define  PIO_TRAIN_VEC_VEC	0x00000000ffffffffULL

#define PIO_ARB_CTL		(FZC_PIO + 0x00070UL)
#define  PIO_ARB_CTL_CTL	0x00000000ffffffffULL

#define PIO_ARB_DBG_VEC		(FZC_PIO + 0x00078UL)
#define  PIO_ARB_DBG_VEC_VEC	0x00000000ffffffffULL

#define SYS_ERR_MASK		(FZC_PIO + 0x00090UL)
#define  SYS_ERR_MASK_META2	0x0000000000000400ULL
#define  SYS_ERR_MASK_META1	0x0000000000000200ULL
#define  SYS_ERR_MASK_PEU	0x0000000000000100ULL
#define  SYS_ERR_MASK_TXC	0x0000000000000080ULL
#define  SYS_ERR_MASK_RDMC	0x0000000000000040ULL
#define  SYS_ERR_MASK_TDMC	0x0000000000000020ULL
#define  SYS_ERR_MASK_ZCP	0x0000000000000010ULL
#define  SYS_ERR_MASK_FFLP	0x0000000000000008ULL
#define  SYS_ERR_MASK_IPP	0x0000000000000004ULL
#define  SYS_ERR_MASK_MAC	0x0000000000000002ULL
#define  SYS_ERR_MASK_SMX	0x0000000000000001ULL

#define SYS_ERR_STAT			(FZC_PIO + 0x00098UL)
#define  SYS_ERR_STAT_META2		0x0000000000000400ULL
#define  SYS_ERR_STAT_META1		0x0000000000000200ULL
#define  SYS_ERR_STAT_PEU		0x0000000000000100ULL
#define  SYS_ERR_STAT_TXC		0x0000000000000080ULL
#define  SYS_ERR_STAT_RDMC		0x0000000000000040ULL
#define  SYS_ERR_STAT_TDMC		0x0000000000000020ULL
#define  SYS_ERR_STAT_ZCP		0x0000000000000010ULL
#define  SYS_ERR_STAT_FFLP		0x0000000000000008ULL
#define  SYS_ERR_STAT_IPP		0x0000000000000004ULL
#define  SYS_ERR_STAT_MAC		0x0000000000000002ULL
#define  SYS_ERR_STAT_SMX		0x0000000000000001ULL

#define SID(LDG)			(FZC_PIO + 0x10200UL + (LDG) * 8UL)
#define  SID_FUNC			0x0000000000000060ULL
#define  SID_FUNC_SHIFT			5
#define  SID_VECTOR			0x000000000000001fULL
#define  SID_VECTOR_SHIFT		0

#define LDG_NUM(LDN)			(FZC_PIO + 0x20000UL + (LDN) * 8UL)

#define XMAC_PORT0_OFF			(FZC_MAC + 0x000000)
#define XMAC_PORT1_OFF			(FZC_MAC + 0x006000)
#define BMAC_PORT2_OFF			(FZC_MAC + 0x00c000)
#define BMAC_PORT3_OFF			(FZC_MAC + 0x010000)

/* XMAC registers, offset from np->mac_regs  */

#define XTXMAC_SW_RST			0x00000UL
#define  XTXMAC_SW_RST_REG_RS		0x0000000000000002ULL
#define  XTXMAC_SW_RST_SOFT_RST		0x0000000000000001ULL

#define XRXMAC_SW_RST			0x00008UL
#define  XRXMAC_SW_RST_REG_RS		0x0000000000000002ULL
#define  XRXMAC_SW_RST_SOFT_RST		0x0000000000000001ULL

#define XTXMAC_STATUS			0x00020UL
#define  XTXMAC_STATUS_FRAME_CNT_EXP	0x0000000000000800ULL
#define  XTXMAC_STATUS_BYTE_CNT_EXP	0x0000000000000400ULL
#define  XTXMAC_STATUS_TXFIFO_XFR_ERR	0x0000000000000010ULL
#define  XTXMAC_STATUS_TXMAC_OFLOW	0x0000000000000008ULL
#define  XTXMAC_STATUS_MAX_PSIZE_ERR	0x0000000000000004ULL
#define  XTXMAC_STATUS_TXMAC_UFLOW	0x0000000000000002ULL
#define  XTXMAC_STATUS_FRAME_XMITED	0x0000000000000001ULL

#define XRXMAC_STATUS			0x00028UL
#define  XRXMAC_STATUS_RXHIST7_CNT_EXP	0x0000000000100000ULL
#define  XRXMAC_STATUS_LCL_FLT_STATUS	0x0000000000080000ULL
#define  XRXMAC_STATUS_RFLT_DET		0x0000000000040000ULL
#define  XRXMAC_STATUS_LFLT_CNT_EXP	0x0000000000020000ULL
#define  XRXMAC_STATUS_PHY_MDINT	0x0000000000010000ULL
#define  XRXMAC_STATUS_ALIGNERR_CNT_EXP	0x0000000000010000ULL
#define  XRXMAC_STATUS_RXFRAG_CNT_EXP	0x0000000000008000ULL
#define  XRXMAC_STATUS_RXMULTF_CNT_EXP	0x0000000000004000ULL
#define  XRXMAC_STATUS_RXBCAST_CNT_EXP	0x0000000000002000ULL
#define  XRXMAC_STATUS_RXHIST6_CNT_EXP	0x0000000000001000ULL
#define  XRXMAC_STATUS_RXHIST5_CNT_EXP	0x0000000000000800ULL
#define  XRXMAC_STATUS_RXHIST4_CNT_EXP	0x0000000000000400ULL
#define  XRXMAC_STATUS_RXHIST3_CNT_EXP	0x0000000000000200ULL
#define  XRXMAC_STATUS_RXHIST2_CNT_EXP	0x0000000000000100ULL
#define  XRXMAC_STATUS_RXHIST1_CNT_EXP	0x0000000000000080ULL
#define  XRXMAC_STATUS_RXOCTET_CNT_EXP	0x0000000000000040ULL
#define  XRXMAC_STATUS_CVIOLERR_CNT_EXP	0x0000000000000020ULL
#define  XRXMAC_STATUS_LENERR_CNT_EXP	0x0000000000000010ULL
#define  XRXMAC_STATUS_CRCERR_CNT_EXP	0x0000000000000008ULL
#define  XRXMAC_STATUS_RXUFLOW		0x0000000000000004ULL
#define  XRXMAC_STATUS_RXOFLOW		0x0000000000000002ULL
#define  XRXMAC_STATUS_FRAME_RCVD	0x0000000000000001ULL

#define XMAC_FC_STAT			0x00030UL
#define  XMAC_FC_STAT_RX_RCV_PAUSE_TIME	0x00000000ffff0000ULL
#define  XMAC_FC_STAT_TX_MAC_NPAUSE	0x0000000000000004ULL
#define  XMAC_FC_STAT_TX_MAC_PAUSE	0x0000000000000002ULL
#define  XMAC_FC_STAT_RX_MAC_RPAUSE	0x0000000000000001ULL

#define XTXMAC_STAT_MSK			0x00040UL
#define  XTXMAC_STAT_MSK_FRAME_CNT_EXP	0x0000000000000800ULL
#define  XTXMAC_STAT_MSK_BYTE_CNT_EXP	0x0000000000000400ULL
#define  XTXMAC_STAT_MSK_TXFIFO_XFR_ERR	0x0000000000000010ULL
#define  XTXMAC_STAT_MSK_TXMAC_OFLOW	0x0000000000000008ULL
#define  XTXMAC_STAT_MSK_MAX_PSIZE_ERR	0x0000000000000004ULL
#define  XTXMAC_STAT_MSK_TXMAC_UFLOW	0x0000000000000002ULL
#define  XTXMAC_STAT_MSK_FRAME_XMITED	0x0000000000000001ULL

#define XRXMAC_STAT_MSK				0x00048UL
#define  XRXMAC_STAT_MSK_LCL_FLT_STAT_MSK	0x0000000000080000ULL
#define  XRXMAC_STAT_MSK_RFLT_DET		0x0000000000040000ULL
#define  XRXMAC_STAT_MSK_LFLT_CNT_EXP		0x0000000000020000ULL
#define  XRXMAC_STAT_MSK_PHY_MDINT		0x0000000000010000ULL
#define  XRXMAC_STAT_MSK_RXFRAG_CNT_EXP		0x0000000000008000ULL
#define  XRXMAC_STAT_MSK_RXMULTF_CNT_EXP	0x0000000000004000ULL
#define  XRXMAC_STAT_MSK_RXBCAST_CNT_EXP	0x0000000000002000ULL
#define  XRXMAC_STAT_MSK_RXHIST6_CNT_EXP	0x0000000000001000ULL
#define  XRXMAC_STAT_MSK_RXHIST5_CNT_EXP	0x0000000000000800ULL
#define  XRXMAC_STAT_MSK_RXHIST4_CNT_EXP	0x0000000000000400ULL
#define  XRXMAC_STAT_MSK_RXHIST3_CNT_EXP	0x0000000000000200ULL
#define  XRXMAC_STAT_MSK_RXHIST2_CNT_EXP	0x0000000000000100ULL
#define  XRXMAC_STAT_MSK_RXHIST1_CNT_EXP	0x0000000000000080ULL
#define  XRXMAC_STAT_MSK_RXOCTET_CNT_EXP	0x0000000000000040ULL
#define  XRXMAC_STAT_MSK_CVIOLERR_CNT_EXP	0x0000000000000020ULL
#define  XRXMAC_STAT_MSK_LENERR_CNT_EXP		0x0000000000000010ULL
#define  XRXMAC_STAT_MSK_CRCERR_CNT_EXP		0x0000000000000008ULL
#define  XRXMAC_STAT_MSK_RXUFLOW_CNT_EXP	0x0000000000000004ULL
#define  XRXMAC_STAT_MSK_RXOFLOW_CNT_EXP	0x0000000000000002ULL
#define  XRXMAC_STAT_MSK_FRAME_RCVD		0x0000000000000001ULL

#define XMAC_FC_MSK			0x00050UL
#define  XMAC_FC_MSK_TX_MAC_NPAUSE	0x0000000000000004ULL
#define  XMAC_FC_MSK_TX_MAC_PAUSE	0x0000000000000002ULL
#define  XMAC_FC_MSK_RX_MAC_RPAUSE	0x0000000000000001ULL

#define XMAC_CONFIG			0x00060UL
#define  XMAC_CONFIG_SEL_CLK_25MHZ	0x0000000080000000ULL
#define  XMAC_CONFIG_1G_PCS_BYPASS	0x0000000040000000ULL
#define  XMAC_CONFIG_10G_XPCS_BYPASS	0x0000000020000000ULL
#define  XMAC_CONFIG_MODE_MASK		0x0000000018000000ULL
#define  XMAC_CONFIG_MODE_XGMII		0x0000000000000000ULL
#define  XMAC_CONFIG_MODE_GMII		0x0000000008000000ULL
#define  XMAC_CONFIG_MODE_MII		0x0000000010000000ULL
#define  XMAC_CONFIG_LFS_DISABLE	0x0000000004000000ULL
#define  XMAC_CONFIG_LOOPBACK		0x0000000002000000ULL
#define  XMAC_CONFIG_TX_OUTPUT_EN	0x0000000001000000ULL
#define  XMAC_CONFIG_SEL_POR_CLK_SRC	0x0000000000800000ULL
#define  XMAC_CONFIG_LED_POLARITY	0x0000000000400000ULL
#define  XMAC_CONFIG_FORCE_LED_ON	0x0000000000200000ULL
#define  XMAC_CONFIG_PASS_FLOW_CTRL	0x0000000000100000ULL
#define  XMAC_CONFIG_RCV_PAUSE_ENABLE	0x0000000000080000ULL
#define  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN	0x0000000000040000ULL
#define  XMAC_CONFIG_STRIP_CRC		0x0000000000020000ULL
#define  XMAC_CONFIG_ADDR_FILTER_EN	0x0000000000010000ULL
#define  XMAC_CONFIG_HASH_FILTER_EN	0x0000000000008000ULL
#define  XMAC_CONFIG_RX_CODEV_CHK_DIS	0x0000000000004000ULL
#define  XMAC_CONFIG_RESERVED_MULTICAST	0x0000000000002000ULL
#define  XMAC_CONFIG_RX_CRC_CHK_DIS	0x0000000000001000ULL
#define  XMAC_CONFIG_ERR_CHK_DIS	0x0000000000000800ULL
#define  XMAC_CONFIG_PROMISC_GROUP	0x0000000000000400ULL
#define  XMAC_CONFIG_PROMISCUOUS	0x0000000000000200ULL
#define  XMAC_CONFIG_RX_MAC_ENABLE	0x0000000000000100ULL
#define  XMAC_CONFIG_WARNING_MSG_EN	0x0000000000000080ULL
#define  XMAC_CONFIG_ALWAYS_NO_CRC	0x0000000000000008ULL
#define  XMAC_CONFIG_VAR_MIN_IPG_EN	0x0000000000000004ULL
#define  XMAC_CONFIG_STRETCH_MODE	0x0000000000000002ULL
#define  XMAC_CONFIG_TX_ENABLE		0x0000000000000001ULL

#define XMAC_IPG			0x00080UL
#define  XMAC_IPG_STRETCH_CONST		0x0000000000e00000ULL
#define  XMAC_IPG_STRETCH_CONST_SHIFT	21
#define  XMAC_IPG_STRETCH_RATIO		0x00000000001f0000ULL
#define  XMAC_IPG_STRETCH_RATIO_SHIFT	16
#define  XMAC_IPG_IPG_MII_GMII		0x000000000000ff00ULL
#define  XMAC_IPG_IPG_MII_GMII_SHIFT	8
#define  XMAC_IPG_IPG_XGMII		0x0000000000000007ULL
#define  XMAC_IPG_IPG_XGMII_SHIFT	0

#define IPG_12_15_XGMII			3
#define IPG_16_19_XGMII			4
#define IPG_20_23_XGMII			5
#define IPG_12_MII_GMII			10
#define IPG_13_MII_GMII			11
#define IPG_14_MII_GMII			12
#define IPG_15_MII_GMII			13
#define IPG_16_MII_GMII			14

#define XMAC_MIN			0x00088UL
#define  XMAC_MIN_RX_MIN_PKT_SIZE	0x000000003ff00000ULL
#define  XMAC_MIN_RX_MIN_PKT_SIZE_SHFT	20
#define  XMAC_MIN_SLOT_TIME		0x000000000003fc00ULL
#define  XMAC_MIN_SLOT_TIME_SHFT	10
#define  XMAC_MIN_TX_MIN_PKT_SIZE	0x00000000000003ffULL
#define  XMAC_MIN_TX_MIN_PKT_SIZE_SHFT	0

#define XMAC_MAX			0x00090UL
#define  XMAC_MAX_FRAME_SIZE		0x0000000000003fffULL
#define  XMAC_MAX_FRAME_SIZE_SHFT	0

#define XMAC_ADDR0			0x000a0UL
#define  XMAC_ADDR0_ADDR0		0x000000000000ffffULL

#define XMAC_ADDR1			0x000a8UL
#define  XMAC_ADDR1_ADDR1		0x000000000000ffffULL

#define XMAC_ADDR2			0x000b0UL 
#define  XMAC_ADDR2_ADDR2		0x000000000000ffffULL

#define XMAC_ADDR_CMPEN			0x00208UL
#define  XMAC_ADDR_CMPEN_EN15		0x0000000000008000ULL
#define  XMAC_ADDR_CMPEN_EN14		0x0000000000004000ULL
#define  XMAC_ADDR_CMPEN_EN13		0x0000000000002000ULL
#define  XMAC_ADDR_CMPEN_EN12		0x0000000000001000ULL
#define  XMAC_ADDR_CMPEN_EN11		0x0000000000000800ULL
#define  XMAC_ADDR_CMPEN_EN10		0x0000000000000400ULL
#define  XMAC_ADDR_CMPEN_EN9		0x0000000000000200ULL
#define  XMAC_ADDR_CMPEN_EN8		0x0000000000000100ULL
#define  XMAC_ADDR_CMPEN_EN7		0x0000000000000080ULL
#define  XMAC_ADDR_CMPEN_EN6		0x0000000000000040ULL
#define  XMAC_ADDR_CMPEN_EN5		0x0000000000000020ULL
#define  XMAC_ADDR_CMPEN_EN4		0x0000000000000010ULL
#define  XMAC_ADDR_CMPEN_EN3		0x0000000000000008ULL
#define  XMAC_ADDR_CMPEN_EN2		0x0000000000000004ULL
#define  XMAC_ADDR_CMPEN_EN1		0x0000000000000002ULL
#define  XMAC_ADDR_CMPEN_EN0		0x0000000000000001ULL

#define XMAC_NUM_ALT_ADDR		16

#define XMAC_ALT_ADDR0(NUM)		(0x00218UL + (NUM)*0x18UL)
#define  XMAC_ALT_ADDR0_ADDR0		0x000000000000ffffULL

#define XMAC_ALT_ADDR1(NUM)		(0x00220UL + (NUM)*0x18UL)
#define  XMAC_ALT_ADDR1_ADDR1		0x000000000000ffffULL

#define XMAC_ALT_ADDR2(NUM)		(0x00228UL + (NUM)*0x18UL)
#define  XMAC_ALT_ADDR2_ADDR2		0x000000000000ffffULL

#define XMAC_ADD_FILT0			0x00818UL
#define  XMAC_ADD_FILT0_FILT0		0x000000000000ffffULL

#define XMAC_ADD_FILT1			0x00820UL
#define  XMAC_ADD_FILT1_FILT1		0x000000000000ffffULL

#define XMAC_ADD_FILT2			0x00828UL
#define  XMAC_ADD_FILT2_FILT2		0x000000000000ffffULL

#define XMAC_ADD_FILT12_MASK		0x00830UL
#define  XMAC_ADD_FILT12_MASK_VAL	0x00000000000000ffULL

#define XMAC_ADD_FILT00_MASK		0x00838UL
#define  XMAC_ADD_FILT00_MASK_VAL	0x000000000000ffffULL

#define XMAC_HASH_TBL(NUM)		(0x00840UL + (NUM) * 0x8UL)
#define XMAC_HASH_TBL_VAL		0x000000000000ffffULL

#define XMAC_NUM_HOST_INFO		20

#define XMAC_HOST_INFO(NUM)		(0x00900UL + (NUM) * 0x8UL)

#define XMAC_PA_DATA0			0x00b80UL
#define XMAC_PA_DATA0_VAL		0x00000000ffffffffULL

#define XMAC_PA_DATA1			0x00b88UL
#define XMAC_PA_DATA1_VAL		0x00000000ffffffffULL

#define XMAC_DEBUG_SEL			0x00b90UL
#define  XMAC_DEBUG_SEL_XMAC		0x0000000000000078ULL
#define  XMAC_DEBUG_SEL_MAC		0x0000000000000007ULL

#define XMAC_TRAIN_VEC			0x00b98UL
#define  XMAC_TRAIN_VEC_VAL		0x00000000ffffffffULL

#define RXMAC_BT_CNT			0x00100UL
#define  RXMAC_BT_CNT_COUNT		0x00000000ffffffffULL

#define RXMAC_BC_FRM_CNT		0x00108UL
#define  RXMAC_BC_FRM_CNT_COUNT		0x00000000001fffffULL

#define RXMAC_MC_FRM_CNT		0x00110UL
#define  RXMAC_MC_FRM_CNT_COUNT		0x00000000001fffffULL

#define RXMAC_FRAG_CNT			0x00118UL
#define  RXMAC_FRAG_CNT_COUNT		0x00000000001fffffULL

#define RXMAC_HIST_CNT1			0x00120UL
#define  RXMAC_HIST_CNT1_COUNT		0x00000000001fffffULL

#define RXMAC_HIST_CNT2			0x00128UL
#define  RXMAC_HIST_CNT2_COUNT		0x00000000001fffffULL

#define RXMAC_HIST_CNT3			0x00130UL
#define  RXMAC_HIST_CNT3_COUNT		0x00000000000fffffULL

#define RXMAC_HIST_CNT4			0x00138UL
#define  RXMAC_HIST_CNT4_COUNT		0x000000000007ffffULL

#define RXMAC_HIST_CNT5			0x00140UL
#define  RXMAC_HIST_CNT5_COUNT		0x000000000003ffffULL

#define RXMAC_HIST_CNT6			0x00148UL
#define  RXMAC_HIST_CNT6_COUNT		0x000000000000ffffULL

#define RXMAC_MPSZER_CNT		0x00150UL
#define  RXMAC_MPSZER_CNT_COUNT		0x00000000000000ffULL

#define RXMAC_CRC_ER_CNT		0x00158UL
#define  RXMAC_CRC_ER_CNT_COUNT		0x00000000000000ffULL

#define RXMAC_CD_VIO_CNT		0x00160UL
#define  RXMAC_CD_VIO_CNT_COUNT		0x00000000000000ffULL

#define RXMAC_ALIGN_ERR_CNT		0x00168UL
#define  RXMAC_ALIGN_ERR_CNT_COUNT	0x00000000000000ffULL

#define TXMAC_FRM_CNT			0x00170UL
#define  TXMAC_FRM_CNT_COUNT		0x00000000ffffffffULL

#define TXMAC_BYTE_CNT			0x00178UL
#define  TXMAC_BYTE_CNT_COUNT		0x00000000ffffffffULL

#define LINK_FAULT_CNT			0x00180UL
#define  LINK_FAULT_CNT_COUNT		0x00000000000000ffULL

#define RXMAC_HIST_CNT7			0x00188UL
#define  RXMAC_HIST_CNT7_COUNT		0x0000000007ffffffULL

#define XMAC_SM_REG			0x001a8UL
#define  XMAC_SM_REG_STATE		0x00000000ffffffffULL

#define XMAC_INTER1			0x001b0UL
#define  XMAC_INTERN1_SIGNALS1		0x00000000ffffffffULL

#define XMAC_INTER2			0x001b8UL
#define  XMAC_INTERN2_SIGNALS2		0x00000000ffffffffULL

/* BMAC registers, offset from np->mac_regs  */

#define BTXMAC_SW_RST			0x00000UL
#define  BTXMAC_SW_RST_RESET		0x0000000000000001ULL

#define BRXMAC_SW_RST			0x00008UL
#define  BRXMAC_SW_RST_RESET		0x0000000000000001ULL

#define BMAC_SEND_PAUSE			0x00010UL
#define  BMAC_SEND_PAUSE_SEND		0x0000000000010000ULL
#define  BMAC_SEND_PAUSE_TIME		0x000000000000ffffULL

#define BTXMAC_STATUS			0x00020UL
#define  BTXMAC_STATUS_XMIT		0x0000000000000001ULL
#define  BTXMAC_STATUS_UNDERRUN		0x0000000000000002ULL
#define  BTXMAC_STATUS_MAX_PKT_ERR	0x0000000000000004ULL
#define  BTXMAC_STATUS_BYTE_CNT_EXP	0x0000000000000400ULL
#define  BTXMAC_STATUS_FRAME_CNT_EXP	0x0000000000000800ULL

#define BRXMAC_STATUS			0x00028UL
#define  BRXMAC_STATUS_RX_PKT		0x0000000000000001ULL
#define  BRXMAC_STATUS_OVERFLOW		0x0000000000000002ULL
#define  BRXMAC_STATUS_FRAME_CNT_EXP	0x0000000000000004ULL
#define  BRXMAC_STATUS_ALIGN_ERR_EXP	0x0000000000000008ULL
#define  BRXMAC_STATUS_CRC_ERR_EXP	0x0000000000000010ULL
#define  BRXMAC_STATUS_LEN_ERR_EXP	0x0000000000000020ULL

#define BMAC_CTRL_STATUS		0x00030UL
#define  BMAC_CTRL_STATUS_PAUSE_RECV	0x0000000000000001ULL
#define  BMAC_CTRL_STATUS_PAUSE		0x0000000000000002ULL
#define  BMAC_CTRL_STATUS_NOPAUSE	0x0000000000000004ULL
#define  BMAC_CTRL_STATUS_TIME		0x00000000ffff0000ULL
#define  BMAC_CTRL_STATUS_TIME_SHIFT	16

#define BTXMAC_STATUS_MASK		0x00040UL
#define BRXMAC_STATUS_MASK		0x00048UL
#define BMAC_CTRL_STATUS_MASK		0x00050UL

#define BTXMAC_CONFIG			0x00060UL
#define  BTXMAC_CONFIG_ENABLE		0x0000000000000001ULL
#define  BTXMAC_CONFIG_FCS_DISABLE	0x0000000000000002ULL

#define BRXMAC_CONFIG			0x00068UL
#define  BRXMAC_CONFIG_DISCARD_DIS	0x0000000000000080ULL
#define  BRXMAC_CONFIG_ADDR_FILT_EN	0x0000000000000040ULL
#define  BRXMAC_CONFIG_HASH_FILT_EN	0x0000000000000020ULL
#define  BRXMAC_CONFIG_PROMISC_GRP	0x0000000000000010ULL
#define  BRXMAC_CONFIG_PROMISC		0x0000000000000008ULL
#define  BRXMAC_CONFIG_STRIP_FCS	0x0000000000000004ULL
#define  BRXMAC_CONFIG_STRIP_PAD	0x0000000000000002ULL
#define  BRXMAC_CONFIG_ENABLE		0x0000000000000001ULL

#define BMAC_CTRL_CONFIG		0x00070UL
#define  BMAC_CTRL_CONFIG_TX_PAUSE_EN	0x0000000000000001ULL
#define  BMAC_CTRL_CONFIG_RX_PAUSE_EN	0x0000000000000002ULL
#define  BMAC_CTRL_CONFIG_PASS_CTRL	0x0000000000000004ULL

#define BMAC_XIF_CONFIG			0x00078UL
#define  BMAC_XIF_CONFIG_TX_OUTPUT_EN	0x0000000000000001ULL
#define  BMAC_XIF_CONFIG_MII_LOOPBACK	0x0000000000000002ULL
#define  BMAC_XIF_CONFIG_GMII_MODE	0x0000000000000008ULL
#define  BMAC_XIF_CONFIG_LINK_LED	0x0000000000000020ULL
#define  BMAC_XIF_CONFIG_LED_POLARITY	0x0000000000000040ULL
#define  BMAC_XIF_CONFIG_25MHZ_CLOCK	0x0000000000000080ULL

#define BMAC_MIN_FRAME			0x000a0UL
#define  BMAC_MIN_FRAME_VAL		0x00000000000003ffULL

#define BMAC_MAX_FRAME			0x000a8UL
#define  BMAC_MAX_FRAME_MAX_BURST	0x000000003fff0000ULL
#define  BMAC_MAX_FRAME_MAX_BURST_SHIFT	16
#define  BMAC_MAX_FRAME_MAX_FRAME	0x0000000000003fffULL
#define  BMAC_MAX_FRAME_MAX_FRAME_SHIFT	0

#define BMAC_PREAMBLE_SIZE		0x000b0UL
#define  BMAC_PREAMBLE_SIZE_VAL		0x00000000000003ffULL

#define BMAC_CTRL_TYPE			0x000c8UL

#define BMAC_ADDR0			0x00100UL
#define  BMAC_ADDR0_ADDR0		0x000000000000ffffULL

#define BMAC_ADDR1			0x00108UL
#define  BMAC_ADDR1_ADDR1		0x000000000000ffffULL

#define BMAC_ADDR2			0x00110UL
#define  BMAC_ADDR2_ADDR2		0x000000000000ffffULL

#define BMAC_NUM_ALT_ADDR		7

#define BMAC_ALT_ADDR0(NUM)		(0x00118UL + (NUM)*0x18UL)
#define  BMAC_ALT_ADDR0_ADDR0		0x000000000000ffffULL

#define BMAC_ALT_ADDR1(NUM)		(0x00120UL + (NUM)*0x18UL)
#define  BMAC_ALT_ADDR1_ADDR1		0x000000000000ffffULL

#define BMAC_ALT_ADDR2(NUM)		(0x00128UL + (NUM)*0x18UL)
#define  BMAC_ALT_ADDR2_ADDR2		0x000000000000ffffULL

#define BMAC_FC_ADDR0			0x00268UL
#define  BMAC_FC_ADDR0_ADDR0		0x000000000000ffffULL

#define BMAC_FC_ADDR1			0x00270UL
#define  BMAC_FC_ADDR1_ADDR1		0x000000000000ffffULL

#define BMAC_FC_ADDR2			0x00278UL
#define  BMAC_FC_ADDR2_ADDR2		0x000000000000ffffULL

#define BMAC_ADD_FILT0			0x00298UL
#define  BMAC_ADD_FILT0_FILT0		0x000000000000ffffULL

#define BMAC_ADD_FILT1			0x002a0UL
#define  BMAC_ADD_FILT1_FILT1		0x000000000000ffffULL

#define BMAC_ADD_FILT2			0x002a8UL
#define  BMAC_ADD_FILT2_FILT2		0x000000000000ffffULL

#define BMAC_ADD_FILT12_MASK		0x002b0UL
#define  BMAC_ADD_FILT12_MASK_VAL	0x00000000000000ffULL

#define BMAC_ADD_FILT00_MASK		0x002b8UL
#define  BMAC_ADD_FILT00_MASK_VAL	0x000000000000ffffULL

#define BMAC_HASH_TBL(NUM)		(0x002c0UL + (NUM) * 0x8UL)
#define BMAC_HASH_TBL_VAL		0x000000000000ffffULL

#define BRXMAC_FRAME_CNT		0x00370
#define  BRXMAC_FRAME_CNT_COUNT		0x000000000000ffffULL

#define BRXMAC_MAX_LEN_ERR_CNT		0x00378

#define BRXMAC_ALIGN_ERR_CNT		0x00380
#define  BRXMAC_ALIGN_ERR_CNT_COUNT	0x000000000000ffffULL

#define BRXMAC_CRC_ERR_CNT		0x00388
#define  BRXMAC_ALIGN_ERR_CNT_COUNT	0x000000000000ffffULL

#define BRXMAC_CODE_VIOL_ERR_CNT	0x00390
#define  BRXMAC_CODE_VIOL_ERR_CNT_COUNT	0x000000000000ffffULL

#define BMAC_STATE_MACHINE		0x003a0

#define BMAC_ADDR_CMPEN			0x003f8UL
#define  BMAC_ADDR_CMPEN_EN15		0x0000000000008000ULL
#define  BMAC_ADDR_CMPEN_EN14		0x0000000000004000ULL
#define  BMAC_ADDR_CMPEN_EN13		0x0000000000002000ULL
#define  BMAC_ADDR_CMPEN_EN12		0x0000000000001000ULL
#define  BMAC_ADDR_CMPEN_EN11		0x0000000000000800ULL
#define  BMAC_ADDR_CMPEN_EN10		0x0000000000000400ULL
#define  BMAC_ADDR_CMPEN_EN9		0x0000000000000200ULL
#define  BMAC_ADDR_CMPEN_EN8		0x0000000000000100ULL
#define  BMAC_ADDR_CMPEN_EN7		0x0000000000000080ULL
#define  BMAC_ADDR_CMPEN_EN6		0x0000000000000040ULL
#define  BMAC_ADDR_CMPEN_EN5		0x0000000000000020ULL
#define  BMAC_ADDR_CMPEN_EN4		0x0000000000000010ULL
#define  BMAC_ADDR_CMPEN_EN3		0x0000000000000008ULL
#define  BMAC_ADDR_CMPEN_EN2		0x0000000000000004ULL
#define  BMAC_ADDR_CMPEN_EN1		0x0000000000000002ULL
#define  BMAC_ADDR_CMPEN_EN0		0x0000000000000001ULL

#define BMAC_NUM_HOST_INFO		9

#define BMAC_HOST_INFO(NUM)		(0x00400UL + (NUM) * 0x8UL)

#define BTXMAC_BYTE_CNT			0x00448UL
#define  BTXMAC_BYTE_CNT_COUNT		0x00000000ffffffffULL

#define BTXMAC_FRM_CNT			0x00450UL
#define  BTXMAC_FRM_CNT_COUNT		0x00000000ffffffffULL

#define BRXMAC_BYTE_CNT			0x00458UL
#define  BRXMAC_BYTE_CNT_COUNT		0x00000000ffffffffULL

#define HOST_INFO_MPR			0x0000000000000100ULL
#define HOST_INFO_MACRDCTBLN		0x0000000000000007ULL

/* XPCS registers, offset from np->regs + np->xpcs_off  */

#define XPCS_CONTROL1			(FZC_MAC + 0x00000UL)
#define  XPCS_CONTROL1_RESET		0x0000000000008000ULL
#define  XPCS_CONTROL1_LOOPBACK		0x0000000000004000ULL
#define  XPCS_CONTROL1_SPEED_SELECT3	0x0000000000002000ULL
#define  XPCS_CONTROL1_CSR_LOW_PWR	0x0000000000000800ULL
#define  XPCS_CONTROL1_CSR_SPEED1	0x0000000000000040ULL
#define  XPCS_CONTROL1_CSR_SPEED0	0x000000000000003cULL

#define XPCS_STATUS1			(FZC_MAC + 0x00008UL)
#define  XPCS_STATUS1_CSR_FAULT		0x0000000000000080ULL
#define  XPCS_STATUS1_CSR_RXLNK_STAT	0x0000000000000004ULL
#define  XPCS_STATUS1_CSR_LPWR_ABLE	0x0000000000000002ULL

#define XPCS_DEVICE_IDENTIFIER		(FZC_MAC + 0x00010UL)
#define  XPCS_DEVICE_IDENTIFIER_VAL	0x00000000ffffffffULL

#define XPCS_SPEED_ABILITY		(FZC_MAC + 0x00018UL)
#define  XPCS_SPEED_ABILITY_10GIG	0x0000000000000001ULL

#define XPCS_DEV_IN_PKG			(FZC_MAC + 0x00020UL)
#define  XPCS_DEV_IN_PKG_CSR_VEND2	0x0000000080000000ULL
#define  XPCS_DEV_IN_PKG_CSR_VEND1	0x0000000040000000ULL
#define  XPCS_DEV_IN_PKG_DTE_XS		0x0000000000000020ULL
#define  XPCS_DEV_IN_PKG_PHY_XS		0x0000000000000010ULL
#define  XPCS_DEV_IN_PKG_PCS		0x0000000000000008ULL
#define  XPCS_DEV_IN_PKG_WIS		0x0000000000000004ULL
#define  XPCS_DEV_IN_PKG_PMD_PMA	0x0000000000000002ULL
#define  XPCS_DEV_IN_PKG_CLS22		0x0000000000000001ULL

#define XPCS_CONTROL2			(FZC_MAC + 0x00028UL)
#define  XPCS_CONTROL2_CSR_PSC_SEL	0x0000000000000003ULL

#define XPCS_STATUS2			(FZC_MAC + 0x00030UL)
#define  XPCS_STATUS2_CSR_DEV_PRES	0x000000000000c000ULL
#define  XPCS_STATUS2_CSR_TX_FAULT	0x0000000000000800ULL
#define  XPCS_STATUS2_CSR_RCV_FAULT	0x0000000000000400ULL
#define  XPCS_STATUS2_TEN_GBASE_W	0x0000000000000004ULL
#define  XPCS_STATUS2_TEN_GBASE_X	0x0000000000000002ULL
#define  XPCS_STATUS2_TEN_GBASE_R	0x0000000000000001ULL

#define XPCS_PKG_ID			(FZC_MAC + 0x00038UL)
#define  XPCS_PKG_ID_VAL		0x00000000ffffffffULL

#define XPCS_STATUS(IDX)		(FZC_MAC + 0x00040UL)
#define  XPCS_STATUS_CSR_LANE_ALIGN	0x0000000000001000ULL
#define  XPCS_STATUS_CSR_PATTEST_CAP	0x0000000000000800ULL
#define  XPCS_STATUS_CSR_LANE3_SYNC	0x0000000000000008ULL
#define  XPCS_STATUS_CSR_LANE2_SYNC	0x0000000000000004ULL
#define  XPCS_STATUS_CSR_LANE1_SYNC	0x0000000000000002ULL
#define  XPCS_STATUS_CSR_LANE0_SYNC	0x0000000000000001ULL

#define XPCS_TEST_CONTROL		(FZC_MAC + 0x00048UL)
#define  XPCS_TEST_CONTROL_TXTST_EN	0x0000000000000004ULL
#define  XPCS_TEST_CONTROL_TPAT_SEL	0x0000000000000003ULL

#define XPCS_CFG_VENDOR1		(FZC_MAC + 0x00050UL)
#define  XPCS_CFG_VENDOR1_DBG_IOTST	0x0000000000000080ULL
#define  XPCS_CFG_VENDOR1_DBG_SEL	0x0000000000000078ULL
#define  XPCS_CFG_VENDOR1_BYPASS_DET	0x0000000000000004ULL
#define  XPCS_CFG_VENDOR1_TXBUF_EN	0x0000000000000002ULL
#define  XPCS_CFG_VENDOR1_XPCS_EN	0x0000000000000001ULL

#define XPCS_DIAG_VENDOR2		(FZC_MAC + 0x00058UL)
#define  XPCS_DIAG_VENDOR2_SSM_LANE3	0x0000000001e00000ULL
#define  XPCS_DIAG_VENDOR2_SSM_LANE2	0x00000000001e0000ULL
#define  XPCS_DIAG_VENDOR2_SSM_LANE1	0x000000000001e000ULL
#define  XPCS_DIAG_VENDOR2_SSM_LANE0	0x0000000000001e00ULL
#define  XPCS_DIAG_VENDOR2_EBUF_SM	0x00000000000001feULL
#define  XPCS_DIAG_VENDOR2_RCV_SM	0x0000000000000001ULL

#define XPCS_MASK1			(FZC_MAC + 0x00060UL)
#define  XPCS_MASK1_FAULT_MASK		0x0000000000000080ULL
#define  XPCS_MASK1_RXALIGN_STAT_MSK	0x0000000000000004ULL

#define XPCS_PKT_COUNT			(FZC_MAC + 0x00068UL)
#define  XPCS_PKT_COUNT_TX		0x00000000ffff0000ULL
#define  XPCS_PKT_COUNT_RX		0x000000000000ffffULL

#define XPCS_TX_SM			(FZC_MAC + 0x00070UL)
#define  XPCS_TX_SM_VAL			0x000000000000000fULL

#define XPCS_DESKEW_ERR_CNT		(FZC_MAC + 0x00078UL)
#define  XPCS_DESKEW_ERR_CNT_VAL	0x00000000000000ffULL

#define XPCS_SYMERR_CNT01		(FZC_MAC + 0x00080UL)
#define  XPCS_SYMERR_CNT01_LANE1	0x00000000ffff0000ULL
#define  XPCS_SYMERR_CNT01_LANE0	0x000000000000ffffULL

#define XPCS_SYMERR_CNT23		(FZC_MAC + 0x00088UL)
#define  XPCS_SYMERR_CNT23_LANE3	0x00000000ffff0000ULL
#define  XPCS_SYMERR_CNT23_LANE2	0x000000000000ffffULL

#define XPCS_TRAINING_VECTOR		(FZC_MAC + 0x00090UL)
#define  XPCS_TRAINING_VECTOR_VAL	0x00000000ffffffffULL

/* PCS registers, offset from np->regs + np->pcs_off  */

#define PCS_MII_CTL			(FZC_MAC + 0x00000UL)
#define  PCS_MII_CTL_RST		0x0000000000008000ULL
#define  PCS_MII_CTL_10_100_SPEED	0x0000000000002000ULL
#define  PCS_MII_AUTONEG_EN		0x0000000000001000ULL
#define  PCS_MII_PWR_DOWN		0x0000000000000800ULL
#define  PCS_MII_ISOLATE		0x0000000000000400ULL
#define  PCS_MII_AUTONEG_RESTART	0x0000000000000200ULL
#define  PCS_MII_DUPLEX			0x0000000000000100ULL
#define  PCS_MII_COLL_TEST		0x0000000000000080ULL
#define  PCS_MII_1000MB_SPEED		0x0000000000000040ULL

#define PCS_MII_STAT			(FZC_MAC + 0x00008UL)
#define  PCS_MII_STAT_EXT_STATUS	0x0000000000000100ULL
#define  PCS_MII_STAT_AUTONEG_DONE	0x0000000000000020ULL
#define  PCS_MII_STAT_REMOTE_FAULT	0x0000000000000010ULL
#define  PCS_MII_STAT_AUTONEG_ABLE	0x0000000000000008ULL
#define  PCS_MII_STAT_LINK_STATUS	0x0000000000000004ULL
#define  PCS_MII_STAT_JABBER_DET	0x0000000000000002ULL
#define  PCS_MII_STAT_EXT_CAP		0x0000000000000001ULL

#define PCS_MII_ADV			(FZC_MAC + 0x00010UL)
#define  PCS_MII_ADV_NEXT_PAGE		0x0000000000008000ULL
#define  PCS_MII_ADV_ACK		0x0000000000004000ULL
#define  PCS_MII_ADV_REMOTE_FAULT	0x0000000000003000ULL
#define  PCS_MII_ADV_ASM_DIR		0x0000000000000100ULL
#define  PCS_MII_ADV_PAUSE		0x0000000000000080ULL
#define  PCS_MII_ADV_HALF_DUPLEX	0x0000000000000040ULL
#define  PCS_MII_ADV_FULL_DUPLEX	0x0000000000000020ULL

#define PCS_MII_PARTNER			(FZC_MAC + 0x00018UL)
#define  PCS_MII_PARTNER_NEXT_PAGE	0x0000000000008000ULL
#define  PCS_MII_PARTNER_ACK		0x0000000000004000ULL
#define  PCS_MII_PARTNER_REMOTE_FAULT	0x0000000000002000ULL
#define  PCS_MII_PARTNER_PAUSE		0x0000000000000180ULL
#define  PCS_MII_PARTNER_HALF_DUPLEX	0x0000000000000040ULL
#define  PCS_MII_PARTNER_FULL_DUPLEX	0x0000000000000020ULL

#define PCS_CONF			(FZC_MAC + 0x00020UL)
#define  PCS_CONF_MASK			0x0000000000000040ULL
#define  PCS_CONF_10MS_TMR_OVERRIDE	0x0000000000000020ULL
#define  PCS_CONF_JITTER_STUDY		0x0000000000000018ULL
#define  PCS_CONF_SIGDET_ACTIVE_LOW	0x0000000000000004ULL
#define  PCS_CONF_SIGDET_OVERRIDE	0x0000000000000002ULL
#define  PCS_CONF_ENABLE		0x0000000000000001ULL

#define PCS_STATE			(FZC_MAC + 0x00028UL)
#define  PCS_STATE_D_PARTNER_FAIL	0x0000000020000000ULL
#define  PCS_STATE_D_WAIT_C_CODES_ACK	0x0000000010000000ULL
#define  PCS_STATE_D_SYNC_LOSS		0x0000000008000000ULL
#define  PCS_STATE_D_NO_GOOD_C_CODES	0x0000000004000000ULL
#define  PCS_STATE_D_SERDES		0x0000000002000000ULL
#define  PCS_STATE_D_BREAKLINK_C_CODES	0x0000000001000000ULL
#define  PCS_STATE_L_SIGDET		0x0000000000400000ULL
#define  PCS_STATE_L_SYNC_LOSS		0x0000000000200000ULL
#define  PCS_STATE_L_C_CODES		0x0000000000100000ULL
#define  PCS_STATE_LINK_CFG_STATE	0x000000000001e000ULL
#define  PCS_STATE_SEQ_DET_STATE	0x0000000000001800ULL
#define  PCS_STATE_WORD_SYNC_STATE	0x0000000000000700ULL
#define  PCS_STATE_NO_IDLE		0x000000000000000fULL

#define PCS_INTERRUPT			(FZC_MAC + 0x00030UL)
#define  PCS_INTERRUPT_LSTATUS		0x0000000000000004ULL

#define PCS_DPATH_MODE			(FZC_MAC + 0x000a0UL)
#define  PCS_DPATH_MODE_PCS		0x0000000000000000ULL
#define  PCS_DPATH_MODE_MII		0x0000000000000002ULL
#define  PCS_DPATH_MODE_LINKUP_F_ENAB	0x0000000000000001ULL

#define PCS_PKT_CNT			(FZC_MAC + 0x000c0UL)
#define  PCS_PKT_CNT_RX			0x0000000007ff0000ULL
#define  PCS_PKT_CNT_TX			0x00000000000007ffULL

#define MIF_BB_MDC			(FZC_MAC + 0x16000UL)
#define  MIF_BB_MDC_CLK			0x0000000000000001ULL

#define MIF_BB_MDO			(FZC_MAC + 0x16008UL)
#define  MIF_BB_MDO_DAT			0x0000000000000001ULL

#define MIF_BB_MDO_EN			(FZC_MAC + 0x16010UL)
#define  MIF_BB_MDO_EN_VAL		0x0000000000000001ULL

#define MIF_FRAME_OUTPUT		(FZC_MAC + 0x16018UL)
#define  MIF_FRAME_OUTPUT_ST		0x00000000c0000000ULL
#define  MIF_FRAME_OUTPUT_ST_SHIFT	30
#define  MIF_FRAME_OUTPUT_OP_ADDR	0x0000000000000000ULL
#define  MIF_FRAME_OUTPUT_OP_WRITE	0x0000000010000000ULL
#define  MIF_FRAME_OUTPUT_OP_READ_INC	0x0000000020000000ULL
#define  MIF_FRAME_OUTPUT_OP_READ	0x0000000030000000ULL
#define  MIF_FRAME_OUTPUT_OP_SHIFT	28
#define  MIF_FRAME_OUTPUT_PORT		0x000000000f800000ULL
#define  MIF_FRAME_OUTPUT_PORT_SHIFT	23
#define  MIF_FRAME_OUTPUT_REG		0x00000000007c0000ULL
#define  MIF_FRAME_OUTPUT_REG_SHIFT	18
#define  MIF_FRAME_OUTPUT_TA		0x0000000000030000ULL
#define  MIF_FRAME_OUTPUT_TA_SHIFT	16
#define  MIF_FRAME_OUTPUT_DATA		0x000000000000ffffULL
#define  MIF_FRAME_OUTPUT_DATA_SHIFT	0

#define MDIO_ADDR_OP(port, dev, reg) \
	((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
	 MIF_FRAME_OUTPUT_OP_ADDR | \
	 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
	 (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
	 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
	 (reg << MIF_FRAME_OUTPUT_DATA_SHIFT))

#define MDIO_READ_OP(port, dev) \
	((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
	 MIF_FRAME_OUTPUT_OP_READ | \
	 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
	 (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
	 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT))

#define MDIO_WRITE_OP(port, dev, data) \
	((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
	 MIF_FRAME_OUTPUT_OP_WRITE | \
	 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
	 (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
	 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
	 (data << MIF_FRAME_OUTPUT_DATA_SHIFT))

#define MII_READ_OP(port, reg) \
	((1 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
	 (2 << MIF_FRAME_OUTPUT_OP_SHIFT) | \
	 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
	 (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \
	 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT))

#define MII_WRITE_OP(port, reg, data) \
	((1 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
	 (1 << MIF_FRAME_OUTPUT_OP_SHIFT) | \
	 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
	 (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \
	 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
	 (data << MIF_FRAME_OUTPUT_DATA_SHIFT))

#define MIF_CONFIG			(FZC_MAC + 0x16020UL)
#define  MIF_CONFIG_ATCA_GE		0x0000000000010000ULL
#define  MIF_CONFIG_INDIRECT_MODE	0x0000000000008000ULL
#define  MIF_CONFIG_POLL_PRT_PHYADDR	0x0000000000003c00ULL
#define  MIF_CONFIG_POLL_DEV_REG_ADDR	0x00000000000003e0ULL
#define  MIF_CONFIG_BB_MODE		0x0000000000000010ULL
#define  MIF_CONFIG_POLL_EN		0x0000000000000008ULL
#define  MIF_CONFIG_BB_SER_SEL		0x0000000000000006ULL
#define  MIF_CONFIG_MANUAL_MODE		0x0000000000000001ULL

#define MIF_POLL_STATUS			(FZC_MAC + 0x16028UL)
#define  MIF_POLL_STATUS_DATA		0x00000000ffff0000ULL
#define  MIF_POLL_STATUS_STAT		0x000000000000ffffULL

#define MIF_POLL_MASK			(FZC_MAC + 0x16030UL)
#define  MIF_POLL_MASK_VAL		0x000000000000ffffULL

#define MIF_SM				(FZC_MAC + 0x16038UL)
#define  MIF_SM_PORT_ADDR		0x00000000001f0000ULL
#define  MIF_SM_MDI_1			0x0000000000004000ULL
#define  MIF_SM_MDI_0			0x0000000000002400ULL
#define  MIF_SM_MDCLK			0x0000000000001000ULL
#define  MIF_SM_MDO_EN			0x0000000000000800ULL
#define  MIF_SM_MDO			0x0000000000000400ULL
#define  MIF_SM_MDI			0x0000000000000200ULL
#define  MIF_SM_CTL			0x00000000000001c0ULL
#define  MIF_SM_EX			0x000000000000003fULL

#define MIF_STATUS			(FZC_MAC + 0x16040UL)
#define  MIF_STATUS_MDINT1		0x0000000000000020ULL
#define  MIF_STATUS_MDINT0		0x0000000000000010ULL

#define MIF_MASK			(FZC_MAC + 0x16048UL)
#define  MIF_MASK_MDINT1		0x0000000000000020ULL
#define  MIF_MASK_MDINT0		0x0000000000000010ULL
#define  MIF_MASK_PEU_ERR		0x0000000000000008ULL
#define  MIF_MASK_YC			0x0000000000000004ULL
#define  MIF_MASK_XGE_ERR0		0x0000000000000002ULL
#define  MIF_MASK_MIF_INIT_DONE		0x0000000000000001ULL

#define ENET_SERDES_RESET		(FZC_MAC + 0x14000UL)
#define  ENET_SERDES_RESET_1		0x0000000000000002ULL
#define  ENET_SERDES_RESET_0		0x0000000000000001ULL

#define ENET_SERDES_CFG			(FZC_MAC + 0x14008UL)
#define  ENET_SERDES_BE_LOOPBACK	0x0000000000000002ULL
#define  ENET_SERDES_CFG_FORCE_RDY	0x0000000000000001ULL

#define ENET_SERDES_0_PLL_CFG		(FZC_MAC + 0x14010UL)
#define  ENET_SERDES_PLL_FBDIV0		0x0000000000000001ULL
#define  ENET_SERDES_PLL_FBDIV1		0x0000000000000002ULL
#define  ENET_SERDES_PLL_FBDIV2		0x0000000000000004ULL
#define  ENET_SERDES_PLL_HRATE0		0x0000000000000008ULL
#define  ENET_SERDES_PLL_HRATE1		0x0000000000000010ULL
#define  ENET_SERDES_PLL_HRATE2		0x0000000000000020ULL
#define  ENET_SERDES_PLL_HRATE3		0x0000000000000040ULL

#define ENET_SERDES_0_CTRL_CFG		(FZC_MAC + 0x14018UL)
#define  ENET_SERDES_CTRL_SDET_0	0x0000000000000001ULL
#define  ENET_SERDES_CTRL_SDET_1	0x0000000000000002ULL
#define  ENET_SERDES_CTRL_SDET_2	0x0000000000000004ULL
#define  ENET_SERDES_CTRL_SDET_3	0x0000000000000008ULL
#define  ENET_SERDES_CTRL_EMPH_0	0x0000000000000070ULL
#define  ENET_SERDES_CTRL_EMPH_0_SHIFT	4
#define  ENET_SERDES_CTRL_EMPH_1	0x0000000000000380ULL
#define  ENET_SERDES_CTRL_EMPH_1_SHIFT	7
#define  ENET_SERDES_CTRL_EMPH_2	0x0000000000001c00ULL
#define  ENET_SERDES_CTRL_EMPH_2_SHIFT	10
#define  ENET_SERDES_CTRL_EMPH_3	0x000000000000e000ULL
#define  ENET_SERDES_CTRL_EMPH_3_SHIFT	13
#define  ENET_SERDES_CTRL_LADJ_0	0x0000000000070000ULL
#define  ENET_SERDES_CTRL_LADJ_0_SHIFT	16
#define  ENET_SERDES_CTRL_LADJ_1	0x0000000000380000ULL
#define  ENET_SERDES_CTRL_LADJ_1_SHIFT	19
#define  ENET_SERDES_CTRL_LADJ_2	0x0000000001c00000ULL
#define  ENET_SERDES_CTRL_LADJ_2_SHIFT	22
#define  ENET_SERDES_CTRL_LADJ_3	0x000000000e000000ULL
#define  ENET_SERDES_CTRL_LADJ_3_SHIFT	25
#define  ENET_SERDES_CTRL_RXITERM_0	0x0000000010000000ULL
#define  ENET_SERDES_CTRL_RXITERM_1	0x0000000020000000ULL
#define  ENET_SERDES_CTRL_RXITERM_2	0x0000000040000000ULL
#define  ENET_SERDES_CTRL_RXITERM_3	0x0000000080000000ULL

#define ENET_SERDES_0_TEST_CFG		(FZC_MAC + 0x14020UL)
#define  ENET_SERDES_TEST_MD_0		0x0000000000000003ULL
#define  ENET_SERDES_TEST_MD_0_SHIFT	0
#define  ENET_SERDES_TEST_MD_1		0x000000000000000cULL
#define  ENET_SERDES_TEST_MD_1_SHIFT	2
#define  ENET_SERDES_TEST_MD_2		0x0000000000000030ULL
#define  ENET_SERDES_TEST_MD_2_SHIFT	4
#define  ENET_SERDES_TEST_MD_3		0x00000000000000c0ULL
#define  ENET_SERDES_TEST_MD_3_SHIFT	6

#define ENET_TEST_MD_NO_LOOPBACK	0x0
#define ENET_TEST_MD_EWRAP		0x1
#define ENET_TEST_MD_PAD_LOOPBACK	0x2
#define ENET_TEST_MD_REV_LOOPBACK	0x3

#define ENET_SERDES_1_PLL_CFG		(FZC_MAC + 0x14028UL)
#define ENET_SERDES_1_CTRL_CFG		(FZC_MAC + 0x14030UL)
#define ENET_SERDES_1_TEST_CFG		(FZC_MAC + 0x14038UL)

#define ENET_RGMII_CFG_REG		(FZC_MAC + 0x14040UL)

#define ESR_INT_SIGNALS			(FZC_MAC + 0x14800UL)
#define  ESR_INT_SIGNALS_ALL		0x00000000ffffffffULL
#define  ESR_INT_SIGNALS_P0_BITS	0x0000000033e0000fULL
#define  ESR_INT_SIGNALS_P1_BITS	0x000000000c1f00f0ULL
#define  ESR_INT_SRDY0_P0		0x0000000020000000ULL
#define  ESR_INT_DET0_P0		0x0000000010000000ULL
#define  ESR_INT_SRDY0_P1		0x0000000008000000ULL
#define  ESR_INT_DET0_P1		0x0000000004000000ULL
#define  ESR_INT_XSRDY_P0		0x0000000002000000ULL
#define  ESR_INT_XDP_P0_CH3		0x0000000001000000ULL
#define  ESR_INT_XDP_P0_CH2		0x0000000000800000ULL
#define  ESR_INT_XDP_P0_CH1		0x0000000000400000ULL
#define  ESR_INT_XDP_P0_CH0		0x0000000000200000ULL
#define  ESR_INT_XSRDY_P1		0x0000000000100000ULL
#define  ESR_INT_XDP_P1_CH3		0x0000000000080000ULL
#define  ESR_INT_XDP_P1_CH2		0x0000000000040000ULL
#define  ESR_INT_XDP_P1_CH1		0x0000000000020000ULL
#define  ESR_INT_XDP_P1_CH0		0x0000000000010000ULL
#define  ESR_INT_SLOSS_P1_CH3		0x0000000000000080ULL
#define  ESR_INT_SLOSS_P1_CH2		0x0000000000000040ULL
#define  ESR_INT_SLOSS_P1_CH1		0x0000000000000020ULL
#define  ESR_INT_SLOSS_P1_CH0		0x0000000000000010ULL
#define  ESR_INT_SLOSS_P0_CH3		0x0000000000000008ULL
#define  ESR_INT_SLOSS_P0_CH2		0x0000000000000004ULL
#define  ESR_INT_SLOSS_P0_CH1		0x0000000000000002ULL
#define  ESR_INT_SLOSS_P0_CH0		0x0000000000000001ULL

#define ESR_DEBUG_SEL			(FZC_MAC + 0x14808UL)
#define  ESR_DEBUG_SEL_VAL		0x000000000000003fULL

/* SerDes registers behind MIF */
#define NIU_ESR_DEV_ADDR		0x1e
#define ESR_BASE			0x0000

#define ESR_RXTX_COMM_CTRL_L		(ESR_BASE + 0x0000)
#define ESR_RXTX_COMM_CTRL_H		(ESR_BASE + 0x0001)

#define ESR_RXTX_RESET_CTRL_L		(ESR_BASE + 0x0002)
#define ESR_RXTX_RESET_CTRL_H		(ESR_BASE + 0x0003)

#define ESR_RX_POWER_CTRL_L		(ESR_BASE + 0x0004)
#define ESR_RX_POWER_CTRL_H		(ESR_BASE + 0x0005)

#define ESR_TX_POWER_CTRL_L		(ESR_BASE + 0x0006)
#define ESR_TX_POWER_CTRL_H		(ESR_BASE + 0x0007)

#define ESR_MISC_POWER_CTRL_L		(ESR_BASE + 0x0008)
#define ESR_MISC_POWER_CTRL_H		(ESR_BASE + 0x0009)

#define ESR_RXTX_CTRL_L(CHAN)		(ESR_BASE + 0x0080 + (CHAN) * 0x10)
#define ESR_RXTX_CTRL_H(CHAN)		(ESR_BASE + 0x0081 + (CHAN) * 0x10)
#define  ESR_RXTX_CTRL_BIASCNTL		0x80000000
#define  ESR_RXTX_CTRL_RESV1		0x7c000000
#define  ESR_RXTX_CTRL_TDENFIFO		0x02000000
#define  ESR_RXTX_CTRL_TDWS20		0x01000000
#define  ESR_RXTX_CTRL_VMUXLO		0x00c00000
#define  ESR_RXTX_CTRL_VMUXLO_SHIFT	22
#define  ESR_RXTX_CTRL_VPULSELO		0x00300000
#define  ESR_RXTX_CTRL_VPULSELO_SHIFT	20
#define  ESR_RXTX_CTRL_RESV2		0x000f0000
#define  ESR_RXTX_CTRL_RESV3		0x0000c000
#define  ESR_RXTX_CTRL_RXPRESWIN	0x00003000
#define  ESR_RXTX_CTRL_RXPRESWIN_SHIFT	12
#define  ESR_RXTX_CTRL_RESV4		0x00000800
#define  ESR_RXTX_CTRL_RISEFALL		0x00000700
#define  ESR_RXTX_CTRL_RISEFALL_SHIFT	8
#define  ESR_RXTX_CTRL_RESV5		0x000000fe
#define  ESR_RXTX_CTRL_ENSTRETCH	0x00000001

#define ESR_RXTX_TUNING_L(CHAN)		(ESR_BASE + 0x0082 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING_H(CHAN)		(ESR_BASE + 0x0083 + (CHAN) * 0x10)

#define ESR_RX_SYNCCHAR_L(CHAN)		(ESR_BASE + 0x0084 + (CHAN) * 0x10)
#define ESR_RX_SYNCCHAR_H(CHAN)		(ESR_BASE + 0x0085 + (CHAN) * 0x10)

#define ESR_RXTX_TEST_L(CHAN)		(ESR_BASE + 0x0086 + (CHAN) * 0x10)
#define ESR_RXTX_TEST_H(CHAN)		(ESR_BASE + 0x0087 + (CHAN) * 0x10)

#define ESR_GLUE_CTRL0_L(CHAN)		(ESR_BASE + 0x0088 + (CHAN) * 0x10)
#define ESR_GLUE_CTRL0_H(CHAN)		(ESR_BASE + 0x0089 + (CHAN) * 0x10)
#define  ESR_GLUE_CTRL0_RESV1		0xf8000000
#define  ESR_GLUE_CTRL0_BLTIME		0x07000000
#define  ESR_GLUE_CTRL0_BLTIME_SHIFT	24
#define  ESR_GLUE_CTRL0_RESV2		0x00ff0000
#define  ESR_GLUE_CTRL0_RXLOS_TEST	0x00008000
#define  ESR_GLUE_CTRL0_RESV3		0x00004000
#define  ESR_GLUE_CTRL0_RXLOSENAB	0x00002000
#define  ESR_GLUE_CTRL0_FASTRESYNC	0x00001000
#define  ESR_GLUE_CTRL0_SRATE		0x00000f00
#define  ESR_GLUE_CTRL0_SRATE_SHIFT	8
#define  ESR_GLUE_CTRL0_THCNT		0x000000ff
#define  ESR_GLUE_CTRL0_THCNT_SHIFT	0

#define BLTIME_64_CYCLES		0
#define BLTIME_128_CYCLES		1
#define BLTIME_256_CYCLES		2
#define BLTIME_300_CYCLES		3
#define BLTIME_384_CYCLES		4
#define BLTIME_512_CYCLES		5
#define BLTIME_1024_CYCLES		6
#define BLTIME_2048_CYCLES		7

#define ESR_GLUE_CTRL1_L(CHAN)		(ESR_BASE + 0x008a + (CHAN) * 0x10)
#define ESR_GLUE_CTRL1_H(CHAN)		(ESR_BASE + 0x008b + (CHAN) * 0x10)
#define ESR_RXTX_TUNING1_L(CHAN)	(ESR_BASE + 0x00c2 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING1_H(CHAN)	(ESR_BASE + 0x00c2 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING2_L(CHAN)	(ESR_BASE + 0x0102 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING2_H(CHAN)	(ESR_BASE + 0x0102 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING3_L(CHAN)	(ESR_BASE + 0x0142 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING3_H(CHAN)	(ESR_BASE + 0x0142 + (CHAN) * 0x10)

#define NIU_ESR2_DEV_ADDR		0x1e
#define ESR2_BASE			0x8000

#define ESR2_TI_PLL_CFG_L		(ESR2_BASE + 0x000)
#define ESR2_TI_PLL_CFG_H		(ESR2_BASE + 0x001)
#define  PLL_CFG_STD			0x00000c00
#define  PLL_CFG_STD_SHIFT		10
#define  PLL_CFG_LD			0x00000300
#define  PLL_CFG_LD_SHIFT		8
#define  PLL_CFG_MPY			0x0000001e
#define  PLL_CFG_MPY_SHIFT		1
#define  PLL_CFG_ENPLL			0x00000001

#define ESR2_TI_PLL_STS_L		(ESR2_BASE + 0x002)
#define ESR2_TI_PLL_STS_H		(ESR2_BASE + 0x003)
#define  PLL_STS_LOCK			0x00000001

#define ESR2_TI_PLL_TEST_CFG_L		(ESR2_BASE + 0x004)
#define ESR2_TI_PLL_TEST_CFG_H		(ESR2_BASE + 0x005)
#define  PLL_TEST_INVPATT		0x00004000
#define  PLL_TEST_RATE			0x00003000
#define  PLL_TEST_RATE_SHIFT		12
#define  PLL_TEST_CFG_ENBSAC		0x00000400
#define  PLL_TEST_CFG_ENBSRX		0x00000200
#define  PLL_TEST_CFG_ENBSTX		0x00000100
#define  PLL_TEST_CFG_LOOPBACK_PAD	0x00000040
#define  PLL_TEST_CFG_LOOPBACK_CML_DIS	0x00000080
#define  PLL_TEST_CFG_LOOPBACK_CML_EN	0x000000c0
#define  PLL_TEST_CFG_CLKBYP		0x00000030
#define  PLL_TEST_CFG_CLKBYP_SHIFT	4
#define  PLL_TEST_CFG_EN_RXPATT		0x00000008
#define  PLL_TEST_CFG_EN_TXPATT		0x00000004
#define  PLL_TEST_CFG_TPATT		0x00000003
#define  PLL_TEST_CFG_TPATT_SHIFT	0

#define ESR2_TI_PLL_TX_CFG_L(CHAN)	(ESR2_BASE + 0x100 + (CHAN) * 4)
#define ESR2_TI_PLL_TX_CFG_H(CHAN)	(ESR2_BASE + 0x101 + (CHAN) * 4)
#define  PLL_TX_CFG_RDTCT		0x00600000
#define  PLL_TX_CFG_RDTCT_SHIFT		21
#define  PLL_TX_CFG_ENIDL		0x00100000
#define  PLL_TX_CFG_BSTX		0x00020000
#define  PLL_TX_CFG_ENFTP		0x00010000
#define  PLL_TX_CFG_DE			0x0000f000
#define  PLL_TX_CFG_DE_SHIFT		12
#define  PLL_TX_CFG_SWING_125MV		0x00000000
#define  PLL_TX_CFG_SWING_250MV		0x00000200
#define  PLL_TX_CFG_SWING_500MV		0x00000400
#define  PLL_TX_CFG_SWING_625MV		0x00000600
#define  PLL_TX_CFG_SWING_750MV		0x00000800
#define  PLL_TX_CFG_SWING_1000MV	0x00000a00
#define  PLL_TX_CFG_SWING_1250MV	0x00000c00
#define  PLL_TX_CFG_SWING_1375MV	0x00000e00
#define  PLL_TX_CFG_CM			0x00000100
#define  PLL_TX_CFG_INVPAIR		0x00000080
#define  PLL_TX_CFG_RATE		0x00000060
#define  PLL_TX_CFG_RATE_SHIFT		5
#define  PLL_TX_CFG_BUSWIDTH		0x0000001c
#define  PLL_TX_CFG_BUSWIDTH_SHIFT	2
#define  PLL_TX_CFG_ENTEST		0x00000002
#define  PLL_TX_CFG_ENTX		0x00000001

#define ESR2_TI_PLL_TX_STS_L(CHAN)	(ESR2_BASE + 0x102 + (CHAN) * 4)
#define ESR2_TI_PLL_TX_STS_H(CHAN)	(ESR2_BASE + 0x103 + (CHAN) * 4)
#define  PLL_TX_STS_RDTCTIP		0x00000002
#define  PLL_TX_STS_TESTFAIL		0x00000001

#define ESR2_TI_PLL_RX_CFG_L(CHAN)	(ESR2_BASE + 0x120 + (CHAN) * 4)
#define ESR2_TI_PLL_RX_CFG_H(CHAN)	(ESR2_BASE + 0x121 + (CHAN) * 4)
#define  PLL_RX_CFG_BSINRXN		0x02000000
#define  PLL_RX_CFG_BSINRXP		0x01000000
#define  PLL_RX_CFG_EQ_MAX_LF		0x00000000
#define  PLL_RX_CFG_EQ_LP_ADAPTIVE	0x00080000
#define  PLL_RX_CFG_EQ_LP_1084MHZ	0x00400000
#define  PLL_RX_CFG_EQ_LP_805MHZ	0x00480000
#define  PLL_RX_CFG_EQ_LP_573MHZ	0x00500000
#define  PLL_RX_CFG_EQ_LP_402MHZ	0x00580000
#define  PLL_RX_CFG_EQ_LP_304MHZ	0x00600000
#define  PLL_RX_CFG_EQ_LP_216MHZ	0x00680000
#define  PLL_RX_CFG_EQ_LP_156MHZ	0x00700000
#define  PLL_RX_CFG_EQ_LP_135MHZ	0x00780000
#define  PLL_RX_CFG_EQ_SHIFT		19
#define  PLL_RX_CFG_CDR			0x00070000
#define  PLL_RX_CFG_CDR_SHIFT		16
#define  PLL_RX_CFG_LOS_DIS		0x00000000
#define  PLL_RX_CFG_LOS_HTHRESH		0x00004000
#define  PLL_RX_CFG_LOS_LTHRESH		0x00008000
#define  PLL_RX_CFG_ALIGN_DIS		0x00000000
#define  PLL_RX_CFG_ALIGN_ENA		0x00001000
#define  PLL_RX_CFG_ALIGN_JOG		0x00002000
#define  PLL_RX_CFG_TERM_VDDT		0x00000000
#define  PLL_RX_CFG_TERM_0P8VDDT	0x00000100
#define  PLL_RX_CFG_TERM_FLOAT		0x00000300
#define  PLL_RX_CFG_INVPAIR		0x00000080
#define  PLL_RX_CFG_RATE		0x00000060
#define  PLL_RX_CFG_RATE_SHIFT		5
#define  PLL_RX_CFG_BUSWIDTH		0x0000001c
#define  PLL_RX_CFG_BUSWIDTH_SHIFT	2
#define  PLL_RX_CFG_ENTEST		0x00000002
#define  PLL_RX_CFG_ENRX		0x00000001

#define ESR2_TI_PLL_RX_STS_L(CHAN)	(ESR2_BASE + 0x122 + (CHAN) * 4)
#define ESR2_TI_PLL_RX_STS_H(CHAN)	(ESR2_BASE + 0x123 + (CHAN) * 4)
#define  PLL_RX_STS_CRCIDTCT		0x00000200
#define  PLL_RX_STS_CWDTCT		0x00000100
#define  PLL_RX_STS_BSRXN		0x00000020
#define  PLL_RX_STS_BSRXP		0x00000010
#define  PLL_RX_STS_LOSDTCT		0x00000008
#define  PLL_RX_STS_ODDCG		0x00000004
#define  PLL_RX_STS_SYNC		0x00000002
#define  PLL_RX_STS_TESTFAIL		0x00000001

#define ENET_VLAN_TBL(IDX)		(FZC_FFLP + 0x00000UL + (IDX) * 8UL)
#define  ENET_VLAN_TBL_PARITY1		0x0000000000020000ULL
#define  ENET_VLAN_TBL_PARITY0		0x0000000000010000ULL
#define  ENET_VLAN_TBL_VPR		0x0000000000000008ULL
#define  ENET_VLAN_TBL_VLANRDCTBLN	0x0000000000000007ULL
#define  ENET_VLAN_TBL_SHIFT(PORT)	((PORT) * 4)

#define ENET_VLAN_TBL_NUM_ENTRIES	4096

#define FFLP_VLAN_PAR_ERR		(FZC_FFLP + 0x0800UL)
#define  FFLP_VLAN_PAR_ERR_ERR		0x0000000080000000ULL
#define  FFLP_VLAN_PAR_ERR_M_ERR	0x0000000040000000ULL
#define  FFLP_VLAN_PAR_ERR_ADDR		0x000000003ffc0000ULL
#define  FFLP_VLAN_PAR_ERR_DATA		0x000000000003ffffULL

#define L2_CLS(IDX)			(FZC_FFLP + 0x20000UL + (IDX) * 8UL)
#define  L2_CLS_VLD			0x0000000000010000ULL
#define  L2_CLS_ETYPE			0x000000000000ffffULL
#define  L2_CLS_ETYPE_SHIFT		0

#define L3_CLS(IDX)			(FZC_FFLP + 0x20010UL + (IDX) * 8UL)
#define  L3_CLS_VALID			0x0000000002000000ULL
#define  L3_CLS_IPVER			0x0000000001000000ULL
#define  L3_CLS_PID			0x0000000000ff0000ULL
#define  L3_CLS_PID_SHIFT		16
#define  L3_CLS_TOSMASK			0x000000000000ff00ULL
#define  L3_CLS_TOSMASK_SHIFT		8
#define  L3_CLS_TOS			0x00000000000000ffULL
#define  L3_CLS_TOS_SHIFT		0

#define TCAM_KEY(IDX)			(FZC_FFLP + 0x20030UL + (IDX) * 8UL)
#define  TCAM_KEY_DISC			0x0000000000000008ULL
#define  TCAM_KEY_TSEL			0x0000000000000004ULL
#define  TCAM_KEY_IPADDR		0x0000000000000001ULL

#define TCAM_KEY_0			(FZC_FFLP + 0x20090UL)
#define  TCAM_KEY_0_KEY			0x00000000000000ffULL /* bits 192-199 */

#define TCAM_KEY_1			(FZC_FFLP + 0x20098UL)
#define  TCAM_KEY_1_KEY			0xffffffffffffffffULL /* bits 128-191 */

#define TCAM_KEY_2			(FZC_FFLP + 0x200a0UL)
#define  TCAM_KEY_2_KEY			0xffffffffffffffffULL /* bits 64-127 */

#define TCAM_KEY_3			(FZC_FFLP + 0x200a8UL)
#define  TCAM_KEY_3_KEY			0xffffffffffffffffULL /* bits 0-63 */

#define TCAM_KEY_MASK_0			(FZC_FFLP + 0x200b0UL)
#define  TCAM_KEY_MASK_0_KEY_SEL	0x00000000000000ffULL /* bits 192-199 */

#define TCAM_KEY_MASK_1			(FZC_FFLP + 0x200b8UL)
#define  TCAM_KEY_MASK_1_KEY_SEL	0xffffffffffffffffULL /* bits 128-191 */

#define TCAM_KEY_MASK_2			(FZC_FFLP + 0x200c0UL)
#define  TCAM_KEY_MASK_2_KEY_SEL	0xffffffffffffffffULL /* bits 64-127 */

#define TCAM_KEY_MASK_3			(FZC_FFLP + 0x200c8UL)
#define  TCAM_KEY_MASK_3_KEY_SEL	0xffffffffffffffffULL /* bits 0-63 */

#define TCAM_CTL			(FZC_FFLP + 0x200d0UL)
#define  TCAM_CTL_RWC			0x00000000001c0000ULL
#define  TCAM_CTL_RWC_TCAM_WRITE	0x0000000000000000ULL
#define  TCAM_CTL_RWC_TCAM_READ		0x0000000000040000ULL
#define  TCAM_CTL_RWC_TCAM_COMPARE	0x0000000000080000ULL
#define  TCAM_CTL_RWC_RAM_WRITE		0x0000000000100000ULL
#define  TCAM_CTL_RWC_RAM_READ		0x0000000000140000ULL
#define  TCAM_CTL_STAT			0x0000000000020000ULL
#define  TCAM_CTL_MATCH			0x0000000000010000ULL
#define  TCAM_CTL_LOC			0x00000000000003ffULL

#define TCAM_ERR			(FZC_FFLP + 0x200d8UL)
#define  TCAM_ERR_ERR			0x0000000080000000ULL
#define  TCAM_ERR_P_ECC			0x0000000040000000ULL
#define  TCAM_ERR_MULT			0x0000000020000000ULL
#define  TCAM_ERR_ADDR			0x0000000000ff0000ULL
#define  TCAM_ERR_SYNDROME		0x000000000000ffffULL

#define HASH_LOOKUP_ERR_LOG1		(FZC_FFLP + 0x200e0UL)
#define  HASH_LOOKUP_ERR_LOG1_ERR	0x0000000000000008ULL
#define  HASH_LOOKUP_ERR_LOG1_MULT_LK	0x0000000000000004ULL
#define  HASH_LOOKUP_ERR_LOG1_CU	0x0000000000000002ULL
#define  HASH_LOOKUP_ERR_LOG1_MULT_BIT	0x0000000000000001ULL

#define HASH_LOOKUP_ERR_LOG2		(FZC_FFLP + 0x200e8UL)
#define  HASH_LOOKUP_ERR_LOG2_H1	0x000000007ffff800ULL
#define  HASH_LOOKUP_ERR_LOG2_SUBAREA	0x0000000000000700ULL
#define  HASH_LOOKUP_ERR_LOG2_SYNDROME	0x00000000000000ffULL

#define FFLP_CFG_1			(FZC_FFLP + 0x20100UL)
#define  FFLP_CFG_1_TCAM_DIS		0x0000000004000000ULL
#define  FFLP_CFG_1_PIO_DBG_SEL		0x0000000003800000ULL
#define  FFLP_CFG_1_PIO_FIO_RST		0x0000000000400000ULL
#define  FFLP_CFG_1_PIO_FIO_LAT		0x0000000000300000ULL
#define  FFLP_CFG_1_CAMLAT		0x00000000000f0000ULL
#define  FFLP_CFG_1_CAMLAT_SHIFT	16
#define  FFLP_CFG_1_CAMRATIO		0x000000000000f000ULL
#define  FFLP_CFG_1_CAMRATIO_SHIFT	12
#define  FFLP_CFG_1_FCRAMRATIO		0x0000000000000f00ULL
#define  FFLP_CFG_1_FCRAMRATIO_SHIFT	8
#define  FFLP_CFG_1_FCRAMOUTDR_MASK	0x00000000000000f0ULL
#define  FFLP_CFG_1_FCRAMOUTDR_NORMAL	0x0000000000000000ULL
#define  FFLP_CFG_1_FCRAMOUTDR_STRONG	0x0000000000000050ULL
#define  FFLP_CFG_1_FCRAMOUTDR_WEAK	0x00000000000000a0ULL
#define  FFLP_CFG_1_FCRAMQS		0x0000000000000008ULL
#define  FFLP_CFG_1_ERRORDIS		0x0000000000000004ULL
#define  FFLP_CFG_1_FFLPINITDONE	0x0000000000000002ULL
#define  FFLP_CFG_1_LLCSNAP		0x0000000000000001ULL

#define DEFAULT_FCRAMRATIO		10

#define DEFAULT_TCAM_LATENCY		4
#define DEFAULT_TCAM_ACCESS_RATIO	10

#define TCP_CFLAG_MSK			(FZC_FFLP + 0x20108UL)
#define  TCP_CFLAG_MSK_MASK		0x0000000000000fffULL

#define FCRAM_REF_TMR			(FZC_FFLP + 0x20110UL)
#define  FCRAM_REF_TMR_MAX		0x00000000ffff0000ULL
#define  FCRAM_REF_TMR_MAX_SHIFT	16
#define  FCRAM_REF_TMR_MIN		0x000000000000ffffULL
#define  FCRAM_REF_TMR_MIN_SHIFT	0

#define DEFAULT_FCRAM_REFRESH_MAX	512
#define DEFAULT_FCRAM_REFRESH_MIN	512

#define FCRAM_FIO_ADDR			(FZC_FFLP + 0x20118UL)
#define  FCRAM_FIO_ADDR_ADDR		0x00000000000000ffULL

#define FCRAM_FIO_DAT			(FZC_FFLP + 0x20120UL)


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