dsa: add switch chip cascading support

The initial version of the DSA driver only supported a single switch
chip per network interface, while DSA-capable switch chips can be
interconnected to form a tree of switch chips.  This patch adds support
for multiple switch chips on a network interface.

An example topology for a 16-port device with an embedded CPU is as
follows:

	+-----+          +--------+       +--------+
	|     |eth0    10| switch |9    10| switch |
	| CPU +----------+        +-------+        |
	|     |          | chip 0 |       | chip 1 |
	+-----+          +---++---+       +---++---+
	                     ||               ||
	                     ||               ||
	                     ||1000baseT      ||1000baseT
	                     ||ports 1-8      ||ports 9-16

This requires a couple of interdependent changes in the DSA layer:

- The dsa platform driver data needs to be extended: there is still
  only one netdevice per DSA driver instance (eth0 in the example
  above), but each of the switch chips in the tree needs its own
  mii_bus device pointer, MII management bus address, and port name
  array. (include/net/dsa.h)  The existing in-tree dsa users need
  some small changes to deal with this. (arch/arm)

- The DSA and Ethertype DSA tagging modules need to be extended to
  use the DSA device ID field on receive and demultiplex the packet
  accordingly, and fill in the DSA device ID field on transmit
  according to which switch chip the packet is heading to.
  (net/dsa/tag_{dsa,edsa}.c)

- The concept of "CPU port", which is the switch chip port that the
  CPU is connected to (port 10 on switch chip 0 in the example), needs
  to be extended with the concept of "upstream port", which is the
  port on the switch chip that will bring us one hop closer to the CPU
  (port 10 for both switch chips in the example above).

- The dsa platform data needs to specify which ports on which switch
  chips are links to other switch chips, so that we can enable DSA
  tagging mode on them.  (For inter-switch links, we always use
  non-EtherType DSA tagging, since it has lower overhead.  The CPU
  link uses dsa or edsa tagging depending on what the 'root' switch
  chip supports.)  This is done by specifying "dsa" for the given
  port in the port array.

- The dsa platform data needs to be extended with information on via
  which port to reach any given switch chip from any given switch chip.
  This info is specified via the per-switch chip data struct ->rtable[]
  array, which gives the nexthop ports for each of the other switches
  in the tree.

For the example topology above, the dsa platform data would look
something like this:

	static struct dsa_chip_data sw[2] = {
		{
			.mii_bus	= &foo,
			.sw_addr	= 1,
			.port_names[0]	= "p1",
			.port_names[1]	= "p2",
			.port_names[2]	= "p3",
			.port_names[3]	= "p4",
			.port_names[4]	= "p5",
			.port_names[5]	= "p6",
			.port_names[6]	= "p7",
			.port_names[7]	= "p8",
			.port_names[9]	= "dsa",
			.port_names[10]	= "cpu",
			.rtable		= (s8 []){ -1, 9, },
		}, {
			.mii_bus	= &foo,
			.sw_addr	= 2,
			.port_names[0]	= "p9",
			.port_names[1]	= "p10",
			.port_names[2]	= "p11",
			.port_names[3]	= "p12",
			.port_names[4]	= "p13",
			.port_names[5]	= "p14",
			.port_names[6]	= "p15",
			.port_names[7]	= "p16",
			.port_names[10]	= "dsa",
			.rtable		= (s8 []){ 10, -1, },
		},
	},

	static struct dsa_platform_data pd = {
		.netdev		= &foo,
		.nr_switches	= 2,
		.sw		= sw,
	};

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Gary Thomas <gary@mlbassoc.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 81 insertions, 16 deletions

diff --git a/net/dsa/dsa_priv.h b/net/dsa/dsa_priv.h
index 7063378a1ebf..41055f33d28a 100644
--- a/net/dsa/dsa_priv.h
+++ b/net/dsa/dsa_priv.h
@@ -1,6 +1,6 @@
 /*
  * net/dsa/dsa_priv.h - Hardware switch handling
- * Copyright (c) 2008 Marvell Semiconductor
+ * Copyright (c) 2008-2009 Marvell Semiconductor
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -19,42 +19,107 @@
 
 struct dsa_switch {
         /*
-         * Configuration data for the platform device that owns
-         * this dsa switch instance.
+         * Parent switch tree, and switch index.
          */
-        struct dsa_platform_data        *pd;
+        struct dsa_switch_tree  *dst;
+        int                     index;
 
         /*
-         * References to network device and mii bus to use.
+         * Configuration data for this switch.
          */
-        struct net_device               *master_netdev;
-        struct mii_bus                  *master_mii_bus;
+        struct dsa_chip_data    *pd;
 
         /*
-         * The used switch driver and frame tagging type.
+         * The used switch driver.
          */
         struct dsa_switch_driver        *drv;
-        __be16                          tag_protocol;
+
+        /*
+         * Reference to mii bus to use.
+         */
+        struct mii_bus          *master_mii_bus;
 
         /*
          * Slave mii_bus and devices for the individual ports.
          */
-        int                             cpu_port;
-        u32                             valid_port_mask;
-        struct mii_bus                  *slave_mii_bus;
-        struct net_device               *ports[DSA_MAX_PORTS];
+        u32                     dsa_port_mask;
+        u32                     phys_port_mask;
+        struct mii_bus          *slave_mii_bus;
+        struct net_device       *ports[DSA_MAX_PORTS];
+};
+
+struct dsa_switch_tree {
+        /*
+         * Configuration data for the platform device that owns
+         * this dsa switch tree instance.
+         */
+        struct dsa_platform_data        *pd;
+
+        /*
+         * Reference to network device to use, and which tagging
+         * protocol to use.
+         */
+        struct net_device       *master_netdev;
+        __be16                  tag_protocol;
+
+        /*
+         * The switch and port to which the CPU is attached.
+         */
+        s8                      cpu_switch;
+        s8                      cpu_port;
 
         /*
          * Link state polling.
          */
-        struct work_struct              link_poll_work;
-        struct timer_list               link_poll_timer;
+        int                     link_poll_needed;
+        struct work_struct      link_poll_work;
+        struct timer_list       link_poll_timer;
+
+        /*
+         * Data for the individual switch chips.
+         */
+        struct dsa_switch       *ds[DSA_MAX_SWITCHES];
 };
 
+static inline bool dsa_is_cpu_port(struct dsa_switch *ds, int p)
+{
+        return !!(ds->index == ds->dst->cpu_switch && p == ds->dst->cpu_port);
+}
+
+static inline u8 dsa_upstream_port(struct dsa_switch *ds)
+{
+        struct dsa_switch_tree *dst = ds->dst;
+
+        /*
+         * If this is the root switch (i.e. the switch that connects
+         * to the CPU), return the cpu port number on this switch.
+         * Else return the (DSA) port number that connects to the
+         * switch that is one hop closer to the cpu.
+         */
+        if (dst->cpu_switch == ds->index)
+                return dst->cpu_port;
+        else
+                return ds->pd->rtable[dst->cpu_switch];
+}
+
 struct dsa_slave_priv {
+        /*
+         * The linux network interface corresponding to this
+         * switch port.
+         */
         struct net_device       *dev;
+
+        /*
+         * Which switch this port is a part of, and the port index
+         * for this port.
+         */
         struct dsa_switch       *parent;
-        int                     port;
+        u8                      port;
+
+        /*
+         * The phylib phy_device pointer for the PHY connected
+         * to this port.
+         */
         struct phy_device       *phy;
 };