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| author | Paul Walmsley <paul@pwsan.com> | 2009-06-19 21:08:24 -0400 |
|---|---|---|
| committer | paul <paul@twilight.(none)> | 2009-06-19 21:09:30 -0400 |
| commit | 6adb8f388ef2f23d4a81e1e42d15f22d62749a06 (patch) | |
| tree | 217206b7b4751b6644e3cbe91cfff8e4df861e48 /net/ax25/ax25_ds_timer.c | |
| parent | cd07ecc828486e5887113c7dc4d9f9022145811b (diff) | |
OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize
The original CDP kernel that this code comes from waited for 0x800
loops after switching the CORE DPLL M2 divider. This does not appear
to be necessary.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'net/ax25/ax25_ds_timer.c')
0 files changed, 0 insertions, 0 deletions