litmus-rt.git - The LITMUS^RT kernel.

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author	David Decotigny <decot@googlers.com>	2013-01-11 17:31:36 -0500
committer	Linus Torvalds <torvalds@linux-foundation.org>	2013-01-11 17:54:54 -0500
commit	896f97ea95c1d29c0520ee0766b66b7f64cb967c (patch)
tree	9898ba669c2348294452fcfd5b7b81fe04cb072f /lib
parent	254adaa465c40151df11fc1f88f93e6e86eb61d4 (diff)

lib: cpu_rmap: avoid flushing all workqueues

In some cases, free_irq_cpu_rmap() is called while holding a lock (eg rtnl). This can lead to deadlocks, because it invokes flush_scheduled_work() which ends up waiting for whole system workqueue to flush, but some pending works might try to acquire the lock we are already holding. This commit uses reference-counting to replace irq_run_affinity_notifiers(). It also removes irq_run_affinity_notifiers() altogether. [akpm@linux-foundation.org: eliminate free_cpu_rmap, rename cpu_rmap_reclaim() to cpu_rmap_release(), propagate kref_put() retval from cpu_rmap_put()] Signed-off-by: David Decotigny <decot@googlers.com> Reviewed-by: Ben Hutchings <bhutchings@solarflare.com> Acked-by: Eric Dumazet <edumazet@google.com> Reviewed-by: Josh Triplett <josh@joshtriplett.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Or Gerlitz <ogerlitz@mellanox.com> Acked-by: Amir Vadai <amirv@mellanox.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Diffstat (limited to 'lib')

-rw-r--r--

lib/cpu_rmap.c

1 files changed, 49 insertions, 5 deletions

         if (!rmap)
                 return NULL;
+        kref_init(&rmap->refcount);
         rmap->obj = (void **)((char *)rmap + obj_offset);
         /* Initially assign CPUs to objects on a rota, since we have
 }
 EXPORT_SYMBOL(alloc_cpu_rmap);
+/**
+ * cpu_rmap_release - internal reclaiming helper called from kref_put
+ * @ref: kref to struct cpu_rmap
+ */
+static void cpu_rmap_release(struct kref *ref)
+{
+        struct cpu_rmap *rmap = container_of(ref, struct cpu_rmap, refcount);
+        kfree(rmap);
+}
+/**
+ * cpu_rmap_get - internal helper to get new ref on a cpu_rmap
+ * @rmap: reverse-map allocated with alloc_cpu_rmap()
+ */
+static inline void cpu_rmap_get(struct cpu_rmap *rmap)
+{
+        kref_get(&rmap->refcount);
+}
+/**
+ * cpu_rmap_put - release ref on a cpu_rmap
+ * @rmap: reverse-map allocated with alloc_cpu_rmap()
+ */
+int cpu_rmap_put(struct cpu_rmap *rmap)
+{
+        return kref_put(&rmap->refcount, cpu_rmap_release);
+}
+EXPORT_SYMBOL(cpu_rmap_put);
 /* Reevaluate nearest object for given CPU, comparing with the given
  * neighbours at the given distance.
  */
  * free_irq_cpu_rmap - free a CPU affinity reverse-map used for IRQs
  * @rmap: Reverse-map allocated with alloc_irq_cpu_map(), or %NULL
  *
- * Must be called in process context, before freeing the IRQs, and
+ * Must be called in process context, before freeing the IRQs.
- * without holding any locks required by global workqueue items.
  */
 void free_irq_cpu_rmap(struct cpu_rmap *rmap)
 {
                 glue = rmap->obj[index];
                 irq_set_affinity_notifier(glue->notify.irq, NULL);
         }
-        irq_run_affinity_notifiers();
-        kfree(rmap);
+        cpu_rmap_put(rmap);
 }
 EXPORT_SYMBOL(free_irq_cpu_rmap);
+/**
+ * irq_cpu_rmap_notify - callback for IRQ subsystem when IRQ affinity updated
+ * @notify: struct irq_affinity_notify passed by irq/manage.c
+ * @mask: cpu mask for new SMP affinity
+ *
+ * This is executed in workqueue context.
+ */
 static void
 irq_cpu_rmap_notify(struct irq_affinity_notify *notify, const cpumask_t *mask)
 {
                 pr_warning("irq_cpu_rmap_notify: update failed: %d\n", rc);
 }
+/**
+ * irq_cpu_rmap_release - reclaiming callback for IRQ subsystem
+ * @ref: kref to struct irq_affinity_notify passed by irq/manage.c
+ */
 static void irq_cpu_rmap_release(struct kref *ref)
 {
         struct irq_glue *glue =
                 container_of(ref, struct irq_glue, notify.kref);
+        cpu_rmap_put(glue->rmap);
         kfree(glue);
 }
         glue->notify.notify = irq_cpu_rmap_notify;
         glue->notify.release = irq_cpu_rmap_release;
         glue->rmap = rmap;
+        cpu_rmap_get(rmap);
         glue->index = cpu_rmap_add(rmap, glue);
         rc = irq_set_affinity_notifier(irq, &glue->notify);
-        if (rc)
+        if (rc) {
+                cpu_rmap_put(glue->rmap);
                 kfree(glue);
+        }
         return rc;
 }
 EXPORT_SYMBOL(irq_cpu_rmap_add);

/* * sata_nv.c - NVIDIA nForce SATA * * Copyright 2004 NVIDIA Corp. All rights reserved. * Copyright 2004 Andrew Chew * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2, or (at your option) * any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; see the file COPYING. If not, write to * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. * * * libata documentation is available via 'make {ps|pdf}docs', * as Documentation/DocBook/libata.* * * No hardware documentation available outside of NVIDIA. * This driver programs the NVIDIA SATA controller in a similar * fashion as with other PCI IDE BMDMA controllers, with a few * NV-specific details such as register offsets, SATA phy location, * hotplug info, etc. * * CK804/MCP04 controllers support an alternate programming interface * similar to the ADMA specification (with some modifications). * This allows the use of NCQ. Non-DMA-mapped ATA commands are still * sent through the legacy interface. * */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/gfp.h> #include <linux/pci.h> #include <linux/init.h> #include <linux/blkdev.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/device.h> #include <scsi/scsi_host.h> #include <scsi/scsi_device.h> #include <linux/libata.h> #define DRV_NAME "sata_nv" #define DRV_VERSION "3.5" #define NV_ADMA_DMA_BOUNDARY 0xffffffffUL enum { NV_MMIO_BAR = 5, NV_PORTS = 2, NV_PIO_MASK = ATA_PIO4, NV_MWDMA_MASK = ATA_MWDMA2, NV_UDMA_MASK = ATA_UDMA6, NV_PORT0_SCR_REG_OFFSET = 0x00, NV_PORT1_SCR_REG_OFFSET = 0x40, /* INT_STATUS/ENABLE */ NV_INT_STATUS = 0x10, NV_INT_ENABLE = 0x11, NV_INT_STATUS_CK804 = 0x440, NV_INT_ENABLE_CK804 = 0x441, /* INT_STATUS/ENABLE bits */ NV_INT_DEV = 0x01, NV_INT_PM = 0x02, NV_INT_ADDED = 0x04, NV_INT_REMOVED = 0x08, NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */ NV_INT_ALL = 0x0f, NV_INT_MASK = NV_INT_DEV | NV_INT_ADDED | NV_INT_REMOVED, /* INT_CONFIG */ NV_INT_CONFIG = 0x12, NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI // For PCI config register 20 NV_MCP_SATA_CFG_20 = 0x50, NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04, NV_MCP_SATA_CFG_20_PORT0_EN = (1 << 17), NV_MCP_SATA_CFG_20_PORT1_EN = (1 << 16), NV_MCP_SATA_CFG_20_PORT0_PWB_EN = (1 << 14), NV_MCP_SATA_CFG_20_PORT1_PWB_EN = (1 << 12), NV_ADMA_MAX_CPBS = 32, NV_ADMA_CPB_SZ = 128, NV_ADMA_APRD_SZ = 16, NV_ADMA_SGTBL_LEN = (1024 - NV_ADMA_CPB_SZ) / NV_ADMA_APRD_SZ, NV_ADMA_SGTBL_TOTAL_LEN = NV_ADMA_SGTBL_LEN + 5, NV_ADMA_SGTBL_SZ = NV_ADMA_SGTBL_LEN * NV_ADMA_APRD_SZ, NV_ADMA_PORT_PRIV_DMA_SZ = NV_ADMA_MAX_CPBS * (NV_ADMA_CPB_SZ + NV_ADMA_SGTBL_SZ), /* BAR5 offset to ADMA general registers */ NV_ADMA_GEN = 0x400, NV_ADMA_GEN_CTL = 0x00, NV_ADMA_NOTIFIER_CLEAR = 0x30, /* BAR5 offset to ADMA ports */ NV_ADMA_PORT = 0x480, /* size of ADMA port register space */ NV_ADMA_PORT_SIZE = 0x100, /* ADMA port registers */ NV_ADMA_CTL = 0x40, NV_ADMA_CPB_COUNT = 0x42, NV_ADMA_NEXT_CPB_IDX = 0x43, NV_ADMA_STAT = 0x44, NV_ADMA_CPB_BASE_LOW = 0x48, NV_ADMA_CPB_BASE_HIGH = 0x4C, NV_ADMA_APPEND = 0x50, NV_ADMA_NOTIFIER = 0x68, NV_ADMA_NOTIFIER_ERROR = 0x6C, /* NV_ADMA_CTL register bits */ NV_ADMA_CTL_HOTPLUG_IEN = (1 << 0), NV_ADMA_CTL_CHANNEL_RESET = (1 << 5), NV_ADMA_CTL_GO = (1 << 7), NV_ADMA_CTL_AIEN = (1 << 8), NV_ADMA_CTL_READ_NON_COHERENT = (1 << 11), NV_ADMA_CTL_WRITE_NON_COHERENT = (1 << 12), /* CPB response flag bits */ NV_CPB_RESP_DONE = (1 << 0), NV_CPB_RESP_ATA_ERR = (1 << 3), NV_CPB_RESP_CMD_ERR = (1 << 4), NV_CPB_RESP_CPB_ERR = (1 << 7), /* CPB control flag bits */ NV_CPB_CTL_CPB_VALID = (1 << 0), NV_CPB_CTL_QUEUE = (1 << 1), NV_CPB_CTL_APRD_VALID = (1 << 2), NV_CPB_CTL_IEN = (1 << 3), NV_CPB_CTL_FPDMA = (1 << 4), /* APRD flags */ NV_APRD_WRITE = (1 << 1), NV_APRD_END = (1 << 2), NV_APRD_CONT = (1 << 3), /* NV_ADMA_STAT flags */ NV_ADMA_STAT_TIMEOUT = (1 << 0), NV_ADMA_STAT_HOTUNPLUG = (1 << 1), NV_ADMA_STAT_HOTPLUG = (1 << 2), NV_ADMA_STAT_CPBERR = (1 << 4), NV_ADMA_STAT_SERROR = (1 << 5), NV_ADMA_STAT_CMD_COMPLETE = (1 << 6), NV_ADMA_STAT_IDLE = (1 << 8), NV_ADMA_STAT_LEGACY = (1 << 9), NV_ADMA_STAT_STOPPED = (1 << 10), NV_ADMA_STAT_DONE = (1 << 12), NV_ADMA_STAT_ERR = NV_ADMA_STAT_CPBERR | NV_ADMA_STAT_TIMEOUT, /* port flags */ NV_ADMA_PORT_REGISTER_MODE = (1 << 0), NV_ADMA_ATAPI_SETUP_COMPLETE = (1 << 1), /* MCP55 reg offset */ NV_CTL_MCP55 = 0x400, NV_INT_STATUS_MCP55 = 0x440, NV_INT_ENABLE_MCP55 = 0x444, NV_NCQ_REG_MCP55 = 0x448, /* MCP55 */ NV_INT_ALL_MCP55 = 0xffff, NV_INT_PORT_SHIFT_MCP55 = 16, /* each port occupies 16 bits */ NV_INT_MASK_MCP55 = NV_INT_ALL_MCP55 & 0xfffd, /* SWNCQ ENABLE BITS*/ NV_CTL_PRI_SWNCQ = 0x02, NV_CTL_SEC_SWNCQ = 0x04, /* SW NCQ status bits*/ NV_SWNCQ_IRQ_DEV = (1 << 0), NV_SWNCQ_IRQ_PM = (1 << 1), NV_SWNCQ_IRQ_ADDED = (1 << 2), NV_SWNCQ_IRQ_REMOVED = (1 << 3), NV_SWNCQ_IRQ_BACKOUT = (1 << 4), NV_SWNCQ_IRQ_SDBFIS = (1 << 5), NV_SWNCQ_IRQ_DHREGFIS = (1 << 6), NV_SWNCQ_IRQ_DMASETUP = (1 << 7), NV_SWNCQ_IRQ_HOTPLUG = NV_SWNCQ_IRQ_ADDED | NV_SWNCQ_IRQ_REMOVED, }; /* ADMA Physical Region Descriptor - one SG segment */ struct nv_adma_prd { __le64 addr; __le32 len; u8 flags; u8 packet_len; __le16 reserved; }; enum nv_adma_regbits { CMDEND = (1 << 15), /* end of command list */ WNB = (1 << 14), /* wait-not-BSY */ IGN = (1 << 13), /* ignore this entry */ CS1n = (1 << (4 + 8)), /* std. PATA signals follow... */ DA2 = (1 << (2 + 8)), DA1 = (1 << (1 + 8)), DA0 = (1 << (0 + 8)), }; /* ADMA Command Parameter Block The first 5 SG segments are stored inside the Command Parameter Block itself. If there are more than 5 segments the remainder are stored in a separate memory area indicated by next_aprd. */ struct nv_adma_cpb { u8 resp_flags; /* 0 */ u8 reserved1; /* 1 */ u8 ctl_flags; /* 2 */ /* len is length of taskfile in 64 bit words */ u8 len; /* 3 */ u8 tag; /* 4 */ u8 next_cpb_idx; /* 5 */ __le16 reserved2; /* 6-7 */ __le16 tf[12]; /* 8-31 */ struct nv_adma_prd aprd[5]; /* 32-111 */ __le64 next_aprd; /* 112-119 */ __le64 reserved3; /* 120-127 */ }; struct nv_adma_port_priv { struct nv_adma_cpb *cpb; dma_addr_t cpb_dma; struct nv_adma_prd *aprd; dma_addr_t aprd_dma; void __iomem *ctl_block; void __iomem *gen_block; void __iomem *notifier_clear_block; u64 adma_dma_mask; u8 flags; int last_issue_ncq; }; struct nv_host_priv { unsigned long type; }; struct defer_queue { u32 defer_bits; unsigned int head; unsigned int tail; unsigned int tag[ATA_MAX_QUEUE]; }; enum ncq_saw_flag_list { ncq_saw_d2h = (1U << 0), ncq_saw_dmas = (1U << 1), ncq_saw_sdb = (1U << 2), ncq_saw_backout = (1U << 3), }; struct nv_swncq_port_priv { struct ata_bmdma_prd *prd; /* our SG list */ dma_addr_t prd_dma; /* and its DMA mapping */ void __iomem *sactive_block; void __iomem *irq_block; void __iomem *tag_block; u32 qc_active; unsigned int last_issue_tag; /* fifo circular queue to store deferral command */ struct defer_queue defer_queue; /* for NCQ interrupt analysis */ u32 dhfis_bits; u32 dmafis_bits; u32 sdbfis_bits; unsigned int ncq_flags; }; #define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & (1 << (19 + (12 * (PORT))))) static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); #ifdef CONFIG_PM static int nv_pci_device_resume(struct pci_dev *pdev); #endif static void nv_ck804_host_stop(struct ata_host *host); static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance); static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance); static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance); static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); static int nv_hardreset(struct ata_link *link, unsigned int *class, unsigned long deadline); static void nv_nf2_freeze(struct ata_port *ap); static void nv_nf2_thaw(struct ata_port *ap); static void nv_ck804_freeze(struct ata_port *ap); static void nv_ck804_thaw(struct ata_port *ap); static int nv_adma_slave_config(struct scsi_device *sdev); static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc); static void nv_adma_qc_prep(struct ata_queued_cmd *qc); static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc); static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance); static void nv_adma_irq_clear(struct ata_port *ap); static int nv_adma_port_start(struct ata_port *ap); static void nv_adma_port_stop(struct ata_port *ap); #ifdef CONFIG_PM static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg); static int nv_adma_port_resume(struct ata_port *ap); #endif static void nv_adma_freeze(struct ata_port *ap); static void nv_adma_thaw(struct ata_port *ap); static void nv_adma_error_handler(struct ata_port *ap); static void nv_adma_host_stop(struct ata_host *host); static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc); static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf); static void nv_mcp55_thaw(struct ata_port *ap); static void nv_mcp55_freeze(struct ata_port *ap); static void nv_swncq_error_handler(struct ata_port *ap); static int nv_swncq_slave_config(struct scsi_device *sdev); static int nv_swncq_port_start(struct ata_port *ap); static void nv_swncq_qc_prep(struct ata_queued_cmd *qc); static void nv_swncq_fill_sg(struct ata_queued_cmd *qc); static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc); static void nv_swncq_irq_clear(struct ata_port *ap, u16 fis); static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance); #ifdef CONFIG_PM static int nv_swncq_port_suspend(struct ata_port *ap, pm_message_t mesg); static int nv_swncq_port_resume(struct ata_port *ap); #endif enum nv_host_type { GENERIC, NFORCE2, NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */ CK804, ADMA, MCP5x, SWNCQ, }; static const struct pci_device_id nv_pci_tbl[] = { { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), MCP5x }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), MCP5x }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), MCP5x }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), MCP5x }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC }, { } /* terminate list */ }; static struct pci_driver nv_pci_driver = { .name = DRV_NAME, .id_table = nv_pci_tbl, .probe = nv_init_one, #ifdef CONFIG_PM .suspend = ata_pci_device_suspend, .resume = nv_pci_device_resume, #endif .remove = ata_pci_remove_one, }; static struct scsi_host_template nv_sht = { ATA_BMDMA_SHT(DRV_NAME), }; static struct scsi_host_template nv_adma_sht = { ATA_NCQ_SHT(DRV_NAME), .can_queue = NV_ADMA_MAX_CPBS, .sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN, .dma_boundary = NV_ADMA_DMA_BOUNDARY, .slave_configure = nv_adma_slave_config, }; static struct scsi_host_template nv_swncq_sht = { ATA_NCQ_SHT(DRV_NAME), .can_queue = ATA_MAX_QUEUE, .sg_tablesize = LIBATA_MAX_PRD, .dma_boundary = ATA_DMA_BOUNDARY, .slave_configure = nv_swncq_slave_config, }; /* * NV SATA controllers have various different problems with hardreset * protocol depending on the specific controller and device. * * GENERIC: * * bko11195 reports that link doesn't come online after hardreset on * generic nv's and there have been several other similar reports on * linux-ide. * * bko12351#c23 reports that warmplug on MCP61 doesn't work with * softreset. * * NF2/3: * * bko3352 reports nf2/3 controllers can't determine device signature * reliably after hardreset. The following thread reports detection * failure on cold boot with the standard debouncing timing. * * http://thread.gmane.org/gmane.linux.ide/34098 * * bko12176 reports that hardreset fails to bring up the link during * boot on nf2. * * CK804: * * For initial probing after boot and hot plugging, hardreset mostly * works fine on CK804 but curiously, reprobing on the initial port * by rescanning or rmmod/insmod fails to acquire the initial D2H Reg * FIS in somewhat undeterministic way. * * SWNCQ: * * bko12351 reports that when SWNCQ is enabled, for hotplug to work, * hardreset should be used and hardreset can't report proper * signature, which suggests that mcp5x is closer to nf2 as long as * reset quirkiness is concerned. * * bko12703 reports that boot probing fails for intel SSD with * hardreset. Link fails to come online. Softreset works fine. * * The failures are varied but the following patterns seem true for * all flavors. * * - Softreset during boot always works. * * - Hardreset during boot sometimes fails to bring up the link on * certain comibnations and device signature acquisition is * unreliable. * * - Hardreset is often necessary after hotplug. * * So, preferring softreset for boot probing and error handling (as * hardreset might bring down the link) but using hardreset for * post-boot probing should work around the above issues in most * cases. Define nv_hardreset() which only kicks in for post-boot * probing and use it for all variants. */ static struct ata_port_operations nv_generic_ops = { .inherits = &ata_bmdma_port_ops, .lost_interrupt = ATA_OP_NULL, .scr_read = nv_scr_read, .scr_write = nv_scr_write, .hardreset = nv_hardreset, }; static struct ata_port_operations nv_nf2_ops = { .inherits = &nv_generic_ops, .freeze = nv_nf2_freeze, .thaw = nv_nf2_thaw, }; static struct ata_port_operations nv_ck804_ops = { .inherits = &nv_generic_ops, .freeze = nv_ck804_freeze, .thaw = nv_ck804_thaw, .host_stop = nv_ck804_host_stop, }; static struct ata_port_operations nv_adma_ops = { .inherits = &nv_ck804_ops, .check_atapi_dma = nv_adma_check_atapi_dma, .sff_tf_read = nv_adma_tf_read, .qc_defer = ata_std_qc_defer, .qc_prep = nv_adma_qc_prep, .qc_issue = nv_adma_qc_issue, .sff_irq_clear = nv_adma_irq_clear, .freeze = nv_adma_freeze, .thaw = nv_adma_thaw, .error_handler = nv_adma_error_handler, .post_internal_cmd = nv_adma_post_internal_cmd, .port_start = nv_adma_port_start, .port_stop = nv_adma_port_stop, #ifdef CONFIG_PM .port_suspend = nv_adma_port_suspend, .port_resume = nv_adma_port_resume, #endif .host_stop = nv_adma_host_stop, }; static struct ata_port_operations nv_swncq_ops = { .inherits = &nv_generic_ops, .qc_defer = ata_std_qc_defer, .qc_prep = nv_swncq_qc_prep, .qc_issue = nv_swncq_qc_issue, .freeze = nv_mcp55_freeze, .thaw = nv_mcp55_thaw, .error_handler = nv_swncq_error_handler, #ifdef CONFIG_PM .port_suspend = nv_swncq_port_suspend, .port_resume = nv_swncq_port_resume, #endif .port_start = nv_swncq_port_start, }; struct nv_pi_priv { irq_handler_t irq_handler; struct scsi_host_template *sht; }; #define NV_PI_PRIV(_irq_handler, _sht) \ &(struct nv_pi_priv){ .irq_handler = _irq_handler, .sht = _sht } static const struct ata_port_info nv_port_info[] = { /* generic */ { .flags = ATA_FLAG_SATA, .pio_mask = NV_PIO_MASK, .mwdma_mask = NV_MWDMA_MASK, .udma_mask = NV_UDMA_MASK, .port_ops = &nv_generic_ops, .private_data = NV_PI_PRIV(nv_generic_interrupt, &nv_sht), }, /* nforce2/3 */ { .flags = ATA_FLAG_SATA, .pio_mask = NV_PIO_MASK, .mwdma_mask = NV_MWDMA_MASK, .udma_mask = NV_UDMA_MASK, .port_ops = &nv_nf2_ops, .private_data = NV_PI_PRIV(nv_nf2_interrupt, &nv_sht), }, /* ck804 */ { .flags = ATA_FLAG_SATA, .pio_mask = NV_PIO_MASK, .mwdma_mask = NV_MWDMA_MASK, .udma_mask = NV_UDMA_MASK, .port_ops = &nv_ck804_ops, .private_data = NV_PI_PRIV(nv_ck804_interrupt, &nv_sht), }, /* ADMA */ { .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ, .pio_mask = NV_PIO_MASK, .mwdma_mask = NV_MWDMA_MASK, .udma_mask = NV_UDMA_MASK, .port_ops = &nv_adma_ops, .private_data = NV_PI_PRIV(nv_adma_interrupt, &nv_adma_sht), }, /* MCP5x */ { .flags = ATA_FLAG_SATA, .pio_mask = NV_PIO_MASK, .mwdma_mask = NV_MWDMA_MASK, .udma_mask = NV_UDMA_MASK, .port_ops = &nv_generic_ops, .private_data = NV_PI_PRIV(nv_generic_interrupt, &nv_sht), }, /* SWNCQ */ { .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ, .pio_mask = NV_PIO_MASK, .mwdma_mask = NV_MWDMA_MASK, .udma_mask = NV_UDMA_MASK, .port_ops = &nv_swncq_ops, .private_data = NV_PI_PRIV(nv_swncq_interrupt, &nv_swncq_sht), }, }; MODULE_AUTHOR("NVIDIA"); MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller"); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(pci, nv_pci_tbl); MODULE_VERSION(DRV_VERSION); static bool adma_enabled; static bool swncq_enabled = 1; static bool msi_enabled; static void nv_adma_register_mode(struct ata_port *ap) { struct nv_adma_port_priv *pp = ap->private_data; void __iomem *mmio = pp->ctl_block; u16 tmp, status; int count = 0; if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) return; status = readw(mmio + NV_ADMA_STAT); while (!(status & NV_ADMA_STAT_IDLE) && count < 20) { ndelay(50); status = readw(mmio + NV_ADMA_STAT); count++; } if (count == 20) ata_port_warn(ap, "timeout waiting for ADMA IDLE, stat=0x%hx\n", status); tmp = readw(mmio + NV_ADMA_CTL); writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL); count = 0; status = readw(mmio + NV_ADMA_STAT); while (!(status & NV_ADMA_STAT_LEGACY) && count < 20) { ndelay(50); status = readw(mmio + NV_ADMA_STAT); count++; } if (count == 20) ata_port_warn(ap, "timeout waiting for ADMA LEGACY, stat=0x%hx\n", status); pp->flags |= NV_ADMA_PORT_REGISTER_MODE; } static void nv_adma_mode(struct ata_port *ap) { struct nv_adma_port_priv *pp = ap->private_data; void __iomem *mmio = pp->ctl_block; u16 tmp, status; int count = 0; if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) return; WARN_ON(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE); tmp = readw(mmio + NV_ADMA_CTL); writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL); status = readw(mmio + NV_ADMA_STAT); while (((status & NV_ADMA_STAT_LEGACY) || !(status & NV_ADMA_STAT_IDLE)) && count < 20) { ndelay(50); status = readw(mmio + NV_ADMA_STAT); count++; } if (count == 20) ata_port_warn(ap, "timeout waiting for ADMA LEGACY clear and IDLE, stat=0x%hx\n", status); pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE; } static int nv_adma_slave_config(struct scsi_device *sdev) { struct ata_port *ap = ata_shost_to_port(sdev->host); struct nv_adma_port_priv *pp = ap->private_data; struct nv_adma_port_priv *port0, *port1; struct scsi_device *sdev0, *sdev1; struct pci_dev *pdev = to_pci_dev(ap->host->dev); unsigned long segment_boundary, flags; unsigned short sg_tablesize; int rc; int adma_enable; u32 current_reg, new_reg, config_mask; rc = ata_scsi_slave_config(sdev); if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun) /* Not a proper libata device, ignore */ return rc; spin_lock_irqsave(ap->lock, flags); if (ap->link.device[sdev->id].class == ATA_DEV_ATAPI) { /* * NVIDIA reports that ADMA mode does not support ATAPI commands. * Therefore ATAPI commands are sent through the legacy interface. * However, the legacy interface only supports 32-bit DMA. * Restrict DMA parameters as required by the legacy interface * when an ATAPI device is connected. */ segment_boundary = ATA_DMA_BOUNDARY; /* Subtract 1 since an extra entry may be needed for padding, see libata-scsi.c */ sg_tablesize = LIBATA_MAX_PRD - 1; /* Since the legacy DMA engine is in use, we need to disable ADMA on the port. */ adma_enable = 0; nv_adma_register_mode(ap); } else { segment_boundary = NV_ADMA_DMA_BOUNDARY; sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN; adma_enable = 1; } pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &current_reg); if (ap->port_no == 1) config_mask = NV_MCP_SATA_CFG_20_PORT1_EN | NV_MCP_SATA_CFG_20_PORT1_PWB_EN; else config_mask = NV_MCP_SATA_CFG_20_PORT0_EN | NV_MCP_SATA_CFG_20_PORT0_PWB_EN; if (adma_enable) { new_reg = current_reg | config_mask; pp->flags &= ~NV_ADMA_ATAPI_SETUP_COMPLETE; } else { new_reg = current_reg & ~config_mask; pp->flags |= NV_ADMA_ATAPI_SETUP_COMPLETE; } if (current_reg != new_reg) pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, new_reg); port0 = ap->host->ports[0]->private_data; port1 = ap->host->ports[1]->private_data;


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