Merge tag 'md-3.8' of git://neil.brown.name/md

Pull md update from Neil Brown:
 "Mostly just little fixes.  Probably biggest part is AVX accelerated
  RAID6 calculations."

* tag 'md-3.8' of git://neil.brown.name/md:
  md/raid5: add blktrace calls
  md/raid5: use async_tx_quiesce() instead of open-coding it.
  md: Use ->curr_resync as last completed request when cleanly aborting resync.
  lib/raid6: build proper files on corresponding arch
  lib/raid6: Add AVX2 optimized gen_syndrome functions
  lib/raid6: Add AVX2 optimized recovery functions
  md: Update checkpoint of resync/recovery based on time.
  md:Add place to update ->recovery_cp.
  md.c: re-indent various 'switch' statements.
  md: close race between removing and adding a device.
  md: removed unused variable in calc_sb_1_csm.

11 files changed, 631 insertions, 26 deletions

diff --git a/lib/raid6/Makefile b/lib/raid6/Makefile
index de06dfe165b8..9f7c184725d7 100644
--- a/lib/raid6/Makefile
+++ b/lib/raid6/Makefile
@@ -1,8 +1,11 @@
 obj-$(CONFIG_RAID6_PQ)  += raid6_pq.o
 
-raid6_pq-y      += algos.o recov.o recov_ssse3.o tables.o int1.o int2.o int4.o \
-                   int8.o int16.o int32.o altivec1.o altivec2.o altivec4.o \
-                   altivec8.o mmx.o sse1.o sse2.o
+raid6_pq-y      += algos.o recov.o tables.o int1.o int2.o int4.o \
+                   int8.o int16.o int32.o
+
+raid6_pq-$(CONFIG_X86) += recov_ssse3.o recov_avx2.o mmx.o sse1.o sse2.o avx2.o
+raid6_pq-$(CONFIG_ALTIVEC) += altivec1.o altivec2.o altivec4.o altivec8.o
+
 hostprogs-y     += mktables
 
 quiet_cmd_unroll = UNROLL  $@
diff --git a/lib/raid6/algos.c b/lib/raid6/algos.c
index 589f5f50ad2e..6d7316fe9f30 100644
--- a/lib/raid6/algos.c
+++ b/lib/raid6/algos.c
@@ -45,11 +45,20 @@ const struct raid6_calls * const raid6_algos[] = {
         &raid6_sse1x2,
         &raid6_sse2x1,
         &raid6_sse2x2,
+#ifdef CONFIG_AS_AVX2
+        &raid6_avx2x1,
+        &raid6_avx2x2,
+#endif
 #endif
 #if defined(__x86_64__) && !defined(__arch_um__)
         &raid6_sse2x1,
         &raid6_sse2x2,
         &raid6_sse2x4,
+#ifdef CONFIG_AS_AVX2
+        &raid6_avx2x1,
+        &raid6_avx2x2,
+        &raid6_avx2x4,
+#endif
 #endif
 #ifdef CONFIG_ALTIVEC
         &raid6_altivec1,
@@ -72,6 +81,9 @@ EXPORT_SYMBOL_GPL(raid6_datap_recov);
 
 const struct raid6_recov_calls *const raid6_recov_algos[] = {
 #if (defined(__i386__) || defined(__x86_64__)) && !defined(__arch_um__)
+#ifdef CONFIG_AS_AVX2
+        &raid6_recov_avx2,
+#endif
         &raid6_recov_ssse3,
 #endif
         &raid6_recov_intx1,
diff --git a/lib/raid6/altivec.uc b/lib/raid6/altivec.uc
index b71012b756f4..7cc12b532e95 100644
--- a/lib/raid6/altivec.uc
+++ b/lib/raid6/altivec.uc
@@ -24,13 +24,10 @@
 
 #include <linux/raid/pq.h>
 
-#ifdef CONFIG_ALTIVEC
-
 #include <altivec.h>
 #ifdef __KERNEL__
 # include <asm/cputable.h>
 # include <asm/switch_to.h>
-#endif
 
 /*
  * This is the C data type to use.  We use a vector of
diff --git a/lib/raid6/avx2.c b/lib/raid6/avx2.c
new file mode 100644
index 000000000000..bc3b1dd436eb
--- /dev/null
+++ b/lib/raid6/avx2.c
@@ -0,0 +1,251 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright (C) 2012 Intel Corporation
+ *   Author: Yuanhan Liu <yuanhan.liu@linux.intel.com>
+ *
+ *   Based on sse2.c: Copyright 2002 H. Peter Anvin - All Rights Reserved
+ *
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
+ *   Boston MA 02111-1307, USA; either version 2 of the License, or
+ *   (at your option) any later version; incorporated herein by reference.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * AVX2 implementation of RAID-6 syndrome functions
+ *
+ */
+
+#ifdef CONFIG_AS_AVX2
+
+#include <linux/raid/pq.h>
+#include "x86.h"
+
+static const struct raid6_avx2_constants {
+        u64 x1d[4];
+} raid6_avx2_constants __aligned(32) = {
+        { 0x1d1d1d1d1d1d1d1dULL, 0x1d1d1d1d1d1d1d1dULL,
+          0x1d1d1d1d1d1d1d1dULL, 0x1d1d1d1d1d1d1d1dULL,},
+};
+
+static int raid6_have_avx2(void)
+{
+        return boot_cpu_has(X86_FEATURE_AVX2) && boot_cpu_has(X86_FEATURE_AVX);
+}
+
+/*
+ * Plain AVX2 implementation
+ */
+static void raid6_avx21_gen_syndrome(int disks, size_t bytes, void **ptrs)
+{
+        u8 **dptr = (u8 **)ptrs;
+        u8 *p, *q;
+        int d, z, z0;
+
+        z0 = disks - 3;         /* Highest data disk */
+        p = dptr[z0+1];         /* XOR parity */
+        q = dptr[z0+2];         /* RS syndrome */
+
+        kernel_fpu_begin();
+
+        asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0]));
+        asm volatile("vpxor %ymm3,%ymm3,%ymm3");        /* Zero temp */
+
+        for (d = 0; d < bytes; d += 32) {
+                asm volatile("prefetchnta %0" : : "m" (dptr[z0][d]));
+                asm volatile("vmovdqa %0,%%ymm2" : : "m" (dptr[z0][d]));/* P[0] */
+                asm volatile("prefetchnta %0" : : "m" (dptr[z0-1][d]));
+                asm volatile("vmovdqa %ymm2,%ymm4");/* Q[0] */
+                asm volatile("vmovdqa %0,%%ymm6" : : "m" (dptr[z0-1][d]));
+                for (z = z0-2; z >= 0; z--) {
+                        asm volatile("prefetchnta %0" : : "m" (dptr[z][d]));
+                        asm volatile("vpcmpgtb %ymm4,%ymm3,%ymm5");
+                        asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
+                        asm volatile("vpand %ymm0,%ymm5,%ymm5");
+                        asm volatile("vpxor %ymm5,%ymm4,%ymm4");
+                        asm volatile("vpxor %ymm6,%ymm2,%ymm2");
+                        asm volatile("vpxor %ymm6,%ymm4,%ymm4");
+                        asm volatile("vmovdqa %0,%%ymm6" : : "m" (dptr[z][d]));
+                }
+                asm volatile("vpcmpgtb %ymm4,%ymm3,%ymm5");
+                asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
+                asm volatile("vpand %ymm0,%ymm5,%ymm5");
+                asm volatile("vpxor %ymm5,%ymm4,%ymm4");
+                asm volatile("vpxor %ymm6,%ymm2,%ymm2");
+                asm volatile("vpxor %ymm6,%ymm4,%ymm4");
+
+                asm volatile("vmovntdq %%ymm2,%0" : "=m" (p[d]));
+                asm volatile("vpxor %ymm2,%ymm2,%ymm2");
+                asm volatile("vmovntdq %%ymm4,%0" : "=m" (q[d]));
+                asm volatile("vpxor %ymm4,%ymm4,%ymm4");
+        }
+
+        asm volatile("sfence" : : : "memory");
+        kernel_fpu_end();
+}
+
+const struct raid6_calls raid6_avx2x1 = {
+        raid6_avx21_gen_syndrome,
+        raid6_have_avx2,
+        "avx2x1",
+        1                       /* Has cache hints */
+};
+
+/*
+ * Unrolled-by-2 AVX2 implementation
+ */
+static void raid6_avx22_gen_syndrome(int disks, size_t bytes, void **ptrs)
+{
+        u8 **dptr = (u8 **)ptrs;
+        u8 *p, *q;
+        int d, z, z0;
+
+        z0 = disks - 3;         /* Highest data disk */
+        p = dptr[z0+1];         /* XOR parity */
+        q = dptr[z0+2];         /* RS syndrome */
+
+        kernel_fpu_begin();
+
+        asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0]));
+        asm volatile("vpxor %ymm1,%ymm1,%ymm1"); /* Zero temp */
+
+        /* We uniformly assume a single prefetch covers at least 32 bytes */
+        for (d = 0; d < bytes; d += 64) {
+                asm volatile("prefetchnta %0" : : "m" (dptr[z0][d]));
+                asm volatile("prefetchnta %0" : : "m" (dptr[z0][d+32]));
+                asm volatile("vmovdqa %0,%%ymm2" : : "m" (dptr[z0][d]));/* P[0] */
+                asm volatile("vmovdqa %0,%%ymm3" : : "m" (dptr[z0][d+32]));/* P[1] */
+                asm volatile("vmovdqa %ymm2,%ymm4"); /* Q[0] */
+                asm volatile("vmovdqa %ymm3,%ymm6"); /* Q[1] */
+                for (z = z0-1; z >= 0; z--) {
+                        asm volatile("prefetchnta %0" : : "m" (dptr[z][d]));
+                        asm volatile("prefetchnta %0" : : "m" (dptr[z][d+32]));
+                        asm volatile("vpcmpgtb %ymm4,%ymm1,%ymm5");
+                        asm volatile("vpcmpgtb %ymm6,%ymm1,%ymm7");
+                        asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
+                        asm volatile("vpaddb %ymm6,%ymm6,%ymm6");
+                        asm volatile("vpand %ymm0,%ymm5,%ymm5");
+                        asm volatile("vpand %ymm0,%ymm7,%ymm7");
+                        asm volatile("vpxor %ymm5,%ymm4,%ymm4");
+                        asm volatile("vpxor %ymm7,%ymm6,%ymm6");
+                        asm volatile("vmovdqa %0,%%ymm5" : : "m" (dptr[z][d]));
+                        asm volatile("vmovdqa %0,%%ymm7" : : "m" (dptr[z][d+32]));
+                        asm volatile("vpxor %ymm5,%ymm2,%ymm2");
+                        asm volatile("vpxor %ymm7,%ymm3,%ymm3");
+                        asm volatile("vpxor %ymm5,%ymm4,%ymm4");
+                        asm volatile("vpxor %ymm7,%ymm6,%ymm6");
+                }
+                asm volatile("vmovntdq %%ymm2,%0" : "=m" (p[d]));
+                asm volatile("vmovntdq %%ymm3,%0" : "=m" (p[d+32]));
+                asm volatile("vmovntdq %%ymm4,%0" : "=m" (q[d]));
+                asm volatile("vmovntdq %%ymm6,%0" : "=m" (q[d+32]));
+        }
+
+        asm volatile("sfence" : : : "memory");
+        kernel_fpu_end();
+}
+
+const struct raid6_calls raid6_avx2x2 = {
+        raid6_avx22_gen_syndrome,
+        raid6_have_avx2,
+        "avx2x2",
+        1                       /* Has cache hints */
+};
+
+#ifdef CONFIG_X86_64
+
+/*
+ * Unrolled-by-4 AVX2 implementation
+ */
+static void raid6_avx24_gen_syndrome(int disks, size_t bytes, void **ptrs)
+{
+        u8 **dptr = (u8 **)ptrs;
+        u8 *p, *q;
+        int d, z, z0;
+
+        z0 = disks - 3;         /* Highest data disk */
+        p = dptr[z0+1];         /* XOR parity */
+        q = dptr[z0+2];         /* RS syndrome */
+
+        kernel_fpu_begin();
+
+        asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0]));
+        asm volatile("vpxor %ymm1,%ymm1,%ymm1");        /* Zero temp */
+        asm volatile("vpxor %ymm2,%ymm2,%ymm2");        /* P[0] */
+        asm volatile("vpxor %ymm3,%ymm3,%ymm3");        /* P[1] */
+        asm volatile("vpxor %ymm4,%ymm4,%ymm4");        /* Q[0] */
+        asm volatile("vpxor %ymm6,%ymm6,%ymm6");        /* Q[1] */
+        asm volatile("vpxor %ymm10,%ymm10,%ymm10");     /* P[2] */
+        asm volatile("vpxor %ymm11,%ymm11,%ymm11");     /* P[3] */
+        asm volatile("vpxor %ymm12,%ymm12,%ymm12");     /* Q[2] */
+        asm volatile("vpxor %ymm14,%ymm14,%ymm14");     /* Q[3] */
+
+        for (d = 0; d < bytes; d += 128) {
+                for (z = z0; z >= 0; z--) {
+                        asm volatile("prefetchnta %0" : : "m" (dptr[z][d]));
+                        asm volatile("prefetchnta %0" : : "m" (dptr[z][d+32]));
+                        asm volatile("prefetchnta %0" : : "m" (dptr[z][d+64]));
+                        asm volatile("prefetchnta %0" : : "m" (dptr[z][d+96]));
+                        asm volatile("vpcmpgtb %ymm4,%ymm1,%ymm5");
+                        asm volatile("vpcmpgtb %ymm6,%ymm1,%ymm7");
+                        asm volatile("vpcmpgtb %ymm12,%ymm1,%ymm13");
+                        asm volatile("vpcmpgtb %ymm14,%ymm1,%ymm15");
+                        asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
+                        asm volatile("vpaddb %ymm6,%ymm6,%ymm6");
+                        asm volatile("vpaddb %ymm12,%ymm12,%ymm12");
+                        asm volatile("vpaddb %ymm14,%ymm14,%ymm14");
+                        asm volatile("vpand %ymm0,%ymm5,%ymm5");
+                        asm volatile("vpand %ymm0,%ymm7,%ymm7");
+                        asm volatile("vpand %ymm0,%ymm13,%ymm13");
+                        asm volatile("vpand %ymm0,%ymm15,%ymm15");
+                        asm volatile("vpxor %ymm5,%ymm4,%ymm4");
+                        asm volatile("vpxor %ymm7,%ymm6,%ymm6");
+                        asm volatile("vpxor %ymm13,%ymm12,%ymm12");
+                        asm volatile("vpxor %ymm15,%ymm14,%ymm14");
+                        asm volatile("vmovdqa %0,%%ymm5" : : "m" (dptr[z][d]));
+                        asm volatile("vmovdqa %0,%%ymm7" : : "m" (dptr[z][d+32]));
+                        asm volatile("vmovdqa %0,%%ymm13" : : "m" (dptr[z][d+64]));
+                        asm volatile("vmovdqa %0,%%ymm15" : : "m" (dptr[z][d+96]));
+                        asm volatile("vpxor %ymm5,%ymm2,%ymm2");
+                        asm volatile("vpxor %ymm7,%ymm3,%ymm3");
+                        asm volatile("vpxor %ymm13,%ymm10,%ymm10");
+                        asm volatile("vpxor %ymm15,%ymm11,%ymm11");
+                        asm volatile("vpxor %ymm5,%ymm4,%ymm4");
+                        asm volatile("vpxor %ymm7,%ymm6,%ymm6");
+                        asm volatile("vpxor %ymm13,%ymm12,%ymm12");
+                        asm volatile("vpxor %ymm15,%ymm14,%ymm14");
+                }
+                asm volatile("vmovntdq %%ymm2,%0" : "=m" (p[d]));
+                asm volatile("vpxor %ymm2,%ymm2,%ymm2");
+                asm volatile("vmovntdq %%ymm3,%0" : "=m" (p[d+32]));
+                asm volatile("vpxor %ymm3,%ymm3,%ymm3");
+                asm volatile("vmovntdq %%ymm10,%0" : "=m" (p[d+64]));
+                asm volatile("vpxor %ymm10,%ymm10,%ymm10");
+                asm volatile("vmovntdq %%ymm11,%0" : "=m" (p[d+96]));
+                asm volatile("vpxor %ymm11,%ymm11,%ymm11");
+                asm volatile("vmovntdq %%ymm4,%0" : "=m" (q[d]));
+                asm volatile("vpxor %ymm4,%ymm4,%ymm4");
+                asm volatile("vmovntdq %%ymm6,%0" : "=m" (q[d+32]));
+                asm volatile("vpxor %ymm6,%ymm6,%ymm6");
+                asm volatile("vmovntdq %%ymm12,%0" : "=m" (q[d+64]));
+                asm volatile("vpxor %ymm12,%ymm12,%ymm12");
+                asm volatile("vmovntdq %%ymm14,%0" : "=m" (q[d+96]));
+                asm volatile("vpxor %ymm14,%ymm14,%ymm14");
+        }
+
+        asm volatile("sfence" : : : "memory");
+        kernel_fpu_end();
+}
+
+const struct raid6_calls raid6_avx2x4 = {
+        raid6_avx24_gen_syndrome,
+        raid6_have_avx2,
+        "avx2x4",
+        1                       /* Has cache hints */
+};
+#endif
+
+#endif /* CONFIG_AS_AVX2 */
diff --git a/lib/raid6/mmx.c b/lib/raid6/mmx.c
index 279347f23094..590c71c9e200 100644
--- a/lib/raid6/mmx.c
+++ b/lib/raid6/mmx.c
@@ -16,7 +16,7 @@
  * MMX implementation of RAID-6 syndrome functions
  */
 
-#if defined(__i386__) && !defined(__arch_um__)
+#ifdef CONFIG_X86_32
 
 #include <linux/raid/pq.h>
 #include "x86.h"
diff --git a/lib/raid6/recov_avx2.c b/lib/raid6/recov_avx2.c
new file mode 100644
index 000000000000..e1eea433a493
--- /dev/null
+++ b/lib/raid6/recov_avx2.c
@@ -0,0 +1,323 @@
+/*
+ * Copyright (C) 2012 Intel Corporation
+ * Author: Jim Kukunas <james.t.kukunas@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ */
+
+#if CONFIG_AS_AVX2
+
+#include <linux/raid/pq.h>
+#include "x86.h"
+
+static int raid6_has_avx2(void)
+{
+        return boot_cpu_has(X86_FEATURE_AVX2) &&
+                boot_cpu_has(X86_FEATURE_AVX);
+}
+
+static void raid6_2data_recov_avx2(int disks, size_t bytes, int faila,
+                int failb, void **ptrs)
+{
+        u8 *p, *q, *dp, *dq;
+        const u8 *pbmul;        /* P multiplier table for B data */
+        const u8 *qmul;         /* Q multiplier table (for both) */
+        const u8 x0f = 0x0f;
+
+        p = (u8 *)ptrs[disks-2];
+        q = (u8 *)ptrs[disks-1];
+
+        /* Compute syndrome with zero for the missing data pages
+           Use the dead data pages as temporary storage for
+           delta p and delta q */
+        dp = (u8 *)ptrs[faila];
+        ptrs[faila] = (void *)raid6_empty_zero_page;
+        ptrs[disks-2] = dp;
+        dq = (u8 *)ptrs[failb];
+        ptrs[failb] = (void *)raid6_empty_zero_page;
+        ptrs[disks-1] = dq;
+
+        raid6_call.gen_syndrome(disks, bytes, ptrs);
+
+        /* Restore pointer table */
+        ptrs[faila]   = dp;
+        ptrs[failb]   = dq;
+        ptrs[disks-2] = p;
+        ptrs[disks-1] = q;
+
+        /* Now, pick the proper data tables */
+        pbmul = raid6_vgfmul[raid6_gfexi[failb-faila]];
+        qmul  = raid6_vgfmul[raid6_gfinv[raid6_gfexp[faila] ^
+                raid6_gfexp[failb]]];
+
+        kernel_fpu_begin();
+
+        /* ymm0 = x0f[16] */
+        asm volatile("vpbroadcastb %0, %%ymm7" : : "m" (x0f));
+
+        while (bytes) {
+#ifdef CONFIG_X86_64
+                asm volatile("vmovdqa %0, %%ymm1" : : "m" (q[0]));
+                asm volatile("vmovdqa %0, %%ymm9" : : "m" (q[32]));
+                asm volatile("vmovdqa %0, %%ymm0" : : "m" (p[0]));
+                asm volatile("vmovdqa %0, %%ymm8" : : "m" (p[32]));
+                asm volatile("vpxor %0, %%ymm1, %%ymm1" : : "m" (dq[0]));
+                asm volatile("vpxor %0, %%ymm9, %%ymm9" : : "m" (dq[32]));
+                asm volatile("vpxor %0, %%ymm0, %%ymm0" : : "m" (dp[0]));
+                asm volatile("vpxor %0, %%ymm8, %%ymm8" : : "m" (dp[32]));
+
+                /*
+                 * 1 = dq[0]  ^ q[0]
+                 * 9 = dq[32] ^ q[32]
+                 * 0 = dp[0]  ^ p[0]
+                 * 8 = dp[32] ^ p[32]
+                 */
+
+                asm volatile("vbroadcasti128 %0, %%ymm4" : : "m" (qmul[0]));
+                asm volatile("vbroadcasti128 %0, %%ymm5" : : "m" (qmul[16]));
+
+                asm volatile("vpsraw $4, %ymm1, %ymm3");
+                asm volatile("vpsraw $4, %ymm9, %ymm12");
+                asm volatile("vpand %ymm7, %ymm1, %ymm1");
+                asm volatile("vpand %ymm7, %ymm9, %ymm9");
+                asm volatile("vpand %ymm7, %ymm3, %ymm3");
+                asm volatile("vpand %ymm7, %ymm12, %ymm12");
+                asm volatile("vpshufb %ymm9, %ymm4, %ymm14");
+                asm volatile("vpshufb %ymm1, %ymm4, %ymm4");
+                asm volatile("vpshufb %ymm12, %ymm5, %ymm15");
+                asm volatile("vpshufb %ymm3, %ymm5, %ymm5");
+                asm volatile("vpxor %ymm14, %ymm15, %ymm15");
+                asm volatile("vpxor %ymm4, %ymm5, %ymm5");
+
+                /*
+                 * 5 = qx[0]
+                 * 15 = qx[32]
+                 */
+
+                asm volatile("vbroadcasti128 %0, %%ymm4" : : "m" (pbmul[0]));
+                asm volatile("vbroadcasti128 %0, %%ymm1" : : "m" (pbmul[16]));
+                asm volatile("vpsraw $4, %ymm0, %ymm2");
+                asm volatile("vpsraw $4, %ymm8, %ymm6");
+                asm volatile("vpand %ymm7, %ymm0, %ymm3");
+                asm volatile("vpand %ymm7, %ymm8, %ymm14");
+                asm volatile("vpand %ymm7, %ymm2, %ymm2");
+                asm volatile("vpand %ymm7, %ymm6, %ymm6");
+                asm volatile("vpshufb %ymm14, %ymm4, %ymm12");
+                asm volatile("vpshufb %ymm3, %ymm4, %ymm4");
+                asm volatile("vpshufb %ymm6, %ymm1, %ymm13");
+                asm volatile("vpshufb %ymm2, %ymm1, %ymm1");
+                asm volatile("vpxor %ymm4, %ymm1, %ymm1");
+                asm volatile("vpxor %ymm12, %ymm13, %ymm13");
+
+                /*
+                 * 1  = pbmul[px[0]]
+                 * 13 = pbmul[px[32]]
+                 */
+                asm volatile("vpxor %ymm5, %ymm1, %ymm1");
+                asm volatile("vpxor %ymm15, %ymm13, %ymm13");
+
+                /*
+                 * 1 = db = DQ
+                 * 13 = db[32] = DQ[32]
+                 */
+                asm volatile("vmovdqa %%ymm1, %0" : "=m" (dq[0]));
+                asm volatile("vmovdqa %%ymm13,%0" : "=m" (dq[32]));
+                asm volatile("vpxor %ymm1, %ymm0, %ymm0");
+                asm volatile("vpxor %ymm13, %ymm8, %ymm8");
+
+                asm volatile("vmovdqa %%ymm0, %0" : "=m" (dp[0]));
+                asm volatile("vmovdqa %%ymm8, %0" : "=m" (dp[32]));
+
+                bytes -= 64;
+                p += 64;
+                q += 64;
+                dp += 64;
+                dq += 64;
+#else
+                asm volatile("vmovdqa %0, %%ymm1" : : "m" (*q));
+                asm volatile("vmovdqa %0, %%ymm0" : : "m" (*p));
+                asm volatile("vpxor %0, %%ymm1, %%ymm1" : : "m" (*dq));
+                asm volatile("vpxor %0, %%ymm0, %%ymm0" : : "m" (*dp));
+
+                /* 1 = dq ^ q;  0 = dp ^ p */
+
+                asm volatile("vbroadcasti128 %0, %%ymm4" : : "m" (qmul[0]));
+                asm volatile("vbroadcasti128 %0, %%ymm5" : : "m" (qmul[16]));
+
+                /*
+                 * 1 = dq ^ q
+                 * 3 = dq ^ p >> 4
+                 */
+                asm volatile("vpsraw $4, %ymm1, %ymm3");
+                asm volatile("vpand %ymm7, %ymm1, %ymm1");
+                asm volatile("vpand %ymm7, %ymm3, %ymm3");
+                asm volatile("vpshufb %ymm1, %ymm4, %ymm4");
+                asm volatile("vpshufb %ymm3, %ymm5, %ymm5");
+                asm volatile("vpxor %ymm4, %ymm5, %ymm5");
+
+                /* 5 = qx */
+
+                asm volatile("vbroadcasti128 %0, %%ymm4" : : "m" (pbmul[0]));
+                asm volatile("vbroadcasti128 %0, %%ymm1" : : "m" (pbmul[16]));
+
+                asm volatile("vpsraw $4, %ymm0, %ymm2");
+                asm volatile("vpand %ymm7, %ymm0, %ymm3");
+                asm volatile("vpand %ymm7, %ymm2, %ymm2");
+                asm volatile("vpshufb %ymm3, %ymm4, %ymm4");
+                asm volatile("vpshufb %ymm2, %ymm1, %ymm1");
+                asm volatile("vpxor %ymm4, %ymm1, %ymm1");
+
+                /* 1 = pbmul[px] */
+                asm volatile("vpxor %ymm5, %ymm1, %ymm1");
+                /* 1 = db = DQ */
+                asm volatile("vmovdqa %%ymm1, %0" : "=m" (dq[0]));
+
+                asm volatile("vpxor %ymm1, %ymm0, %ymm0");
+                asm volatile("vmovdqa %%ymm0, %0" : "=m" (dp[0]));
+
+                bytes -= 32;
+                p += 32;
+                q += 32;
+                dp += 32;
+                dq += 32;
+#endif
+        }
+
+        kernel_fpu_end();
+}
+
+static void raid6_datap_recov_avx2(int disks, size_t bytes, int faila,
+                void **ptrs)
+{
+        u8 *p, *q, *dq;
+        const u8 *qmul;         /* Q multiplier table */
+        const u8 x0f = 0x0f;
+
+        p = (u8 *)ptrs[disks-2];
+        q = (u8 *)ptrs[disks-1];
+
+        /* Compute syndrome with zero for the missing data page
+           Use the dead data page as temporary storage for delta q */
+        dq = (u8 *)ptrs[faila];
+        ptrs[faila] = (void *)raid6_empty_zero_page;
+        ptrs[disks-1] = dq;
+
+        raid6_call.gen_syndrome(disks, bytes, ptrs);
+
+        /* Restore pointer table */
+        ptrs[faila]   = dq;
+        ptrs[disks-1] = q;
+
+        /* Now, pick the proper data tables */
+        qmul  = raid6_vgfmul[raid6_gfinv[raid6_gfexp[faila]]];
+
+        kernel_fpu_begin();
+
+        asm volatile("vpbroadcastb %0, %%ymm7" : : "m" (x0f));
+
+        while (bytes) {
+#ifdef CONFIG_X86_64
+                asm volatile("vmovdqa %0, %%ymm3" : : "m" (dq[0]));
+                asm volatile("vmovdqa %0, %%ymm8" : : "m" (dq[32]));
+                asm volatile("vpxor %0, %%ymm3, %%ymm3" : : "m" (q[0]));
+                asm volatile("vpxor %0, %%ymm8, %%ymm8" : : "m" (q[32]));
+
+                /*
+                 * 3 = q[0] ^ dq[0]
+                 * 8 = q[32] ^ dq[32]
+                 */
+                asm volatile("vbroadcasti128 %0, %%ymm0" : : "m" (qmul[0]));
+                asm volatile("vmovapd %ymm0, %ymm13");
+                asm volatile("vbroadcasti128 %0, %%ymm1" : : "m" (qmul[16]));
+                asm volatile("vmovapd %ymm1, %ymm14");
+
+                asm volatile("vpsraw $4, %ymm3, %ymm6");
+                asm volatile("vpsraw $4, %ymm8, %ymm12");
+                asm volatile("vpand %ymm7, %ymm3, %ymm3");
+                asm volatile("vpand %ymm7, %ymm8, %ymm8");
+                asm volatile("vpand %ymm7, %ymm6, %ymm6");
+                asm volatile("vpand %ymm7, %ymm12, %ymm12");
+                asm volatile("vpshufb %ymm3, %ymm0, %ymm0");
+                asm volatile("vpshufb %ymm8, %ymm13, %ymm13");
+                asm volatile("vpshufb %ymm6, %ymm1, %ymm1");
+                asm volatile("vpshufb %ymm12, %ymm14, %ymm14");
+                asm volatile("vpxor %ymm0, %ymm1, %ymm1");
+                asm volatile("vpxor %ymm13, %ymm14, %ymm14");
+
+                /*
+                 * 1  = qmul[q[0]  ^ dq[0]]
+                 * 14 = qmul[q[32] ^ dq[32]]
+                 */
+                asm volatile("vmovdqa %0, %%ymm2" : : "m" (p[0]));
+                asm volatile("vmovdqa %0, %%ymm12" : : "m" (p[32]));
+                asm volatile("vpxor %ymm1, %ymm2, %ymm2");
+                asm volatile("vpxor %ymm14, %ymm12, %ymm12");
+
+                /*
+                 * 2  = p[0]  ^ qmul[q[0]  ^ dq[0]]
+                 * 12 = p[32] ^ qmul[q[32] ^ dq[32]]
+                 */
+
+                asm volatile("vmovdqa %%ymm1, %0" : "=m" (dq[0]));
+                asm volatile("vmovdqa %%ymm14, %0" : "=m" (dq[32]));
+                asm volatile("vmovdqa %%ymm2, %0" : "=m" (p[0]));
+                asm volatile("vmovdqa %%ymm12,%0" : "=m" (p[32]));
+
+                bytes -= 64;
+                p += 64;
+                q += 64;
+                dq += 64;
+#else
+                asm volatile("vmovdqa %0, %%ymm3" : : "m" (dq[0]));
+                asm volatile("vpxor %0, %%ymm3, %%ymm3" : : "m" (q[0]));
+
+                /* 3 = q ^ dq */
+
+                asm volatile("vbroadcasti128 %0, %%ymm0" : : "m" (qmul[0]));
+                asm volatile("vbroadcasti128 %0, %%ymm1" : : "m" (qmul[16]));
+
+                asm volatile("vpsraw $4, %ymm3, %ymm6");
+                asm volatile("vpand %ymm7, %ymm3, %ymm3");
+                asm volatile("vpand %ymm7, %ymm6, %ymm6");
+                asm volatile("vpshufb %ymm3, %ymm0, %ymm0");
+                asm volatile("vpshufb %ymm6, %ymm1, %ymm1");
+                asm volatile("vpxor %ymm0, %ymm1, %ymm1");
+
+                /* 1 = qmul[q ^ dq] */
+
+                asm volatile("vmovdqa %0, %%ymm2" : : "m" (p[0]));
+                asm volatile("vpxor %ymm1, %ymm2, %ymm2");
+
+                /* 2 = p ^ qmul[q ^ dq] */
+
+                asm volatile("vmovdqa %%ymm1, %0" : "=m" (dq[0]));
+                asm volatile("vmovdqa %%ymm2, %0" : "=m" (p[0]));
+
+                bytes -= 32;
+                p += 32;
+                q += 32;
+                dq += 32;
+#endif
+        }
+
+        kernel_fpu_end();
+}
+
+const struct raid6_recov_calls raid6_recov_avx2 = {
+        .data2 = raid6_2data_recov_avx2,
+        .datap = raid6_datap_recov_avx2,
+        .valid = raid6_has_avx2,
+#ifdef CONFIG_X86_64
+        .name = "avx2x2",
+#else
+        .name = "avx2x1",
+#endif
+        .priority = 2,
+};
+
+#else
+#warning "your version of binutils lacks AVX2 support"
+#endif
diff --git a/lib/raid6/recov_ssse3.c b/lib/raid6/recov_ssse3.c
index ecb710c0b4d9..a9168328f03b 100644
--- a/lib/raid6/recov_ssse3.c
+++ b/lib/raid6/recov_ssse3.c
@@ -7,8 +7,6 @@
  * of the License.
  */
 
-#if (defined(__i386__) || defined(__x86_64__)) && !defined(__arch_um__)
-
 #include <linux/raid/pq.h>
 #include "x86.h"
 
@@ -332,5 +330,3 @@ const struct raid6_recov_calls raid6_recov_ssse3 = {
 #endif
         .priority = 1,
 };
-
-#endif
diff --git a/lib/raid6/sse1.c b/lib/raid6/sse1.c
index 10dd91948c07..f76297139445 100644
--- a/lib/raid6/sse1.c
+++ b/lib/raid6/sse1.c
@@ -21,7 +21,7 @@
  * worthwhile as a separate implementation.
  */
 
-#if defined(__i386__) && !defined(__arch_um__)
+#ifdef CONFIG_X86_32
 
 #include <linux/raid/pq.h>
 #include "x86.h"
diff --git a/lib/raid6/sse2.c b/lib/raid6/sse2.c
index bc2d57daa589..85b82c85f28e 100644
--- a/lib/raid6/sse2.c
+++ b/lib/raid6/sse2.c
@@ -17,8 +17,6 @@
  *
  */
 
-#if (defined(__i386__) || defined(__x86_64__)) && !defined(__arch_um__)
-
 #include <linux/raid/pq.h>
 #include "x86.h"
 
@@ -159,9 +157,7 @@ const struct raid6_calls raid6_sse2x2 = {
         1                       /* Has cache hints */
 };
 
-#endif
-
-#if defined(__x86_64__) && !defined(__arch_um__)
+#ifdef CONFIG_X86_64
 
 /*
  * Unrolled-by-4 SSE2 implementation
@@ -259,4 +255,4 @@ const struct raid6_calls raid6_sse2x4 = {
         1                       /* Has cache hints */
 };
 
-#endif
+#endif /* CONFIG_X86_64 */
diff --git a/lib/raid6/test/Makefile b/lib/raid6/test/Makefile
index c76151d94764..087332dbf8aa 100644
--- a/lib/raid6/test/Makefile
+++ b/lib/raid6/test/Makefile
@@ -10,6 +10,31 @@ LD	 = ld
 AWK      = awk -f
 AR       = ar
 RANLIB   = ranlib
+OBJS     = int1.o int2.o int4.o int8.o int16.o int32.o recov.o algos.o tables.o
+
+ARCH := $(shell uname -m 2>/dev/null | sed -e /s/i.86/i386/)
+ifeq ($(ARCH),i386)
+        CFLAGS += -DCONFIG_X86_32
+        IS_X86 = yes
+endif
+ifeq ($(ARCH),x86_64)
+        CFLAGS += -DCONFIG_X86_64
+        IS_X86 = yes
+endif
+
+ifeq ($(IS_X86),yes)
+        OBJS   += mmx.o sse1.o sse2.o avx2.o recov_ssse3.o recov_avx2.o
+        CFLAGS += $(shell echo "vpbroadcastb %xmm0, %ymm1" |    \
+                    gcc -c -x assembler - >&/dev/null &&        \
+                    rm ./-.o && echo -DCONFIG_AS_AVX2=1)
+else
+        HAS_ALTIVEC := $(shell echo -e '\#include <altivec.h>\nvector int a;' |\
+                         gcc -c -x c - >&/dev/null && \
+                         rm ./-.o && echo yes)
+        ifeq ($(HAS_ALTIVEC),yes)
+                OBJS += altivec1.o altivec2.o altivec4.o altivec8.o
+        endif
+endif
 
 .c.o:
         $(CC) $(CFLAGS) -c -o $@ $<
@@ -22,9 +47,7 @@ RANLIB	 = ranlib
 
 all:    raid6.a raid6test
 
-raid6.a: int1.o int2.o int4.o int8.o int16.o int32.o mmx.o sse1.o sse2.o \
-         altivec1.o altivec2.o altivec4.o altivec8.o recov.o recov_ssse3.o algos.o \
-         tables.o
+raid6.a: $(OBJS)
          rm -f $@
          $(AR) cq $@ $^
          $(RANLIB) $@
diff --git a/lib/raid6/x86.h b/lib/raid6/x86.h
index d55d63232c55..b7595484a815 100644
--- a/lib/raid6/x86.h
+++ b/lib/raid6/x86.h
@@ -45,19 +45,23 @@ static inline void kernel_fpu_end(void)
 #define X86_FEATURE_XMM3        (4*32+ 0) /* "pni" SSE-3 */
 #define X86_FEATURE_SSSE3       (4*32+ 9) /* Supplemental SSE-3 */
 #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
+#define X86_FEATURE_AVX2        (9*32+ 5) /* AVX2 instructions */
 #define X86_FEATURE_MMXEXT      (1*32+22) /* AMD MMX extensions */
 
 /* Should work well enough on modern CPUs for testing */
 static inline int boot_cpu_has(int flag)
 {
-        u32 eax = (flag & 0x20) ? 0x80000001 : 1;
-        u32 ecx, edx;
+        u32 eax, ebx, ecx, edx;
+
+        eax = (flag & 0x100) ? 7 :
+                (flag & 0x20) ? 0x80000001 : 1;
+        ecx = 0;
 
         asm volatile("cpuid"
-                     : "+a" (eax), "=d" (edx), "=c" (ecx)
-                     : : "ebx");
+                     : "+a" (eax), "=b" (ebx), "=d" (edx), "+c" (ecx));
 
-        return ((flag & 0x80 ? ecx : edx) >> (flag & 31)) & 1;
+        return ((flag & 0x100 ? ebx :
+                (flag & 0x80) ? ecx : edx) >> (flag & 31)) & 1;
 }
 
 #endif /* ndef __KERNEL__ */