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authorShan Hai <haishan.bai@gmail.com>2011-08-31 23:32:03 -0400
committerIngo Molnar <mingo@elte.hu>2011-09-13 05:12:22 -0400
commitf59ca05871a055a73f8e626f2d868f0da248e22c (patch)
treedd077b2cbbf92f9dbda925d8bff9e567f5a56b3f /lib
parent3b8f40481513a7b6123def5a02db4cff96ae2198 (diff)
locking, lib/atomic64: Annotate atomic64_lock::lock as raw
The spinlock protected atomic64 operations must be irq safe as they are used in hard interrupt context and cannot be preempted on -rt: NIP [c068b218] rt_spin_lock_slowlock+0x78/0x3a8 LR [c068b1e0] rt_spin_lock_slowlock+0x40/0x3a8 Call Trace: [eb459b90] [c068b1e0] rt_spin_lock_slowlock+0x40/0x3a8 (unreliable) [eb459c20] [c068bdb0] rt_spin_lock+0x40/0x98 [eb459c40] [c03d2a14] atomic64_read+0x48/0x84 [eb459c60] [c001aaf4] perf_event_interrupt+0xec/0x28c [eb459d10] [c0010138] performance_monitor_exception+0x7c/0x150 [eb459d30] [c0014170] ret_from_except_full+0x0/0x4c So annotate it. In mainline this change documents the low level nature of the lock - otherwise there's no functional difference. Lockdep and Sparse checking will work as usual. Signed-off-by: Shan Hai <haishan.bai@gmail.com> Reviewed-by: Yong Zhang <yong.zhang0@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'lib')
-rw-r--r--lib/atomic64.c44
1 files changed, 22 insertions, 22 deletions
diff --git a/lib/atomic64.c b/lib/atomic64.c
index e12ae0dd08a8..82b33134e141 100644
--- a/lib/atomic64.c
+++ b/lib/atomic64.c
@@ -29,7 +29,7 @@
29 * Ensure each lock is in a separate cacheline. 29 * Ensure each lock is in a separate cacheline.
30 */ 30 */
31static union { 31static union {
32 spinlock_t lock; 32 raw_spinlock_t lock;
33 char pad[L1_CACHE_BYTES]; 33 char pad[L1_CACHE_BYTES];
34} atomic64_lock[NR_LOCKS] __cacheline_aligned_in_smp; 34} atomic64_lock[NR_LOCKS] __cacheline_aligned_in_smp;
35 35
@@ -48,9 +48,9 @@ long long atomic64_read(const atomic64_t *v)
48 spinlock_t *lock = lock_addr(v); 48 spinlock_t *lock = lock_addr(v);
49 long long val; 49 long long val;
50 50
51 spin_lock_irqsave(lock, flags); 51 raw_spin_lock_irqsave(lock, flags);
52 val = v->counter; 52 val = v->counter;
53 spin_unlock_irqrestore(lock, flags); 53 raw_spin_unlock_irqrestore(lock, flags);
54 return val; 54 return val;
55} 55}
56EXPORT_SYMBOL(atomic64_read); 56EXPORT_SYMBOL(atomic64_read);
@@ -60,9 +60,9 @@ void atomic64_set(atomic64_t *v, long long i)
60 unsigned long flags; 60 unsigned long flags;
61 spinlock_t *lock = lock_addr(v); 61 spinlock_t *lock = lock_addr(v);
62 62
63 spin_lock_irqsave(lock, flags); 63 raw_spin_lock_irqsave(lock, flags);
64 v->counter = i; 64 v->counter = i;
65 spin_unlock_irqrestore(lock, flags); 65 raw_spin_unlock_irqrestore(lock, flags);
66} 66}
67EXPORT_SYMBOL(atomic64_set); 67EXPORT_SYMBOL(atomic64_set);
68 68
@@ -71,9 +71,9 @@ void atomic64_add(long long a, atomic64_t *v)
71 unsigned long flags; 71 unsigned long flags;
72 spinlock_t *lock = lock_addr(v); 72 spinlock_t *lock = lock_addr(v);
73 73
74 spin_lock_irqsave(lock, flags); 74 raw_spin_lock_irqsave(lock, flags);
75 v->counter += a; 75 v->counter += a;
76 spin_unlock_irqrestore(lock, flags); 76 raw_spin_unlock_irqrestore(lock, flags);
77} 77}
78EXPORT_SYMBOL(atomic64_add); 78EXPORT_SYMBOL(atomic64_add);
79 79
@@ -83,9 +83,9 @@ long long atomic64_add_return(long long a, atomic64_t *v)
83 spinlock_t *lock = lock_addr(v); 83 spinlock_t *lock = lock_addr(v);
84 long long val; 84 long long val;
85 85
86 spin_lock_irqsave(lock, flags); 86 raw_spin_lock_irqsave(lock, flags);
87 val = v->counter += a; 87 val = v->counter += a;
88 spin_unlock_irqrestore(lock, flags); 88 raw_spin_unlock_irqrestore(lock, flags);
89 return val; 89 return val;
90} 90}
91EXPORT_SYMBOL(atomic64_add_return); 91EXPORT_SYMBOL(atomic64_add_return);
@@ -95,9 +95,9 @@ void atomic64_sub(long long a, atomic64_t *v)
95 unsigned long flags; 95 unsigned long flags;
96 spinlock_t *lock = lock_addr(v); 96 spinlock_t *lock = lock_addr(v);
97 97
98 spin_lock_irqsave(lock, flags); 98 raw_spin_lock_irqsave(lock, flags);
99 v->counter -= a; 99 v->counter -= a;
100 spin_unlock_irqrestore(lock, flags); 100 raw_spin_unlock_irqrestore(lock, flags);
101} 101}
102EXPORT_SYMBOL(atomic64_sub); 102EXPORT_SYMBOL(atomic64_sub);
103 103
@@ -107,9 +107,9 @@ long long atomic64_sub_return(long long a, atomic64_t *v)
107 spinlock_t *lock = lock_addr(v); 107 spinlock_t *lock = lock_addr(v);
108 long long val; 108 long long val;
109 109
110 spin_lock_irqsave(lock, flags); 110 raw_spin_lock_irqsave(lock, flags);
111 val = v->counter -= a; 111 val = v->counter -= a;
112 spin_unlock_irqrestore(lock, flags); 112 raw_spin_unlock_irqrestore(lock, flags);
113 return val; 113 return val;
114} 114}
115EXPORT_SYMBOL(atomic64_sub_return); 115EXPORT_SYMBOL(atomic64_sub_return);
@@ -120,11 +120,11 @@ long long atomic64_dec_if_positive(atomic64_t *v)
120 spinlock_t *lock = lock_addr(v); 120 spinlock_t *lock = lock_addr(v);
121 long long val; 121 long long val;
122 122
123 spin_lock_irqsave(lock, flags); 123 raw_spin_lock_irqsave(lock, flags);
124 val = v->counter - 1; 124 val = v->counter - 1;
125 if (val >= 0) 125 if (val >= 0)
126 v->counter = val; 126 v->counter = val;
127 spin_unlock_irqrestore(lock, flags); 127 raw_spin_unlock_irqrestore(lock, flags);
128 return val; 128 return val;
129} 129}
130EXPORT_SYMBOL(atomic64_dec_if_positive); 130EXPORT_SYMBOL(atomic64_dec_if_positive);
@@ -135,11 +135,11 @@ long long atomic64_cmpxchg(atomic64_t *v, long long o, long long n)
135 spinlock_t *lock = lock_addr(v); 135 spinlock_t *lock = lock_addr(v);
136 long long val; 136 long long val;
137 137
138 spin_lock_irqsave(lock, flags); 138 raw_spin_lock_irqsave(lock, flags);
139 val = v->counter; 139 val = v->counter;
140 if (val == o) 140 if (val == o)
141 v->counter = n; 141 v->counter = n;
142 spin_unlock_irqrestore(lock, flags); 142 raw_spin_unlock_irqrestore(lock, flags);
143 return val; 143 return val;
144} 144}
145EXPORT_SYMBOL(atomic64_cmpxchg); 145EXPORT_SYMBOL(atomic64_cmpxchg);
@@ -150,10 +150,10 @@ long long atomic64_xchg(atomic64_t *v, long long new)
150 spinlock_t *lock = lock_addr(v); 150 spinlock_t *lock = lock_addr(v);
151 long long val; 151 long long val;
152 152
153 spin_lock_irqsave(lock, flags); 153 raw_spin_lock_irqsave(lock, flags);
154 val = v->counter; 154 val = v->counter;
155 v->counter = new; 155 v->counter = new;
156 spin_unlock_irqrestore(lock, flags); 156 raw_spin_unlock_irqrestore(lock, flags);
157 return val; 157 return val;
158} 158}
159EXPORT_SYMBOL(atomic64_xchg); 159EXPORT_SYMBOL(atomic64_xchg);
@@ -164,12 +164,12 @@ int atomic64_add_unless(atomic64_t *v, long long a, long long u)
164 spinlock_t *lock = lock_addr(v); 164 spinlock_t *lock = lock_addr(v);
165 int ret = 0; 165 int ret = 0;
166 166
167 spin_lock_irqsave(lock, flags); 167 raw_spin_lock_irqsave(lock, flags);
168 if (v->counter != u) { 168 if (v->counter != u) {
169 v->counter += a; 169 v->counter += a;
170 ret = 1; 170 ret = 1;
171 } 171 }
172 spin_unlock_irqrestore(lock, flags); 172 raw_spin_unlock_irqrestore(lock, flags);
173 return ret; 173 return ret;
174} 174}
175EXPORT_SYMBOL(atomic64_add_unless); 175EXPORT_SYMBOL(atomic64_add_unless);
@@ -179,7 +179,7 @@ static int init_atomic64_lock(void)
179 int i; 179 int i;
180 180
181 for (i = 0; i < NR_LOCKS; ++i) 181 for (i = 0; i < NR_LOCKS; ++i)
182 spin_lock_init(&atomic64_lock[i].lock); 182 raw_spin_lock_init(&atomic64_lock[i].lock);
183 return 0; 183 return 0;
184} 184}
185 185