litmus-rt.git - The LITMUS^RT kernel.

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author	Kevin Wells <kevin.wells@nxp.com>	2009-11-11 18:23:00 -0500
committer	Ben Dooks <ben-linux@fluff.org>	2009-11-19 19:25:42 -0500
commit	4ced24c8973f79113444d1e00ee8bd9e74fbf43e (patch)
tree	aeab7b72d009b15f918b0dfeb17bfc5a1603b071 /lib/ts_kmp.c
parent	b2f125bcf5eac41a6d74f75ac573b77753213b74 (diff)

i2c: i2c-pnx: Made buf type unsigned to prevent sign extension

Made buf type unsigned to prevent sign extension Signed-off-by: Kevin Wells <kevin.wells@nxp.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>

Diffstat (limited to 'lib/ts_kmp.c')

0 files changed, 0 insertions, 0 deletions

/* * An SPI driver for the Philips PCF2123 RTC * Copyright 2009 Cyber Switching, Inc. * * Author: Chris Verges <chrisv@cyberswitching.com> * Maintainers: http://www.cyberswitching.com * * based on the RS5C348 driver in this same directory. * * Thanks to Christian Pellegrin <chripell@fsfe.org> for * the sysfs contributions to this driver. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * Please note that the CS is active high, so platform data * should look something like: * * static struct spi_board_info ek_spi_devices[] = { * ... * { * .modalias = "rtc-pcf2123", * .chip_select = 1, * .controller_data = (void *)AT91_PIN_PA10, * .max_speed_hz = 1000 * 1000, * .mode = SPI_CS_HIGH, * .bus_num = 0, * }, * ... *}; * */ #include <linux/bcd.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/errno.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/of.h> #include <linux/string.h> #include <linux/slab.h> #include <linux/rtc.h> #include <linux/spi/spi.h> #include <linux/module.h> #include <linux/sysfs.h> /* REGISTERS */ #define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */ #define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */ #define PCF2123_REG_SC (0x02) /* datetime */ #define PCF2123_REG_MN (0x03) #define PCF2123_REG_HR (0x04) #define PCF2123_REG_DM (0x05) #define PCF2123_REG_DW (0x06) #define PCF2123_REG_MO (0x07) #define PCF2123_REG_YR (0x08) #define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */ #define PCF2123_REG_ALRM_HR (0x0a) #define PCF2123_REG_ALRM_DM (0x0b) #define PCF2123_REG_ALRM_DW (0x0c) #define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */ #define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */ #define PCF2123_REG_CTDWN_TMR (0x0f) /* PCF2123_REG_CTRL1 BITS */ #define CTRL1_CLEAR (0) /* Clear */ #define CTRL1_CORR_INT BIT(1) /* Correction irq enable */ #define CTRL1_12_HOUR BIT(2) /* 12 hour time */ #define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */ #define CTRL1_STOP BIT(5) /* Stop the clock */ #define CTRL1_EXT_TEST BIT(7) /* External clock test mode */ /* PCF2123_REG_CTRL2 BITS */ #define CTRL2_TIE BIT(0) /* Countdown timer irq enable */ #define CTRL2_AIE BIT(1) /* Alarm irq enable */ #define CTRL2_TF BIT(2) /* Countdown timer flag */ #define CTRL2_AF BIT(3) /* Alarm flag */ #define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */ #define CTRL2_MSF BIT(5) /* Minute or second irq flag */ #define CTRL2_SI BIT(6) /* Second irq enable */ #define CTRL2_MI BIT(7) /* Minute irq enable */ /* PCF2123_REG_SC BITS */ #define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */ /* PCF2123_REG_ALRM_XX BITS */ #define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */ /* PCF2123_REG_TMR_CLKOUT BITS */ #define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */ #define CD_TMR_64HZ (1) /* 64 Hz countdown timer */ #define CD_TMR_1HZ (2) /* 1 Hz countdown timer */ #define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */ #define CD_TMR_TE BIT(3) /* Countdown timer enable */ /* PCF2123_REG_OFFSET BITS */ #define OFFSET_SIGN_BIT BIT(6) /* 2's complement sign bit */ #define OFFSET_COARSE BIT(7) /* Coarse mode offset */ #define OFFSET_STEP (2170) /* Offset step in parts per billion */ /* READ/WRITE ADDRESS BITS */ #define PCF2123_WRITE BIT(4) #define PCF2123_READ (BIT(4) | BIT(7)) static struct spi_driver pcf2123_driver; struct pcf2123_sysfs_reg { struct device_attribute attr; char name[2]; }; struct pcf2123_plat_data { struct rtc_device *rtc; struct pcf2123_sysfs_reg regs[16]; }; /* * Causes a 30 nanosecond delay to ensure that the PCF2123 chip select * is released properly after an SPI write. This function should be * called after EVERY read/write call over SPI. */ static inline void pcf2123_delay_trec(void) { ndelay(30); } static int pcf2123_read(struct device *dev, u8 reg, u8 *rxbuf, size_t size) { struct spi_device *spi = to_spi_device(dev); int ret; reg |= PCF2123_READ; ret = spi_write_then_read(spi, &reg, 1, rxbuf, size); pcf2123_delay_trec(); return ret; } static int pcf2123_write(struct device *dev, u8 *txbuf, size_t size) { struct spi_device *spi = to_spi_device(dev); int ret; txbuf[0] |= PCF2123_WRITE; ret = spi_write(spi, txbuf, size); pcf2123_delay_trec(); return ret; } static int pcf2123_write_reg(struct device *dev, u8 reg, u8 val) { u8 txbuf[2]; txbuf[0] = reg; txbuf[1] = val; return pcf2123_write(dev, txbuf, sizeof(txbuf)); } static ssize_t pcf2123_show(struct device *dev, struct device_attribute *attr, char *buffer) { struct pcf2123_sysfs_reg *r; u8 rxbuf[1]; unsigned long reg; int ret; r = container_of(attr, struct pcf2123_sysfs_reg, attr); ret = kstrtoul(r->name, 16, &reg); if (ret) return ret; ret = pcf2123_read(dev, reg, rxbuf, 1); if (ret < 0) return -EIO; return sprintf(buffer, "0x%x\n", rxbuf[0]); } static ssize_t pcf2123_store(struct device *dev, struct device_attribute *attr, const char *buffer, size_t count) { struct pcf2123_sysfs_reg *r; unsigned long reg; unsigned long val; int ret; r = container_of(attr, struct pcf2123_sysfs_reg, attr); ret = kstrtoul(r->name, 16, &reg); if (ret) return ret; ret = kstrtoul(buffer, 10, &val); if (ret) return ret; pcf2123_write_reg(dev, reg, val); if (ret < 0) return -EIO; return count; } static int pcf2123_read_offset(struct device *dev, long *offset) { int ret; s8 reg; ret = pcf2123_read(dev, PCF2123_REG_OFFSET, &reg, 1); if (ret < 0) return ret; if (reg & OFFSET_COARSE) reg <<= 1; /* multiply by 2 and sign extend */ else reg |= (reg & OFFSET_SIGN_BIT) << 1; /* sign extend only */ *offset = ((long)reg) * OFFSET_STEP; return 0; } /* * The offset register is a 7 bit signed value with a coarse bit in bit 7. * The main difference between the two is normal offset adjusts the first * second of n minutes every other hour, with 61, 62 and 63 being shoved * into the 60th minute. * The coarse adjustment does the same, but every hour. * the two overlap, with every even normal offset value corresponding * to a coarse offset. Based on this algorithm, it seems that despite the * name, coarse offset is a better fit for overlapping values. */ static int pcf2123_set_offset(struct device *dev, long offset) { s8 reg; if (offset > OFFSET_STEP * 127) reg = 127; else if (offset < OFFSET_STEP * -128) reg = -128; else reg = (s8)((offset + (OFFSET_STEP >> 1)) / OFFSET_STEP); /* choose fine offset only for odd values in the normal range */ if (reg & 1 && reg <= 63 && reg >= -64) { /* Normal offset. Clear the coarse bit */ reg &= ~OFFSET_COARSE; } else { /* Coarse offset. Divide by 2 and set the coarse bit */ reg >>= 1; reg |= OFFSET_COARSE; } return pcf2123_write_reg(dev, PCF2123_REG_OFFSET, reg); } static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm) { u8 rxbuf[7]; int ret; ret = pcf2123_read(dev, PCF2123_REG_SC, rxbuf, sizeof(rxbuf)); if (ret < 0) return ret; if (rxbuf[0] & OSC_HAS_STOPPED) { dev_info(dev, "clock was stopped. Time is not valid\n"); return -EINVAL; } tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F); tm->tm_min = bcd2bin(rxbuf[1] & 0x7F); tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */


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