litmus-rt.git - The LITMUS^RT kernel.

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author	Bob Moore <robert.moore@intel.com>	2012-05-22 04:35:00 -0400
committer	Len Brown <len.brown@intel.com>	2012-06-01 11:51:53 -0400
commit	66be71ff477389ff12c9c43dc6ee176cf8e1dd3a (patch)
tree	23ab26563ea17c99694235009e8126d358f95301 /lib/mpi/mpi-inv.c
parent	bd6f10a5f984e48cb56a39f2698cd58e7a33d56b (diff)

ACPICA: Add FADT error message for GAS BitWidth overflow

Error for possible overflow during conversion from 32-bit legacy register addresses to GAS format. The GAS struct contains a one-byte BitWidth field, meaning that the maximum length of a register is 255 bits. ACPICA BZ 953. https://www.acpica.org/bugzilla/show_bug.cgi?id=953 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>

Diffstat (limited to 'lib/mpi/mpi-inv.c')

0 files changed, 0 insertions, 0 deletions

/* * GPIO driver for Marvell SoCs * * Copyright (C) 2012 Marvell * * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> * Andrew Lunn <andrew@lunn.ch> * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. * * This driver is a fairly straightforward GPIO driver for the * complete family of Marvell EBU SoC platforms (Orion, Dove, * Kirkwood, Discovery, Armada 370/XP). The only complexity of this * driver is the different register layout that exists between the * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP * platforms (MV78200 from the Discovery family and the Armada * XP). Therefore, this driver handles three variants of the GPIO * block: * - the basic variant, called "orion-gpio", with the simplest * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and * non-SMP Discovery systems * - the mv78200 variant for MV78200 Discovery systems. This variant * turns the edge mask and level mask registers into CPU0 edge * mask/level mask registers, and adds CPU1 edge mask/level mask * registers. * - the armadaxp variant for Armada XP systems. This variant keeps * the normal cause/edge mask/level mask registers when the global * interrupts are used, but adds per-CPU cause/edge mask/level mask * registers n a separate memory area for the per-CPU GPIO * interrupts. */ #include <linux/err.h> #include <linux/module.h> #include <linux/gpio.h> #include <linux/irq.h> #include <linux/slab.h> #include <linux/irqdomain.h> #include <linux/io.h> #include <linux/of_irq.h> #include <linux/of_device.h> #include <linux/clk.h> #include <linux/pinctrl/consumer.h> /* * GPIO unit register offsets. */ #define GPIO_OUT_OFF 0x0000 #define GPIO_IO_CONF_OFF 0x0004 #define GPIO_BLINK_EN_OFF 0x0008 #define GPIO_IN_POL_OFF 0x000c #define GPIO_DATA_IN_OFF 0x0010 #define GPIO_EDGE_CAUSE_OFF 0x0014 #define GPIO_EDGE_MASK_OFF 0x0018 #define GPIO_LEVEL_MASK_OFF 0x001c /* The MV78200 has per-CPU registers for edge mask and level mask */ #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) /* The Armada XP has per-CPU registers for interrupt cause, interrupt * mask and interrupt level mask. Those are relative to the * percpu_membase. */ #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 #define MVEBU_MAX_GPIO_PER_BANK 32 struct mvebu_gpio_chip { struct gpio_chip chip; spinlock_t lock; void __iomem *membase; void __iomem *percpu_membase; int irqbase; struct irq_domain *domain; int soc_variant; }; /* * Functions returning addresses of individual registers for a given * GPIO controller. */ static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip) { return mvchip->membase + GPIO_OUT_OFF; } static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip) { return mvchip->membase + GPIO_BLINK_EN_OFF; } static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip) { return mvchip->membase + GPIO_IO_CONF_OFF; } static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip) { return mvchip->membase + GPIO_IN_POL_OFF; } static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip) { return mvchip->membase + GPIO_DATA_IN_OFF; } static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip) { int cpu; switch (mvchip->soc_variant) { case MVEBU_GPIO_SOC_VARIANT_ORION: case MVEBU_GPIO_SOC_VARIANT_MV78200: return mvchip->membase + GPIO_EDGE_CAUSE_OFF; case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: cpu = smp_processor_id(); return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); default: BUG(); } } static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip) { int cpu; switch (mvchip->soc_variant) { case MVEBU_GPIO_SOC_VARIANT_ORION: return mvchip->membase + GPIO_EDGE_MASK_OFF; case MVEBU_GPIO_SOC_VARIANT_MV78200: cpu = smp_processor_id(); return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu); case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: cpu = smp_processor_id(); return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); default: BUG(); } } static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip) { int cpu; switch (mvchip->soc_variant) { case MVEBU_GPIO_SOC_VARIANT_ORION: return mvchip->membase + GPIO_LEVEL_MASK_OFF; case MVEBU_GPIO_SOC_VARIANT_MV78200: cpu = smp_processor_id(); return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu); case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: cpu = smp_processor_id(); return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); default: BUG(); } } /* * Functions implementing the gpio_chip methods */ static int mvebu_gpio_request(struct gpio_chip *chip, unsigned pin) { return pinctrl_request_gpio(chip->base + pin); } static void mvebu_gpio_free(struct gpio_chip *chip, unsigned pin) { pinctrl_free_gpio(chip->base + pin); } static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value) { struct mvebu_gpio_chip *mvchip = container_of(chip, struct mvebu_gpio_chip, chip); unsigned long flags; u32 u; spin_lock_irqsave(&mvchip->lock, flags); u = readl_relaxed(mvebu_gpioreg_out(mvchip)); if (value) u |= 1 << pin; else u &= ~(1 << pin); writel_relaxed(u, mvebu_gpioreg_out(mvchip)); spin_unlock_irqrestore(&mvchip->lock, flags); } static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin) { struct mvebu_gpio_chip *mvchip = container_of(chip, struct mvebu_gpio_chip, chip); u32 u; if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) { u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^ readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); } else { u = readl_relaxed(mvebu_gpioreg_out(mvchip)); } return (u >> pin) & 1; } static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value) { struct mvebu_gpio_chip *mvchip = container_of(chip, struct mvebu_gpio_chip, chip); unsigned long flags; u32 u; spin_lock_irqsave(&mvchip->lock, flags); u = readl_relaxed(mvebu_gpioreg_blink(mvchip)); if (value) u |= 1 << pin; else u &= ~(1 << pin); writel_relaxed(u, mvebu_gpioreg_blink(mvchip)); spin_unlock_irqrestore(&mvchip->lock, flags); } static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin) { struct mvebu_gpio_chip *mvchip = container_of(chip, struct mvebu_gpio_chip, chip); unsigned long flags; int ret; u32 u; /* Check with the pinctrl driver whether this pin is usable as * an input GPIO */ ret = pinctrl_gpio_direction_input(chip->base + pin); if (ret) return ret; spin_lock_irqsave(&mvchip->lock, flags); u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); u |= 1 << pin; writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); spin_unlock_irqrestore(&mvchip->lock, flags); return 0; } static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value) { struct mvebu_gpio_chip *mvchip = container_of(chip, struct mvebu_gpio_chip, chip); unsigned long flags; int ret; u32 u; /* Check with the pinctrl driver whether this pin is usable as * an output GPIO */ ret = pinctrl_gpio_direction_output(chip->base + pin); if (ret) return ret; mvebu_gpio_blink(chip, pin, 0); mvebu_gpio_set(chip, pin, value); spin_lock_irqsave(&mvchip->lock, flags); u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); u &= ~(1 << pin); writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); spin_unlock_irqrestore(&mvchip->lock, flags); return 0; } static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin) { struct mvebu_gpio_chip *mvchip = container_of(chip, struct mvebu_gpio_chip, chip); return irq_create_mapping(mvchip->domain, pin); } /* * Functions implementing the irq_chip methods */ static void mvebu_gpio_irq_ack(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = ~(1 << (d->irq - gc->irq_base)); irq_gc_lock(gc); writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip)); irq_gc_unlock(gc); } static void mvebu_gpio_edge_irq_mask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); gc->mask_cache &= ~mask; writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); irq_gc_unlock(gc); } static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); gc->mask_cache |= mask; writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); irq_gc_unlock(gc); } static void mvebu_gpio_level_irq_mask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); gc->mask_cache &= ~mask; writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); irq_gc_unlock(gc); } static void mvebu_gpio_level_irq_unmask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct mvebu_gpio_chip *mvchip = gc->private; u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc); gc->mask_cache |= mask; writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); irq_gc_unlock(gc); } /***************************************************************************** * MVEBU GPIO IRQ * * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same * value of the line or the opposite value. * * Level IRQ handlers: DATA_IN is used directly as cause register. * Interrupt are masked by LEVEL_MASK registers. * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. * Interrupt are masked by EDGE_MASK registers. * Both-edge handlers: Similar to regular Edge handlers, but also swaps * the polarity to catch the next line transaction. * This is a race condition that might not perfectly * work on some use cases. * * Every eight GPIO lines are grouped (OR'ed) before going up to main * cause register. * * EDGE cause mask * data-in /--------| |-----| |----\ * -----| |----- ---- to main cause reg * X \----------------| |----/ * polarity LEVEL mask * ****************************************************************************/ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct irq_chip_type *ct = irq_data_get_chip_type(d); struct mvebu_gpio_chip *mvchip = gc->private; int pin; u32 u; pin = d->hwirq; u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin); if (!u) { return -EINVAL; } type &= IRQ_TYPE_SENSE_MASK; if (type == IRQ_TYPE_NONE) return -EINVAL; /* Check if we need to change chip and handler */ if (!(ct->type & type)) if (irq_setup_alt_chip(d, type)) return -EINVAL; /* * Configure interrupt polarity. */ switch (type) { case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_LEVEL_HIGH: u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); u &= ~(1 << pin); writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); break; case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_LEVEL_LOW: u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); u |= 1 << pin; writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); break; case IRQ_TYPE_EDGE_BOTH: { u32 v; v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^ readl_relaxed(mvebu_gpioreg_data_in(mvchip)); /* * set initial polarity based on current input level */ u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); if (v & (1 << pin)) u |= 1 << pin; /* falling */ else u &= ~(1 << pin); /* rising */ writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); break; } } return 0; } static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq); u32 cause, type; int i; if (mvchip == NULL) return; cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) & readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) & readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); for (i = 0; i < mvchip->chip.ngpio; i++) { int irq; irq = mvchip->irqbase + i; if (!(cause & (1 << i))) continue; type = irq_get_trigger_type(irq); if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { /* Swap polarity (race with GPIO line) */ u32 polarity;


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