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authorEric W. Biederman <ebiederm@xmission.com>2009-11-16 05:30:16 -0500
committerEric W. Biederman <ebiederm@xmission.com>2009-11-18 10:06:48 -0500
commit60a0a52df149286a25fddf9b2d0cfe77cf0bc516 (patch)
treec169f1a790357fb5ea1ca9780e28af12d31c0ece /lib/debugobjects.c
parentbb9074ff58fe745e4f244f76209241909c82ec9c (diff)
sysctl: kill dead ctl_handler definitions.
When removing the sysctl strategy routines I overlooked their definitions in sysctl.h. So remove those unnecessary definitions now. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
Diffstat (limited to 'lib/debugobjects.c')
0 files changed, 0 insertions, 0 deletions
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-01 01:06:53 -0400
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/*****************************************************************************/

/*
 *	sc26198.h  -- SC26198 UART hardware info.
 *
 *	Copyright (C) 1995-1998  Stallion Technologies
 *
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2 of the License, or
 *	(at your option) any later version.
 *
 *	This program is distributed in the hope that it will be useful,
 *	but WITHOUT ANY WARRANTY; without even the implied warranty of
 *	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *	GNU General Public License for more details.
 *
 *	You should have received a copy of the GNU General Public License
 *	along with this program; if not, write to the Free Software
 *	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/*****************************************************************************/
#ifndef	_SC26198_H
#define	_SC26198_H
/*****************************************************************************/

/*
 *	Define the number of async ports per sc26198 uart device.
 */
#define	SC26198_PORTS		8

/*
 *	Baud rate timing clocks. All derived from a master 14.7456 MHz clock.
 */
#define	SC26198_MASTERCLOCK	14745600L
#define	SC26198_DCLK		(SC26198_MASTERCLOCK)
#define	SC26198_CCLK		(SC26198_MASTERCLOCK / 2)
#define	SC26198_BCLK		(SC26198_MASTERCLOCK / 4)

/*
 *	Define internal FIFO sizes for the 26198 ports.
 */
#define	SC26198_TXFIFOSIZE	16
#define	SC26198_RXFIFOSIZE	16

/*****************************************************************************/

/*
 *	Global register definitions. These registers are global to each 26198
 *	device, not specific ports on it.
 */
#define	TSTR		0x0d
#define	GCCR		0x0f
#define	ICR		0x1b
#define	WDTRCR		0x1d
#define	IVR		0x1f
#define	BRGTRUA		0x84
#define	GPOSR		0x87
#define	GPOC		0x8b
#define	UCIR		0x8c
#define	CIR		0x8c
#define	BRGTRUB		0x8d
#define	GRXFIFO		0x8e
#define	GTXFIFO		0x8e
#define	GCCR2		0x8f
#define	BRGTRLA		0x94
#define	GPOR		0x97
#define	GPOD		0x9b
#define	BRGTCR		0x9c
#define	GICR		0x9c
#define	BRGTRLB		0x9d
#define	GIBCR		0x9d
#define	GITR		0x9f

/*
 *	Per port channel registers. These are the register offsets within
 *	the port address space, so need to have the port address (0 to 7)
 *	inserted in bit positions 4:6.
 */
#define	MR0		0x00
#define	MR1		0x01
#define	IOPCR		0x02
#define	BCRBRK		0x03
#define	BCRCOS		0x04
#define	BCRX		0x06
#define	BCRA		0x07
#define	XONCR		0x08
#define	XOFFCR		0x09
#define	ARCR		0x0a
#define	RXCSR		0x0c
#define	TXCSR		0x0e
#define	MR2		0x80
#define	SR		0x81
#define SCCR		0x81
#define	ISR		0x82
#define	IMR		0x82
#define	TXFIFO		0x83
#define	RXFIFO		0x83
#define	IPR		0x84
#define	IOPIOR		0x85
#define	XISR		0x86

/*
 *	For any given port calculate the address to use to access a specified
 *	register. This is only used for unusual access, mostly this is done
 *	through the assembler access routines.
 */
#define	SC26198_PORTREG(port,reg)	((((port) & 0x07) << 4) | (reg))

/*****************************************************************************/

/*
 *	Global configuration control register bit definitions.
 */
#define	GCCR_NOACK		0x00
#define	GCCR_IVRACK		0x02
#define	GCCR_IVRCHANACK		0x04
#define	GCCR_IVRTYPCHANACK	0x06
#define	GCCR_ASYNCCYCLE		0x00
#define	GCCR_SYNCCYCLE		0x40

/*****************************************************************************/

/*
 *	Mode register 0 bit definitions.
 */
#define	MR0_ADDRNONE		0x00
#define	MR0_AUTOWAKE		0x01
#define	MR0_AUTODOZE		0x02
#define	MR0_AUTOWAKEDOZE	0x03
#define	MR0_SWFNONE		0x00
#define	MR0_SWFTX		0x04
#define	MR0_SWFRX		0x08
#define	MR0_SWFRXTX		0x0c
#define	MR0_TXMASK		0x30
#define	MR0_TXEMPTY		0x00
#define	MR0_TXHIGH		0x10
#define	MR0_TXHALF		0x20
#define	MR0_TXRDY		0x00
#define	MR0_ADDRNT		0x00
#define	MR0_ADDRT		0x40
#define	MR0_SWFNT		0x00
#define	MR0_SWFT		0x80

/*
 *	Mode register 1 bit definitions.
 */
#define	MR1_CS5			0x00
#define	MR1_CS6			0x01
#define	MR1_CS7			0x02
#define	MR1_CS8			0x03
#define	MR1_PAREVEN		0x00
#define	MR1_PARODD		0x04
#define	MR1_PARENB		0x00
#define	MR1_PARFORCE		0x08
#define	MR1_PARNONE		0x10
#define	MR1_PARSPECIAL		0x18
#define	MR1_ERRCHAR		0x00
#define	MR1_ERRBLOCK		0x20
#define	MR1_ISRUNMASKED		0x00
#define	MR1_ISRMASKED		0x40
#define	MR1_AUTORTS		0x80

/*
 *	Mode register 2 bit definitions.
 */
#define	MR2_STOP1		0x00
#define	MR2_STOP15		0x01
#define	MR2_STOP2		0x02
#define	MR2_STOP916		0x03
#define	MR2_RXFIFORDY		0x00
#define	MR2_RXFIFOHALF		0x04
#define	MR2_RXFIFOHIGH		0x08
#define	MR2_RXFIFOFULL		0x0c
#define	MR2_AUTOCTS		0x10
#define	MR2_TXRTS		0x20
#define	MR2_MODENORM		0x00
#define	MR2_MODEAUTOECHO	0x40
#define	MR2_MODELOOP		0x80
#define	MR2_MODEREMECHO		0xc0

/*****************************************************************************/

/*
 *	Baud Rate Generator (BRG) selector values.
 */
#define	BRG_50			0x00
#define	BRG_75			0x01
#define	BRG_150			0x02
#define	BRG_200			0x03
#define	BRG_300			0x04
#define	BRG_450			0x05
#define	BRG_600			0x06
#define	BRG_900			0x07
#define	BRG_1200		0x08
#define	BRG_1800		0x09
#define	BRG_2400		0x0a
#define	BRG_3600		0x0b
#define	BRG_4800		0x0c
#define	BRG_7200		0x0d
#define	BRG_9600		0x0e
#define	BRG_14400		0x0f
#define	BRG_19200		0x10
#define	BRG_28200		0x11
#define	BRG_38400		0x12
#define	BRG_57600		0x13
#define	BRG_115200		0x14
#define	BRG_230400		0x15
#define	BRG_GIN0		0x16
#define	BRG_GIN1		0x17
#define	BRG_CT0			0x18
#define	BRG_CT1			0x19