litmus-rt.git - The LITMUS^RT kernel.

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author	Michael Ellerman <michael@ellerman.id.au>	2006-01-09 02:19:49 -0500
committer	Paul Mackerras <paulus@samba.org>	2006-01-09 04:18:19 -0500
commit	e0fa93d6e6f0f36f39b813e561dbb890c58da58f (patch)
tree	d1ceb7ffc8742df26b7d2553ac6fb43cc64c4c8a /kernel/sched.c
parent	0a498d96a3324c16add35da0435bc7c13b6c6f3f (diff)

[PATCH] powerpc: Don't use KERNELBASE in add_memory()

In add_memory() we should be using __va() to get a virtual address. Spotted by Mike Kravetz. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>

Diffstat (limited to 'kernel/sched.c')

0 files changed, 0 insertions, 0 deletions

/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <linux/module.h> #include <linux/init.h> #include <linux/rtc.h> #include <linux/pm.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/mfd/pm8xxx/core.h> #include <linux/mfd/pm8xxx/rtc.h> /* RTC Register offsets from RTC CTRL REG */ #define PM8XXX_ALARM_CTRL_OFFSET 0x01 #define PM8XXX_RTC_WRITE_OFFSET 0x02 #define PM8XXX_RTC_READ_OFFSET 0x06 #define PM8XXX_ALARM_RW_OFFSET 0x0A /* RTC_CTRL register bit fields */ #define PM8xxx_RTC_ENABLE BIT(7) #define PM8xxx_RTC_ALARM_ENABLE BIT(1) #define PM8xxx_RTC_ALARM_CLEAR BIT(0) #define NUM_8_BIT_RTC_REGS 0x4 /** * struct pm8xxx_rtc - rtc driver internal structure * @rtc: rtc device for this driver. * @rtc_alarm_irq: rtc alarm irq number. * @rtc_base: address of rtc control register. * @rtc_read_base: base address of read registers. * @rtc_write_base: base address of write registers. * @alarm_rw_base: base address of alarm registers. * @ctrl_reg: rtc control register. * @rtc_dev: device structure. * @ctrl_reg_lock: spinlock protecting access to ctrl_reg. */ struct pm8xxx_rtc { struct rtc_device *rtc; int rtc_alarm_irq; int rtc_base; int rtc_read_base; int rtc_write_base; int alarm_rw_base; u8 ctrl_reg; struct device *rtc_dev; spinlock_t ctrl_reg_lock; }; /* * The RTC registers need to be read/written one byte at a time. This is a * hardware limitation. */ static int pm8xxx_read_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_val, int base, int count) { int i, rc; struct device *parent = rtc_dd->rtc_dev->parent; for (i = 0; i < count; i++) { rc = pm8xxx_readb(parent, base + i, &rtc_val[i]); if (rc < 0) { dev_err(rtc_dd->rtc_dev, "PMIC read failed\n"); return rc; } } return 0; } static int pm8xxx_write_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_val, int base, int count) { int i, rc; struct device *parent = rtc_dd->rtc_dev->parent; for (i = 0; i < count; i++) { rc = pm8xxx_writeb(parent, base + i, rtc_val[i]); if (rc < 0) { dev_err(rtc_dd->rtc_dev, "PMIC write failed\n"); return rc; } } return 0; } /* * Steps to write the RTC registers. * 1. Disable alarm if enabled. * 2. Write 0x00 to LSB. * 3. Write Byte[1], Byte[2], Byte[3] then Byte[0]. * 4. Enable alarm if disabled in step 1. */ static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm) { int rc, i; unsigned long secs, irq_flags; u8 value[NUM_8_BIT_RTC_REGS], reg = 0, alarm_enabled = 0, ctrl_reg; struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); rtc_tm_to_time(tm, &secs); for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) { value[i] = secs & 0xFF; secs >>= 8; } dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs); spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); ctrl_reg = rtc_dd->ctrl_reg; if (ctrl_reg & PM8xxx_RTC_ALARM_ENABLE) { alarm_enabled = 1; ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE; rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1); if (rc < 0) { dev_err(dev, "Write to RTC control register " "failed\n"); goto rtc_rw_fail; } rtc_dd->ctrl_reg = ctrl_reg; } else spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); /* Write 0 to Byte[0] */ reg = 0; rc = pm8xxx_write_wrapper(rtc_dd, &reg, rtc_dd->rtc_write_base, 1); if (rc < 0) { dev_err(dev, "Write to RTC write data register failed\n"); goto rtc_rw_fail; } /* Write Byte[1], Byte[2], Byte[3] */ rc = pm8xxx_write_wrapper(rtc_dd, value + 1, rtc_dd->rtc_write_base + 1, 3); if (rc < 0) { dev_err(dev, "Write to RTC write data register failed\n"); goto rtc_rw_fail; } /* Write Byte[0] */ rc = pm8xxx_write_wrapper(rtc_dd, value, rtc_dd->rtc_write_base, 1); if (rc < 0) { dev_err(dev, "Write to RTC write data register failed\n"); goto rtc_rw_fail; } if (alarm_enabled) { ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE; rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1); if (rc < 0) { dev_err(dev, "Write to RTC control register " "failed\n"); goto rtc_rw_fail; } rtc_dd->ctrl_reg = ctrl_reg; } rtc_rw_fail: if (alarm_enabled) spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); return rc; } static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm) { int rc; u8 value[NUM_8_BIT_RTC_REGS], reg; unsigned long secs; struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); rc = pm8xxx_read_wrapper(rtc_dd, value, rtc_dd->rtc_read_base, NUM_8_BIT_RTC_REGS); if (rc < 0) { dev_err(dev, "RTC read data register failed\n"); return rc; } /* * Read the LSB again and check if there has been a carry over. * If there is, redo the read operation. */ rc = pm8xxx_read_wrapper(rtc_dd, &reg, rtc_dd->rtc_read_base, 1); if (rc < 0) { dev_err(dev, "RTC read data register failed\n"); return rc; } if (unlikely(reg < value[0])) { rc = pm8xxx_read_wrapper(rtc_dd, value, rtc_dd->rtc_read_base, NUM_8_BIT_RTC_REGS); if (rc < 0) { dev_err(dev, "RTC read data register failed\n"); return rc; } } secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24); rtc_time_to_tm(secs, tm); rc = rtc_valid_tm(tm); if (rc < 0) { dev_err(dev, "Invalid time read from RTC\n"); return rc; } dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n", secs, tm->tm_hour, tm->tm_min, tm->tm_sec, tm->tm_mday, tm->tm_mon, tm->tm_year); return 0; } static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) { int rc, i; u8 value[NUM_8_BIT_RTC_REGS], ctrl_reg; unsigned long secs, irq_flags; struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); rtc_tm_to_time(&alarm->time, &secs); for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) { value[i] = secs & 0xFF; secs >>= 8; } spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); rc = pm8xxx_write_wrapper(rtc_dd, value, rtc_dd->alarm_rw_base, NUM_8_BIT_RTC_REGS); if (rc < 0) { dev_err(dev, "Write to RTC ALARM register failed\n"); goto rtc_rw_fail; }


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