Merge commit 'linux-2.6/master' (early part) into oprofile/core

This branch depends on these apic patches:

      apic, x86: Use BIOS settings for IBS and MCE threshold interrupt LVT offsets
      apic, x86: Check if EILVT APIC registers are available (AMD only)

Signed-off-by: Robert Richter <robert.richter@amd.com>

1 files changed, 7 insertions, 5 deletions

diff --git a/kernel/irq/migration.c b/kernel/irq/migration.c
index 241962280836..1d2541940480 100644
--- a/kernel/irq/migration.c
+++ b/kernel/irq/migration.c
@@ -7,6 +7,7 @@
 void move_masked_irq(int irq)
 {
         struct irq_desc *desc = irq_to_desc(irq);
+        struct irq_chip *chip = desc->irq_data.chip;
 
         if (likely(!(desc->status & IRQ_MOVE_PENDING)))
                 return;
@@ -24,7 +25,7 @@ void move_masked_irq(int irq)
         if (unlikely(cpumask_empty(desc->pending_mask)))
                 return;
 
-        if (!desc->chip->set_affinity)
+        if (!chip->irq_set_affinity)
                 return;
 
         assert_raw_spin_locked(&desc->lock);
@@ -43,8 +44,9 @@ void move_masked_irq(int irq)
          */
         if (likely(cpumask_any_and(desc->pending_mask, cpu_online_mask)
                    < nr_cpu_ids))
-                if (!desc->chip->set_affinity(irq, desc->pending_mask)) {
-                        cpumask_copy(desc->affinity, desc->pending_mask);
+                if (!chip->irq_set_affinity(&desc->irq_data,
+                                            desc->pending_mask, false)) {
+                        cpumask_copy(desc->irq_data.affinity, desc->pending_mask);
                         irq_set_thread_affinity(desc);
                 }
 
@@ -61,8 +63,8 @@ void move_native_irq(int irq)
         if (unlikely(desc->status & IRQ_DISABLED))
                 return;
 
-        desc->chip->mask(irq);
+        desc->irq_data.chip->irq_mask(&desc->irq_data);
         move_masked_irq(irq);
-        desc->chip->unmask(irq);
+        desc->irq_data.chip->irq_unmask(&desc->irq_data);
 }