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authorThomas Gleixner <tglx@linutronix.de>2011-02-08 06:36:06 -0500
committerThomas Gleixner <tglx@linutronix.de>2011-02-19 06:58:17 -0500
commit6e40262ea43c4b0e3f435b3a083e4461ef921c17 (patch)
tree4548c1607f81701b77c0d63b544096cdee8ccde0 /kernel/irq/internals.h
parent2a0d6fb335d4428285dab2d254911748e6040807 (diff)
genirq: Move IRQ_MASKED to core
Keep status in sync until all users are fixed. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'kernel/irq/internals.h')
-rw-r--r--kernel/irq/internals.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h
index fdf2524437eb..3f2fcc194dcc 100644
--- a/kernel/irq/internals.h
+++ b/kernel/irq/internals.h
@@ -47,6 +47,7 @@ enum {
47 * IRQS_WAITING - irq is waiting 47 * IRQS_WAITING - irq is waiting
48 * IRQS_DISABLED - irq is disabled 48 * IRQS_DISABLED - irq is disabled
49 * IRQS_PENDING - irq is pending and replayed later 49 * IRQS_PENDING - irq is pending and replayed later
50 * IRQS_MASKED - irq is masked
50 */ 51 */
51enum { 52enum {
52 IRQS_AUTODETECT = 0x00000001, 53 IRQS_AUTODETECT = 0x00000001,
@@ -58,6 +59,7 @@ enum {
58 IRQS_WAITING = 0x00000080, 59 IRQS_WAITING = 0x00000080,
59 IRQS_DISABLED = 0x00000100, 60 IRQS_DISABLED = 0x00000100,
60 IRQS_PENDING = 0x00000200, 61 IRQS_PENDING = 0x00000200,
62 IRQS_MASKED = 0x00000400,
61}; 63};
62 64
63#define irq_data_to_desc(data) container_of(data, struct irq_desc, irq_data) 65#define irq_data_to_desc(data) container_of(data, struct irq_desc, irq_data)
@@ -142,7 +144,6 @@ static inline void print_irq_desc(unsigned int irq, struct irq_desc *desc)
142 } 144 }
143 145
144 P(IRQ_LEVEL); 146 P(IRQ_LEVEL);
145 P(IRQ_MASKED);
146#ifdef CONFIG_IRQ_PER_CPU 147#ifdef CONFIG_IRQ_PER_CPU
147 P(IRQ_PER_CPU); 148 P(IRQ_PER_CPU);
148#endif 149#endif
@@ -156,6 +157,7 @@ static inline void print_irq_desc(unsigned int irq, struct irq_desc *desc)
156 PS(IRQS_WAITING); 157 PS(IRQS_WAITING);
157 PS(IRQS_DISABLED); 158 PS(IRQS_DISABLED);
158 PS(IRQS_PENDING); 159 PS(IRQS_PENDING);
160 PS(IRQS_MASKED);
159} 161}
160 162
161#undef P 163#undef P