diff options
| author | Trond Myklebust <Trond.Myklebust@netapp.com> | 2006-07-03 13:49:45 -0400 |
|---|---|---|
| committer | Trond Myklebust <Trond.Myklebust@netapp.com> | 2006-07-03 13:49:45 -0400 |
| commit | 026477c1141b67e98e3bd8bdedb7d4b88a3ecd09 (patch) | |
| tree | 2624a44924c625c367f3cebf937853b9da2de282 /kernel/irq/chip.c | |
| parent | 9f2fa466383ce100b90fe52cb4489d7a26bf72a9 (diff) | |
| parent | 29454dde27d8e340bb1987bad9aa504af7081eba (diff) | |
Merge branch 'master' of /home/trondmy/kernel/linux-2.6/
Diffstat (limited to 'kernel/irq/chip.c')
| -rw-r--r-- | kernel/irq/chip.c | 534 |
1 files changed, 534 insertions, 0 deletions
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c new file mode 100644 index 000000000000..54105bdfe20d --- /dev/null +++ b/kernel/irq/chip.c | |||
| @@ -0,0 +1,534 @@ | |||
| 1 | /* | ||
| 2 | * linux/kernel/irq/chip.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | ||
| 5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | ||
| 6 | * | ||
| 7 | * This file contains the core interrupt handling code, for irq-chip | ||
| 8 | * based architectures. | ||
| 9 | * | ||
| 10 | * Detailed information is available in Documentation/DocBook/genericirq | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/irq.h> | ||
| 14 | #include <linux/module.h> | ||
| 15 | #include <linux/interrupt.h> | ||
| 16 | #include <linux/kernel_stat.h> | ||
| 17 | |||
| 18 | #include "internals.h" | ||
| 19 | |||
| 20 | /** | ||
| 21 | * set_irq_chip - set the irq chip for an irq | ||
| 22 | * @irq: irq number | ||
| 23 | * @chip: pointer to irq chip description structure | ||
| 24 | */ | ||
| 25 | int set_irq_chip(unsigned int irq, struct irq_chip *chip) | ||
| 26 | { | ||
| 27 | struct irq_desc *desc; | ||
| 28 | unsigned long flags; | ||
| 29 | |||
| 30 | if (irq >= NR_IRQS) { | ||
| 31 | printk(KERN_ERR "Trying to install chip for IRQ%d\n", irq); | ||
| 32 | WARN_ON(1); | ||
| 33 | return -EINVAL; | ||
| 34 | } | ||
| 35 | |||
| 36 | if (!chip) | ||
| 37 | chip = &no_irq_chip; | ||
| 38 | |||
| 39 | desc = irq_desc + irq; | ||
| 40 | spin_lock_irqsave(&desc->lock, flags); | ||
| 41 | irq_chip_set_defaults(chip); | ||
| 42 | desc->chip = chip; | ||
| 43 | /* | ||
| 44 | * For compatibility only: | ||
| 45 | */ | ||
| 46 | desc->chip = chip; | ||
| 47 | spin_unlock_irqrestore(&desc->lock, flags); | ||
| 48 | |||
| 49 | return 0; | ||
| 50 | } | ||
| 51 | EXPORT_SYMBOL(set_irq_chip); | ||
| 52 | |||
| 53 | /** | ||
| 54 | * set_irq_type - set the irq type for an irq | ||
| 55 | * @irq: irq number | ||
| 56 | * @type: interrupt type - see include/linux/interrupt.h | ||
| 57 | */ | ||
| 58 | int set_irq_type(unsigned int irq, unsigned int type) | ||
| 59 | { | ||
| 60 | struct irq_desc *desc; | ||
| 61 | unsigned long flags; | ||
| 62 | int ret = -ENXIO; | ||
| 63 | |||
| 64 | if (irq >= NR_IRQS) { | ||
| 65 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); | ||
| 66 | return -ENODEV; | ||
| 67 | } | ||
| 68 | |||
| 69 | desc = irq_desc + irq; | ||
| 70 | if (desc->chip->set_type) { | ||
| 71 | spin_lock_irqsave(&desc->lock, flags); | ||
| 72 | ret = desc->chip->set_type(irq, type); | ||
| 73 | spin_unlock_irqrestore(&desc->lock, flags); | ||
| 74 | } | ||
| 75 | return ret; | ||
| 76 | } | ||
| 77 | EXPORT_SYMBOL(set_irq_type); | ||
| 78 | |||
| 79 | /** | ||
| 80 | * set_irq_data - set irq type data for an irq | ||
| 81 | * @irq: Interrupt number | ||
| 82 | * @data: Pointer to interrupt specific data | ||
| 83 | * | ||
| 84 | * Set the hardware irq controller data for an irq | ||
| 85 | */ | ||
| 86 | int set_irq_data(unsigned int irq, void *data) | ||
| 87 | { | ||
| 88 | struct irq_desc *desc; | ||
| 89 | unsigned long flags; | ||
| 90 | |||
| 91 | if (irq >= NR_IRQS) { | ||
| 92 | printk(KERN_ERR | ||
| 93 | "Trying to install controller data for IRQ%d\n", irq); | ||
| 94 | return -EINVAL; | ||
| 95 | } | ||
| 96 | |||
| 97 | desc = irq_desc + irq; | ||
| 98 | spin_lock_irqsave(&desc->lock, flags); | ||
| 99 | desc->handler_data = data; | ||
| 100 | spin_unlock_irqrestore(&desc->lock, flags); | ||
| 101 | return 0; | ||
| 102 | } | ||
| 103 | EXPORT_SYMBOL(set_irq_data); | ||
| 104 | |||
| 105 | /** | ||
| 106 | * set_irq_chip_data - set irq chip data for an irq | ||
| 107 | * @irq: Interrupt number | ||
| 108 | * @data: Pointer to chip specific data | ||
| 109 | * | ||
| 110 | * Set the hardware irq chip data for an irq | ||
| 111 | */ | ||
| 112 | int set_irq_chip_data(unsigned int irq, void *data) | ||
| 113 | { | ||
| 114 | struct irq_desc *desc = irq_desc + irq; | ||
| 115 | unsigned long flags; | ||
| 116 | |||
| 117 | if (irq >= NR_IRQS || !desc->chip) { | ||
| 118 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); | ||
| 119 | return -EINVAL; | ||
| 120 | } | ||
| 121 | |||
| 122 | spin_lock_irqsave(&desc->lock, flags); | ||
| 123 | desc->chip_data = data; | ||
| 124 | spin_unlock_irqrestore(&desc->lock, flags); | ||
| 125 | |||
| 126 | return 0; | ||
| 127 | } | ||
| 128 | EXPORT_SYMBOL(set_irq_chip_data); | ||
| 129 | |||
| 130 | /* | ||
| 131 | * default enable function | ||
| 132 | */ | ||
| 133 | static void default_enable(unsigned int irq) | ||
| 134 | { | ||
| 135 | struct irq_desc *desc = irq_desc + irq; | ||
| 136 | |||
| 137 | desc->chip->unmask(irq); | ||
| 138 | desc->status &= ~IRQ_MASKED; | ||
| 139 | } | ||
| 140 | |||
| 141 | /* | ||
| 142 | * default disable function | ||
| 143 | */ | ||
| 144 | static void default_disable(unsigned int irq) | ||
| 145 | { | ||
| 146 | struct irq_desc *desc = irq_desc + irq; | ||
| 147 | |||
| 148 | if (!(desc->status & IRQ_DELAYED_DISABLE)) | ||
| 149 | irq_desc[irq].chip->mask(irq); | ||
| 150 | } | ||
| 151 | |||
| 152 | /* | ||
| 153 | * default startup function | ||
| 154 | */ | ||
| 155 | static unsigned int default_startup(unsigned int irq) | ||
| 156 | { | ||
| 157 | irq_desc[irq].chip->enable(irq); | ||
| 158 | |||
| 159 | return 0; | ||
| 160 | } | ||
| 161 | |||
| 162 | /* | ||
| 163 | * Fixup enable/disable function pointers | ||
| 164 | */ | ||
| 165 | void irq_chip_set_defaults(struct irq_chip *chip) | ||
| 166 | { | ||
| 167 | if (!chip->enable) | ||
| 168 | chip->enable = default_enable; | ||
| 169 | if (!chip->disable) | ||
| 170 | chip->disable = default_disable; | ||
| 171 | if (!chip->startup) | ||
| 172 | chip->startup = default_startup; | ||
| 173 | if (!chip->shutdown) | ||
| 174 | chip->shutdown = chip->disable; | ||
| 175 | if (!chip->name) | ||
| 176 | chip->name = chip->typename; | ||
| 177 | } | ||
| 178 | |||
| 179 | static inline void mask_ack_irq(struct irq_desc *desc, int irq) | ||
| 180 | { | ||
| 181 | if (desc->chip->mask_ack) | ||
| 182 | desc->chip->mask_ack(irq); | ||
| 183 | else { | ||
| 184 | desc->chip->mask(irq); | ||
| 185 | desc->chip->ack(irq); | ||
| 186 | } | ||
| 187 | } | ||
| 188 | |||
| 189 | /** | ||
| 190 | * handle_simple_irq - Simple and software-decoded IRQs. | ||
| 191 | * @irq: the interrupt number | ||
| 192 | * @desc: the interrupt description structure for this irq | ||
| 193 | * @regs: pointer to a register structure | ||
| 194 | * | ||
| 195 | * Simple interrupts are either sent from a demultiplexing interrupt | ||
| 196 | * handler or come from hardware, where no interrupt hardware control | ||
| 197 | * is necessary. | ||
| 198 | * | ||
| 199 | * Note: The caller is expected to handle the ack, clear, mask and | ||
| 200 | * unmask issues if necessary. | ||
| 201 | */ | ||
| 202 | void fastcall | ||
| 203 | handle_simple_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs) | ||
| 204 | { | ||
| 205 | struct irqaction *action; | ||
| 206 | irqreturn_t action_ret; | ||
| 207 | const unsigned int cpu = smp_processor_id(); | ||
| 208 | |||
| 209 | spin_lock(&desc->lock); | ||
| 210 | |||
| 211 | if (unlikely(desc->status & IRQ_INPROGRESS)) | ||
| 212 | goto out_unlock; | ||
| 213 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | ||
| 214 | kstat_cpu(cpu).irqs[irq]++; | ||
| 215 | |||
| 216 | action = desc->action; | ||
| 217 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) | ||
| 218 | goto out_unlock; | ||
| 219 | |||
| 220 | desc->status |= IRQ_INPROGRESS; | ||
| 221 | spin_unlock(&desc->lock); | ||
| 222 | |||
| 223 | action_ret = handle_IRQ_event(irq, regs, action); | ||
| 224 | if (!noirqdebug) | ||
| 225 | note_interrupt(irq, desc, action_ret, regs); | ||
| 226 | |||
| 227 | spin_lock(&desc->lock); | ||
| 228 | desc->status &= ~IRQ_INPROGRESS; | ||
| 229 | out_unlock: | ||
| 230 | spin_unlock(&desc->lock); | ||
| 231 | } | ||
| 232 | |||
| 233 | /** | ||
| 234 | * handle_level_irq - Level type irq handler | ||
| 235 | * @irq: the interrupt number | ||
| 236 | * @desc: the interrupt description structure for this irq | ||
| 237 | * @regs: pointer to a register structure | ||
| 238 | * | ||
| 239 | * Level type interrupts are active as long as the hardware line has | ||
| 240 | * the active level. This may require to mask the interrupt and unmask | ||
| 241 | * it after the associated handler has acknowledged the device, so the | ||
| 242 | * interrupt line is back to inactive. | ||
| 243 | */ | ||
| 244 | void fastcall | ||
| 245 | handle_level_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs) | ||
| 246 | { | ||
| 247 | unsigned int cpu = smp_processor_id(); | ||
| 248 | struct irqaction *action; | ||
| 249 | irqreturn_t action_ret; | ||
| 250 | |||
| 251 | spin_lock(&desc->lock); | ||
| 252 | mask_ack_irq(desc, irq); | ||
| 253 | |||
| 254 | if (unlikely(desc->status & IRQ_INPROGRESS)) | ||
| 255 | goto out; | ||
| 256 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | ||
| 257 | kstat_cpu(cpu).irqs[irq]++; | ||
| 258 | |||
| 259 | /* | ||
| 260 | * If its disabled or no action available | ||
| 261 | * keep it masked and get out of here | ||
| 262 | */ | ||
| 263 | action = desc->action; | ||
| 264 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) | ||
| 265 | goto out; | ||
| 266 | |||
| 267 | desc->status |= IRQ_INPROGRESS; | ||
| 268 | spin_unlock(&desc->lock); | ||
| 269 | |||
| 270 | action_ret = handle_IRQ_event(irq, regs, action); | ||
| 271 | if (!noirqdebug) | ||
| 272 | note_interrupt(irq, desc, action_ret, regs); | ||
| 273 | |||
| 274 | spin_lock(&desc->lock); | ||
| 275 | desc->status &= ~IRQ_INPROGRESS; | ||
| 276 | out: | ||
| 277 | if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) | ||
| 278 | desc->chip->unmask(irq); | ||
| 279 | spin_unlock(&desc->lock); | ||
| 280 | } | ||
| 281 | |||
| 282 | /** | ||
| 283 | * handle_fasteoi_irq - irq handler for transparent controllers | ||
| 284 | * @irq: the interrupt number | ||
| 285 | * @desc: the interrupt description structure for this irq | ||
| 286 | * @regs: pointer to a register structure | ||
| 287 | * | ||
| 288 | * Only a single callback will be issued to the chip: an ->eoi() | ||
| 289 | * call when the interrupt has been serviced. This enables support | ||
| 290 | * for modern forms of interrupt handlers, which handle the flow | ||
| 291 | * details in hardware, transparently. | ||
| 292 | */ | ||
| 293 | void fastcall | ||
| 294 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc, | ||
| 295 | struct pt_regs *regs) | ||
| 296 | { | ||
| 297 | unsigned int cpu = smp_processor_id(); | ||
| 298 | struct irqaction *action; | ||
| 299 | irqreturn_t action_ret; | ||
| 300 | |||
| 301 | spin_lock(&desc->lock); | ||
| 302 | |||
| 303 | if (unlikely(desc->status & IRQ_INPROGRESS)) | ||
| 304 | goto out; | ||
| 305 | |||
| 306 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | ||
| 307 | kstat_cpu(cpu).irqs[irq]++; | ||
| 308 | |||
| 309 | /* | ||
| 310 | * If its disabled or no action available | ||
| 311 | * keep it masked and get out of here | ||
| 312 | */ | ||
| 313 | action = desc->action; | ||
| 314 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { | ||
| 315 | desc->status |= IRQ_PENDING; | ||
| 316 | goto out; | ||
| 317 | } | ||
| 318 | |||
| 319 | desc->status |= IRQ_INPROGRESS; | ||
| 320 | desc->status &= ~IRQ_PENDING; | ||
| 321 | spin_unlock(&desc->lock); | ||
| 322 | |||
| 323 | action_ret = handle_IRQ_event(irq, regs, action); | ||
| 324 | if (!noirqdebug) | ||
| 325 | note_interrupt(irq, desc, action_ret, regs); | ||
| 326 | |||
| 327 | spin_lock(&desc->lock); | ||
| 328 | desc->status &= ~IRQ_INPROGRESS; | ||
| 329 | out: | ||
| 330 | desc->chip->eoi(irq); | ||
| 331 | |||
| 332 | spin_unlock(&desc->lock); | ||
| 333 | } | ||
| 334 | |||
| 335 | /** | ||
| 336 | * handle_edge_irq - edge type IRQ handler | ||
| 337 | * @irq: the interrupt number | ||
| 338 | * @desc: the interrupt description structure for this irq | ||
| 339 | * @regs: pointer to a register structure | ||
| 340 | * | ||
| 341 | * Interrupt occures on the falling and/or rising edge of a hardware | ||
| 342 | * signal. The occurence is latched into the irq controller hardware | ||
| 343 | * and must be acked in order to be reenabled. After the ack another | ||
| 344 | * interrupt can happen on the same source even before the first one | ||
| 345 | * is handled by the assosiacted event handler. If this happens it | ||
| 346 | * might be necessary to disable (mask) the interrupt depending on the | ||
| 347 | * controller hardware. This requires to reenable the interrupt inside | ||
| 348 | * of the loop which handles the interrupts which have arrived while | ||
| 349 | * the handler was running. If all pending interrupts are handled, the | ||
| 350 | * loop is left. | ||
| 351 | */ | ||
| 352 | void fastcall | ||
| 353 | handle_edge_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs) | ||
| 354 | { | ||
| 355 | const unsigned int cpu = smp_processor_id(); | ||
| 356 | |||
| 357 | spin_lock(&desc->lock); | ||
| 358 | |||
| 359 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | ||
| 360 | |||
| 361 | /* | ||
| 362 | * If we're currently running this IRQ, or its disabled, | ||
| 363 | * we shouldn't process the IRQ. Mark it pending, handle | ||
| 364 | * the necessary masking and go out | ||
| 365 | */ | ||
| 366 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || | ||
| 367 | !desc->action)) { | ||
| 368 | desc->status |= (IRQ_PENDING | IRQ_MASKED); | ||
| 369 | mask_ack_irq(desc, irq); | ||
| 370 | goto out_unlock; | ||
| 371 | } | ||
| 372 | |||
| 373 | kstat_cpu(cpu).irqs[irq]++; | ||
| 374 | |||
| 375 | /* Start handling the irq */ | ||
| 376 | desc->chip->ack(irq); | ||
| 377 | |||
| 378 | /* Mark the IRQ currently in progress.*/ | ||
| 379 | desc->status |= IRQ_INPROGRESS; | ||
| 380 | |||
| 381 | do { | ||
| 382 | struct irqaction *action = desc->action; | ||
| 383 | irqreturn_t action_ret; | ||
| 384 | |||
| 385 | if (unlikely(!action)) { | ||
| 386 | desc->chip->mask(irq); | ||
| 387 | goto out_unlock; | ||
| 388 | } | ||
| 389 | |||
| 390 | /* | ||
| 391 | * When another irq arrived while we were handling | ||
| 392 | * one, we could have masked the irq. | ||
| 393 | * Renable it, if it was not disabled in meantime. | ||
| 394 | */ | ||
| 395 | if (unlikely((desc->status & | ||
| 396 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == | ||
| 397 | (IRQ_PENDING | IRQ_MASKED))) { | ||
| 398 | desc->chip->unmask(irq); | ||
| 399 | desc->status &= ~IRQ_MASKED; | ||
| 400 | } | ||
| 401 | |||
| 402 | desc->status &= ~IRQ_PENDING; | ||
| 403 | spin_unlock(&desc->lock); | ||
| 404 | action_ret = handle_IRQ_event(irq, regs, action); | ||
| 405 | if (!noirqdebug) | ||
| 406 | note_interrupt(irq, desc, action_ret, regs); | ||
| 407 | spin_lock(&desc->lock); | ||
| 408 | |||
| 409 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); | ||
| 410 | |||
| 411 | desc->status &= ~IRQ_INPROGRESS; | ||
| 412 | out_unlock: | ||
| 413 | spin_unlock(&desc->lock); | ||
| 414 | } | ||
| 415 | |||
| 416 | #ifdef CONFIG_SMP | ||
| 417 | /** | ||
| 418 | * handle_percpu_IRQ - Per CPU local irq handler | ||
| 419 | * @irq: the interrupt number | ||
| 420 | * @desc: the interrupt description structure for this irq | ||
| 421 | * @regs: pointer to a register structure | ||
| 422 | * | ||
| 423 | * Per CPU interrupts on SMP machines without locking requirements | ||
| 424 | */ | ||
| 425 | void fastcall | ||
| 426 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs) | ||
| 427 | { | ||
| 428 | irqreturn_t action_ret; | ||
| 429 | |||
| 430 | kstat_this_cpu.irqs[irq]++; | ||
| 431 | |||
| 432 | if (desc->chip->ack) | ||
| 433 | desc->chip->ack(irq); | ||
| 434 | |||
| 435 | action_ret = handle_IRQ_event(irq, regs, desc->action); | ||
| 436 | if (!noirqdebug) | ||
| 437 | note_interrupt(irq, desc, action_ret, regs); | ||
| 438 | |||
| 439 | if (desc->chip->eoi) | ||
| 440 | desc->chip->eoi(irq); | ||
| 441 | } | ||
| 442 | |||
| 443 | #endif /* CONFIG_SMP */ | ||
| 444 | |||
| 445 | void | ||
| 446 | __set_irq_handler(unsigned int irq, | ||
| 447 | void fastcall (*handle)(unsigned int, irq_desc_t *, | ||
| 448 | struct pt_regs *), | ||
| 449 | int is_chained) | ||
| 450 | { | ||
| 451 | struct irq_desc *desc; | ||
| 452 | unsigned long flags; | ||
| 453 | |||
| 454 | if (irq >= NR_IRQS) { | ||
| 455 | printk(KERN_ERR | ||
| 456 | "Trying to install type control for IRQ%d\n", irq); | ||
| 457 | return; | ||
| 458 | } | ||
| 459 | |||
| 460 | desc = irq_desc + irq; | ||
| 461 | |||
| 462 | if (!handle) | ||
| 463 | handle = handle_bad_irq; | ||
| 464 | |||
| 465 | if (desc->chip == &no_irq_chip) { | ||
| 466 | printk(KERN_WARNING "Trying to install %sinterrupt handler " | ||
| 467 | "for IRQ%d\n", is_chained ? "chained " : " ", irq); | ||
| 468 | /* | ||
| 469 | * Some ARM implementations install a handler for really dumb | ||
| 470 | * interrupt hardware without setting an irq_chip. This worked | ||
| 471 | * with the ARM no_irq_chip but the check in setup_irq would | ||
| 472 | * prevent us to setup the interrupt at all. Switch it to | ||
| 473 | * dummy_irq_chip for easy transition. | ||
| 474 | */ | ||
| 475 | desc->chip = &dummy_irq_chip; | ||
| 476 | } | ||
| 477 | |||
| 478 | spin_lock_irqsave(&desc->lock, flags); | ||
| 479 | |||
| 480 | /* Uninstall? */ | ||
| 481 | if (handle == handle_bad_irq) { | ||
| 482 | if (desc->chip != &no_irq_chip) { | ||
| 483 | desc->chip->mask(irq); | ||
| 484 | desc->chip->ack(irq); | ||
| 485 | } | ||
| 486 | desc->status |= IRQ_DISABLED; | ||
| 487 | desc->depth = 1; | ||
| 488 | } | ||
| 489 | desc->handle_irq = handle; | ||
| 490 | |||
| 491 | if (handle != handle_bad_irq && is_chained) { | ||
| 492 | desc->status &= ~IRQ_DISABLED; | ||
| 493 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; | ||
| 494 | desc->depth = 0; | ||
| 495 | desc->chip->unmask(irq); | ||
| 496 | } | ||
| 497 | spin_unlock_irqrestore(&desc->lock, flags); | ||
| 498 | } | ||
| 499 | |||
| 500 | void | ||
| 501 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | ||
| 502 | void fastcall (*handle)(unsigned int, | ||
| 503 | struct irq_desc *, | ||
| 504 | struct pt_regs *)) | ||
| 505 | { | ||
| 506 | set_irq_chip(irq, chip); | ||
| 507 | __set_irq_handler(irq, handle, 0); | ||
| 508 | } | ||
| 509 | |||
| 510 | /* | ||
| 511 | * Get a descriptive string for the highlevel handler, for | ||
| 512 | * /proc/interrupts output: | ||
| 513 | */ | ||
| 514 | const char * | ||
| 515 | handle_irq_name(void fastcall (*handle)(unsigned int, struct irq_desc *, | ||
| 516 | struct pt_regs *)) | ||
| 517 | { | ||
| 518 | if (handle == handle_level_irq) | ||
| 519 | return "level "; | ||
| 520 | if (handle == handle_fasteoi_irq) | ||
| 521 | return "fasteoi"; | ||
| 522 | if (handle == handle_edge_irq) | ||
| 523 | return "edge "; | ||
| 524 | if (handle == handle_simple_irq) | ||
| 525 | return "simple "; | ||
| 526 | #ifdef CONFIG_SMP | ||
| 527 | if (handle == handle_percpu_irq) | ||
| 528 | return "percpu "; | ||
| 529 | #endif | ||
| 530 | if (handle == handle_bad_irq) | ||
| 531 | return "bad "; | ||
| 532 | |||
| 533 | return NULL; | ||
| 534 | } | ||
