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authorJeremy Fitzhardinge <jeremy@goop.org>2008-02-04 10:48:02 -0500
committerIngo Molnar <mingo@elte.hu>2008-02-04 10:48:02 -0500
commitf5430f93257d336346a9018c915e879ce43f5f89 (patch)
tree77f896b31b405801c6869694fb6c1eccc4b680c1 /include
parentedd6bcd8209c31b91e1fbc112a756475091c483d (diff)
x86: update reference for PAE tlb flushing
Remove bogus reference to "Pentium-II erratum A13" and point to the actual canonical source of information about what requirements x86 processors have for PAE pagetable updates. Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include')
-rw-r--r--include/asm-x86/pgalloc_32.h6
-rw-r--r--include/asm-x86/pgtable-3level.h6
2 files changed, 8 insertions, 4 deletions
diff --git a/include/asm-x86/pgalloc_32.h b/include/asm-x86/pgalloc_32.h
index 7641e7b5d931..6c21ef951dab 100644
--- a/include/asm-x86/pgalloc_32.h
+++ b/include/asm-x86/pgalloc_32.h
@@ -80,8 +80,10 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd)
80 set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT)); 80 set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT));
81 81
82 /* 82 /*
83 * Pentium-II erratum A13: in PAE mode we explicitly have to flush 83 * According to Intel App note "TLBs, Paging-Structure Caches,
84 * the TLB via cr3 if the top-level pgd is changed... 84 * and Their Invalidation", April 2007, document 317080-001,
85 * section 8.1: in PAE mode we explicitly have to flush the
86 * TLB via cr3 if the top-level pgd is changed...
85 */ 87 */
86 if (mm == current->active_mm) 88 if (mm == current->active_mm)
87 write_cr3(read_cr3()); 89 write_cr3(read_cr3());
diff --git a/include/asm-x86/pgtable-3level.h b/include/asm-x86/pgtable-3level.h
index ad71960bca3a..1d763eec740f 100644
--- a/include/asm-x86/pgtable-3level.h
+++ b/include/asm-x86/pgtable-3level.h
@@ -98,8 +98,10 @@ static inline void pud_clear(pud_t *pudp)
98 set_pud(pudp, __pud(0)); 98 set_pud(pudp, __pud(0));
99 99
100 /* 100 /*
101 * Pentium-II erratum A13: in PAE mode we explicitly have to flush 101 * According to Intel App note "TLBs, Paging-Structure Caches,
102 * the TLB via cr3 if the top-level pgd is changed... 102 * and Their Invalidation", April 2007, document 317080-001,
103 * section 8.1: in PAE mode we explicitly have to flush the
104 * TLB via cr3 if the top-level pgd is changed...
103 * 105 *
104 * Make sure the pud entry we're updating is within the 106 * Make sure the pud entry we're updating is within the
105 * current pgd to avoid unnecessary TLB flushes. 107 * current pgd to avoid unnecessary TLB flushes.