aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
authorChris Zankel <chris@zankel.net>2007-12-19 13:21:50 -0500
committerChris Zankel <chris@zankel.net>2008-02-13 20:24:47 -0500
commitde6b03456e2e11cbff9f4bb147177374b260d04e (patch)
tree0890edb9c5efe46689eb641792b1a66cfb1b1d1d /include
parent03dfa442e5aaf644bb9b3b506abbd76786867eb1 (diff)
[XTENSA] Add volatile keyword to asm statements accessing counter registers
The compiler get's sometimes to smart and doesn't reread the counter registers and the kernel doesn't schedule until the counter wraps around. Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'include')
-rw-r--r--include/asm-xtensa/timex.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/include/asm-xtensa/timex.h b/include/asm-xtensa/timex.h
index a5fca59fba9e..b83a8181d448 100644
--- a/include/asm-xtensa/timex.h
+++ b/include/asm-xtensa/timex.h
@@ -63,10 +63,10 @@ extern cycles_t cacheflush_time;
63 * Register access. 63 * Register access.
64 */ 64 */
65 65
66#define WSR_CCOUNT(r) __asm__("wsr %0,"__stringify(CCOUNT) :: "a" (r)) 66#define WSR_CCOUNT(r) asm volatile ("wsr %0,"__stringify(CCOUNT) :: "a" (r))
67#define RSR_CCOUNT(r) __asm__("rsr %0,"__stringify(CCOUNT) : "=a" (r)) 67#define RSR_CCOUNT(r) asm volatile ("rsr %0,"__stringify(CCOUNT) : "=a" (r))
68#define WSR_CCOMPARE(x,r) __asm__("wsr %0,"__stringify(CCOMPARE)"+"__stringify(x) :: "a"(r)) 68#define WSR_CCOMPARE(x,r) asm volatile ("wsr %0,"__stringify(CCOMPARE)"+"__stringify(x) :: "a"(r))
69#define RSR_CCOMPARE(x,r) __asm__("rsr %0,"__stringify(CCOMPARE)"+"__stringify(x) : "=a"(r)) 69#define RSR_CCOMPARE(x,r) asm volatile ("rsr %0,"__stringify(CCOMPARE)"+"__stringify(x) : "=a"(r))
70 70
71static inline unsigned long get_ccount (void) 71static inline unsigned long get_ccount (void)
72{ 72{