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authorDavid Howells <dhowells@redhat.com>2008-04-10 11:10:45 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-04-10 16:41:28 -0400
commita31b9dd8edc6e4e75b5299fee6093b3c54548446 (patch)
treef1f8fe2c4e98e80c505e869cd1c98caef259a079 /include
parent5d69a029ab13ddef5bdad69174fabafada4a87fd (diff)
FRV: Handle update_mmu_cache() being called when current->mm is NULL [try #2]
Handle update_mmu_cache() being called when current->mm is NULL. We cache static TLB mappings for the current page table in DAMPR4 and DAMPR5 on the theory that the next data lookup is likely to be in the same general region, and thus is likely to be mapped by the same page table. However, we can't get this information if we can't access the appropriate mm_struct. If current->mm is NULL, we just clear the cache in the knowledge that the TLB miss handlers will load it. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-frv/pgtable.h19
1 files changed, 14 insertions, 5 deletions
diff --git a/include/asm-frv/pgtable.h b/include/asm-frv/pgtable.h
index 6c0682ed5fc9..4e219046fe42 100644
--- a/include/asm-frv/pgtable.h
+++ b/include/asm-frv/pgtable.h
@@ -507,13 +507,22 @@ static inline int pte_file(pte_t pte)
507 */ 507 */
508static inline void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) 508static inline void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
509{ 509{
510 struct mm_struct *mm;
510 unsigned long ampr; 511 unsigned long ampr;
511 pgd_t *pge = pgd_offset(current->mm, address);
512 pud_t *pue = pud_offset(pge, address);
513 pmd_t *pme = pmd_offset(pue, address);
514 512
515 ampr = pme->ste[0] & 0xffffff00; 513 mm = current->mm;
516 ampr |= xAMPRx_L | xAMPRx_SS_16Kb | xAMPRx_S | xAMPRx_C | xAMPRx_V; 514 if (mm) {
515 pgd_t *pge = pgd_offset(mm, address);
516 pud_t *pue = pud_offset(pge, address);
517 pmd_t *pme = pmd_offset(pue, address);
518
519 ampr = pme->ste[0] & 0xffffff00;
520 ampr |= xAMPRx_L | xAMPRx_SS_16Kb | xAMPRx_S | xAMPRx_C |
521 xAMPRx_V;
522 } else {
523 address = ULONG_MAX;
524 ampr = 0;
525 }
517 526
518 asm volatile("movgs %0,scr0\n" 527 asm volatile("movgs %0,scr0\n"
519 "movgs %0,scr1\n" 528 "movgs %0,scr1\n"