diff options
author | Timur Tabi <timur@freescale.com> | 2007-07-25 13:30:33 -0400 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2007-09-14 09:54:00 -0400 |
commit | 82925e76db19112cad62066828c1db0bbb3f77e3 (patch) | |
tree | 084adf5913519c7a96ac08b1f31b44c493e8f115 /include | |
parent | dc967d7f5e5d2c9d01c8ea172a1e231908dba9de (diff) |
[POWERPC] 86xx: Fix definition of global-utilites structure
The current definition of struct ccsr_guts in immap_86xx.h was for 85xx.
This patch fixes that and replaces the vague integer types with sized types
of the correct endianness. The unused struct ccsr_pci is also deleted.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-powerpc/immap_86xx.h | 151 |
1 files changed, 46 insertions, 105 deletions
diff --git a/include/asm-powerpc/immap_86xx.h b/include/asm-powerpc/immap_86xx.h index 59b9e07b8e99..c83d7ad16606 100644 --- a/include/asm-powerpc/immap_86xx.h +++ b/include/asm-powerpc/immap_86xx.h | |||
@@ -1,124 +1,65 @@ | |||
1 | /* | 1 | /** |
2 | * MPC86xx Internal Memory Map | 2 | * MPC86xx Internal Memory Map |
3 | * | 3 | * |
4 | * Author: Jeff Brown | 4 | * Authors: Jeff Brown |
5 | * Timur Tabi <timur@freescale.com> | ||
5 | * | 6 | * |
6 | * Copyright 2004 Freescale Semiconductor, Inc | 7 | * Copyright 2004,2007 Freescale Semiconductor, Inc |
7 | * | 8 | * |
8 | * This program is free software; you can redistribute it and/or modify it | 9 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms of the GNU General Public License as published by the | 10 | * under the terms of the GNU General Public License as published by the |
10 | * Free Software Foundation; either version 2 of the License, or (at your | 11 | * Free Software Foundation; either version 2 of the License, or (at your |
11 | * option) any later version. | 12 | * option) any later version. |
12 | * | 13 | * |
14 | * This header file defines structures for various 86xx SOC devices that are | ||
15 | * used by multiple source files. | ||
13 | */ | 16 | */ |
14 | 17 | ||
15 | #ifndef __ASM_POWERPC_IMMAP_86XX_H__ | 18 | #ifndef __ASM_POWERPC_IMMAP_86XX_H__ |
16 | #define __ASM_POWERPC_IMMAP_86XX_H__ | 19 | #define __ASM_POWERPC_IMMAP_86XX_H__ |
17 | #ifdef __KERNEL__ | 20 | #ifdef __KERNEL__ |
18 | 21 | ||
19 | /* Eventually this should define all the IO block registers in 86xx */ | ||
20 | |||
21 | /* PCI Registers */ | ||
22 | typedef struct ccsr_pci { | ||
23 | uint cfg_addr; /* 0x.000 - PCI Configuration Address Register */ | ||
24 | uint cfg_data; /* 0x.004 - PCI Configuration Data Register */ | ||
25 | uint int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ | ||
26 | char res1[3060]; | ||
27 | uint potar0; /* 0x.c00 - PCI Outbound Transaction Address Register 0 */ | ||
28 | uint potear0; /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */ | ||
29 | uint powbar0; /* 0x.c08 - PCI Outbound Window Base Address Register 0 */ | ||
30 | char res2[4]; | ||
31 | uint powar0; /* 0x.c10 - PCI Outbound Window Attributes Register 0 */ | ||
32 | char res3[12]; | ||
33 | uint potar1; /* 0x.c20 - PCI Outbound Transaction Address Register 1 */ | ||
34 | uint potear1; /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */ | ||
35 | uint powbar1; /* 0x.c28 - PCI Outbound Window Base Address Register 1 */ | ||
36 | char res4[4]; | ||
37 | uint powar1; /* 0x.c30 - PCI Outbound Window Attributes Register 1 */ | ||
38 | char res5[12]; | ||
39 | uint potar2; /* 0x.c40 - PCI Outbound Transaction Address Register 2 */ | ||
40 | uint potear2; /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */ | ||
41 | uint powbar2; /* 0x.c48 - PCI Outbound Window Base Address Register 2 */ | ||
42 | char res6[4]; | ||
43 | uint powar2; /* 0x.c50 - PCI Outbound Window Attributes Register 2 */ | ||
44 | char res7[12]; | ||
45 | uint potar3; /* 0x.c60 - PCI Outbound Transaction Address Register 3 */ | ||
46 | uint potear3; /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */ | ||
47 | uint powbar3; /* 0x.c68 - PCI Outbound Window Base Address Register 3 */ | ||
48 | char res8[4]; | ||
49 | uint powar3; /* 0x.c70 - PCI Outbound Window Attributes Register 3 */ | ||
50 | char res9[12]; | ||
51 | uint potar4; /* 0x.c80 - PCI Outbound Transaction Address Register 4 */ | ||
52 | uint potear4; /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */ | ||
53 | uint powbar4; /* 0x.c88 - PCI Outbound Window Base Address Register 4 */ | ||
54 | char res10[4]; | ||
55 | uint powar4; /* 0x.c90 - PCI Outbound Window Attributes Register 4 */ | ||
56 | char res11[268]; | ||
57 | uint pitar3; /* 0x.da0 - PCI Inbound Translation Address Register 3 */ | ||
58 | char res12[4]; | ||
59 | uint piwbar3; /* 0x.da8 - PCI Inbound Window Base Address Register 3 */ | ||
60 | uint piwbear3; /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */ | ||
61 | uint piwar3; /* 0x.db0 - PCI Inbound Window Attributes Register 3 */ | ||
62 | char res13[12]; | ||
63 | uint pitar2; /* 0x.dc0 - PCI Inbound Translation Address Register 2 */ | ||
64 | char res14[4]; | ||
65 | uint piwbar2; /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */ | ||
66 | uint piwbear2; /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */ | ||
67 | uint piwar2; /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */ | ||
68 | char res15[12]; | ||
69 | uint pitar1; /* 0x.de0 - PCI Inbound Translation Address Register 1 */ | ||
70 | char res16[4]; | ||
71 | uint piwbar1; /* 0x.de8 - PCI Inbound Window Base Address Register 1 */ | ||
72 | char res17[4]; | ||
73 | uint piwar1; /* 0x.df0 - PCI Inbound Window Attributes Register 1 */ | ||
74 | char res18[12]; | ||
75 | uint err_dr; /* 0x.e00 - PCI Error Detect Register */ | ||
76 | uint err_cap_dr; /* 0x.e04 - PCI Error Capture Disable Register */ | ||
77 | uint err_en; /* 0x.e08 - PCI Error Enable Register */ | ||
78 | uint err_attrib; /* 0x.e0c - PCI Error Attributes Capture Register */ | ||
79 | uint err_addr; /* 0x.e10 - PCI Error Address Capture Register */ | ||
80 | uint err_ext_addr; /* 0x.e14 - PCI Error Extended Address Capture Register */ | ||
81 | uint err_dl; /* 0x.e18 - PCI Error Data Low Capture Register */ | ||
82 | uint err_dh; /* 0x.e1c - PCI Error Data High Capture Register */ | ||
83 | uint gas_timr; /* 0x.e20 - PCI Gasket Timer Register */ | ||
84 | uint pci_timr; /* 0x.e24 - PCI Timer Register */ | ||
85 | char res19[472]; | ||
86 | } ccsr_pci_t; | ||
87 | |||
88 | /* Global Utility Registers */ | 22 | /* Global Utility Registers */ |
89 | typedef struct ccsr_guts { | 23 | struct ccsr_guts { |
90 | uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ | 24 | __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ |
91 | uint porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ | 25 | __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ |
92 | uint porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ | 26 | __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ |
93 | uint pordevsr; /* 0x.000c - POR I/O Device Status Register */ | 27 | __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */ |
94 | uint pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ | 28 | __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ |
95 | char res1[12]; | 29 | u8 res1[0x20 - 0x14]; |
96 | uint gpporcr; /* 0x.0020 - General-Purpose POR Configuration Register */ | 30 | __be32 porcir; /* 0x.0020 - POR Configuration Information Register */ |
97 | char res2[12]; | 31 | u8 res2[0x30 - 0x24]; |
98 | uint gpiocr; /* 0x.0030 - GPIO Control Register */ | 32 | __be32 gpiocr; /* 0x.0030 - GPIO Control Register */ |
99 | char res3[12]; | 33 | u8 res3[0x40 - 0x34]; |
100 | uint gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ | 34 | __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ |
101 | char res4[12]; | 35 | u8 res4[0x50 - 0x44]; |
102 | uint gpindr; /* 0x.0050 - General-Purpose Input Data Register */ | 36 | __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */ |
103 | char res5[12]; | 37 | u8 res5[0x60 - 0x54]; |
104 | uint pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ | 38 | __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ |
105 | char res6[12]; | 39 | u8 res6[0x70 - 0x64]; |
106 | uint devdisr; /* 0x.0070 - Device Disable Control */ | 40 | __be32 devdisr; /* 0x.0070 - Device Disable Control */ |
107 | char res7[12]; | 41 | u8 res7[0x80 - 0x74]; |
108 | uint powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ | 42 | __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ |
109 | char res8[12]; | 43 | u8 res8[0x90 - 0x84]; |
110 | uint mcpsumr; /* 0x.0090 - Machine Check Summary Register */ | 44 | __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ |
111 | char res9[12]; | 45 | __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */ |
112 | uint pvr; /* 0x.00a0 - Processor Version Register */ | 46 | u8 res9[0xA0 - 0x98]; |
113 | uint svr; /* 0x.00a4 - System Version Register */ | 47 | __be32 pvr; /* 0x.00a0 - Processor Version Register */ |
114 | char res10[3416]; | 48 | __be32 svr; /* 0x.00a4 - System Version Register */ |
115 | uint clkocr; /* 0x.0e00 - Clock Out Select Register */ | 49 | u8 res10[0xB0 - 0xA8]; |
116 | char res11[12]; | 50 | __be32 rstcr; /* 0x.00b0 - Reset Control Register */ |
117 | uint ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ | 51 | u8 res11[0xB20 - 0xB4]; |
118 | char res12[12]; | 52 | __be32 ddr1clkdr; /* 0x.0b20 - DDRC1 Clock Disable Register */ |
119 | uint lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ | 53 | __be32 ddr2clkdr; /* 0x.0b24 - DDRC2 Clock Disable Register */ |
120 | char res13[61916]; | 54 | u8 res12[0xE00 - 0xB28]; |
121 | } ccsr_guts_t; | 55 | __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */ |
56 | u8 res13[0xF04 - 0xE04]; | ||
57 | __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ | ||
58 | __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ | ||
59 | u8 res14[0xF40 - 0xF0C]; | ||
60 | __be32 srds2cr0; /* 0x.0f40 - SerDes1 Control Register 0 */ | ||
61 | __be32 srds2cr1; /* 0x.0f44 - SerDes1 Control Register 0 */ | ||
62 | }; | ||
122 | 63 | ||
123 | #endif /* __ASM_POWERPC_IMMAP_86XX_H__ */ | 64 | #endif /* __ASM_POWERPC_IMMAP_86XX_H__ */ |
124 | #endif /* __KERNEL__ */ | 65 | #endif /* __KERNEL__ */ |