Merge git://git.infradead.org/mtd-2.6

* git://git.infradead.org/mtd-2.6: (69 commits)
  Revert "[MTD] m25p80.c code cleanup"
  [MTD] [NAND] GPIO driver depends on ARM... for now.
  [MTD] [NAND] sh_flctl: fix compile error
  [MTD] [NOR] AT49BV6416 has swapped erase regions
  [MTD] [NAND] GPIO NAND flash driver
  [MTD] cmdlineparts documentation change - explain where mtd-id comes from
  [MTD] cfi_cmdset_0002.c: Add Macronix CFI V1.0 TopBottom detection
  [MTD] [NAND] Fix compilation warnings in drivers/mtd/nand/cs553x_nand.c
  [JFFS2] Write buffer offset adjustment for NOR-ECC (Sibley) flash
  [MTD] mtdoops: Fix a bug where block may not be erased
  [MTD] mtdoops: Add a magic number to logged kernel oops
  [MTD] mtdoops: Fix an off by one error
  [JFFS2] Correct parameter names of jffs2_compress() in comments
  [MTD] [NAND] sh_flctl: add support for Renesas SuperH FLCTL
  [MTD] [NAND] Bug on atmel_nand HW ECC : OOB info not correctly written
  [MTD] [MAPS] Remove unused variable after ROM API cleanup.
  [MTD] m25p80.c extended jedec support (v2)
  [MTD] remove unused mtd parameter in of_mtd_parse_partitions()
  [MTD] [NAND] remove dead Kconfig associated with !CONFIG_PPC_MERGE
  [MTD] [NAND] driver extension to support NAND on TQM85xx modules
  ...

9 files changed, 164 insertions, 3 deletions

diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h
index d6fb115f5a07..ee5124ec319e 100644
--- a/include/linux/mtd/cfi.h
+++ b/include/linux/mtd/cfi.h
@@ -12,6 +12,7 @@
 #include <linux/mtd/flashchip.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/cfi_endian.h>
+#include <linux/mtd/xip.h>
 
 #ifdef CONFIG_MTD_CFI_I1
 #define cfi_interleave(cfi) 1
@@ -430,7 +431,6 @@ static inline uint32_t cfi_send_gen_cmd(u_char cmd, uint32_t cmd_addr, uint32_t
 {
         map_word val;
         uint32_t addr = base + cfi_build_cmd_addr(cmd_addr, cfi_interleave(cfi), type);
-
         val = cfi_build_cmd(cmd, map, cfi);
 
         if (prev_val)
@@ -483,6 +483,13 @@ static inline void cfi_udelay(int us)
         }
 }
 
+int __xipram cfi_qry_present(struct map_info *map, __u32 base,
+                             struct cfi_private *cfi);
+int __xipram cfi_qry_mode_on(uint32_t base, struct map_info *map,
+                             struct cfi_private *cfi);
+void __xipram cfi_qry_mode_off(uint32_t base, struct map_info *map,
+                               struct cfi_private *cfi);
+
 struct cfi_extquery *cfi_read_pri(struct map_info *map, uint16_t adr, uint16_t size,
                              const char* name);
 struct cfi_fixup {
diff --git a/include/linux/mtd/flashchip.h b/include/linux/mtd/flashchip.h
index 08dd131301c1..d4f38c5fd44e 100644
--- a/include/linux/mtd/flashchip.h
+++ b/include/linux/mtd/flashchip.h
@@ -73,6 +73,10 @@ struct flchip {
         int buffer_write_time;
         int erase_time;
 
+        int word_write_time_max;
+        int buffer_write_time_max;
+        int erase_time_max;
+
         void *priv;
 };
 
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 922636548558..eae26bb6430a 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -25,8 +25,10 @@
 #define MTD_ERASE_DONE          0x08
 #define MTD_ERASE_FAILED        0x10
 
+#define MTD_FAIL_ADDR_UNKNOWN 0xffffffff
+
 /* If the erase fails, fail_addr might indicate exactly which block failed.  If
-   fail_addr = 0xffffffff, the failure was not at the device level or was not
+   fail_addr = MTD_FAIL_ADDR_UNKNOWN, the failure was not at the device level or was not
    specific to any particular block. */
 struct erase_info {
         struct mtd_info *mtd;
diff --git a/include/linux/mtd/nand-gpio.h b/include/linux/mtd/nand-gpio.h
new file mode 100644
index 000000000000..51534e50f7fc
--- /dev/null
+++ b/include/linux/mtd/nand-gpio.h
@@ -0,0 +1,19 @@
+#ifndef __LINUX_MTD_NAND_GPIO_H
+#define __LINUX_MTD_NAND_GPIO_H
+
+#include <linux/mtd/nand.h>
+
+struct gpio_nand_platdata {
+        int     gpio_nce;
+        int     gpio_nwp;
+        int     gpio_cle;
+        int     gpio_ale;
+        int     gpio_rdy;
+        void    (*adjust_parts)(struct gpio_nand_platdata *, size_t);
+        struct mtd_partition *parts;
+        unsigned int num_parts;
+        unsigned int options;
+        int     chip_delay;
+};
+
+#endif
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 81774e5facf4..733d3f3b4eb8 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -248,6 +248,7 @@ struct nand_hw_control {
  * @read_page_raw:      function to read a raw page without ECC
  * @write_page_raw:     function to write a raw page without ECC
  * @read_page:  function to read a page according to the ecc generator requirements
+ * @read_subpage:       function to read parts of the page covered by ECC.
  * @write_page: function to write a page according to the ecc generator requirements
  * @read_oob:   function to read chip OOB data
  * @write_oob:  function to write chip OOB data
diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h
index d1b310c92eb4..0c6bbe28f38c 100644
--- a/include/linux/mtd/onenand_regs.h
+++ b/include/linux/mtd/onenand_regs.h
@@ -152,6 +152,8 @@
 #define ONENAND_SYS_CFG1_INT            (1 << 6)
 #define ONENAND_SYS_CFG1_IOBE           (1 << 5)
 #define ONENAND_SYS_CFG1_RDY_CONF       (1 << 4)
+#define ONENAND_SYS_CFG1_HF             (1 << 2)
+#define ONENAND_SYS_CFG1_SYNC_WRITE     (1 << 1)
 
 /*
  * Controller Status Register F240h (R)
diff --git a/include/linux/mtd/partitions.h b/include/linux/mtd/partitions.h
index 5014f7a9f5df..c92b4d439609 100644
--- a/include/linux/mtd/partitions.h
+++ b/include/linux/mtd/partitions.h
@@ -73,7 +73,6 @@ struct device;
 struct device_node;
 
 int __devinit of_mtd_parse_partitions(struct device *dev,
-                                      struct mtd_info *mtd,
                                       struct device_node *node,
                                       struct mtd_partition **pparts);
 
diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
new file mode 100644
index 000000000000..e77c1cea404d
--- /dev/null
+++ b/include/linux/mtd/sh_flctl.h
@@ -0,0 +1,125 @@
+/*
+ * SuperH FLCTL nand controller
+ *
+ * Copyright © 2008 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __SH_FLCTL_H__
+#define __SH_FLCTL_H__
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+
+/* FLCTL registers */
+#define FLCMNCR(f)              (f->reg + 0x0)
+#define FLCMDCR(f)              (f->reg + 0x4)
+#define FLCMCDR(f)              (f->reg + 0x8)
+#define FLADR(f)                (f->reg + 0xC)
+#define FLADR2(f)               (f->reg + 0x3C)
+#define FLDATAR(f)              (f->reg + 0x10)
+#define FLDTCNTR(f)             (f->reg + 0x14)
+#define FLINTDMACR(f)           (f->reg + 0x18)
+#define FLBSYTMR(f)             (f->reg + 0x1C)
+#define FLBSYCNT(f)             (f->reg + 0x20)
+#define FLDTFIFO(f)             (f->reg + 0x24)
+#define FLECFIFO(f)             (f->reg + 0x28)
+#define FLTRCR(f)               (f->reg + 0x2C)
+#define FL4ECCRESULT0(f)        (f->reg + 0x80)
+#define FL4ECCRESULT1(f)        (f->reg + 0x84)
+#define FL4ECCRESULT2(f)        (f->reg + 0x88)
+#define FL4ECCRESULT3(f)        (f->reg + 0x8C)
+#define FL4ECCCR(f)             (f->reg + 0x90)
+#define FL4ECCCNT(f)            (f->reg + 0x94)
+#define FLERRADR(f)             (f->reg + 0x98)
+
+/* FLCMNCR control bits */
+#define ECCPOS2         (0x1 << 25)
+#define _4ECCCNTEN      (0x1 << 24)
+#define _4ECCEN         (0x1 << 23)
+#define _4ECCCORRECT    (0x1 << 22)
+#define SNAND_E         (0x1 << 18)     /* SNAND (0=512 1=2048)*/
+#define QTSEL_E         (0x1 << 17)
+#define ENDIAN          (0x1 << 16)     /* 1 = little endian */
+#define FCKSEL_E        (0x1 << 15)
+#define ECCPOS_00       (0x00 << 12)
+#define ECCPOS_01       (0x01 << 12)
+#define ECCPOS_02       (0x02 << 12)
+#define ACM_SACCES_MODE (0x01 << 10)
+#define NANWF_E         (0x1 << 9)
+#define SE_D            (0x1 << 8)      /* Spare area disable */
+#define CE1_ENABLE      (0x1 << 4)      /* Chip Enable 1 */
+#define CE0_ENABLE      (0x1 << 3)      /* Chip Enable 0 */
+#define TYPESEL_SET     (0x1 << 0)
+
+/* FLCMDCR control bits */
+#define ADRCNT2_E       (0x1 << 31)     /* 5byte address enable */
+#define ADRMD_E         (0x1 << 26)     /* Sector address access */
+#define CDSRC_E         (0x1 << 25)     /* Data buffer selection */
+#define DOSR_E          (0x1 << 24)     /* Status read check */
+#define SELRW           (0x1 << 21)     /*  0:read 1:write */
+#define DOADR_E         (0x1 << 20)     /* Address stage execute */
+#define ADRCNT_1        (0x00 << 18)    /* Address data bytes: 1byte */
+#define ADRCNT_2        (0x01 << 18)    /* Address data bytes: 2byte */
+#define ADRCNT_3        (0x02 << 18)    /* Address data bytes: 3byte */
+#define ADRCNT_4        (0x03 << 18)    /* Address data bytes: 4byte */
+#define DOCMD2_E        (0x1 << 17)     /* 2nd cmd stage execute */
+#define DOCMD1_E        (0x1 << 16)     /* 1st cmd stage execute */
+
+/* FLTRCR control bits */
+#define TRSTRT          (0x1 << 0)      /* translation start */
+#define TREND           (0x1 << 1)      /* translation end */
+
+/* FL4ECCCR control bits */
+#define _4ECCFA         (0x1 << 2)      /* 4 symbols correct fault */
+#define _4ECCEND        (0x1 << 1)      /* 4 symbols end */
+#define _4ECCEXST       (0x1 << 0)      /* 4 symbols exist */
+
+#define INIT_FL4ECCRESULT_VAL   0x03FF03FF
+#define LOOP_TIMEOUT_MAX        0x00010000
+
+#define mtd_to_flctl(mtd)       container_of(mtd, struct sh_flctl, mtd)
+
+struct sh_flctl {
+        struct mtd_info         mtd;
+        struct nand_chip        chip;
+        void __iomem            *reg;
+
+        uint8_t done_buff[2048 + 64];   /* max size 2048 + 64 */
+        int     read_bytes;
+        int     index;
+        int     seqin_column;           /* column in SEQIN cmd */
+        int     seqin_page_addr;        /* page_addr in SEQIN cmd */
+        uint32_t seqin_read_cmd;                /* read cmd in SEQIN cmd */
+        int     erase1_page_addr;       /* page_addr in ERASE1 cmd */
+        uint32_t erase_ADRCNT;          /* bits of FLCMDCR in ERASE1 cmd */
+        uint32_t rw_ADRCNT;     /* bits of FLCMDCR in READ WRITE cmd */
+
+        int     hwecc_cant_correct[4];
+
+        unsigned page_size:1;   /* NAND page size (0 = 512, 1 = 2048) */
+        unsigned hwecc:1;       /* Hardware ECC (0 = disabled, 1 = enabled) */
+};
+
+struct sh_flctl_platform_data {
+        struct mtd_partition    *parts;
+        int                     nr_parts;
+        unsigned long           flcmncr_val;
+
+        unsigned has_hwecc:1;
+};
+
+#endif  /* __SH_FLCTL_H__ */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 98dc6243a706..acf8f24037cd 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -631,6 +631,8 @@ int __must_check pci_assign_resource(struct pci_dev *dev, int i);
 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
 
 /* ROM control related routines */
+int pci_enable_rom(struct pci_dev *pdev);
+void pci_disable_rom(struct pci_dev *pdev);
 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
 size_t pci_get_rom_size(void __iomem *rom, size_t size);