diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-10-30 18:30:01 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-10-30 18:30:01 -0400 |
commit | acff987d94cbdb4049f3706bed1f1792f8ef6837 (patch) | |
tree | 36bded977aab5d80cf9aeb5467f83dd554a25d01 /include | |
parent | ce949717b559709423c1ef716a9db16d1dcadaed (diff) | |
parent | b57287ba497b63a0d87a058631bbddfed9392e9f (diff) |
Merge branch 'fbdev-next' of git://github.com/schandinat/linux-2.6
* 'fbdev-next' of git://github.com/schandinat/linux-2.6: (270 commits)
video: platinumfb: Add __devexit_p at necessary place
drivers/video: fsl-diu-fb: merge diu_pool into fsl_diu_data
drivers/video: fsl-diu-fb: merge diu_hw into fsl_diu_data
drivers/video: fsl-diu-fb: only DIU modes 0 and 1 are supported
drivers/video: fsl-diu-fb: remove unused panel operating mode support
drivers/video: fsl-diu-fb: use an enum for the AOI index
drivers/video: fsl-diu-fb: add several new video modes
drivers/video: fsl-diu-fb: remove broken screen blanking support
drivers/video: fsl-diu-fb: move some definitions out of the header file
drivers/video: fsl-diu-fb: fix some ioctls
video: da8xx-fb: Increased resolution configuration of revised LCDC IP
OMAPDSS: picodlp: add missing #include <linux/module.h>
fb: fix au1100fb bitrot.
mx3fb: fix NULL pointer dereference in screen blanking.
video: irq: Remove IRQF_DISABLED
smscufx: change edid data to u8 instead of char
OMAPDSS: DISPC: zorder support for DSS overlays
OMAPDSS: DISPC: VIDEO3 pipeline support
OMAPDSS/OMAP_VOUT: Fix incorrect OMAP3-alpha compatibility setting
video/omap: fix build dependencies
...
Fix up conflicts in:
- drivers/staging/xgifb/XGI_main_26.c
Changes to XGIfb_pan_var()
- drivers/video/omap/{lcd_apollon.c,lcd_ldp.c,lcd_overo.c}
Removed (or in the case of apollon.c, merged into the generic
DSS panel in drivers/video/omap2/displays/panel-generic-dpi.c)
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/fsl-diu-fb.h | 92 | ||||
-rw-r--r-- | include/video/omap-panel-dvi.h | 37 | ||||
-rw-r--r-- | include/video/omap-panel-n8x0.h | 15 | ||||
-rw-r--r-- | include/video/omap-panel-nokia-dsi.h | 8 | ||||
-rw-r--r-- | include/video/omap-panel-picodlp.h | 23 | ||||
-rw-r--r-- | include/video/omapdss.h | 100 | ||||
-rw-r--r-- | include/video/sh_mobile_lcdc.h | 135 | ||||
-rw-r--r-- | include/video/udlfb.h | 1 |
8 files changed, 300 insertions, 111 deletions
diff --git a/include/linux/fsl-diu-fb.h b/include/linux/fsl-diu-fb.h index daa9952d2174..11c16a1fb9e3 100644 --- a/include/linux/fsl-diu-fb.h +++ b/include/linux/fsl-diu-fb.h | |||
@@ -20,18 +20,8 @@ | |||
20 | #ifndef __FSL_DIU_FB_H__ | 20 | #ifndef __FSL_DIU_FB_H__ |
21 | #define __FSL_DIU_FB_H__ | 21 | #define __FSL_DIU_FB_H__ |
22 | 22 | ||
23 | /* Arbitrary threshold to determine the allocation method | ||
24 | * See mpc8610fb_set_par(), map_video_memory(), and unmap_video_memory() | ||
25 | */ | ||
26 | #define MEM_ALLOC_THRESHOLD (1024*768*4+32) | ||
27 | |||
28 | #include <linux/types.h> | 23 | #include <linux/types.h> |
29 | 24 | ||
30 | struct mfb_alpha { | ||
31 | int enable; | ||
32 | int alpha; | ||
33 | }; | ||
34 | |||
35 | struct mfb_chroma_key { | 25 | struct mfb_chroma_key { |
36 | int enable; | 26 | int enable; |
37 | __u8 red_max; | 27 | __u8 red_max; |
@@ -43,25 +33,29 @@ struct mfb_chroma_key { | |||
43 | }; | 33 | }; |
44 | 34 | ||
45 | struct aoi_display_offset { | 35 | struct aoi_display_offset { |
46 | int x_aoi_d; | 36 | __s32 x_aoi_d; |
47 | int y_aoi_d; | 37 | __s32 y_aoi_d; |
48 | }; | 38 | }; |
49 | 39 | ||
50 | #define MFB_SET_CHROMA_KEY _IOW('M', 1, struct mfb_chroma_key) | 40 | #define MFB_SET_CHROMA_KEY _IOW('M', 1, struct mfb_chroma_key) |
51 | #define MFB_SET_BRIGHTNESS _IOW('M', 3, __u8) | 41 | #define MFB_SET_BRIGHTNESS _IOW('M', 3, __u8) |
42 | #define MFB_SET_ALPHA _IOW('M', 0, __u8) | ||
43 | #define MFB_GET_ALPHA _IOR('M', 0, __u8) | ||
44 | #define MFB_SET_AOID _IOW('M', 4, struct aoi_display_offset) | ||
45 | #define MFB_GET_AOID _IOR('M', 4, struct aoi_display_offset) | ||
46 | #define MFB_SET_PIXFMT _IOW('M', 8, __u32) | ||
47 | #define MFB_GET_PIXFMT _IOR('M', 8, __u32) | ||
52 | 48 | ||
53 | #define MFB_SET_ALPHA 0x80014d00 | 49 | /* |
54 | #define MFB_GET_ALPHA 0x40014d00 | 50 | * The original definitions of MFB_SET_PIXFMT and MFB_GET_PIXFMT used the |
55 | #define MFB_SET_AOID 0x80084d04 | 51 | * wrong value for 'size' field of the ioctl. The current macros above use the |
56 | #define MFB_GET_AOID 0x40084d04 | 52 | * right size, but we still need to provide backwards compatibility, at least |
57 | #define MFB_SET_PIXFMT 0x80014d08 | 53 | * for a while. |
58 | #define MFB_GET_PIXFMT 0x40014d08 | 54 | */ |
59 | 55 | #define MFB_SET_PIXFMT_OLD 0x80014d08 | |
60 | #define FBIOGET_GWINFO 0x46E0 | 56 | #define MFB_GET_PIXFMT_OLD 0x40014d08 |
61 | #define FBIOPUT_GWINFO 0x46E1 | ||
62 | 57 | ||
63 | #ifdef __KERNEL__ | 58 | #ifdef __KERNEL__ |
64 | #include <linux/spinlock.h> | ||
65 | 59 | ||
66 | /* | 60 | /* |
67 | * These are the fields of area descriptor(in DDR memory) for every plane | 61 | * These are the fields of area descriptor(in DDR memory) for every plane |
@@ -159,58 +153,12 @@ struct diu { | |||
159 | __be32 plut; | 153 | __be32 plut; |
160 | } __attribute__ ((packed)); | 154 | } __attribute__ ((packed)); |
161 | 155 | ||
162 | struct diu_hw { | 156 | /* |
163 | struct diu *diu_reg; | 157 | * Modes of operation of DIU. The DIU supports five different modes, but |
164 | spinlock_t reg_lock; | 158 | * the driver only supports modes 0 and 1. |
165 | 159 | */ | |
166 | __u32 mode; /* DIU operation mode */ | ||
167 | }; | ||
168 | |||
169 | struct diu_addr { | ||
170 | __u8 __iomem *vaddr; /* Virtual address */ | ||
171 | dma_addr_t paddr; /* Physical address */ | ||
172 | __u32 offset; | ||
173 | }; | ||
174 | |||
175 | struct diu_pool { | ||
176 | struct diu_addr ad; | ||
177 | struct diu_addr gamma; | ||
178 | struct diu_addr pallete; | ||
179 | struct diu_addr cursor; | ||
180 | }; | ||
181 | |||
182 | #define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of DIU */ | ||
183 | #define INT_LCDC 64 /* DIU interrupt number */ | ||
184 | |||
185 | #define FSL_AOI_NUM 6 /* 5 AOIs and one dummy AOI */ | ||
186 | /* 1 for plane 0, 2 for plane 1&2 each */ | ||
187 | |||
188 | /* Minimum X and Y resolutions */ | ||
189 | #define MIN_XRES 64 | ||
190 | #define MIN_YRES 64 | ||
191 | |||
192 | /* HW cursor parameters */ | ||
193 | #define MAX_CURS 32 | ||
194 | |||
195 | /* Modes of operation of DIU */ | ||
196 | #define MFB_MODE0 0 /* DIU off */ | 160 | #define MFB_MODE0 0 /* DIU off */ |
197 | #define MFB_MODE1 1 /* All three planes output to display */ | 161 | #define MFB_MODE1 1 /* All three planes output to display */ |
198 | #define MFB_MODE2 2 /* Plane 1 to display, planes 2+3 written back*/ | ||
199 | #define MFB_MODE3 3 /* All three planes written back to memory */ | ||
200 | #define MFB_MODE4 4 /* Color bar generation */ | ||
201 | |||
202 | /* INT_STATUS/INT_MASK field descriptions */ | ||
203 | #define INT_VSYNC 0x01 /* Vsync interrupt */ | ||
204 | #define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */ | ||
205 | #define INT_UNDRUN 0x04 /* Under run exception interrupt */ | ||
206 | #define INT_PARERR 0x08 /* Display parameters error interrupt */ | ||
207 | #define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */ | ||
208 | |||
209 | /* Panels'operation modes */ | ||
210 | #define MFB_TYPE_OUTPUT 0 /* Panel output to display */ | ||
211 | #define MFB_TYPE_OFF 1 /* Panel off */ | ||
212 | #define MFB_TYPE_WB 2 /* Panel written back to memory */ | ||
213 | #define MFB_TYPE_TEST 3 /* Panel generate color bar */ | ||
214 | 162 | ||
215 | #endif /* __KERNEL__ */ | 163 | #endif /* __KERNEL__ */ |
216 | #endif /* __FSL_DIU_FB_H__ */ | 164 | #endif /* __FSL_DIU_FB_H__ */ |
diff --git a/include/video/omap-panel-dvi.h b/include/video/omap-panel-dvi.h new file mode 100644 index 000000000000..87ad567b4229 --- /dev/null +++ b/include/video/omap-panel-dvi.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /* | ||
2 | * Header for DVI output driver | ||
3 | * | ||
4 | * Copyright (C) 2011 Texas Instruments Inc | ||
5 | * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License version 2 as published by | ||
9 | * the Free Software Foundation. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
14 | * more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License along with | ||
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | ||
18 | */ | ||
19 | |||
20 | #ifndef __OMAP_PANEL_DVI_H | ||
21 | #define __OMAP_PANEL_DVI_H | ||
22 | |||
23 | struct omap_dss_device; | ||
24 | |||
25 | /** | ||
26 | * struct panel_dvi_platform_data - panel driver configuration data | ||
27 | * @platform_enable: platform specific panel enable function | ||
28 | * @platform_disable: platform specific panel disable function | ||
29 | * @i2c_bus_num: i2c bus id for the panel | ||
30 | */ | ||
31 | struct panel_dvi_platform_data { | ||
32 | int (*platform_enable)(struct omap_dss_device *dssdev); | ||
33 | void (*platform_disable)(struct omap_dss_device *dssdev); | ||
34 | u16 i2c_bus_num; | ||
35 | }; | ||
36 | |||
37 | #endif /* __OMAP_PANEL_DVI_H */ | ||
diff --git a/include/video/omap-panel-n8x0.h b/include/video/omap-panel-n8x0.h new file mode 100644 index 000000000000..50a1302e2cfd --- /dev/null +++ b/include/video/omap-panel-n8x0.h | |||
@@ -0,0 +1,15 @@ | |||
1 | #ifndef __OMAP_PANEL_N8X0_H | ||
2 | #define __OMAP_PANEL_N8X0_H | ||
3 | |||
4 | struct omap_dss_device; | ||
5 | |||
6 | struct panel_n8x0_data { | ||
7 | int (*platform_enable)(struct omap_dss_device *dssdev); | ||
8 | void (*platform_disable)(struct omap_dss_device *dssdev); | ||
9 | int panel_reset; | ||
10 | int ctrl_pwrdown; | ||
11 | |||
12 | int (*set_backlight)(struct omap_dss_device *dssdev, int level); | ||
13 | }; | ||
14 | |||
15 | #endif | ||
diff --git a/include/video/omap-panel-nokia-dsi.h b/include/video/omap-panel-nokia-dsi.h index 921ae9327228..7dc71f9c13e6 100644 --- a/include/video/omap-panel-nokia-dsi.h +++ b/include/video/omap-panel-nokia-dsi.h | |||
@@ -10,9 +10,7 @@ struct omap_dss_device; | |||
10 | * @ext_te_gpio: external TE GPIO | 10 | * @ext_te_gpio: external TE GPIO |
11 | * @esd_interval: interval of ESD checks, 0 = disabled (ms) | 11 | * @esd_interval: interval of ESD checks, 0 = disabled (ms) |
12 | * @ulps_timeout: time to wait before entering ULPS, 0 = disabled (ms) | 12 | * @ulps_timeout: time to wait before entering ULPS, 0 = disabled (ms) |
13 | * @max_backlight_level: maximum backlight level | 13 | * @use_dsi_backlight: true if panel uses DSI command to control backlight |
14 | * @set_backlight: pointer to backlight set function | ||
15 | * @get_backlight: pointer to backlight get function | ||
16 | */ | 14 | */ |
17 | struct nokia_dsi_panel_data { | 15 | struct nokia_dsi_panel_data { |
18 | const char *name; | 16 | const char *name; |
@@ -25,9 +23,7 @@ struct nokia_dsi_panel_data { | |||
25 | unsigned esd_interval; | 23 | unsigned esd_interval; |
26 | unsigned ulps_timeout; | 24 | unsigned ulps_timeout; |
27 | 25 | ||
28 | int max_backlight_level; | 26 | bool use_dsi_backlight; |
29 | int (*set_backlight)(struct omap_dss_device *dssdev, int level); | ||
30 | int (*get_backlight)(struct omap_dss_device *dssdev); | ||
31 | }; | 27 | }; |
32 | 28 | ||
33 | #endif /* __OMAP_NOKIA_DSI_PANEL_H */ | 29 | #endif /* __OMAP_NOKIA_DSI_PANEL_H */ |
diff --git a/include/video/omap-panel-picodlp.h b/include/video/omap-panel-picodlp.h new file mode 100644 index 000000000000..1c342ef6f3a1 --- /dev/null +++ b/include/video/omap-panel-picodlp.h | |||
@@ -0,0 +1,23 @@ | |||
1 | /* | ||
2 | * panel data for picodlp panel | ||
3 | * | ||
4 | * Copyright (C) 2011 Texas Instruments | ||
5 | * | ||
6 | * Author: Mayuresh Janorkar <mayur@ti.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | #ifndef __PANEL_PICODLP_H | ||
13 | #define __PANEL_PICODLP_H | ||
14 | /** | ||
15 | * struct : picodlp panel data | ||
16 | * picodlp_adapter_id: i2c_adapter number for picodlp | ||
17 | */ | ||
18 | struct picodlp_panel_data { | ||
19 | int picodlp_adapter_id; | ||
20 | int emu_done_gpio; | ||
21 | int pwrgood_gpio; | ||
22 | }; | ||
23 | #endif /* __PANEL_PICODLP_H */ | ||
diff --git a/include/video/omapdss.h b/include/video/omapdss.h index 3b55ef22f8db..b66ebb2032c6 100644 --- a/include/video/omapdss.h +++ b/include/video/omapdss.h | |||
@@ -41,8 +41,13 @@ | |||
41 | #define DISPC_IRQ_WAKEUP (1 << 16) | 41 | #define DISPC_IRQ_WAKEUP (1 << 16) |
42 | #define DISPC_IRQ_SYNC_LOST2 (1 << 17) | 42 | #define DISPC_IRQ_SYNC_LOST2 (1 << 17) |
43 | #define DISPC_IRQ_VSYNC2 (1 << 18) | 43 | #define DISPC_IRQ_VSYNC2 (1 << 18) |
44 | #define DISPC_IRQ_VID3_END_WIN (1 << 19) | ||
45 | #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) | ||
44 | #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) | 46 | #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) |
45 | #define DISPC_IRQ_FRAMEDONE2 (1 << 22) | 47 | #define DISPC_IRQ_FRAMEDONE2 (1 << 22) |
48 | #define DISPC_IRQ_FRAMEDONEWB (1 << 23) | ||
49 | #define DISPC_IRQ_FRAMEDONETV (1 << 24) | ||
50 | #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) | ||
46 | 51 | ||
47 | struct omap_dss_device; | 52 | struct omap_dss_device; |
48 | struct omap_overlay_manager; | 53 | struct omap_overlay_manager; |
@@ -60,7 +65,8 @@ enum omap_display_type { | |||
60 | enum omap_plane { | 65 | enum omap_plane { |
61 | OMAP_DSS_GFX = 0, | 66 | OMAP_DSS_GFX = 0, |
62 | OMAP_DSS_VIDEO1 = 1, | 67 | OMAP_DSS_VIDEO1 = 1, |
63 | OMAP_DSS_VIDEO2 = 2 | 68 | OMAP_DSS_VIDEO2 = 2, |
69 | OMAP_DSS_VIDEO3 = 3, | ||
64 | }; | 70 | }; |
65 | 71 | ||
66 | enum omap_channel { | 72 | enum omap_channel { |
@@ -129,6 +135,18 @@ enum omap_dss_venc_type { | |||
129 | OMAP_DSS_VENC_TYPE_SVIDEO, | 135 | OMAP_DSS_VENC_TYPE_SVIDEO, |
130 | }; | 136 | }; |
131 | 137 | ||
138 | enum omap_dss_dsi_pixel_format { | ||
139 | OMAP_DSS_DSI_FMT_RGB888, | ||
140 | OMAP_DSS_DSI_FMT_RGB666, | ||
141 | OMAP_DSS_DSI_FMT_RGB666_PACKED, | ||
142 | OMAP_DSS_DSI_FMT_RGB565, | ||
143 | }; | ||
144 | |||
145 | enum omap_dss_dsi_mode { | ||
146 | OMAP_DSS_DSI_CMD_MODE = 0, | ||
147 | OMAP_DSS_DSI_VIDEO_MODE, | ||
148 | }; | ||
149 | |||
132 | enum omap_display_caps { | 150 | enum omap_display_caps { |
133 | OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0, | 151 | OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0, |
134 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1, | 152 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1, |
@@ -162,11 +180,13 @@ enum omap_dss_rotation_angle { | |||
162 | 180 | ||
163 | enum omap_overlay_caps { | 181 | enum omap_overlay_caps { |
164 | OMAP_DSS_OVL_CAP_SCALE = 1 << 0, | 182 | OMAP_DSS_OVL_CAP_SCALE = 1 << 0, |
165 | OMAP_DSS_OVL_CAP_DISPC = 1 << 1, | 183 | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1, |
184 | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2, | ||
185 | OMAP_DSS_OVL_CAP_ZORDER = 1 << 3, | ||
166 | }; | 186 | }; |
167 | 187 | ||
168 | enum omap_overlay_manager_caps { | 188 | enum omap_overlay_manager_caps { |
169 | OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0, | 189 | OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */ |
170 | }; | 190 | }; |
171 | 191 | ||
172 | enum omap_dss_clk_source { | 192 | enum omap_dss_clk_source { |
@@ -215,26 +235,67 @@ void rfbi_bus_lock(void); | |||
215 | void rfbi_bus_unlock(void); | 235 | void rfbi_bus_unlock(void); |
216 | 236 | ||
217 | /* DSI */ | 237 | /* DSI */ |
238 | |||
239 | struct omap_dss_dsi_videomode_data { | ||
240 | /* DSI video mode blanking data */ | ||
241 | /* Unit: byte clock cycles */ | ||
242 | u16 hsa; | ||
243 | u16 hfp; | ||
244 | u16 hbp; | ||
245 | /* Unit: line clocks */ | ||
246 | u16 vsa; | ||
247 | u16 vfp; | ||
248 | u16 vbp; | ||
249 | |||
250 | /* DSI blanking modes */ | ||
251 | int blanking_mode; | ||
252 | int hsa_blanking_mode; | ||
253 | int hbp_blanking_mode; | ||
254 | int hfp_blanking_mode; | ||
255 | |||
256 | /* Video port sync events */ | ||
257 | int vp_de_pol; | ||
258 | int vp_hsync_pol; | ||
259 | int vp_vsync_pol; | ||
260 | bool vp_vsync_end; | ||
261 | bool vp_hsync_end; | ||
262 | |||
263 | bool ddr_clk_always_on; | ||
264 | int window_sync; | ||
265 | }; | ||
266 | |||
218 | void dsi_bus_lock(struct omap_dss_device *dssdev); | 267 | void dsi_bus_lock(struct omap_dss_device *dssdev); |
219 | void dsi_bus_unlock(struct omap_dss_device *dssdev); | 268 | void dsi_bus_unlock(struct omap_dss_device *dssdev); |
220 | int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, | 269 | int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
221 | int len); | 270 | int len); |
222 | int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, | 271 | int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
223 | u8 dcs_cmd); | 272 | int len); |
273 | int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd); | ||
274 | int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel); | ||
224 | int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, | 275 | int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
225 | u8 param); | 276 | u8 param); |
277 | int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel, | ||
278 | u8 param); | ||
279 | int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel, | ||
280 | u8 param1, u8 param2); | ||
226 | int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, | 281 | int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, |
227 | u8 *data, int len); | 282 | u8 *data, int len); |
283 | int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, | ||
284 | u8 *data, int len); | ||
228 | int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, | 285 | int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
229 | u8 *buf, int buflen); | 286 | u8 *buf, int buflen); |
230 | int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, | 287 | int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf, |
231 | u8 *data); | 288 | int buflen); |
232 | int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, | 289 | int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param, |
233 | u8 *data1, u8 *data2); | 290 | u8 *buf, int buflen); |
291 | int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel, | ||
292 | u8 param1, u8 param2, u8 *buf, int buflen); | ||
234 | int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, | 293 | int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, |
235 | u16 len); | 294 | u16 len); |
236 | int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); | 295 | int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); |
237 | int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel); | 296 | int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel); |
297 | int dsi_video_mode_enable(struct omap_dss_device *dssdev, int channel); | ||
298 | void dsi_video_mode_disable(struct omap_dss_device *dssdev, int channel); | ||
238 | 299 | ||
239 | /* Board specific data */ | 300 | /* Board specific data */ |
240 | struct omap_dss_board_info { | 301 | struct omap_dss_board_info { |
@@ -242,7 +303,8 @@ struct omap_dss_board_info { | |||
242 | int num_devices; | 303 | int num_devices; |
243 | struct omap_dss_device **devices; | 304 | struct omap_dss_device **devices; |
244 | struct omap_dss_device *default_device; | 305 | struct omap_dss_device *default_device; |
245 | void (*dsi_mux_pads)(bool enable); | 306 | int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask); |
307 | void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask); | ||
246 | }; | 308 | }; |
247 | 309 | ||
248 | #if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS) | 310 | #if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS) |
@@ -300,7 +362,6 @@ struct omap_overlay_info { | |||
300 | bool enabled; | 362 | bool enabled; |
301 | 363 | ||
302 | u32 paddr; | 364 | u32 paddr; |
303 | void __iomem *vaddr; | ||
304 | u32 p_uv_addr; /* for NV12 format */ | 365 | u32 p_uv_addr; /* for NV12 format */ |
305 | u16 screen_width; | 366 | u16 screen_width; |
306 | u16 width; | 367 | u16 width; |
@@ -316,6 +377,7 @@ struct omap_overlay_info { | |||
316 | u16 out_height; /* if 0, out_height == height */ | 377 | u16 out_height; /* if 0, out_height == height */ |
317 | u8 global_alpha; | 378 | u8 global_alpha; |
318 | u8 pre_mult_alpha; | 379 | u8 pre_mult_alpha; |
380 | u8 zorder; | ||
319 | }; | 381 | }; |
320 | 382 | ||
321 | struct omap_overlay { | 383 | struct omap_overlay { |
@@ -324,7 +386,7 @@ struct omap_overlay { | |||
324 | 386 | ||
325 | /* static fields */ | 387 | /* static fields */ |
326 | const char *name; | 388 | const char *name; |
327 | int id; | 389 | enum omap_plane id; |
328 | enum omap_color_mode supported_modes; | 390 | enum omap_color_mode supported_modes; |
329 | enum omap_overlay_caps caps; | 391 | enum omap_overlay_caps caps; |
330 | 392 | ||
@@ -332,6 +394,7 @@ struct omap_overlay { | |||
332 | struct omap_overlay_manager *manager; | 394 | struct omap_overlay_manager *manager; |
333 | struct omap_overlay_info info; | 395 | struct omap_overlay_info info; |
334 | 396 | ||
397 | bool manager_changed; | ||
335 | /* if true, info has been changed, but not applied() yet */ | 398 | /* if true, info has been changed, but not applied() yet */ |
336 | bool info_dirty; | 399 | bool info_dirty; |
337 | 400 | ||
@@ -354,7 +417,7 @@ struct omap_overlay_manager_info { | |||
354 | u32 trans_key; | 417 | u32 trans_key; |
355 | bool trans_enabled; | 418 | bool trans_enabled; |
356 | 419 | ||
357 | bool alpha_enabled; | 420 | bool partial_alpha_enabled; |
358 | 421 | ||
359 | bool cpr_enable; | 422 | bool cpr_enable; |
360 | struct omap_dss_cpr_coefs cpr_coefs; | 423 | struct omap_dss_cpr_coefs cpr_coefs; |
@@ -366,7 +429,7 @@ struct omap_overlay_manager { | |||
366 | 429 | ||
367 | /* static fields */ | 430 | /* static fields */ |
368 | const char *name; | 431 | const char *name; |
369 | int id; | 432 | enum omap_channel id; |
370 | enum omap_overlay_manager_caps caps; | 433 | enum omap_overlay_manager_caps caps; |
371 | int num_overlays; | 434 | int num_overlays; |
372 | struct omap_overlay **overlays; | 435 | struct omap_overlay **overlays; |
@@ -454,6 +517,7 @@ struct omap_dss_device { | |||
454 | } dispc; | 517 | } dispc; |
455 | 518 | ||
456 | struct { | 519 | struct { |
520 | /* regn is one greater than TRM's REGN value */ | ||
457 | u16 regn; | 521 | u16 regn; |
458 | u16 regm; | 522 | u16 regm; |
459 | u16 regm_dispc; | 523 | u16 regm_dispc; |
@@ -464,6 +528,7 @@ struct omap_dss_device { | |||
464 | } dsi; | 528 | } dsi; |
465 | 529 | ||
466 | struct { | 530 | struct { |
531 | /* regn is one greater than TRM's REGN value */ | ||
467 | u16 regn; | 532 | u16 regn; |
468 | u16 regm2; | 533 | u16 regm2; |
469 | } hdmi; | 534 | } hdmi; |
@@ -477,6 +542,10 @@ struct omap_dss_device { | |||
477 | int acb; /* ac-bias pin frequency */ | 542 | int acb; /* ac-bias pin frequency */ |
478 | 543 | ||
479 | enum omap_panel_config config; | 544 | enum omap_panel_config config; |
545 | |||
546 | enum omap_dss_dsi_pixel_format dsi_pix_fmt; | ||
547 | enum omap_dss_dsi_mode dsi_mode; | ||
548 | struct omap_dss_dsi_videomode_data dsi_vm_data; | ||
480 | } panel; | 549 | } panel; |
481 | 550 | ||
482 | struct { | 551 | struct { |
@@ -557,6 +626,9 @@ struct omap_dss_driver { | |||
557 | 626 | ||
558 | int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); | 627 | int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); |
559 | u32 (*get_wss)(struct omap_dss_device *dssdev); | 628 | u32 (*get_wss)(struct omap_dss_device *dssdev); |
629 | |||
630 | int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); | ||
631 | bool (*detect)(struct omap_dss_device *dssdev); | ||
560 | }; | 632 | }; |
561 | 633 | ||
562 | int omap_dss_register_driver(struct omap_dss_driver *); | 634 | int omap_dss_register_driver(struct omap_dss_driver *); |
diff --git a/include/video/sh_mobile_lcdc.h b/include/video/sh_mobile_lcdc.h index d964e68fc61d..8101b726b48a 100644 --- a/include/video/sh_mobile_lcdc.h +++ b/include/video/sh_mobile_lcdc.h | |||
@@ -4,26 +4,123 @@ | |||
4 | #include <linux/fb.h> | 4 | #include <linux/fb.h> |
5 | #include <video/sh_mobile_meram.h> | 5 | #include <video/sh_mobile_meram.h> |
6 | 6 | ||
7 | /* Register definitions */ | ||
8 | #define _LDDCKR 0x410 | ||
9 | #define LDDCKR_ICKSEL_BUS (0 << 16) | ||
10 | #define LDDCKR_ICKSEL_MIPI (1 << 16) | ||
11 | #define LDDCKR_ICKSEL_HDMI (2 << 16) | ||
12 | #define LDDCKR_ICKSEL_EXT (3 << 16) | ||
13 | #define LDDCKR_ICKSEL_MASK (7 << 16) | ||
14 | #define LDDCKR_MOSEL (1 << 6) | ||
15 | #define _LDDCKSTPR 0x414 | ||
16 | #define _LDINTR 0x468 | ||
17 | #define LDINTR_FE (1 << 10) | ||
18 | #define LDINTR_VSE (1 << 9) | ||
19 | #define LDINTR_VEE (1 << 8) | ||
20 | #define LDINTR_FS (1 << 2) | ||
21 | #define LDINTR_VSS (1 << 1) | ||
22 | #define LDINTR_VES (1 << 0) | ||
23 | #define LDINTR_STATUS_MASK (0xff << 0) | ||
24 | #define _LDSR 0x46c | ||
25 | #define LDSR_MSS (1 << 10) | ||
26 | #define LDSR_MRS (1 << 8) | ||
27 | #define LDSR_AS (1 << 1) | ||
28 | #define _LDCNT1R 0x470 | ||
29 | #define LDCNT1R_DE (1 << 0) | ||
30 | #define _LDCNT2R 0x474 | ||
31 | #define LDCNT2R_BR (1 << 8) | ||
32 | #define LDCNT2R_MD (1 << 3) | ||
33 | #define LDCNT2R_SE (1 << 2) | ||
34 | #define LDCNT2R_ME (1 << 1) | ||
35 | #define LDCNT2R_DO (1 << 0) | ||
36 | #define _LDRCNTR 0x478 | ||
37 | #define LDRCNTR_SRS (1 << 17) | ||
38 | #define LDRCNTR_SRC (1 << 16) | ||
39 | #define LDRCNTR_MRS (1 << 1) | ||
40 | #define LDRCNTR_MRC (1 << 0) | ||
41 | #define _LDDDSR 0x47c | ||
42 | #define LDDDSR_LS (1 << 2) | ||
43 | #define LDDDSR_WS (1 << 1) | ||
44 | #define LDDDSR_BS (1 << 0) | ||
45 | |||
46 | #define LDMT1R_VPOL (1 << 28) | ||
47 | #define LDMT1R_HPOL (1 << 27) | ||
48 | #define LDMT1R_DWPOL (1 << 26) | ||
49 | #define LDMT1R_DIPOL (1 << 25) | ||
50 | #define LDMT1R_DAPOL (1 << 24) | ||
51 | #define LDMT1R_HSCNT (1 << 17) | ||
52 | #define LDMT1R_DWCNT (1 << 16) | ||
53 | #define LDMT1R_IFM (1 << 12) | ||
54 | #define LDMT1R_MIFTYP_RGB8 (0x0 << 0) | ||
55 | #define LDMT1R_MIFTYP_RGB9 (0x4 << 0) | ||
56 | #define LDMT1R_MIFTYP_RGB12A (0x5 << 0) | ||
57 | #define LDMT1R_MIFTYP_RGB12B (0x6 << 0) | ||
58 | #define LDMT1R_MIFTYP_RGB16 (0x7 << 0) | ||
59 | #define LDMT1R_MIFTYP_RGB18 (0xa << 0) | ||
60 | #define LDMT1R_MIFTYP_RGB24 (0xb << 0) | ||
61 | #define LDMT1R_MIFTYP_YCBCR (0xf << 0) | ||
62 | #define LDMT1R_MIFTYP_SYS8A (0x0 << 0) | ||
63 | #define LDMT1R_MIFTYP_SYS8B (0x1 << 0) | ||
64 | #define LDMT1R_MIFTYP_SYS8C (0x2 << 0) | ||
65 | #define LDMT1R_MIFTYP_SYS8D (0x3 << 0) | ||
66 | #define LDMT1R_MIFTYP_SYS9 (0x4 << 0) | ||
67 | #define LDMT1R_MIFTYP_SYS12 (0x5 << 0) | ||
68 | #define LDMT1R_MIFTYP_SYS16A (0x7 << 0) | ||
69 | #define LDMT1R_MIFTYP_SYS16B (0x8 << 0) | ||
70 | #define LDMT1R_MIFTYP_SYS16C (0x9 << 0) | ||
71 | #define LDMT1R_MIFTYP_SYS18 (0xa << 0) | ||
72 | #define LDMT1R_MIFTYP_SYS24 (0xb << 0) | ||
73 | #define LDMT1R_MIFTYP_MASK (0xf << 0) | ||
74 | |||
75 | #define LDDFR_CF1 (1 << 18) | ||
76 | #define LDDFR_CF0 (1 << 17) | ||
77 | #define LDDFR_CC (1 << 16) | ||
78 | #define LDDFR_YF_420 (0 << 8) | ||
79 | #define LDDFR_YF_422 (1 << 8) | ||
80 | #define LDDFR_YF_444 (2 << 8) | ||
81 | #define LDDFR_YF_MASK (3 << 8) | ||
82 | #define LDDFR_PKF_ARGB32 (0x00 << 0) | ||
83 | #define LDDFR_PKF_RGB16 (0x03 << 0) | ||
84 | #define LDDFR_PKF_RGB24 (0x0b << 0) | ||
85 | #define LDDFR_PKF_MASK (0x1f << 0) | ||
86 | |||
87 | #define LDSM1R_OS (1 << 0) | ||
88 | |||
89 | #define LDSM2R_OSTRG (1 << 0) | ||
90 | |||
91 | #define LDPMR_LPS (3 << 0) | ||
92 | |||
93 | #define _LDDWD0R 0x800 | ||
94 | #define LDDWDxR_WDACT (1 << 28) | ||
95 | #define LDDWDxR_RSW (1 << 24) | ||
96 | #define _LDDRDR 0x840 | ||
97 | #define LDDRDR_RSR (1 << 24) | ||
98 | #define LDDRDR_DRD_MASK (0x3ffff << 0) | ||
99 | #define _LDDWAR 0x900 | ||
100 | #define LDDWAR_WA (1 << 0) | ||
101 | #define _LDDRAR 0x904 | ||
102 | #define LDDRAR_RA (1 << 0) | ||
103 | |||
7 | enum { | 104 | enum { |
8 | RGB8, /* 24bpp, 8:8:8 */ | 105 | RGB8 = LDMT1R_MIFTYP_RGB8, /* 24bpp, 8:8:8 */ |
9 | RGB9, /* 18bpp, 9:9 */ | 106 | RGB9 = LDMT1R_MIFTYP_RGB9, /* 18bpp, 9:9 */ |
10 | RGB12A, /* 24bpp, 12:12 */ | 107 | RGB12A = LDMT1R_MIFTYP_RGB12A, /* 24bpp, 12:12 */ |
11 | RGB12B, /* 12bpp */ | 108 | RGB12B = LDMT1R_MIFTYP_RGB12B, /* 12bpp */ |
12 | RGB16, /* 16bpp */ | 109 | RGB16 = LDMT1R_MIFTYP_RGB16, /* 16bpp */ |
13 | RGB18, /* 18bpp */ | 110 | RGB18 = LDMT1R_MIFTYP_RGB18, /* 18bpp */ |
14 | RGB24, /* 24bpp */ | 111 | RGB24 = LDMT1R_MIFTYP_RGB24, /* 24bpp */ |
15 | YUV422, /* 16bpp */ | 112 | YUV422 = LDMT1R_MIFTYP_YCBCR, /* 16bpp */ |
16 | SYS8A, /* 24bpp, 8:8:8 */ | 113 | SYS8A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8A, /* 24bpp, 8:8:8 */ |
17 | SYS8B, /* 18bpp, 8:8:2 */ | 114 | SYS8B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8B, /* 18bpp, 8:8:2 */ |
18 | SYS8C, /* 18bpp, 2:8:8 */ | 115 | SYS8C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8C, /* 18bpp, 2:8:8 */ |
19 | SYS8D, /* 16bpp, 8:8 */ | 116 | SYS8D = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8D, /* 16bpp, 8:8 */ |
20 | SYS9, /* 18bpp, 9:9 */ | 117 | SYS9 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS9, /* 18bpp, 9:9 */ |
21 | SYS12, /* 24bpp, 12:12 */ | 118 | SYS12 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS12, /* 24bpp, 12:12 */ |
22 | SYS16A, /* 16bpp */ | 119 | SYS16A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16A, /* 16bpp */ |
23 | SYS16B, /* 18bpp, 16:2 */ | 120 | SYS16B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16B, /* 18bpp, 16:2 */ |
24 | SYS16C, /* 18bpp, 2:16 */ | 121 | SYS16C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16C, /* 18bpp, 2:16 */ |
25 | SYS18, /* 18bpp */ | 122 | SYS18 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS18, /* 18bpp */ |
26 | SYS24, /* 24bpp */ | 123 | SYS24 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS24, /* 24bpp */ |
27 | }; | 124 | }; |
28 | 125 | ||
29 | enum { LCDC_CHAN_DISABLED = 0, | 126 | enum { LCDC_CHAN_DISABLED = 0, |
diff --git a/include/video/udlfb.h b/include/video/udlfb.h index 69d485a4a026..c41f308c9636 100644 --- a/include/video/udlfb.h +++ b/include/video/udlfb.h | |||
@@ -50,6 +50,7 @@ struct dlfb_data { | |||
50 | int base16; | 50 | int base16; |
51 | int base8; | 51 | int base8; |
52 | u32 pseudo_palette[256]; | 52 | u32 pseudo_palette[256]; |
53 | int blank_mode; /*one of FB_BLANK_ */ | ||
53 | /* blit-only rendering path metrics, exposed through sysfs */ | 54 | /* blit-only rendering path metrics, exposed through sysfs */ |
54 | atomic_t bytes_rendered; /* raw pixel-bytes driver asked to render */ | 55 | atomic_t bytes_rendered; /* raw pixel-bytes driver asked to render */ |
55 | atomic_t bytes_identical; /* saved effort with backbuffer comparison */ | 56 | atomic_t bytes_identical; /* saved effort with backbuffer comparison */ |