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authorJon Loeliger <jdl@jdl.com>2006-06-17 18:52:51 -0400
committerPaul Mackerras <paulus@samba.org>2006-06-21 01:01:28 -0400
commit6b543404058a5ffdca8c48e95e0b8a69bb4bdba9 (patch)
tree0bde02196ca8de01df257679ddfc6ae66404472b /include
parentb809b3e86f39651475b30ceb1caf535071534d4d (diff)
[POWERPC] Add 8641 Register space and IRQ definitions.
Signed-off-by: Jeff Brown <Jeff.Brown@freescale.com> Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-powerpc/immap_86xx.h199
-rw-r--r--include/asm-powerpc/irq.h86
-rw-r--r--include/asm-powerpc/mpc86xx.h47
3 files changed, 332 insertions, 0 deletions
diff --git a/include/asm-powerpc/immap_86xx.h b/include/asm-powerpc/immap_86xx.h
new file mode 100644
index 000000000000..d905b6622268
--- /dev/null
+++ b/include/asm-powerpc/immap_86xx.h
@@ -0,0 +1,199 @@
1/*
2 * MPC86xx Internal Memory Map
3 *
4 * Author: Jeff Brown
5 *
6 * Copyright 2004 Freescale Semiconductor, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __ASM_POWERPC_IMMAP_86XX_H__
16#define __ASM_POWERPC_IMMAP_86XX_H__
17#ifdef __KERNEL__
18
19/* Eventually this should define all the IO block registers in 86xx */
20
21/* PCI Registers */
22typedef struct ccsr_pci {
23 uint cfg_addr; /* 0x.000 - PCI Configuration Address Register */
24 uint cfg_data; /* 0x.004 - PCI Configuration Data Register */
25 uint int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
26 char res1[3060];
27 uint potar0; /* 0x.c00 - PCI Outbound Transaction Address Register 0 */
28 uint potear0; /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */
29 uint powbar0; /* 0x.c08 - PCI Outbound Window Base Address Register 0 */
30 char res2[4];
31 uint powar0; /* 0x.c10 - PCI Outbound Window Attributes Register 0 */
32 char res3[12];
33 uint potar1; /* 0x.c20 - PCI Outbound Transaction Address Register 1 */
34 uint potear1; /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */
35 uint powbar1; /* 0x.c28 - PCI Outbound Window Base Address Register 1 */
36 char res4[4];
37 uint powar1; /* 0x.c30 - PCI Outbound Window Attributes Register 1 */
38 char res5[12];
39 uint potar2; /* 0x.c40 - PCI Outbound Transaction Address Register 2 */
40 uint potear2; /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */
41 uint powbar2; /* 0x.c48 - PCI Outbound Window Base Address Register 2 */
42 char res6[4];
43 uint powar2; /* 0x.c50 - PCI Outbound Window Attributes Register 2 */
44 char res7[12];
45 uint potar3; /* 0x.c60 - PCI Outbound Transaction Address Register 3 */
46 uint potear3; /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */
47 uint powbar3; /* 0x.c68 - PCI Outbound Window Base Address Register 3 */
48 char res8[4];
49 uint powar3; /* 0x.c70 - PCI Outbound Window Attributes Register 3 */
50 char res9[12];
51 uint potar4; /* 0x.c80 - PCI Outbound Transaction Address Register 4 */
52 uint potear4; /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */
53 uint powbar4; /* 0x.c88 - PCI Outbound Window Base Address Register 4 */
54 char res10[4];
55 uint powar4; /* 0x.c90 - PCI Outbound Window Attributes Register 4 */
56 char res11[268];
57 uint pitar3; /* 0x.da0 - PCI Inbound Translation Address Register 3 */
58 char res12[4];
59 uint piwbar3; /* 0x.da8 - PCI Inbound Window Base Address Register 3 */
60 uint piwbear3; /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */
61 uint piwar3; /* 0x.db0 - PCI Inbound Window Attributes Register 3 */
62 char res13[12];
63 uint pitar2; /* 0x.dc0 - PCI Inbound Translation Address Register 2 */
64 char res14[4];
65 uint piwbar2; /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */
66 uint piwbear2; /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */
67 uint piwar2; /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */
68 char res15[12];
69 uint pitar1; /* 0x.de0 - PCI Inbound Translation Address Register 1 */
70 char res16[4];
71 uint piwbar1; /* 0x.de8 - PCI Inbound Window Base Address Register 1 */
72 char res17[4];
73 uint piwar1; /* 0x.df0 - PCI Inbound Window Attributes Register 1 */
74 char res18[12];
75 uint err_dr; /* 0x.e00 - PCI Error Detect Register */
76 uint err_cap_dr; /* 0x.e04 - PCI Error Capture Disable Register */
77 uint err_en; /* 0x.e08 - PCI Error Enable Register */
78 uint err_attrib; /* 0x.e0c - PCI Error Attributes Capture Register */
79 uint err_addr; /* 0x.e10 - PCI Error Address Capture Register */
80 uint err_ext_addr; /* 0x.e14 - PCI Error Extended Address Capture Register */
81 uint err_dl; /* 0x.e18 - PCI Error Data Low Capture Register */
82 uint err_dh; /* 0x.e1c - PCI Error Data High Capture Register */
83 uint gas_timr; /* 0x.e20 - PCI Gasket Timer Register */
84 uint pci_timr; /* 0x.e24 - PCI Timer Register */
85 char res19[472];
86} ccsr_pci_t;
87
88/* PCI Express Registers */
89typedef struct ccsr_pex {
90 uint pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
91 uint pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
92 char res1[4];
93 uint pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
94 uint pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
95 char res2[12];
96 uint pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
97 uint pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
98 uint pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
99 uint pex_pmcr; /* 0x.02c - PCI Express power management command register */
100 char res3[3024];
101 uint pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
102 uint pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
103 char res4[8];
104 uint pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
105 char res5[12];
106 uint pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
107 uint pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
108 uint pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
109 char res6[4];
110 uint pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
111 char res7[12];
112 uint pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
113 uint pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
114 uint pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
115 char res8[4];
116 uint pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
117 char res9[12];
118 uint pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
119 uint pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
120 uint pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
121 char res10[4];
122 uint pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
123 char res11[12];
124 uint pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
125 uint pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
126 uint pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
127 char res12[4];
128 uint pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
129 char res13[12];
130 char res14[256];
131 uint pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
132 char res15[4];
133 uint pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
134 uint pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
135 uint pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
136 char res16[12];
137 uint pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
138 char res17[4];
139 uint pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
140 uint pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
141 uint pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
142 char res18[12];
143 uint pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
144 char res19[4];
145 uint pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
146 uint pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
147 uint pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
148 char res20[12];
149 uint pex_err_dr; /* 0x.e00 - PCI Express error detect register */
150 char res21[4];
151 uint pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
152 char res22[4];
153 uint pex_err_disr; /* 0x.e10 - PCI Express error disable register */
154 char res23[12];
155 uint pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
156 char res24[4];
157 uint pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
158 uint pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
159 uint pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
160 uint pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
161} ccsr_pex_t;
162
163/* Global Utility Registers */
164typedef struct ccsr_guts {
165 uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
166 uint porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
167 uint porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
168 uint pordevsr; /* 0x.000c - POR I/O Device Status Register */
169 uint pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
170 char res1[12];
171 uint gpporcr; /* 0x.0020 - General-Purpose POR Configuration Register */
172 char res2[12];
173 uint gpiocr; /* 0x.0030 - GPIO Control Register */
174 char res3[12];
175 uint gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
176 char res4[12];
177 uint gpindr; /* 0x.0050 - General-Purpose Input Data Register */
178 char res5[12];
179 uint pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
180 char res6[12];
181 uint devdisr; /* 0x.0070 - Device Disable Control */
182 char res7[12];
183 uint powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
184 char res8[12];
185 uint mcpsumr; /* 0x.0090 - Machine Check Summary Register */
186 char res9[12];
187 uint pvr; /* 0x.00a0 - Processor Version Register */
188 uint svr; /* 0x.00a4 - System Version Register */
189 char res10[3416];
190 uint clkocr; /* 0x.0e00 - Clock Out Select Register */
191 char res11[12];
192 uint ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
193 char res12[12];
194 uint lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
195 char res13[61916];
196} ccsr_guts_t;
197
198#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */
199#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
index 7bc6d73b2823..7a762096f196 100644
--- a/include/asm-powerpc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -348,6 +348,92 @@ extern u64 ppc64_interrupt_controller;
348#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET) 348#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
349#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET) 349#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
350 350
351#elif defined(CONFIG_PPC_86xx)
352#include <asm/mpc86xx.h>
353
354#define NR_EPIC_INTS 48
355#ifndef NR_8259_INTS
356#define NR_8259_INTS 16 /*ULI 1575 can route 12 interrupts */
357#endif
358#define NUM_8259_INTERRUPTS NR_8259_INTS
359
360#ifndef I8259_OFFSET
361#define I8259_OFFSET 0
362#endif
363
364#define NR_IRQS 256
365
366/* Internal IRQs on MPC86xx OpenPIC */
367
368#ifndef MPC86xx_OPENPIC_IRQ_OFFSET
369#define MPC86xx_OPENPIC_IRQ_OFFSET NR_8259_INTS
370#endif
371
372/* The 48 internal sources */
373#define MPC86xx_IRQ_NULL ( 0 + MPC86xx_OPENPIC_IRQ_OFFSET)
374#define MPC86xx_IRQ_MCM ( 1 + MPC86xx_OPENPIC_IRQ_OFFSET)
375#define MPC86xx_IRQ_DDR ( 2 + MPC86xx_OPENPIC_IRQ_OFFSET)
376#define MPC86xx_IRQ_LBC ( 3 + MPC86xx_OPENPIC_IRQ_OFFSET)
377#define MPC86xx_IRQ_DMA0 ( 4 + MPC86xx_OPENPIC_IRQ_OFFSET)
378#define MPC86xx_IRQ_DMA1 ( 5 + MPC86xx_OPENPIC_IRQ_OFFSET)
379#define MPC86xx_IRQ_DMA2 ( 6 + MPC86xx_OPENPIC_IRQ_OFFSET)
380#define MPC86xx_IRQ_DMA3 ( 7 + MPC86xx_OPENPIC_IRQ_OFFSET)
381
382/* no 10,11 */
383#define MPC86xx_IRQ_UART2 (12 + MPC86xx_OPENPIC_IRQ_OFFSET)
384#define MPC86xx_IRQ_TSEC1_TX (13 + MPC86xx_OPENPIC_IRQ_OFFSET)
385#define MPC86xx_IRQ_TSEC1_RX (14 + MPC86xx_OPENPIC_IRQ_OFFSET)
386#define MPC86xx_IRQ_TSEC3_TX (15 + MPC86xx_OPENPIC_IRQ_OFFSET)
387#define MPC86xx_IRQ_TSEC3_RX (16 + MPC86xx_OPENPIC_IRQ_OFFSET)
388#define MPC86xx_IRQ_TSEC3_ERROR (17 + MPC86xx_OPENPIC_IRQ_OFFSET)
389#define MPC86xx_IRQ_TSEC1_ERROR (18 + MPC86xx_OPENPIC_IRQ_OFFSET)
390#define MPC86xx_IRQ_TSEC2_TX (19 + MPC86xx_OPENPIC_IRQ_OFFSET)
391#define MPC86xx_IRQ_TSEC2_RX (20 + MPC86xx_OPENPIC_IRQ_OFFSET)
392#define MPC86xx_IRQ_TSEC4_TX (21 + MPC86xx_OPENPIC_IRQ_OFFSET)
393#define MPC86xx_IRQ_TSEC4_RX (22 + MPC86xx_OPENPIC_IRQ_OFFSET)
394#define MPC86xx_IRQ_TSEC4_ERROR (23 + MPC86xx_OPENPIC_IRQ_OFFSET)
395#define MPC86xx_IRQ_TSEC2_ERROR (24 + MPC86xx_OPENPIC_IRQ_OFFSET)
396/* no 25 */
397#define MPC86xx_IRQ_UART1 (26 + MPC86xx_OPENPIC_IRQ_OFFSET)
398#define MPC86xx_IRQ_IIC (27 + MPC86xx_OPENPIC_IRQ_OFFSET)
399#define MPC86xx_IRQ_PERFMON (28 + MPC86xx_OPENPIC_IRQ_OFFSET)
400/* no 29,30,31 */
401#define MPC86xx_IRQ_SRIO_ERROR (32 + MPC86xx_OPENPIC_IRQ_OFFSET)
402#define MPC86xx_IRQ_SRIO_OUT_BELL (33 + MPC86xx_OPENPIC_IRQ_OFFSET)
403#define MPC86xx_IRQ_SRIO_IN_BELL (34 + MPC86xx_OPENPIC_IRQ_OFFSET)
404/* no 35,36 */
405#define MPC86xx_IRQ_SRIO_OUT_MSG1 (37 + MPC86xx_OPENPIC_IRQ_OFFSET)
406#define MPC86xx_IRQ_SRIO_IN_MSG1 (38 + MPC86xx_OPENPIC_IRQ_OFFSET)
407#define MPC86xx_IRQ_SRIO_OUT_MSG2 (39 + MPC86xx_OPENPIC_IRQ_OFFSET)
408#define MPC86xx_IRQ_SRIO_IN_MSG2 (40 + MPC86xx_OPENPIC_IRQ_OFFSET)
409
410/* The 12 external interrupt lines */
411#define MPC86xx_IRQ_EXT_BASE 48
412#define MPC86xx_IRQ_EXT0 (0 + MPC86xx_IRQ_EXT_BASE \
413 + MPC86xx_OPENPIC_IRQ_OFFSET)
414#define MPC86xx_IRQ_EXT1 (1 + MPC86xx_IRQ_EXT_BASE \
415 + MPC86xx_OPENPIC_IRQ_OFFSET)
416#define MPC86xx_IRQ_EXT2 (2 + MPC86xx_IRQ_EXT_BASE \
417 + MPC86xx_OPENPIC_IRQ_OFFSET)
418#define MPC86xx_IRQ_EXT3 (3 + MPC86xx_IRQ_EXT_BASE \
419 + MPC86xx_OPENPIC_IRQ_OFFSET)
420#define MPC86xx_IRQ_EXT4 (4 + MPC86xx_IRQ_EXT_BASE \
421 + MPC86xx_OPENPIC_IRQ_OFFSET)
422#define MPC86xx_IRQ_EXT5 (5 + MPC86xx_IRQ_EXT_BASE \
423 + MPC86xx_OPENPIC_IRQ_OFFSET)
424#define MPC86xx_IRQ_EXT6 (6 + MPC86xx_IRQ_EXT_BASE \
425 + MPC86xx_OPENPIC_IRQ_OFFSET)
426#define MPC86xx_IRQ_EXT7 (7 + MPC86xx_IRQ_EXT_BASE \
427 + MPC86xx_OPENPIC_IRQ_OFFSET)
428#define MPC86xx_IRQ_EXT8 (8 + MPC86xx_IRQ_EXT_BASE \
429 + MPC86xx_OPENPIC_IRQ_OFFSET)
430#define MPC86xx_IRQ_EXT9 (9 + MPC86xx_IRQ_EXT_BASE \
431 + MPC86xx_OPENPIC_IRQ_OFFSET)
432#define MPC86xx_IRQ_EXT10 (10 + MPC86xx_IRQ_EXT_BASE \
433 + MPC86xx_OPENPIC_IRQ_OFFSET)
434#define MPC86xx_IRQ_EXT11 (11 + MPC86xx_IRQ_EXT_BASE \
435 + MPC86xx_OPENPIC_IRQ_OFFSET)
436
351#else /* CONFIG_40x + CONFIG_8xx */ 437#else /* CONFIG_40x + CONFIG_8xx */
352/* 438/*
353 * this is the # irq's for all ppc arch's (pmac/chrp/prep) 439 * this is the # irq's for all ppc arch's (pmac/chrp/prep)
diff --git a/include/asm-powerpc/mpc86xx.h b/include/asm-powerpc/mpc86xx.h
new file mode 100644
index 000000000000..d0a6718d188b
--- /dev/null
+++ b/include/asm-powerpc/mpc86xx.h
@@ -0,0 +1,47 @@
1/*
2 * MPC86xx definitions
3 *
4 * Author: Jeff Brown
5 *
6 * Copyright 2004 Freescale Semiconductor, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_POWERPC_MPC86xx_H__
16#define __ASM_POWERPC_MPC86xx_H__
17
18#include <linux/config.h>
19#include <asm/mmu.h>
20
21#ifdef CONFIG_PPC_86xx
22
23#ifdef CONFIG_MPC8641_HPCN
24#include <platforms/86xx/mpc8641_hpcn.h>
25#endif
26
27#define _IO_BASE isa_io_base
28#define _ISA_MEM_BASE isa_mem_base
29#ifdef CONFIG_PCI
30#define PCI_DRAM_OFFSET pci_dram_offset
31#else
32#define PCI_DRAM_OFFSET 0
33#endif
34
35#define CPU0_BOOT_RELEASE 0x01000000
36#define CPU1_BOOT_RELEASE 0x02000000
37#define CPU_ALL_RELEASED (CPU0_BOOT_RELEASE | CPU1_BOOT_RELEASE)
38#define MCM_PORT_CONFIG_OFFSET 0x1010
39
40/* Offset from CCSRBAR */
41#define MPC86xx_OPENPIC_OFFSET (0x40000)
42#define MPC86xx_MCM_OFFSET (0x00000)
43#define MPC86xx_MCM_SIZE (0x02000)
44
45#endif /* CONFIG_PPC_86xx */
46#endif /* __ASM_POWERPC_MPC86xx_H__ */
47#endif /* __KERNEL__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 09:28:33 -0500