Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] IP27: Build fix
  [MIPS] Wire up ioprio_set and ioprio_get.
  [MIPS] Fix __raw_read_trylock() to allow multiple readers
  [MIPS] Export __copy_user_inatomic.
  [MIPS] R2 bitops compile fix for gcc < 4.0.
  [MIPS] TX39: Remove redundant tx39_blast_icache() calls
  [MIPS] Cobalt: Fix early printk
  [MIPS] SMTC: De-obscure Malta hooks.
  [MIPS] SMTC: Add fordward declarations for mm_struct and task_struct.
  [MIPS] SMTC: <asm/mips_mt.h> must include <linux/cpumask.h>
  [MIPS] SMTC: <asm/smtc_ipi.h> must include <linux/spinlock.h>
  [MIPS] Atlas, Malta: Fix build warning.

7 files changed, 56 insertions, 31 deletions

diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 89436b96ad66..8959da245cfb 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -54,6 +54,7 @@
 static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
 {
         unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+        unsigned short bit = nr & SZLONG_MASK;
         unsigned long temp;
 
         if (cpu_has_llsc && R10000_LLSC_WAR) {
@@ -65,9 +66,9 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
                 "       beqzl   %0, 1b                                  \n"
                 "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (*m)
-                : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+                : "ir" (1UL << bit), "m" (*m));
 #ifdef CONFIG_CPU_MIPSR2
-        } else if (__builtin_constant_p(nr)) {
+        } else if (__builtin_constant_p(bit)) {
                 __asm__ __volatile__(
                 "1:     " __LL "%0, %1                  # set_bit       \n"
                 "       " __INS "%0, %4, %2, 1                          \n"
@@ -77,7 +78,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
                 "2:     b       1b                                      \n"
                 "       .previous                                       \n"
                 : "=&r" (temp), "=m" (*m)
-                : "ir" (nr & SZLONG_MASK), "m" (*m), "r" (~0));
+                : "ir" (bit), "m" (*m), "r" (~0));
 #endif /* CONFIG_CPU_MIPSR2 */
         } else if (cpu_has_llsc) {
                 __asm__ __volatile__(
@@ -91,14 +92,14 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
                 "       .previous                                       \n"
                 "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (*m)
-                : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+                : "ir" (1UL << bit), "m" (*m));
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
                 unsigned long flags;
 
                 a += nr >> SZLONG_LOG;
-                mask = 1UL << (nr & SZLONG_MASK);
+                mask = 1UL << bit;
                 local_irq_save(flags);
                 *a |= mask;
                 local_irq_restore(flags);
@@ -118,6 +119,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
 static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
 {
         unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+        unsigned short bit = nr & SZLONG_MASK;
         unsigned long temp;
 
         if (cpu_has_llsc && R10000_LLSC_WAR) {
@@ -129,9 +131,9 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
                 "       beqzl   %0, 1b                                  \n"
                 "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (*m)
-                : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
+                : "ir" (~(1UL << bit)), "m" (*m));
 #ifdef CONFIG_CPU_MIPSR2
-        } else if (__builtin_constant_p(nr)) {
+        } else if (__builtin_constant_p(bit)) {
                 __asm__ __volatile__(
                 "1:     " __LL "%0, %1                  # clear_bit     \n"
                 "       " __INS "%0, $0, %2, 1                          \n"
@@ -141,7 +143,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
                 "2:     b       1b                                      \n"
                 "       .previous                                       \n"
                 : "=&r" (temp), "=m" (*m)
-                : "ir" (nr & SZLONG_MASK), "m" (*m));
+                : "ir" (bit), "m" (*m));
 #endif /* CONFIG_CPU_MIPSR2 */
         } else if (cpu_has_llsc) {
                 __asm__ __volatile__(
@@ -155,14 +157,14 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
                 "       .previous                                       \n"
                 "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (*m)
-                : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
+                : "ir" (~(1UL << bit)), "m" (*m));
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
                 unsigned long flags;
 
                 a += nr >> SZLONG_LOG;
-                mask = 1UL << (nr & SZLONG_MASK);
+                mask = 1UL << bit;
                 local_irq_save(flags);
                 *a &= ~mask;
                 local_irq_restore(flags);
@@ -180,6 +182,8 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
  */
 static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
 {
+        unsigned short bit = nr & SZLONG_MASK;
+
         if (cpu_has_llsc && R10000_LLSC_WAR) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp;
@@ -192,7 +196,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
                 "       beqzl   %0, 1b                          \n"
                 "       .set    mips0                           \n"
                 : "=&r" (temp), "=m" (*m)
-                : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+                : "ir" (1UL << bit), "m" (*m));
         } else if (cpu_has_llsc) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp;
@@ -208,14 +212,14 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
                 "       .previous                               \n"
                 "       .set    mips0                           \n"
                 : "=&r" (temp), "=m" (*m)
-                : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+                : "ir" (1UL << bit), "m" (*m));
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
                 unsigned long flags;
 
                 a += nr >> SZLONG_LOG;
-                mask = 1UL << (nr & SZLONG_MASK);
+                mask = 1UL << bit;
                 local_irq_save(flags);
                 *a ^= mask;
                 local_irq_restore(flags);
@@ -233,6 +237,8 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
 static inline int test_and_set_bit(unsigned long nr,
         volatile unsigned long *addr)
 {
+        unsigned short bit = nr & SZLONG_MASK;
+
         if (cpu_has_llsc && R10000_LLSC_WAR) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp, res;
@@ -246,7 +252,7 @@ static inline int test_and_set_bit(unsigned long nr,
                 "       and     %2, %0, %3                              \n"
                 "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+                : "r" (1UL << bit), "m" (*m)
                 : "memory");
 
                 return res != 0;
@@ -269,7 +275,7 @@ static inline int test_and_set_bit(unsigned long nr,
                 "       .previous                                       \n"
                 "       .set    pop                                     \n"
                 : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+                : "r" (1UL << bit), "m" (*m)
                 : "memory");
 
                 return res != 0;
@@ -280,7 +286,7 @@ static inline int test_and_set_bit(unsigned long nr,
                 unsigned long flags;
 
                 a += nr >> SZLONG_LOG;
-                mask = 1UL << (nr & SZLONG_MASK);
+                mask = 1UL << bit;
                 local_irq_save(flags);
                 retval = (mask & *a) != 0;
                 *a |= mask;
@@ -303,6 +309,8 @@ static inline int test_and_set_bit(unsigned long nr,
 static inline int test_and_clear_bit(unsigned long nr,
         volatile unsigned long *addr)
 {
+        unsigned short bit = nr & SZLONG_MASK;
+
         if (cpu_has_llsc && R10000_LLSC_WAR) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp, res;
@@ -317,7 +325,7 @@ static inline int test_and_clear_bit(unsigned long nr,
                 "       and     %2, %0, %3                              \n"
                 "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+                : "r" (1UL << bit), "m" (*m)
                 : "memory");
 
                 return res != 0;
@@ -336,7 +344,7 @@ static inline int test_and_clear_bit(unsigned long nr,
                 "2:     b       1b                                      \n"
                 "       .previous                                       \n"
                 : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "ri" (nr & SZLONG_MASK), "m" (*m)
+                : "ri" (bit), "m" (*m)
                 : "memory");
 
                 return res;
@@ -361,7 +369,7 @@ static inline int test_and_clear_bit(unsigned long nr,
                 "       .previous                                       \n"
                 "       .set    pop                                     \n"
                 : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+                : "r" (1UL << bit), "m" (*m)
                 : "memory");
 
                 return res != 0;
@@ -372,7 +380,7 @@ static inline int test_and_clear_bit(unsigned long nr,
                 unsigned long flags;
 
                 a += nr >> SZLONG_LOG;
-                mask = 1UL << (nr & SZLONG_MASK);
+                mask = 1UL << bit;
                 local_irq_save(flags);
                 retval = (mask & *a) != 0;
                 *a &= ~mask;
@@ -395,6 +403,8 @@ static inline int test_and_clear_bit(unsigned long nr,
 static inline int test_and_change_bit(unsigned long nr,
         volatile unsigned long *addr)
 {
+        unsigned short bit = nr & SZLONG_MASK;
+
         if (cpu_has_llsc && R10000_LLSC_WAR) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp, res;
@@ -408,7 +418,7 @@ static inline int test_and_change_bit(unsigned long nr,
                 "       and     %2, %0, %3                              \n"
                 "       .set    mips0                                   \n"
                 : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+                : "r" (1UL << bit), "m" (*m)
                 : "memory");
 
                 return res != 0;
@@ -431,7 +441,7 @@ static inline int test_and_change_bit(unsigned long nr,
                 "       .previous                                       \n"
                 "       .set    pop                                     \n"
                 : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+                : "r" (1UL << bit), "m" (*m)
                 : "memory");
 
                 return res != 0;
@@ -441,7 +451,7 @@ static inline int test_and_change_bit(unsigned long nr,
                 unsigned long flags;
 
                 a += nr >> SZLONG_LOG;
-                mask = 1UL << (nr & SZLONG_MASK);
+                mask = 1UL << bit;
                 local_irq_save(flags);
                 retval = (mask & *a) != 0;
                 *a ^= mask;
diff --git a/include/asm-mips/mips_mt.h b/include/asm-mips/mips_mt.h
index fdfff0b8ce42..8045abc78d0f 100644
--- a/include/asm-mips/mips_mt.h
+++ b/include/asm-mips/mips_mt.h
@@ -6,6 +6,8 @@
 #ifndef __ASM_MIPS_MT_H
 #define __ASM_MIPS_MT_H
 
+#include <linux/cpumask.h>
+
 extern cpumask_t mt_fpu_cpumask;
 extern unsigned long mt_fpemul_threshold;
 
diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h
index e1941d1b8726..44dfa4adecf3 100644
--- a/include/asm-mips/smtc.h
+++ b/include/asm-mips/smtc.h
@@ -34,6 +34,9 @@ typedef long asiduse;
 
 extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
 
+struct mm_struct;
+struct task_struct;
+
 void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu);
 
 void smtc_flush_tlb_asid(unsigned long asid);
diff --git a/include/asm-mips/smtc_ipi.h b/include/asm-mips/smtc_ipi.h
index 55f3419f6546..360ea6d250c7 100644
--- a/include/asm-mips/smtc_ipi.h
+++ b/include/asm-mips/smtc_ipi.h
@@ -4,6 +4,8 @@
 #ifndef __ASM_SMTC_IPI_H
 #define __ASM_SMTC_IPI_H
 
+#include <linux/spinlock.h>
+
 //#define SMTC_IPI_DEBUG
 
 #ifdef SMTC_IPI_DEBUG
diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h
index f1755d28a36a..35e431cd796b 100644
--- a/include/asm-mips/spinlock.h
+++ b/include/asm-mips/spinlock.h
@@ -287,7 +287,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
                 "       .set    noreorder       # __raw_read_trylock    \n"
                 "       li      %2, 0                                   \n"
                 "1:     ll      %1, %3                                  \n"
-                "       bnez    %1, 2f                                  \n"
+                "       bltz    %1, 2f                                  \n"
                 "        addu   %1, 1                                   \n"
                 "       sc      %1, %0                                  \n"
                 "       .set    reorder                                 \n"
@@ -304,7 +304,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
                 "       .set    noreorder       # __raw_read_trylock    \n"
                 "       li      %2, 0                                   \n"
                 "1:     ll      %1, %3                                  \n"
-                "       bnez    %1, 2f                                  \n"
+                "       bltz    %1, 2f                                  \n"
                 "        addu   %1, 1                                   \n"
                 "       sc      %1, %0                                  \n"
                 "       beqz    %1, 1b                                  \n"
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h
index c62c20e7b5c6..b25511787ee0 100644
--- a/include/asm-mips/uaccess.h
+++ b/include/asm-mips/uaccess.h
@@ -435,6 +435,8 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
         __cu_len;                                                       \
 })
 
+extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
+
 #define __copy_to_user_inatomic(to,from,n)                              \
 ({                                                                      \
         void __user *__cu_to;                                           \
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
index 696cff39a1d3..2f1087b3a202 100644
--- a/include/asm-mips/unistd.h
+++ b/include/asm-mips/unistd.h
@@ -334,16 +334,18 @@
 #define __NR_kexec_load                 (__NR_Linux + 311)
 #define __NR_getcpu                     (__NR_Linux + 312)
 #define __NR_epoll_pwait                (__NR_Linux + 313)
+#define __NR_ioprio_set                 (__NR_Linux + 314)
+#define __NR_ioprio_get                 (__NR_Linux + 315)
 
 /*
  * Offset of the last Linux o32 flavoured syscall
  */
-#define __NR_Linux_syscalls             313
+#define __NR_Linux_syscalls             315
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 #define __NR_O32_Linux                  4000
-#define __NR_O32_Linux_syscalls         313
+#define __NR_O32_Linux_syscalls         315
 
 #if _MIPS_SIM == _MIPS_SIM_ABI64
 
@@ -624,16 +626,18 @@
 #define __NR_kexec_load                 (__NR_Linux + 270)
 #define __NR_getcpu                     (__NR_Linux + 271)
 #define __NR_epoll_pwait                (__NR_Linux + 272)
+#define __NR_ioprio_set                 (__NR_Linux + 273)
+#define __NR_ioprio_get                 (__NR_Linux + 274)
 
 /*
  * Offset of the last Linux 64-bit flavoured syscall
  */
-#define __NR_Linux_syscalls             272
+#define __NR_Linux_syscalls             274
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
 
 #define __NR_64_Linux                   5000
-#define __NR_64_Linux_syscalls          272
+#define __NR_64_Linux_syscalls          274
 
 #if _MIPS_SIM == _MIPS_SIM_NABI32
 
@@ -918,16 +922,18 @@
 #define __NR_kexec_load                 (__NR_Linux + 274)
 #define __NR_getcpu                     (__NR_Linux + 275)
 #define __NR_epoll_pwait                (__NR_Linux + 276)
+#define __NR_ioprio_set                 (__NR_Linux + 277)
+#define __NR_ioprio_get                 (__NR_Linux + 278)
 
 /*
  * Offset of the last N32 flavoured syscall
  */
-#define __NR_Linux_syscalls             276
+#define __NR_Linux_syscalls             278
 
 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
 
 #define __NR_N32_Linux                  6000
-#define __NR_N32_Linux_syscalls         276
+#define __NR_N32_Linux_syscalls         278
 
 #ifdef __KERNEL__