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authorBen Dooks <ben-linux@fluff.org>2005-10-20 18:21:20 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-10-20 18:21:20 -0400
commit7fe8785e4198ad6b5dfd4a76c44c97e9b4463534 (patch)
tree72b3df4ec83116fad9546c41f0ef549dad52236b /include
parentb048dbf4d428c89f219efc2eddf2771f13500503 (diff)
[ARM] 3028/1: S3C2410 - add DCLK mask definitions
Patch from Ben Dooks From: Guillaume Gourat <guillaume.gourat@nexvision.fr> Add MASK definitions for DCLK0 and DCLK1 Signed-off-by: Guillaume Gourat <guillaume.gourat@nexvision.fr> Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-s3c2410/regs-clock.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index 66794b13e185..34360706e016 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -19,6 +19,7 @@
19 * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA 19 * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA
20 * 27-Aug-2005 Ben Dooks Add clock-slow info 20 * 27-Aug-2005 Ben Dooks Add clock-slow info
21 * 20-Oct-2005 Ben Dooks Fixed overflow in PLL (Guillaume Gourat) 21 * 20-Oct-2005 Ben Dooks Fixed overflow in PLL (Guillaume Gourat)
22 * 20-Oct-2005 Ben Dooks Add masks for DCLK (Guillaume Gourat)
22*/ 23*/
23 24
24#ifndef __ASM_ARM_REGS_CLOCK 25#ifndef __ASM_ARM_REGS_CLOCK
@@ -67,11 +68,16 @@
67#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1) 68#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1)
68#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4) 69#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
69#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8) 70#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
71#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4)
72#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8)
70 73
71#define S3C2410_DCLKCON_DCLK1EN (1<<16) 74#define S3C2410_DCLKCON_DCLK1EN (1<<16)
72#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17) 75#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17)
73#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17) 76#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17)
74#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20) 77#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
78#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24)
79#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20)
80#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24)
75 81
76#define S3C2410_CLKDIVN_PDIVN (1<<0) 82#define S3C2410_CLKDIVN_PDIVN (1<<0)
77#define S3C2410_CLKDIVN_HDIVN (1<<1) 83#define S3C2410_CLKDIVN_HDIVN (1<<1)