diff options
author | Ryusuke Sakato <sakato@hsdv.com> | 2006-10-11 23:16:13 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2006-10-11 23:16:13 -0400 |
commit | 8ae91b9ad88a130cd50fc0b78b16e7b9510b8067 (patch) | |
tree | 663d99ba90da95c166962bbdee7e207f2b98183f /include | |
parent | baf4326e49801526e4516e4de7f37b5e51468c49 (diff) |
sh: SH-4A UBC support
A simple patch to enable the UBC on SH-4A.
Signed-off-by: Ryusuke Sakato <sakato@hsdv.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-sh/cpu-sh4/ubc.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/include/asm-sh/cpu-sh4/ubc.h b/include/asm-sh/cpu-sh4/ubc.h index 3d0943167659..c86e17050935 100644 --- a/include/asm-sh/cpu-sh4/ubc.h +++ b/include/asm-sh/cpu-sh4/ubc.h | |||
@@ -3,6 +3,7 @@ | |||
3 | * | 3 | * |
4 | * Copyright (C) 1999 Niibe Yutaka | 4 | * Copyright (C) 1999 Niibe Yutaka |
5 | * Copyright (C) 2003 Paul Mundt | 5 | * Copyright (C) 2003 Paul Mundt |
6 | * Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC | ||
6 | * | 7 | * |
7 | * This file is subject to the terms and conditions of the GNU General Public | 8 | * This file is subject to the terms and conditions of the GNU General Public |
8 | * License. See the file "COPYING" in the main directory of this archive | 9 | * License. See the file "COPYING" in the main directory of this archive |
@@ -11,6 +12,41 @@ | |||
11 | #ifndef __ASM_CPU_SH4_UBC_H | 12 | #ifndef __ASM_CPU_SH4_UBC_H |
12 | #define __ASM_CPU_SH4_UBC_H | 13 | #define __ASM_CPU_SH4_UBC_H |
13 | 14 | ||
15 | #if defined(CONFIG_CPU_SH4A) | ||
16 | #define UBC_CBR0 0xff200000 | ||
17 | #define UBC_CRR0 0xff200004 | ||
18 | #define UBC_CAR0 0xff200008 | ||
19 | #define UBC_CAMR0 0xff20000c | ||
20 | #define UBC_CBR1 0xff200020 | ||
21 | #define UBC_CRR1 0xff200024 | ||
22 | #define UBC_CAR1 0xff200028 | ||
23 | #define UBC_CAMR1 0xff20002c | ||
24 | #define UBC_CDR1 0xff200030 | ||
25 | #define UBC_CDMR1 0xff200034 | ||
26 | #define UBC_CETR1 0xff200038 | ||
27 | #define UBC_CCMFR 0xff200600 | ||
28 | #define UBC_CBCR 0xff200620 | ||
29 | |||
30 | /* CBR */ | ||
31 | #define UBC_CBR_AIE (0x01<<30) | ||
32 | #define UBC_CBR_ID_INST (0x01<<4) | ||
33 | #define UBC_CBR_RW_READ (0x01<<1) | ||
34 | #define UBC_CBR_CE (0x01) | ||
35 | |||
36 | #define UBC_CBR_AIV_MASK (0x00FF0000) | ||
37 | #define UBC_CBR_AIV_SHIFT (16) | ||
38 | #define UBC_CBR_AIV_SET(asid) (((asid)<<UBC_CBR_AIV_SHIFT) & UBC_CBR_AIV_MASK) | ||
39 | |||
40 | #define UBC_CBR_INIT 0x20000000 | ||
41 | |||
42 | /* CRR */ | ||
43 | #define UBC_CRR_RES (0x01<<13) | ||
44 | #define UBC_CRR_PCB (0x01<<1) | ||
45 | #define UBC_CRR_BIE (0x01) | ||
46 | |||
47 | #define UBC_CRR_INIT 0x00002000 | ||
48 | |||
49 | #else /* CONFIG_CPU_SH4 */ | ||
14 | #define UBC_BARA 0xff200000 | 50 | #define UBC_BARA 0xff200000 |
15 | #define UBC_BAMRA 0xff200004 | 51 | #define UBC_BAMRA 0xff200004 |
16 | #define UBC_BBRA 0xff200008 | 52 | #define UBC_BBRA 0xff200008 |
@@ -22,6 +58,7 @@ | |||
22 | #define UBC_BDRB 0xff200018 | 58 | #define UBC_BDRB 0xff200018 |
23 | #define UBC_BDMRB 0xff20001c | 59 | #define UBC_BDMRB 0xff20001c |
24 | #define UBC_BRCR 0xff200020 | 60 | #define UBC_BRCR 0xff200020 |
61 | #endif /* CONFIG_CPU_SH4 */ | ||
25 | 62 | ||
26 | #endif /* __ASM_CPU_SH4_UBC_H */ | 63 | #endif /* __ASM_CPU_SH4_UBC_H */ |
27 | 64 | ||