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authorDavid Woodhouse <dwmw2@shinybook.infradead.org>2005-08-09 11:51:35 -0400
committerDavid Woodhouse <dwmw2@shinybook.infradead.org>2005-08-09 11:51:35 -0400
commitc973b112c76c9d8fd042991128f218a738cc8d0a (patch)
treee813b0da5d0a0e19e06de6462d145a29ad683026 /include
parentc5fbc3966f48279dbebfde10248c977014aa9988 (diff)
parent00dd1e433967872f3997a45d5adf35056fdf2f56 (diff)
Merge with /shiny/git/linux-2.6/.git
Diffstat (limited to 'include')
-rw-r--r--include/acpi/acpi_drivers.h3
-rw-r--r--include/asm-alpha/pci.h3
-rw-r--r--include/asm-alpha/unistd.h7
-rw-r--r--include/asm-arm/bitops.h5
-rw-r--r--include/asm-arm/pci.h4
-rw-r--r--include/asm-cris/arch-v10/atomic.h7
-rw-r--r--include/asm-cris/arch-v10/bitops.h2
-rw-r--r--include/asm-cris/arch-v10/dma.h28
-rw-r--r--include/asm-cris/arch-v10/elf.h10
-rw-r--r--include/asm-cris/arch-v10/ide.h99
-rw-r--r--include/asm-cris/arch-v10/io.h1
-rw-r--r--include/asm-cris/arch-v10/io_interface_mux.h75
-rw-r--r--include/asm-cris/arch-v10/irq.h27
-rw-r--r--include/asm-cris/arch-v10/memmap.h22
-rw-r--r--include/asm-cris/arch-v10/mmu.h5
-rw-r--r--include/asm-cris/arch-v10/offset.h2
-rw-r--r--include/asm-cris/arch-v10/processor.h8
-rw-r--r--include/asm-cris/arch-v10/system.h2
-rw-r--r--include/asm-cris/arch-v32/arbiter.h30
-rw-r--r--include/asm-cris/arch-v32/atomic.h36
-rw-r--r--include/asm-cris/arch-v32/bitops.h64
-rw-r--r--include/asm-cris/arch-v32/byteorder.h20
-rw-r--r--include/asm-cris/arch-v32/cache.h9
-rw-r--r--include/asm-cris/arch-v32/checksum.h29
-rw-r--r--include/asm-cris/arch-v32/cryptocop.h272
-rw-r--r--include/asm-cris/arch-v32/delay.h18
-rw-r--r--include/asm-cris/arch-v32/dma.h79
-rw-r--r--include/asm-cris/arch-v32/elf.h73
-rw-r--r--include/asm-cris/arch-v32/hwregs/Makefile187
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h222
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h319
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h495
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h249
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h131
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h41
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h114
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h10
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h368
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h498
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h276
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/intr_vect.h38
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h355
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h69
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h579
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h212
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h7
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h632
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h96
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h142
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h359
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h462
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h84
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h100
-rw-r--r--include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h229
-rw-r--r--include/asm-cris/arch-v32/hwregs/ata_defs.h222
-rw-r--r--include/asm-cris/arch-v32/hwregs/bif_core_defs.h284
-rw-r--r--include/asm-cris/arch-v32/hwregs/bif_dma_defs.h473
-rw-r--r--include/asm-cris/arch-v32/hwregs/bif_slave_defs.h249
-rw-r--r--include/asm-cris/arch-v32/hwregs/config_defs.h142
-rw-r--r--include/asm-cris/arch-v32/hwregs/cpu_vect.h41
-rw-r--r--include/asm-cris/arch-v32/hwregs/dma.h128
-rw-r--r--include/asm-cris/arch-v32/hwregs/dma_defs.h436
-rw-r--r--include/asm-cris/arch-v32/hwregs/eth_defs.h384
-rw-r--r--include/asm-cris/arch-v32/hwregs/extmem_defs.h369
-rw-r--r--include/asm-cris/arch-v32/hwregs/gio_defs.h295
-rw-r--r--include/asm-cris/arch-v32/hwregs/intr_vect.h39
-rw-r--r--include/asm-cris/arch-v32/hwregs/intr_vect_defs.h225
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/Makefile146
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h171
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h321
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h349
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h234
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h155
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h254
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h158
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h177
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h44
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h182
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h346
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h111
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h105
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h573
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h1052
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h1758
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h1776
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h691
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h237
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h157
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h64
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h232
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h325
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h326
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h255
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h164
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h278
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h164
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h190
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h764
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h44
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h179
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h306
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h160
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h146
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h453
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h1042
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h853
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h893
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h552
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h249
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h170
-rw-r--r--include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h99
-rw-r--r--include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h104
-rw-r--r--include/asm-cris/arch-v32/hwregs/marb_bp_defs.h205
-rw-r--r--include/asm-cris/arch-v32/hwregs/marb_defs.h475
-rw-r--r--include/asm-cris/arch-v32/hwregs/pinmux_defs.h357
-rw-r--r--include/asm-cris/arch-v32/hwregs/reg_map.h103
-rw-r--r--include/asm-cris/arch-v32/hwregs/reg_rdwr.h15
-rw-r--r--include/asm-cris/arch-v32/hwregs/rt_trace_defs.h173
-rw-r--r--include/asm-cris/arch-v32/hwregs/ser_defs.h308
-rw-r--r--include/asm-cris/arch-v32/hwregs/sser_defs.h331
-rw-r--r--include/asm-cris/arch-v32/hwregs/strcop.h57
-rw-r--r--include/asm-cris/arch-v32/hwregs/strcop_defs.h109
-rw-r--r--include/asm-cris/arch-v32/hwregs/strmux_defs.h127
-rw-r--r--include/asm-cris/arch-v32/hwregs/supp_reg.h78
-rw-r--r--include/asm-cris/arch-v32/hwregs/timer_defs.h266
-rw-r--r--include/asm-cris/arch-v32/ide.h61
-rw-r--r--include/asm-cris/arch-v32/intmem.h9
-rw-r--r--include/asm-cris/arch-v32/io.h98
-rw-r--r--include/asm-cris/arch-v32/irq.h120
-rw-r--r--include/asm-cris/arch-v32/juliette.h326
-rw-r--r--include/asm-cris/arch-v32/memmap.h24
-rw-r--r--include/asm-cris/arch-v32/mmu.h111
-rw-r--r--include/asm-cris/arch-v32/offset.h35
-rw-r--r--include/asm-cris/arch-v32/page.h28
-rw-r--r--include/asm-cris/arch-v32/pgtable.h9
-rw-r--r--include/asm-cris/arch-v32/pinmux.h39
-rw-r--r--include/asm-cris/arch-v32/processor.h60
-rw-r--r--include/asm-cris/arch-v32/ptrace.h114
-rw-r--r--include/asm-cris/arch-v32/spinlock.h163
-rw-r--r--include/asm-cris/arch-v32/system.h79
-rw-r--r--include/asm-cris/arch-v32/thread_info.h13
-rw-r--r--include/asm-cris/arch-v32/timex.h31
-rw-r--r--include/asm-cris/arch-v32/tlb.h14
-rw-r--r--include/asm-cris/arch-v32/uaccess.h748
-rw-r--r--include/asm-cris/arch-v32/unistd.h148
-rw-r--r--include/asm-cris/arch-v32/user.h41
-rw-r--r--include/asm-cris/atomic.h66
-rw-r--r--include/asm-cris/axisflashmap.h3
-rw-r--r--include/asm-cris/bitops.h35
-rw-r--r--include/asm-cris/dma-mapping.h170
-rw-r--r--include/asm-cris/dma.h8
-rw-r--r--include/asm-cris/elf.h45
-rw-r--r--include/asm-cris/etraxgpio.h10
-rw-r--r--include/asm-cris/hardirq.h5
-rw-r--r--include/asm-cris/hw_irq.h7
-rw-r--r--include/asm-cris/ide.h1
-rw-r--r--include/asm-cris/io.h103
-rw-r--r--include/asm-cris/irq.h10
-rw-r--r--include/asm-cris/kmap_types.h4
-rw-r--r--include/asm-cris/mmu_context.h2
-rw-r--r--include/asm-cris/page.h7
-rw-r--r--include/asm-cris/pci.h102
-rw-r--r--include/asm-cris/pgalloc.h10
-rw-r--r--include/asm-cris/pgtable.h42
-rw-r--r--include/asm-cris/processor.h9
-rw-r--r--include/asm-cris/ptrace.h2
-rw-r--r--include/asm-cris/semaphore.h21
-rw-r--r--include/asm-cris/smp.h7
-rw-r--r--include/asm-cris/spinlock.h1
-rw-r--r--include/asm-cris/sync_serial.h106
-rw-r--r--include/asm-cris/termbits.h2
-rw-r--r--include/asm-cris/thread_info.h2
-rw-r--r--include/asm-cris/timex.h2
-rw-r--r--include/asm-cris/tlbflush.h19
-rw-r--r--include/asm-cris/types.h2
-rw-r--r--include/asm-cris/unistd.h11
-rw-r--r--include/asm-generic/pci.h8
-rw-r--r--include/asm-generic/sections.h1
-rw-r--r--include/asm-i386/bitops.h53
-rw-r--r--include/asm-i386/mach-visws/do_timer.h1
-rw-r--r--include/asm-i386/pci.h4
-rw-r--r--include/asm-i386/ptrace.h3
-rw-r--r--include/asm-i386/smp.h3
-rw-r--r--include/asm-ia64/unistd.h3
-rw-r--r--include/asm-parisc/pci.h4
-rw-r--r--include/asm-ppc/cpm2.h5
-rw-r--r--include/asm-ppc/dma-mapping.h2
-rw-r--r--include/asm-ppc/ibm44x.h34
-rw-r--r--include/asm-ppc/ibm4xx.h4
-rw-r--r--include/asm-ppc/ibm_ocp.h12
-rw-r--r--include/asm-ppc/mpc10x.h3
-rw-r--r--include/asm-ppc/pci.h4
-rw-r--r--include/asm-ppc/pgtable.h52
-rw-r--r--include/asm-ppc/ppc_asm.h6
-rw-r--r--include/asm-ppc/unistd.h5
-rw-r--r--include/asm-ppc64/iSeries/HvReleaseData.h11
-rw-r--r--include/asm-ppc64/iSeries/LparMap.h23
-rw-r--r--include/asm-ppc64/machdep.h2
-rw-r--r--include/asm-ppc64/mmu.h5
-rw-r--r--include/asm-ppc64/pci.h4
-rw-r--r--include/asm-ppc64/topology.h5
-rw-r--r--include/asm-ppc64/unistd.h5
-rw-r--r--include/asm-ppc64/xics.h2
-rw-r--r--include/asm-s390/atomic.h8
-rw-r--r--include/asm-s390/bitops.h440
-rw-r--r--include/asm-s390/lowcore.h4
-rw-r--r--include/asm-s390/processor.h5
-rw-r--r--include/asm-s390/spinlock.h252
-rw-r--r--include/asm-s390/unistd.h7
-rw-r--r--include/asm-sparc/unistd.h6
-rw-r--r--include/asm-sparc64/unistd.h6
-rw-r--r--include/asm-um/vm86.h6
-rw-r--r--include/asm-v850/bitops.h6
-rw-r--r--include/asm-v850/cache.h7
-rw-r--r--include/asm-v850/io.h37
-rw-r--r--include/asm-v850/page.h5
-rw-r--r--include/asm-v850/pci.h37
-rw-r--r--include/asm-v850/pgtable.h2
-rw-r--r--include/asm-v850/v850e2_cache.h5
-rw-r--r--include/asm-x86_64/bitops.h3
-rw-r--r--include/asm-x86_64/bug.h13
-rw-r--r--include/asm-x86_64/desc.h1
-rw-r--r--include/asm-x86_64/ipi.h45
-rw-r--r--include/asm-x86_64/irq.h2
-rw-r--r--include/asm-x86_64/msr.h2
-rw-r--r--include/asm-x86_64/pci.h4
-rw-r--r--include/asm-x86_64/pgtable.h2
-rw-r--r--include/asm-x86_64/smp.h6
-rw-r--r--include/asm-x86_64/system.h7
-rw-r--r--include/asm-x86_64/tlbflush.h9
-rw-r--r--include/linux/acpi.h4
-rw-r--r--include/linux/blkdev.h1
-rw-r--r--include/linux/dcookies.h4
-rw-r--r--include/linux/fs.h6
-rw-r--r--include/linux/fsnotify.h31
-rw-r--r--include/linux/ftape.h2
-rw-r--r--include/linux/input.h6
-rw-r--r--include/linux/mbcache.h2
-rw-r--r--include/linux/mm.h22
-rw-r--r--include/linux/netlink.h4
-rw-r--r--include/linux/pci.h5
-rw-r--r--include/linux/pci_ids.h1
-rw-r--r--include/linux/raid/bitmap.h1
-rw-r--r--include/linux/serial_core.h2
-rw-r--r--include/linux/slab.h2
-rw-r--r--include/linux/swap.h3
-rw-r--r--include/linux/sysctl.h1
-rw-r--r--include/linux/uinput.h5
-rw-r--r--include/linux/usb_input.h25
-rw-r--r--include/linux/watchdog.h10
-rw-r--r--include/linux/zlib.h5
-rw-r--r--include/media/tuner.h4
-rw-r--r--include/media/tveeprom.h1
-rw-r--r--include/net/bluetooth/bluetooth.h8
-rw-r--r--include/net/tcp.h2
-rw-r--r--include/sound/core.h37
-rw-r--r--include/sound/driver.h2
-rw-r--r--include/sound/emu10k1.h1
-rw-r--r--include/sound/version.h4
-rw-r--r--include/sound/vx_core.h16
260 files changed, 33615 insertions, 992 deletions
diff --git a/include/acpi/acpi_drivers.h b/include/acpi/acpi_drivers.h
index caeaa71a5663..579fe191b7e7 100644
--- a/include/acpi/acpi_drivers.h
+++ b/include/acpi/acpi_drivers.h
@@ -56,8 +56,9 @@
56/* ACPI PCI Interrupt Link (pci_link.c) */ 56/* ACPI PCI Interrupt Link (pci_link.c) */
57 57
58int acpi_irq_penalty_init (void); 58int acpi_irq_penalty_init (void);
59int acpi_pci_link_get_irq (acpi_handle handle, int index, int *edge_level, 59int acpi_pci_link_allocate_irq (acpi_handle handle, int index, int *edge_level,
60 int *active_high_low, char **name); 60 int *active_high_low, char **name);
61int acpi_pci_link_free_irq(acpi_handle handle);
61 62
62/* ACPI PCI Interrupt Routing (pci_irq.c) */ 63/* ACPI PCI Interrupt Routing (pci_irq.c) */
63 64
diff --git a/include/asm-alpha/pci.h b/include/asm-alpha/pci.h
index 28957697e59c..f681e675b823 100644
--- a/include/asm-alpha/pci.h
+++ b/include/asm-alpha/pci.h
@@ -251,6 +251,9 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
251extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *, 251extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *,
252 struct resource *); 252 struct resource *);
253 253
254extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
255 struct pci_bus_region *region);
256
254#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index 257#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
255 258
256static inline int pci_proc_domain(struct pci_bus *bus) 259static inline int pci_proc_domain(struct pci_bus *bus)
diff --git a/include/asm-alpha/unistd.h b/include/asm-alpha/unistd.h
index 535bc425f243..ef25b6585119 100644
--- a/include/asm-alpha/unistd.h
+++ b/include/asm-alpha/unistd.h
@@ -377,8 +377,13 @@
377#define __NR_add_key 439 377#define __NR_add_key 439
378#define __NR_request_key 440 378#define __NR_request_key 440
379#define __NR_keyctl 441 379#define __NR_keyctl 441
380#define __NR_ioprio_set 442
381#define __NR_ioprio_get 443
382#define __NR_inotify_init 444
383#define __NR_inotify_add_watch 445
384#define __NR_inotify_rm_watch 446
380 385
381#define NR_SYSCALLS 442 386#define NR_SYSCALLS 447
382 387
383#if defined(__GNUC__) 388#if defined(__GNUC__)
384 389
diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h
index c1adc6b3e86d..aad7aad026b3 100644
--- a/include/asm-arm/bitops.h
+++ b/include/asm-arm/bitops.h
@@ -229,6 +229,7 @@ extern int _find_next_zero_bit_be(const void * p, int size, int offset);
229extern int _find_first_bit_be(const unsigned long *p, unsigned size); 229extern int _find_first_bit_be(const unsigned long *p, unsigned size);
230extern int _find_next_bit_be(const unsigned long *p, int size, int offset); 230extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
231 231
232#ifndef CONFIG_SMP
232/* 233/*
233 * The __* form of bitops are non-atomic and may be reordered. 234 * The __* form of bitops are non-atomic and may be reordered.
234 */ 235 */
@@ -241,6 +242,10 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
241 (__builtin_constant_p(nr) ? \ 242 (__builtin_constant_p(nr) ? \
242 ____atomic_##name(nr, p) : \ 243 ____atomic_##name(nr, p) : \
243 _##name##_be(nr,p)) 244 _##name##_be(nr,p))
245#else
246#define ATOMIC_BITOP_LE(name,nr,p) _##name##_le(nr,p)
247#define ATOMIC_BITOP_BE(name,nr,p) _##name##_be(nr,p)
248#endif
244 249
245#define NONATOMIC_BITOP(name,nr,p) \ 250#define NONATOMIC_BITOP(name,nr,p) \
246 (____nonatomic_##name(nr, p)) 251 (____nonatomic_##name(nr, p))
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
index b28f1c95dd62..38ea5899a580 100644
--- a/include/asm-arm/pci.h
+++ b/include/asm-arm/pci.h
@@ -60,6 +60,10 @@ extern void
60pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 60pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
61 struct resource *res); 61 struct resource *res);
62 62
63extern void
64pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
65 struct pci_bus_region *region);
66
63static inline void pcibios_add_platform_entries(struct pci_dev *dev) 67static inline void pcibios_add_platform_entries(struct pci_dev *dev)
64{ 68{
65} 69}
diff --git a/include/asm-cris/arch-v10/atomic.h b/include/asm-cris/arch-v10/atomic.h
new file mode 100644
index 000000000000..6ef5e7d09024
--- /dev/null
+++ b/include/asm-cris/arch-v10/atomic.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_CRIS_ARCH_ATOMIC__
2#define __ASM_CRIS_ARCH_ATOMIC__
3
4#define cris_atomic_save(addr, flags) local_irq_save(flags);
5#define cris_atomic_restore(addr, flags) local_irq_restore(flags);
6
7#endif
diff --git a/include/asm-cris/arch-v10/bitops.h b/include/asm-cris/arch-v10/bitops.h
index 21b7ae8c9bb3..b73f5396e5a6 100644
--- a/include/asm-cris/arch-v10/bitops.h
+++ b/include/asm-cris/arch-v10/bitops.h
@@ -51,7 +51,7 @@ extern inline unsigned long ffz(unsigned long w)
51 * 51 *
52 * Undefined if no bit exists, so code should check against 0 first. 52 * Undefined if no bit exists, so code should check against 0 first.
53 */ 53 */
54extern __inline__ unsigned long __ffs(unsigned long word) 54extern inline unsigned long __ffs(unsigned long word)
55{ 55{
56 return cris_swapnwbrlz(~word); 56 return cris_swapnwbrlz(~word);
57} 57}
diff --git a/include/asm-cris/arch-v10/dma.h b/include/asm-cris/arch-v10/dma.h
index 9e078b9bc934..ecb9dba6fa4f 100644
--- a/include/asm-cris/arch-v10/dma.h
+++ b/include/asm-cris/arch-v10/dma.h
@@ -44,3 +44,31 @@
44#define USB_RX_DMA_NBR 9 44#define USB_RX_DMA_NBR 9
45 45
46#endif 46#endif
47
48enum dma_owner
49{
50 dma_eth,
51 dma_ser0,
52 dma_ser1, /* Async and sync */
53 dma_ser2,
54 dma_ser3, /* Async and sync */
55 dma_ata,
56 dma_par0,
57 dma_par1,
58 dma_ext0,
59 dma_ext1,
60 dma_int6,
61 dma_int7,
62 dma_usb,
63 dma_scsi0,
64 dma_scsi1
65};
66
67/* Masks used by cris_request_dma options: */
68#define DMA_VERBOSE_ON_ERROR (1<<0)
69#define DMA_PANIC_ON_ERROR ((1<<1)|DMA_VERBOSE_ON_ERROR)
70
71int cris_request_dma(unsigned int dmanr, const char * device_id,
72 unsigned options, enum dma_owner owner);
73
74void cris_free_dma(unsigned int dmanr, const char * device_id);
diff --git a/include/asm-cris/arch-v10/elf.h b/include/asm-cris/arch-v10/elf.h
index 2a2201ca538e..1c38ee728b17 100644
--- a/include/asm-cris/arch-v10/elf.h
+++ b/include/asm-cris/arch-v10/elf.h
@@ -1,6 +1,16 @@
1#ifndef __ASMCRIS_ARCH_ELF_H 1#ifndef __ASMCRIS_ARCH_ELF_H
2#define __ASMCRIS_ARCH_ELF_H 2#define __ASMCRIS_ARCH_ELF_H
3 3
4#define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10
5
6/*
7 * This is used to ensure we don't load something for the wrong architecture.
8 */
9#define elf_check_arch(x) \
10 ((x)->e_machine == EM_CRIS \
11 && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10 \
12 || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32))))
13
4/* 14/*
5 * ELF register definitions.. 15 * ELF register definitions..
6 */ 16 */
diff --git a/include/asm-cris/arch-v10/ide.h b/include/asm-cris/arch-v10/ide.h
new file mode 100644
index 000000000000..8cf2d7cb22ac
--- /dev/null
+++ b/include/asm-cris/arch-v10/ide.h
@@ -0,0 +1,99 @@
1/*
2 * linux/include/asm-cris/ide.h
3 *
4 * Copyright (C) 2000, 2001, 2002 Axis Communications AB
5 *
6 * Authors: Bjorn Wesen
7 *
8 */
9
10/*
11 * This file contains the ETRAX 100LX specific IDE code.
12 */
13
14#ifndef __ASMCRIS_IDE_H
15#define __ASMCRIS_IDE_H
16
17#ifdef __KERNEL__
18
19#include <asm/arch/svinto.h>
20#include <asm/io.h>
21#include <asm-generic/ide_iops.h>
22
23
24/* ETRAX 100 can support 4 IDE busses on the same pins (serialized) */
25
26#define MAX_HWIFS 4
27
28extern __inline__ int ide_default_irq(unsigned long base)
29{
30 /* all IDE busses share the same IRQ, number 4.
31 * this has the side-effect that ide-probe.c will cluster our 4 interfaces
32 * together in a hwgroup, and will serialize accesses. this is good, because
33 * we can't access more than one interface at the same time on ETRAX100.
34 */
35 return 4;
36}
37
38extern __inline__ unsigned long ide_default_io_base(int index)
39{
40 /* we have no real I/O base address per interface, since all go through the
41 * same register. but in a bitfield in that register, we have the i/f number.
42 * so we can use the io_base to remember that bitfield.
43 */
44 static const unsigned long io_bases[MAX_HWIFS] = {
45 IO_FIELD(R_ATA_CTRL_DATA, sel, 0),
46 IO_FIELD(R_ATA_CTRL_DATA, sel, 1),
47 IO_FIELD(R_ATA_CTRL_DATA, sel, 2),
48 IO_FIELD(R_ATA_CTRL_DATA, sel, 3)
49 };
50 return io_bases[index];
51}
52
53/* this is called once for each interface, to setup the port addresses. data_port is the result
54 * of the ide_default_io_base call above. ctrl_port will be 0, but that is don't care for us.
55 */
56
57extern __inline__ void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port, unsigned long ctrl_port, int *irq)
58{
59 int i;
60
61 /* fill in ports for ATA addresses 0 to 7 */
62
63 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
64 hw->io_ports[i] = data_port |
65 IO_FIELD(R_ATA_CTRL_DATA, addr, i) |
66 IO_STATE(R_ATA_CTRL_DATA, cs0, active);
67 }
68
69 /* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */
70
71 hw->io_ports[IDE_CONTROL_OFFSET] = data_port |
72 IO_FIELD(R_ATA_CTRL_DATA, addr, 6) |
73 IO_STATE(R_ATA_CTRL_DATA, cs1, active);
74
75 /* whats this for ? */
76
77 hw->io_ports[IDE_IRQ_OFFSET] = 0;
78}
79
80extern __inline__ void ide_init_default_hwifs(void)
81{
82 hw_regs_t hw;
83 int index;
84
85 for(index = 0; index < MAX_HWIFS; index++) {
86 ide_init_hwif_ports(&hw, ide_default_io_base(index), 0, NULL);
87 hw.irq = ide_default_irq(ide_default_io_base(index));
88 ide_register_hw(&hw, NULL);
89 }
90}
91
92/* some configuration options we don't need */
93
94#undef SUPPORT_VLB_SYNC
95#define SUPPORT_VLB_SYNC 0
96
97#endif /* __KERNEL__ */
98
99#endif /* __ASMCRIS_IDE_H */
diff --git a/include/asm-cris/arch-v10/io.h b/include/asm-cris/arch-v10/io.h
index 0bc38a0313c1..dd39198ec67d 100644
--- a/include/asm-cris/arch-v10/io.h
+++ b/include/asm-cris/arch-v10/io.h
@@ -6,6 +6,7 @@
6 6
7/* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */ 7/* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */
8 8
9extern unsigned long gen_config_ii_shadow;
9extern unsigned long port_g_data_shadow; 10extern unsigned long port_g_data_shadow;
10extern unsigned char port_pa_dir_shadow; 11extern unsigned char port_pa_dir_shadow;
11extern unsigned char port_pa_data_shadow; 12extern unsigned char port_pa_data_shadow;
diff --git a/include/asm-cris/arch-v10/io_interface_mux.h b/include/asm-cris/arch-v10/io_interface_mux.h
new file mode 100644
index 000000000000..d92500080883
--- /dev/null
+++ b/include/asm-cris/arch-v10/io_interface_mux.h
@@ -0,0 +1,75 @@
1/* IO interface mux allocator for ETRAX100LX.
2 * Copyright 2004, Axis Communications AB
3 * $Id: io_interface_mux.h,v 1.1 2004/12/13 12:21:53 starvik Exp $
4 */
5
6
7#ifndef _IO_INTERFACE_MUX_H
8#define _IO_INTERFACE_MUX_H
9
10
11/* C.f. ETRAX100LX Designer's Reference 20.9 */
12
13/* The order in enum must match the order of interfaces[] in
14 * io_interface_mux.c */
15enum cris_io_interface {
16 /* Begin Non-multiplexed interfaces */
17 if_eth = 0,
18 if_serial_0,
19 /* End Non-multiplexed interfaces */
20 if_serial_1,
21 if_serial_2,
22 if_serial_3,
23 if_sync_serial_1,
24 if_sync_serial_3,
25 if_shared_ram,
26 if_shared_ram_w,
27 if_par_0,
28 if_par_1,
29 if_par_w,
30 if_scsi8_0,
31 if_scsi8_1,
32 if_scsi_w,
33 if_ata,
34 if_csp,
35 if_i2c,
36 if_usb_1,
37 if_usb_2,
38 /* GPIO pins */
39 if_gpio_grp_a,
40 if_gpio_grp_b,
41 if_gpio_grp_c,
42 if_gpio_grp_d,
43 if_gpio_grp_e,
44 if_gpio_grp_f,
45 if_max_interfaces,
46 if_unclaimed
47};
48
49int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id);
50
51void cris_free_io_interface(enum cris_io_interface ioif);
52
53/* port can be 'a', 'b' or 'g' */
54int cris_io_interface_allocate_pins(const enum cris_io_interface ioif,
55 const char port,
56 const unsigned start_bit,
57 const unsigned stop_bit);
58
59/* port can be 'a', 'b' or 'g' */
60int cris_io_interface_free_pins(const enum cris_io_interface ioif,
61 const char port,
62 const unsigned start_bit,
63 const unsigned stop_bit);
64
65int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available,
66 const unsigned int gpio_out_available,
67 const unsigned char pa_available,
68 const unsigned char pb_available));
69
70void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available,
71 const unsigned int gpio_out_available,
72 const unsigned char pa_available,
73 const unsigned char pb_available));
74
75#endif /* _IO_INTERFACE_MUX_H */
diff --git a/include/asm-cris/arch-v10/irq.h b/include/asm-cris/arch-v10/irq.h
index a2a6e1533ea0..4fa8945b0263 100644
--- a/include/asm-cris/arch-v10/irq.h
+++ b/include/asm-cris/arch-v10/irq.h
@@ -74,12 +74,9 @@ struct etrax_interrupt_vector {
74}; 74};
75 75
76extern struct etrax_interrupt_vector *etrax_irv; 76extern struct etrax_interrupt_vector *etrax_irv;
77void set_int_vector(int n, irqvectptr addr, irqvectptr saddr); 77void set_int_vector(int n, irqvectptr addr);
78void set_break_vector(int n, irqvectptr addr); 78void set_break_vector(int n, irqvectptr addr);
79 79
80#define mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr));
81#define unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr));
82
83#define __STR(x) #x 80#define __STR(x) #x
84#define STR(x) __STR(x) 81#define STR(x) __STR(x)
85 82
@@ -121,26 +118,17 @@ void set_break_vector(int n, irqvectptr addr);
121 118
122#define BUILD_IRQ(nr,mask) \ 119#define BUILD_IRQ(nr,mask) \
123void IRQ_NAME(nr); \ 120void IRQ_NAME(nr); \
124void sIRQ_NAME(nr); \
125void BAD_IRQ_NAME(nr); \
126__asm__ ( \ 121__asm__ ( \
127 ".text\n\t" \ 122 ".text\n\t" \
128 "IRQ" #nr "_interrupt:\n\t" \ 123 "IRQ" #nr "_interrupt:\n\t" \
129 SAVE_ALL \ 124 SAVE_ALL \
130 "sIRQ" #nr "_interrupt:\n\t" /* shortcut for the multiple irq handler */ \
131 BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \ 125 BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \
132 "moveq "#nr",$r10\n\t" \ 126 "moveq "#nr",$r10\n\t" \
133 "move.d $sp,$r11\n\t" \ 127 "move.d $sp,$r11\n\t" \
134 "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ 128 "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
135 UNBLOCK_IRQ(mask) \ 129 UNBLOCK_IRQ(mask) \
136 "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ 130 "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
137 "jump ret_from_intr\n\t" \ 131 "jump ret_from_intr\n\t");
138 "bad_IRQ" #nr "_interrupt:\n\t" \
139 "push $r0\n\t" \
140 BLOCK_IRQ(mask,nr) \
141 "pop $r0\n\t" \
142 "reti\n\t" \
143 "nop\n");
144 132
145/* This is subtle. The timer interrupt is crucial and it should not be disabled for 133/* This is subtle. The timer interrupt is crucial and it should not be disabled for
146 * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would 134 * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would
@@ -159,23 +147,14 @@ __asm__ ( \
159 147
160#define BUILD_TIMER_IRQ(nr,mask) \ 148#define BUILD_TIMER_IRQ(nr,mask) \
161void IRQ_NAME(nr); \ 149void IRQ_NAME(nr); \
162void sIRQ_NAME(nr); \
163void BAD_IRQ_NAME(nr); \
164__asm__ ( \ 150__asm__ ( \
165 ".text\n\t" \ 151 ".text\n\t" \
166 "IRQ" #nr "_interrupt:\n\t" \ 152 "IRQ" #nr "_interrupt:\n\t" \
167 SAVE_ALL \ 153 SAVE_ALL \
168 "sIRQ" #nr "_interrupt:\n\t" /* shortcut for the multiple irq handler */ \
169 "moveq "#nr",$r10\n\t" \ 154 "moveq "#nr",$r10\n\t" \
170 "move.d $sp,$r11\n\t" \ 155 "move.d $sp,$r11\n\t" \
171 "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ 156 "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
172 "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ 157 "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
173 "jump ret_from_intr\n\t" \ 158 "jump ret_from_intr\n\t");
174 "bad_IRQ" #nr "_interrupt:\n\t" \
175 "push $r0\n\t" \
176 BLOCK_IRQ(mask,nr) \
177 "pop $r0\n\t" \
178 "reti\n\t" \
179 "nop\n");
180 159
181#endif 160#endif
diff --git a/include/asm-cris/arch-v10/memmap.h b/include/asm-cris/arch-v10/memmap.h
new file mode 100644
index 000000000000..13f3b971407f
--- /dev/null
+++ b/include/asm-cris/arch-v10/memmap.h
@@ -0,0 +1,22 @@
1#ifndef _ASM_ARCH_MEMMAP_H
2#define _ASM_ARCH_MEMMAP_H
3
4#define MEM_CSE0_START (0x00000000)
5#define MEM_CSE0_SIZE (0x04000000)
6#define MEM_CSE1_START (0x04000000)
7#define MEM_CSE1_SIZE (0x04000000)
8#define MEM_CSR0_START (0x08000000)
9#define MEM_CSR1_START (0x0c000000)
10#define MEM_CSP0_START (0x10000000)
11#define MEM_CSP1_START (0x14000000)
12#define MEM_CSP2_START (0x18000000)
13#define MEM_CSP3_START (0x1c000000)
14#define MEM_CSP4_START (0x20000000)
15#define MEM_CSP5_START (0x24000000)
16#define MEM_CSP6_START (0x28000000)
17#define MEM_CSP7_START (0x2c000000)
18#define MEM_DRAM_START (0x40000000)
19
20#define MEM_NON_CACHEABLE (0x80000000)
21
22#endif
diff --git a/include/asm-cris/arch-v10/mmu.h b/include/asm-cris/arch-v10/mmu.h
index d18aa00e50bc..df84f1716e6b 100644
--- a/include/asm-cris/arch-v10/mmu.h
+++ b/include/asm-cris/arch-v10/mmu.h
@@ -7,7 +7,10 @@
7 7
8/* type used in struct mm to couple an MMU context to an active mm */ 8/* type used in struct mm to couple an MMU context to an active mm */
9 9
10typedef unsigned int mm_context_t; 10typedef struct
11{
12 unsigned int page_id;
13} mm_context_t;
11 14
12/* kernel memory segments */ 15/* kernel memory segments */
13 16
diff --git a/include/asm-cris/arch-v10/offset.h b/include/asm-cris/arch-v10/offset.h
index fcbd77eab281..675b51d85639 100644
--- a/include/asm-cris/arch-v10/offset.h
+++ b/include/asm-cris/arch-v10/offset.h
@@ -25,7 +25,7 @@
25#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ 25#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */
26#define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */ 26#define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */
27 27
28#define TASK_pid 133 /* offsetof(struct task_struct, pid) */ 28#define TASK_pid 141 /* offsetof(struct task_struct, pid) */
29 29
30#define LCLONE_VM 256 /* CLONE_VM */ 30#define LCLONE_VM 256 /* CLONE_VM */
31#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ 31#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */
diff --git a/include/asm-cris/arch-v10/processor.h b/include/asm-cris/arch-v10/processor.h
index 9355d8675a58..e23df8dc96e8 100644
--- a/include/asm-cris/arch-v10/processor.h
+++ b/include/asm-cris/arch-v10/processor.h
@@ -59,4 +59,12 @@ struct thread_struct {
59 wrusp(usp); \ 59 wrusp(usp); \
60} while(0) 60} while(0)
61 61
62/* Called when handling a kernel bus fault fixup.
63 *
64 * After a fixup we do not want to return by restoring the CPU-state
65 * anymore, so switch frame-types (see ptrace.h)
66 */
67#define arch_fixup(regs) \
68 regs->frametype = CRIS_FRAME_NORMAL;
69
62#endif 70#endif
diff --git a/include/asm-cris/arch-v10/system.h b/include/asm-cris/arch-v10/system.h
index 781ca30229a8..6cc35642b8ab 100644
--- a/include/asm-cris/arch-v10/system.h
+++ b/include/asm-cris/arch-v10/system.h
@@ -11,6 +11,8 @@ extern inline unsigned long rdvr(void) {
11 return vr; 11 return vr;
12} 12}
13 13
14#define cris_machine_name "cris"
15
14/* read/write the user-mode stackpointer */ 16/* read/write the user-mode stackpointer */
15 17
16extern inline unsigned long rdusp(void) { 18extern inline unsigned long rdusp(void) {
diff --git a/include/asm-cris/arch-v32/arbiter.h b/include/asm-cris/arch-v32/arbiter.h
new file mode 100644
index 000000000000..dba3c285cacd
--- /dev/null
+++ b/include/asm-cris/arch-v32/arbiter.h
@@ -0,0 +1,30 @@
1#ifndef _ASM_CRIS_ARCH_ARBITER_H
2#define _ASM_CRIS_ARCH_ARBITER_H
3
4#define EXT_REGION 0
5#define INT_REGION 1
6
7typedef void (watch_callback)(void);
8
9enum
10{
11 arbiter_all_dmas = 0x3ff,
12 arbiter_cpu = 0xc00,
13 arbiter_all_clients = 0x3fff
14};
15
16enum
17{
18 arbiter_all_read = 0x55,
19 arbiter_all_write = 0xaa,
20 arbiter_all_accesses = 0xff
21};
22
23int crisv32_arbiter_allocate_bandwith(int client, int region,
24 unsigned long bandwidth);
25int crisv32_arbiter_watch(unsigned long start, unsigned long size,
26 unsigned long clients, unsigned long accesses,
27 watch_callback* cb);
28int crisv32_arbiter_unwatch(int id);
29
30#endif
diff --git a/include/asm-cris/arch-v32/atomic.h b/include/asm-cris/arch-v32/atomic.h
new file mode 100644
index 000000000000..bbfb7a5ae315
--- /dev/null
+++ b/include/asm-cris/arch-v32/atomic.h
@@ -0,0 +1,36 @@
1#ifndef __ASM_CRIS_ARCH_ATOMIC__
2#define __ASM_CRIS_ARCH_ATOMIC__
3
4#include <asm/system.h>
5
6extern void cris_spin_unlock(void *l, int val);
7extern void cris_spin_lock(void *l);
8extern int cris_spin_trylock(void* l);
9
10#ifndef CONFIG_SMP
11#define cris_atomic_save(addr, flags) local_irq_save(flags);
12#define cris_atomic_restore(addr, flags) local_irq_restore(flags);
13#else
14
15extern spinlock_t cris_atomic_locks[];
16#define LOCK_COUNT 128
17#define HASH_ADDR(a) (((int)a) & 127)
18
19#define cris_atomic_save(addr, flags) \
20 local_irq_save(flags); \
21 cris_spin_lock((void*)&cris_atomic_locks[HASH_ADDR(addr)].lock);
22
23#define cris_atomic_restore(addr, flags) \
24 { \
25 spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \
26 __asm__ volatile ("move.d %1,%0" \
27 : "=m" (lock->lock) \
28 : "r" (1) \
29 : "memory"); \
30 local_irq_restore(flags); \
31 }
32
33#endif
34
35#endif
36
diff --git a/include/asm-cris/arch-v32/bitops.h b/include/asm-cris/arch-v32/bitops.h
new file mode 100644
index 000000000000..e40a58d3b862
--- /dev/null
+++ b/include/asm-cris/arch-v32/bitops.h
@@ -0,0 +1,64 @@
1#ifndef _ASM_CRIS_ARCH_BITOPS_H
2#define _ASM_CRIS_ARCH_BITOPS_H
3
4/*
5 * Helper functions for the core of the ff[sz] functions. They compute the
6 * number of leading zeroes of a bits-in-byte, byte-in-word and
7 * word-in-dword-swapped number. They differ in that the first function also
8 * inverts all bits in the input.
9 */
10
11extern inline unsigned long
12cris_swapnwbrlz(unsigned long w)
13{
14 unsigned long res;
15
16 __asm__ __volatile__ ("swapnwbr %0\n\t"
17 "lz %0,%0"
18 : "=r" (res) : "0" (w));
19
20 return res;
21}
22
23extern inline unsigned long
24cris_swapwbrlz(unsigned long w)
25{
26 unsigned long res;
27
28 __asm__ __volatile__ ("swapwbr %0\n\t"
29 "lz %0,%0"
30 : "=r" (res) : "0" (w));
31
32 return res;
33}
34
35/*
36 * Find First Zero in word. Undefined if no zero exist, so the caller should
37 * check against ~0 first.
38 */
39extern inline unsigned long
40ffz(unsigned long w)
41{
42 return cris_swapnwbrlz(w);
43}
44
45/*
46 * Find First Set bit in word. Undefined if no 1 exist, so the caller
47 * should check against 0 first.
48 */
49extern inline unsigned long
50__ffs(unsigned long w)
51{
52 return cris_swapnwbrlz(~w);
53}
54
55/*
56 * Find First Bit that is set.
57 */
58extern inline unsigned long
59kernel_ffs(unsigned long w)
60{
61 return w ? cris_swapwbrlz (w) + 1 : 0;
62}
63
64#endif /* _ASM_CRIS_ARCH_BITOPS_H */
diff --git a/include/asm-cris/arch-v32/byteorder.h b/include/asm-cris/arch-v32/byteorder.h
new file mode 100644
index 000000000000..74846ee6cf99
--- /dev/null
+++ b/include/asm-cris/arch-v32/byteorder.h
@@ -0,0 +1,20 @@
1#ifndef _ASM_CRIS_ARCH_BYTEORDER_H
2#define _ASM_CRIS_ARCH_BYTEORDER_H
3
4#include <asm/types.h>
5
6extern __inline__ __const__ __u32
7___arch__swab32(__u32 x)
8{
9 __asm__ __volatile__ ("swapwb %0" : "=r" (x) : "0" (x));
10 return (x);
11}
12
13extern __inline__ __const__ __u16
14___arch__swab16(__u16 x)
15{
16 __asm__ __volatile__ ("swapb %0" : "=r" (x) : "0" (x));
17 return (x);
18}
19
20#endif /* _ASM_CRIS_ARCH_BYTEORDER_H */
diff --git a/include/asm-cris/arch-v32/cache.h b/include/asm-cris/arch-v32/cache.h
new file mode 100644
index 000000000000..4fed8d62ccc8
--- /dev/null
+++ b/include/asm-cris/arch-v32/cache.h
@@ -0,0 +1,9 @@
1#ifndef _ASM_CRIS_ARCH_CACHE_H
2#define _ASM_CRIS_ARCH_CACHE_H
3
4/* A cache-line is 32 bytes. */
5#define L1_CACHE_BYTES 32
6#define L1_CACHE_SHIFT 5
7#define L1_CACHE_SHIFT_MAX 5
8
9#endif /* _ASM_CRIS_ARCH_CACHE_H */
diff --git a/include/asm-cris/arch-v32/checksum.h b/include/asm-cris/arch-v32/checksum.h
new file mode 100644
index 000000000000..a1d6b2a6cc44
--- /dev/null
+++ b/include/asm-cris/arch-v32/checksum.h
@@ -0,0 +1,29 @@
1#ifndef _ASM_CRIS_ARCH_CHECKSUM_H
2#define _ASM_CRIS_ARCH_CHECKSUM_H
3
4/*
5 * Check values used in TCP/UDP headers.
6 *
7 * The gain of doing this in assembler instead of C, is that C doesn't
8 * generate carry-additions for the 32-bit components of the
9 * checksum. Which means it would be necessary to split all those into
10 * 16-bit components and then add.
11 */
12extern inline unsigned int
13csum_tcpudp_nofold(unsigned long saddr, unsigned long daddr,
14 unsigned short len, unsigned short proto, unsigned int sum)
15{
16 int res;
17
18 __asm__ __volatile__ ("add.d %2, %0\n\t"
19 "addc %3, %0\n\t"
20 "addc %4, %0\n\t"
21 "addc 0, %0\n\t"
22 : "=r" (res)
23 : "0" (sum), "r" (daddr), "r" (saddr), \
24 "r" ((ntohs(len) << 16) + (proto << 8)));
25
26 return res;
27}
28
29#endif /* _ASM_CRIS_ARCH_CHECKSUM_H */
diff --git a/include/asm-cris/arch-v32/cryptocop.h b/include/asm-cris/arch-v32/cryptocop.h
new file mode 100644
index 000000000000..dfa1f66fb987
--- /dev/null
+++ b/include/asm-cris/arch-v32/cryptocop.h
@@ -0,0 +1,272 @@
1/*
2 * The device /dev/cryptocop is accessible using this driver using
3 * CRYPTOCOP_MAJOR (254) and minor number 0.
4 */
5
6#ifndef CRYPTOCOP_H
7#define CRYPTOCOP_H
8
9#include <linux/uio.h>
10
11
12#define CRYPTOCOP_SESSION_ID_NONE (0)
13
14typedef unsigned long long int cryptocop_session_id;
15
16/* cryptocop ioctls */
17#define ETRAXCRYPTOCOP_IOCTYPE (250)
18
19#define CRYPTOCOP_IO_CREATE_SESSION _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op)
20#define CRYPTOCOP_IO_CLOSE_SESSION _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op)
21#define CRYPTOCOP_IO_PROCESS_OP _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op)
22#define CRYPTOCOP_IO_MAXNR (3)
23
24typedef enum {
25 cryptocop_cipher_des = 0,
26 cryptocop_cipher_3des = 1,
27 cryptocop_cipher_aes = 2,
28 cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */
29 cryptocop_cipher_none
30} cryptocop_cipher_type;
31
32typedef enum {
33 cryptocop_digest_sha1 = 0,
34 cryptocop_digest_md5 = 1,
35 cryptocop_digest_none
36} cryptocop_digest_type;
37
38typedef enum {
39 cryptocop_csum_le = 0,
40 cryptocop_csum_be = 1,
41 cryptocop_csum_none
42} cryptocop_csum_type;
43
44typedef enum {
45 cryptocop_cipher_mode_ecb = 0,
46 cryptocop_cipher_mode_cbc,
47 cryptocop_cipher_mode_none
48} cryptocop_cipher_mode;
49
50typedef enum {
51 cryptocop_3des_eee = 0,
52 cryptocop_3des_eed = 1,
53 cryptocop_3des_ede = 2,
54 cryptocop_3des_edd = 3,
55 cryptocop_3des_dee = 4,
56 cryptocop_3des_ded = 5,
57 cryptocop_3des_dde = 6,
58 cryptocop_3des_ddd = 7
59} cryptocop_3des_mode;
60
61/* Usermode accessible (ioctl) operations. */
62struct strcop_session_op{
63 cryptocop_session_id ses_id;
64
65 cryptocop_cipher_type cipher; /* AES, DES, 3DES, m2m, none */
66
67 cryptocop_cipher_mode cmode; /* ECB, CBC, none */
68 cryptocop_3des_mode des3_mode;
69
70 cryptocop_digest_type digest; /* MD5, SHA1, none */
71
72 cryptocop_csum_type csum; /* BE, LE, none */
73
74 unsigned char *key;
75 size_t keylen;
76};
77
78#define CRYPTOCOP_CSUM_LENGTH (2)
79#define CRYPTOCOP_MAX_DIGEST_LENGTH (20) /* SHA-1 20, MD5 16 */
80#define CRYPTOCOP_MAX_IV_LENGTH (16) /* (3)DES==8, AES == 16 */
81#define CRYPTOCOP_MAX_KEY_LENGTH (32)
82
83struct strcop_crypto_op{
84 cryptocop_session_id ses_id;
85
86 /* Indata. */
87 unsigned char *indata;
88 size_t inlen; /* Total indata length. */
89
90 /* Cipher configuration. */
91 unsigned char do_cipher:1;
92 unsigned char decrypt:1; /* 1 == decrypt, 0 == encrypt */
93 unsigned char cipher_explicit:1;
94 size_t cipher_start;
95 size_t cipher_len;
96 /* cipher_iv is used if do_cipher and cipher_explicit and the cipher
97 mode is CBC. The length is controlled by the type of cipher,
98 e.g. DES/3DES 8 octets and AES 16 octets. */
99 unsigned char cipher_iv[CRYPTOCOP_MAX_IV_LENGTH];
100 /* Outdata. */
101 unsigned char *cipher_outdata;
102 size_t cipher_outlen;
103
104 /* digest configuration. */
105 unsigned char do_digest:1;
106 size_t digest_start;
107 size_t digest_len;
108 /* Outdata. The actual length is determined by the type of the digest. */
109 unsigned char digest[CRYPTOCOP_MAX_DIGEST_LENGTH];
110
111 /* Checksum configuration. */
112 unsigned char do_csum:1;
113 size_t csum_start;
114 size_t csum_len;
115 /* Outdata. */
116 unsigned char csum[CRYPTOCOP_CSUM_LENGTH];
117};
118
119
120
121#ifdef __KERNEL__
122
123/********** The API to use from inside the kernel. ************/
124
125#include <asm/arch/hwregs/dma.h>
126
127typedef enum {
128 cryptocop_alg_csum = 0,
129 cryptocop_alg_mem2mem,
130 cryptocop_alg_md5,
131 cryptocop_alg_sha1,
132 cryptocop_alg_des,
133 cryptocop_alg_3des,
134 cryptocop_alg_aes,
135 cryptocop_no_alg,
136} cryptocop_algorithm;
137
138typedef u8 cryptocop_tfrm_id;
139
140
141struct cryptocop_operation;
142
143typedef void (cryptocop_callback)(struct cryptocop_operation*, void*);
144
145struct cryptocop_transform_init {
146 cryptocop_algorithm alg;
147 /* Keydata for ciphers. */
148 unsigned char key[CRYPTOCOP_MAX_KEY_LENGTH];
149 unsigned int keylen;
150 cryptocop_cipher_mode cipher_mode;
151 cryptocop_3des_mode tdes_mode;
152 cryptocop_csum_type csum_mode; /* cryptocop_csum_none is not allowed when alg==cryptocop_alg_csum */
153
154 cryptocop_tfrm_id tid; /* Locally unique in session; assigned by user, checked by driver. */
155 struct cryptocop_transform_init *next;
156};
157
158
159typedef enum {
160 cryptocop_source_dma = 0,
161 cryptocop_source_des,
162 cryptocop_source_3des,
163 cryptocop_source_aes,
164 cryptocop_source_md5,
165 cryptocop_source_sha1,
166 cryptocop_source_csum,
167 cryptocop_source_none,
168} cryptocop_source;
169
170
171struct cryptocop_desc_cfg {
172 cryptocop_tfrm_id tid;
173 cryptocop_source src;
174 unsigned int last:1; /* Last use of this transform in the operation. Will push outdata when encountered. */
175 struct cryptocop_desc_cfg *next;
176};
177
178struct cryptocop_desc {
179 size_t length;
180 struct cryptocop_desc_cfg *cfg;
181 struct cryptocop_desc *next;
182};
183
184
185/* Flags for cryptocop_tfrm_cfg */
186#define CRYPTOCOP_NO_FLAG (0x00)
187#define CRYPTOCOP_ENCRYPT (0x01)
188#define CRYPTOCOP_DECRYPT (0x02)
189#define CRYPTOCOP_EXPLICIT_IV (0x04)
190
191struct cryptocop_tfrm_cfg {
192 cryptocop_tfrm_id tid;
193
194 unsigned int flags; /* DECRYPT, ENCRYPT, EXPLICIT_IV */
195
196 /* CBC initialisation vector for cihers. */
197 u8 iv[CRYPTOCOP_MAX_IV_LENGTH];
198
199 /* The position in output where to write the transform output. The order
200 in which the driver writes the output is unspecified, hence if several
201 transforms write on the same positions in the output the result is
202 unspecified. */
203 size_t inject_ix;
204
205 struct cryptocop_tfrm_cfg *next;
206};
207
208
209
210struct cryptocop_dma_list_operation{
211 /* The consumer can provide DMA lists to send to the co-processor. 'use_dmalists' in
212 struct cryptocop_operation must be set for the driver to use them. outlist,
213 out_data_buf, inlist and in_data_buf must all be physical addresses since they will
214 be loaded to DMA . */
215 dma_descr_data *outlist; /* Out from memory to the co-processor. */
216 char *out_data_buf;
217 dma_descr_data *inlist; /* In from the co-processor to memory. */
218 char *in_data_buf;
219
220 cryptocop_3des_mode tdes_mode;
221 cryptocop_csum_type csum_mode;
222};
223
224
225struct cryptocop_tfrm_operation{
226 /* Operation configuration, if not 'use_dmalists' is set. */
227 struct cryptocop_tfrm_cfg *tfrm_cfg;
228 struct cryptocop_desc *desc;
229
230 struct iovec *indata;
231 size_t incount;
232 size_t inlen; /* Total inlength. */
233
234 struct iovec *outdata;
235 size_t outcount;
236 size_t outlen; /* Total outlength. */
237};
238
239
240struct cryptocop_operation {
241 cryptocop_callback *cb;
242 void *cb_data;
243
244 cryptocop_session_id sid;
245
246 /* The status of the operation when returned to consumer. */
247 int operation_status; /* 0, -EAGAIN */
248
249 /* Flags */
250 unsigned int use_dmalists:1; /* Use outlist and inlist instead of the desc/tfrm_cfg configuration. */
251 unsigned int in_interrupt:1; /* Set if inserting job from interrupt context. */
252 unsigned int fast_callback:1; /* Set if fast callback wanted, i.e. from interrupt context. */
253
254 union{
255 struct cryptocop_dma_list_operation list_op;
256 struct cryptocop_tfrm_operation tfrm_op;
257 };
258};
259
260
261int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag);
262int cryptocop_free_session(cryptocop_session_id sid);
263
264int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation);
265
266int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation);
267
268int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation);
269
270#endif /* __KERNEL__ */
271
272#endif /* CRYPTOCOP_H */
diff --git a/include/asm-cris/arch-v32/delay.h b/include/asm-cris/arch-v32/delay.h
new file mode 100644
index 000000000000..f36f7f760e89
--- /dev/null
+++ b/include/asm-cris/arch-v32/delay.h
@@ -0,0 +1,18 @@
1#ifndef _ASM_CRIS_ARCH_DELAY_H
2#define _ASM_CRIS_ARCH_DELAY_H
3
4extern __inline__ void
5__delay(int loops)
6{
7 __asm__ __volatile__ (
8 "move.d %0, $r9\n\t"
9 "beq 2f\n\t"
10 "subq 1, $r9\n\t"
11 "1:\n\t"
12 "bne 1b\n\t"
13 "subq 1, $r9\n"
14 "2:"
15 : : "g" (loops) : "r9");
16}
17
18#endif /* _ASM_CRIS_ARCH_DELAY_H */
diff --git a/include/asm-cris/arch-v32/dma.h b/include/asm-cris/arch-v32/dma.h
new file mode 100644
index 000000000000..3674081389fd
--- /dev/null
+++ b/include/asm-cris/arch-v32/dma.h
@@ -0,0 +1,79 @@
1#ifndef _ASM_ARCH_CRIS_DMA_H
2#define _ASM_ARCH_CRIS_DMA_H
3
4/* Defines for using and allocating dma channels. */
5
6#define MAX_DMA_CHANNELS 10
7
8#define NETWORK_ETH0_TX_DMA_NBR 0 /* Ethernet 0 out. */
9#define NETWORK_ETH0 RX_DMA_NBR 1 /* Ethernet 0 in. */
10
11#define IO_PROC_DMA0_TX_DMA_NBR 2 /* IO processor DMA0 out. */
12#define IO_PROC_DMA0_RX_DMA_NBR 3 /* IO processor DMA0 in. */
13
14#define ATA_TX_DMA_NBR 2 /* ATA interface out. */
15#define ATA_RX_DMA_NBR 3 /* ATA interface in. */
16
17#define ASYNC_SER2_TX_DMA_NBR 2 /* Asynchronous serial port 2 out. */
18#define ASYNC_SER2_RX_DMA_NBR 3 /* Asynchronous serial port 2 in. */
19
20#define IO_PROC_DMA1_TX_DMA_NBR 4 /* IO processor DMA1 out. */
21#define IO_PROC_DMA1_RX_DMA_NBR 5 /* IO processor DMA1 in. */
22
23#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */
24#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */
25
26#define SYNC_SER0_TX_DMA_NBR 4 /* Synchronous serial port 0 out. */
27#define SYNC_SER0_RX_DMA_NBR 5 /* Synchronous serial port 0 in. */
28
29#define EXTDMA0_TX_DMA_NBR 6 /* External DMA 0 out. */
30#define EXTDMA1_RX_DMA_NBR 7 /* External DMA 1 in. */
31
32#define ASYNC_SER0_TX_DMA_NBR 6 /* Asynchronous serial port 0 out. */
33#define ASYNC_SER0_RX_DMA_NBR 7 /* Asynchronous serial port 0 in. */
34
35#define SYNC_SER1_TX_DMA_NBR 6 /* Synchronous serial port 1 out. */
36#define SYNC_SER1_RX_DMA_NBR 7 /* Synchronous serial port 1 in. */
37
38#define NETWORK_ETH1_TX_DMA_NBR 6 /* Ethernet 1 out. */
39#define NETWORK_ETH1_RX_DMA_NBR 7 /* Ethernet 1 in. */
40
41#define EXTDMA2_TX_DMA_NBR 8 /* External DMA 2 out. */
42#define EXTDMA3_RX_DMA_NBR 9 /* External DMA 3 in. */
43
44#define STRCOP_TX_DMA_NBR 8 /* Stream co-processor out. */
45#define STRCOP_RX_DMA_NBR 9 /* Stream co-processor in. */
46
47#define ASYNC_SER3_TX_DMA_NBR 8 /* Asynchronous serial port 3 out. */
48#define ASYNC_SER3_RX_DMA_NBR 9 /* Asynchronous serial port 3 in. */
49
50enum dma_owner
51{
52 dma_eth0,
53 dma_eth1,
54 dma_iop0,
55 dma_iop1,
56 dma_ser0,
57 dma_ser1,
58 dma_ser2,
59 dma_ser3,
60 dma_sser0,
61 dma_sser1,
62 dma_ata,
63 dma_strp,
64 dma_ext0,
65 dma_ext1,
66 dma_ext2,
67 dma_ext3
68};
69
70int crisv32_request_dma(unsigned int dmanr, const char * device_id,
71 unsigned options, unsigned bandwidth, enum dma_owner owner);
72void crisv32_free_dma(unsigned int dmanr);
73
74/* Masks used by crisv32_request_dma options: */
75#define DMA_VERBOSE_ON_ERROR 1
76#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
77#define DMA_INT_MEM 4
78
79#endif /* _ASM_ARCH_CRIS_DMA_H */
diff --git a/include/asm-cris/arch-v32/elf.h b/include/asm-cris/arch-v32/elf.h
new file mode 100644
index 000000000000..1324e505a4d8
--- /dev/null
+++ b/include/asm-cris/arch-v32/elf.h
@@ -0,0 +1,73 @@
1#ifndef _ASM_CRIS_ELF_H
2#define _ASM_CRIS_ELF_H
3
4#define ELF_CORE_EFLAGS EF_CRIS_VARIANT_V32
5
6/*
7 * This is used to ensure we don't load something for the wrong architecture.
8 */
9#define elf_check_arch(x) \
10 ((x)->e_machine == EM_CRIS \
11 && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_V32 \
12 || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32))))
13
14/* CRISv32 ELF register definitions. */
15
16#include <asm/ptrace.h>
17
18/* Explicitly zero out registers to increase determinism. */
19#define ELF_PLAT_INIT(_r, load_addr) do { \
20 (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \
21 (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \
22 (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \
23 (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \
24 (_r)->acr = 0; \
25} while (0)
26
27/*
28 * An executable for which elf_read_implies_exec() returns TRUE will
29 * have the READ_IMPLIES_EXEC personality flag set automatically.
30 */
31#define elf_read_implies_exec_binary(ex, have_pt_gnu_stack) (!(have_pt_gnu_stack))
32
33/*
34 * This is basically a pt_regs with the additional definition
35 * of the stack pointer since it's needed in a core dump.
36 * pr_regs is a elf_gregset_t and should be filled according
37 * to the layout of user_regs_struct.
38 */
39#define ELF_CORE_COPY_REGS(pr_reg, regs) \
40 pr_reg[0] = regs->r0; \
41 pr_reg[1] = regs->r1; \
42 pr_reg[2] = regs->r2; \
43 pr_reg[3] = regs->r3; \
44 pr_reg[4] = regs->r4; \
45 pr_reg[5] = regs->r5; \
46 pr_reg[6] = regs->r6; \
47 pr_reg[7] = regs->r7; \
48 pr_reg[8] = regs->r8; \
49 pr_reg[9] = regs->r9; \
50 pr_reg[10] = regs->r10; \
51 pr_reg[11] = regs->r11; \
52 pr_reg[12] = regs->r12; \
53 pr_reg[13] = regs->r13; \
54 pr_reg[14] = rdusp(); /* SP */ \
55 pr_reg[15] = regs->acr; /* ACR */ \
56 pr_reg[16] = 0; /* BZ */ \
57 pr_reg[17] = rdvr(); /* VR */ \
58 pr_reg[18] = 0; /* PID */ \
59 pr_reg[19] = regs->srs; /* SRS */ \
60 pr_reg[20] = 0; /* WZ */ \
61 pr_reg[21] = regs->exs; /* EXS */ \
62 pr_reg[22] = regs->eda; /* EDA */ \
63 pr_reg[23] = regs->mof; /* MOF */ \
64 pr_reg[24] = 0; /* DZ */ \
65 pr_reg[25] = 0; /* EBP */ \
66 pr_reg[26] = regs->erp; /* ERP */ \
67 pr_reg[27] = regs->srp; /* SRP */ \
68 pr_reg[28] = 0; /* NRP */ \
69 pr_reg[29] = regs->ccs; /* CCS */ \
70 pr_reg[30] = rdusp(); /* USP */ \
71 pr_reg[31] = regs->spc; /* SPC */ \
72
73#endif /* _ASM_CRIS_ELF_H */
diff --git a/include/asm-cris/arch-v32/hwregs/Makefile b/include/asm-cris/arch-v32/hwregs/Makefile
new file mode 100644
index 000000000000..c9160f9949a9
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/Makefile
@@ -0,0 +1,187 @@
1# $Id: Makefile,v 1.8 2004/01/07 21:16:18 johana Exp $
2# Makefile to generate or copy the latest register definitions
3# and related datastructures and helpermacros.
4# The offical place for these files is at:
5RELEASE ?= r1_alfa5
6OFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/
7
8# which is updated on each new release.
9INCL_ASMFILES =
10INCL_FILES = ata_defs.h
11INCL_FILES += bif_core_defs.h
12INCL_ASMFILES += bif_core_defs_asm.h
13INCL_FILES += bif_slave_defs.h
14#INCL_FILES += bif_slave_ext_defs.h
15INCL_FILES += config_defs.h
16INCL_ASMFILES += config_defs_asm.h
17INCL_FILES += cpu_vect.h
18#INCL_FILES += cris_defs.h
19#INCL_FILES += cris_supp_reg.h # In handcrafted supp_reg.h
20INCL_FILES += dma.h
21INCL_FILES += dma_defs.h
22INCL_FILES += eth_defs.h
23INCL_FILES += extmem_defs.h
24INCL_FILES += gio_defs.h
25INCL_ASMFILES += gio_defs_asm.h
26INCL_FILES += intr_vect.h
27INCL_FILES += intr_vect_defs.h
28INCL_ASMFILES += intr_vect_defs_asm.h
29INCL_FILES += marb_bp_defs.h
30INCL_FILES += marb_defs.h
31INCL_ASMFILES += mmu_defs_asm.h
32#INCL_FILES += mmu_supp_reg.h # In handcrafted supp_reg.h
33#INCL_FILES += par_defs.h # No useful content
34INCL_FILES += pinmux_defs.h
35INCL_FILES += reg_map.h
36INCL_ASMFILES += reg_map_asm.h
37INCL_FILES += reg_rdwr.h
38INCL_FILES += ser_defs.h
39#INCL_FILES += spec_reg.h # In handcrafted supp_reg.h
40INCL_FILES += sser_defs.h
41INCL_FILES += strcop_defs.h
42#INCL_FILES += strcop.h # Where is this?
43INCL_FILES += strmux_defs.h
44#INCL_FILES += supp_reg.h # Handcrafted instead
45INCL_FILES += timer_defs.h
46
47REGDESC =
48REGDESC += $(BASEDIR)/io/ata/rtl/ata_regs.r
49REGDESC += $(BASEDIR)/io/bif/rtl/bif_core_regs.r
50REGDESC += $(BASEDIR)/io/bif/rtl/bif_slave_regs.r
51#REGDESC += $(BASEDIR)/io/bif/sw/bif_slave_ext_regs.r
52REGDESC += $(DESIGNDIR)/top/rtl/config_regs.r
53REGDESC += $(BASEDIR)/mod/dma_common/rtl/dma_regdes.r
54REGDESC += $(BASEDIR)/io/eth/rtl/eth_regs.r
55REGDESC += $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r
56REGDESC += $(DESIGNDIR)/gio/rtl/gio_regs.r
57REGDESC += $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
58REGDESC += $(BASEDIR)/core/memarb/rtl/guinness/marb_top.r
59REGDESC += $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r
60#REGDESC += $(BASEDIR)/io/par_port/rtl/par_regs.r
61REGDESC += $(BASEDIR)/io/pinmux/rtl/guinness/pinmux_regs.r
62REGDESC += $(BASEDIR)/io/ser/rtl/ser_regs.r
63REGDESC += $(BASEDIR)/core/strcop/rtl/strcop_regs.r
64REGDESC += $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r
65REGDESC += $(BASEDIR)/io/timer/rtl/timer_regs.r
66#REGDESC += $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r
67
68
69BASEDIR = /n/asic/design
70DESIGNDIR = /n/asic/projects/guinness/design
71RDES2C = /n/asic/bin/rdes2c
72RDES2C = /n/asic/design/tools/rdesc/rdes2c
73RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr
74RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt
75
76## all - Just print help - you probably want to do 'make gen'
77all: help
78
79# Disable implicit rule that may generate deleted files from RCS/ directory.
80%.r:
81
82%.h:
83
84## help - This help
85help:
86 @grep '^## ' Makefile
87
88## gen - Generate include files
89gen: $(INCL_FILES) $(INCL_ASMFILES)
90
91ata_defs.h: $(BASEDIR)/io/ata/rtl/ata_regs.r
92 $(RDES2C) $<
93config_defs.h: $(DESIGNDIR)/top/rtl/config_regs.r
94 $(RDES2C) $<
95config_defs_asm.h: $(DESIGNDIR)/top/rtl/config_regs.r
96 $(RDES2C) -asm $<
97# Can't generate cpu_vect.h yet
98#cpu_vect.h: $(DESIGNDIR)/top/rtl/cpu_vect.r # ????
99# $(RDES2INTR) $<
100cpu_vect.h: $(OFFICIAL_INCDIR)cpu_vect.h
101 cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
102dma_defs.h: $(BASEDIR)/core/dma/rtl/common/dma_regdes.r
103 $(RDES2C) $<
104$(BASEDIR)/core/dma/sw/dma.h:
105dma.h: $(BASEDIR)/core/dma/sw/dma.h
106 cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
107eth_defs.h: $(BASEDIR)/io/eth/rtl/eth_regs.r
108 $(RDES2C) $<
109extmem_defs.h: $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r
110 $(RDES2C) $<
111gio_defs.h: $(DESIGNDIR)/gio/rtl/gio_regs.r
112 $(RDES2C) $<
113intr_vect_defs.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
114 $(RDES2C) $<
115intr_vect_defs_asm.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
116 $(RDES2C) -asm $<
117# Can't generate intr_vect.h yet
118#intr_vect.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
119# $(RDES2INTR) $<
120intr_vect.h: $(OFFICIAL_INCDIR)intr_vect.h
121 cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
122mmu_defs_asm.h: $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r
123 $(RDES2C) -asm $<
124par_defs.h: $(BASEDIR)/io/par_port/rtl/par_regs.r
125 $(RDES2C) $<
126
127# From /n/asic/projects/guinness/design/
128reg_map.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap
129 $(RDES2C) -base 0xb0000000 $^
130reg_map_asm.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap
131 $(RDES2C) -base 0xb0000000 -asm -outfile $@ $^
132
133reg_rdwr.h: $(DESIGNDIR)/top/sw/include/reg_rdwr.h
134 cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
135
136ser_defs.h: $(BASEDIR)/io/ser/rtl/ser_regs.r
137 $(RDES2C) $<
138strcop_defs.h: $(BASEDIR)/core/strcop/rtl/strcop_regs.r
139 $(RDES2C) $<
140strcop.h: $(BASEDIR)/core/strcop/rtl/strcop.h
141 cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
142strmux_defs.h: $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r
143 $(RDES2C) $<
144timer_defs.h: $(BASEDIR)/io/timer/rtl/timer_regs.r
145 $(RDES2C) $<
146usb_defs.h: $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r
147 $(RDES2C) $<
148
149## copy - Copy files from official location
150copy:
151 @for HFILE in $(INCL_FILES); do \
152 echo " $$HFILE"; \
153 cat $(OFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
154 done
155 @for HFILE in $(INCL_ASMFILES); do \
156 echo " $$HFILE"; \
157 cat $(OFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
158 done
159## ls_official - List official location
160ls_official:
161 (cd $(OFFICIAL_INCDIR); ls -l *.h )
162
163## diff_official - Diff current directory with official location
164diff_official:
165 diff . $(OFFICIAL_INCDIR)
166
167## doc - Generate .axw files from register description.
168doc: $(REGDESC)
169 for RDES in $^; do \
170 $(RDES2TXT) $$RDES; \
171 done
172
173.PHONY: axw
174## %.axw - Generate the specified .axw file (doesn't work for all files
175## due to inconsistent naming ir .r files.
176%.axw: axw
177 @for RDES in $(REGDESC); do \
178 if echo "$$RDES" | grep $* ; then \
179 $(RDES2TXT) $$RDES; \
180 fi \
181 done
182
183.PHONY: clean
184## clean - Remove .h files and .axw files.
185clean:
186 rm -rf $(INCL_FILES) *.axw
187
diff --git a/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h
new file mode 100644
index 000000000000..866191418f9c
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h
@@ -0,0 +1,222 @@
1#ifndef __ata_defs_asm_h
2#define __ata_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/ata/rtl/ata_regs.r
7 * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
8 * last modfied: Mon Apr 11 16:06:25 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r
11 * id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_ctrl0, scope ata, type rw */
57#define reg_ata_rw_ctrl0___pio_hold___lsb 0
58#define reg_ata_rw_ctrl0___pio_hold___width 6
59#define reg_ata_rw_ctrl0___pio_strb___lsb 6
60#define reg_ata_rw_ctrl0___pio_strb___width 6
61#define reg_ata_rw_ctrl0___pio_setup___lsb 12
62#define reg_ata_rw_ctrl0___pio_setup___width 6
63#define reg_ata_rw_ctrl0___dma_hold___lsb 18
64#define reg_ata_rw_ctrl0___dma_hold___width 6
65#define reg_ata_rw_ctrl0___dma_strb___lsb 24
66#define reg_ata_rw_ctrl0___dma_strb___width 6
67#define reg_ata_rw_ctrl0___rst___lsb 30
68#define reg_ata_rw_ctrl0___rst___width 1
69#define reg_ata_rw_ctrl0___rst___bit 30
70#define reg_ata_rw_ctrl0___en___lsb 31
71#define reg_ata_rw_ctrl0___en___width 1
72#define reg_ata_rw_ctrl0___en___bit 31
73#define reg_ata_rw_ctrl0_offset 12
74
75/* Register rw_ctrl1, scope ata, type rw */
76#define reg_ata_rw_ctrl1___udma_tcyc___lsb 0
77#define reg_ata_rw_ctrl1___udma_tcyc___width 4
78#define reg_ata_rw_ctrl1___udma_tdvs___lsb 4
79#define reg_ata_rw_ctrl1___udma_tdvs___width 4
80#define reg_ata_rw_ctrl1_offset 16
81
82/* Register rw_ctrl2, scope ata, type rw */
83#define reg_ata_rw_ctrl2___data___lsb 0
84#define reg_ata_rw_ctrl2___data___width 16
85#define reg_ata_rw_ctrl2___dma_size___lsb 19
86#define reg_ata_rw_ctrl2___dma_size___width 1
87#define reg_ata_rw_ctrl2___dma_size___bit 19
88#define reg_ata_rw_ctrl2___multi___lsb 20
89#define reg_ata_rw_ctrl2___multi___width 1
90#define reg_ata_rw_ctrl2___multi___bit 20
91#define reg_ata_rw_ctrl2___hsh___lsb 21
92#define reg_ata_rw_ctrl2___hsh___width 2
93#define reg_ata_rw_ctrl2___trf_mode___lsb 23
94#define reg_ata_rw_ctrl2___trf_mode___width 1
95#define reg_ata_rw_ctrl2___trf_mode___bit 23
96#define reg_ata_rw_ctrl2___rw___lsb 24
97#define reg_ata_rw_ctrl2___rw___width 1
98#define reg_ata_rw_ctrl2___rw___bit 24
99#define reg_ata_rw_ctrl2___addr___lsb 25
100#define reg_ata_rw_ctrl2___addr___width 3
101#define reg_ata_rw_ctrl2___cs0___lsb 28
102#define reg_ata_rw_ctrl2___cs0___width 1
103#define reg_ata_rw_ctrl2___cs0___bit 28
104#define reg_ata_rw_ctrl2___cs1___lsb 29
105#define reg_ata_rw_ctrl2___cs1___width 1
106#define reg_ata_rw_ctrl2___cs1___bit 29
107#define reg_ata_rw_ctrl2___sel___lsb 30
108#define reg_ata_rw_ctrl2___sel___width 2
109#define reg_ata_rw_ctrl2_offset 0
110
111/* Register rs_stat_data, scope ata, type rs */
112#define reg_ata_rs_stat_data___data___lsb 0
113#define reg_ata_rs_stat_data___data___width 16
114#define reg_ata_rs_stat_data___dav___lsb 16
115#define reg_ata_rs_stat_data___dav___width 1
116#define reg_ata_rs_stat_data___dav___bit 16
117#define reg_ata_rs_stat_data___busy___lsb 17
118#define reg_ata_rs_stat_data___busy___width 1
119#define reg_ata_rs_stat_data___busy___bit 17
120#define reg_ata_rs_stat_data_offset 4
121
122/* Register r_stat_data, scope ata, type r */
123#define reg_ata_r_stat_data___data___lsb 0
124#define reg_ata_r_stat_data___data___width 16
125#define reg_ata_r_stat_data___dav___lsb 16
126#define reg_ata_r_stat_data___dav___width 1
127#define reg_ata_r_stat_data___dav___bit 16
128#define reg_ata_r_stat_data___busy___lsb 17
129#define reg_ata_r_stat_data___busy___width 1
130#define reg_ata_r_stat_data___busy___bit 17
131#define reg_ata_r_stat_data_offset 8
132
133/* Register rw_trf_cnt, scope ata, type rw */
134#define reg_ata_rw_trf_cnt___cnt___lsb 0
135#define reg_ata_rw_trf_cnt___cnt___width 17
136#define reg_ata_rw_trf_cnt_offset 20
137
138/* Register r_stat_misc, scope ata, type r */
139#define reg_ata_r_stat_misc___crc___lsb 0
140#define reg_ata_r_stat_misc___crc___width 16
141#define reg_ata_r_stat_misc_offset 24
142
143/* Register rw_intr_mask, scope ata, type rw */
144#define reg_ata_rw_intr_mask___bus0___lsb 0
145#define reg_ata_rw_intr_mask___bus0___width 1
146#define reg_ata_rw_intr_mask___bus0___bit 0
147#define reg_ata_rw_intr_mask___bus1___lsb 1
148#define reg_ata_rw_intr_mask___bus1___width 1
149#define reg_ata_rw_intr_mask___bus1___bit 1
150#define reg_ata_rw_intr_mask___bus2___lsb 2
151#define reg_ata_rw_intr_mask___bus2___width 1
152#define reg_ata_rw_intr_mask___bus2___bit 2
153#define reg_ata_rw_intr_mask___bus3___lsb 3
154#define reg_ata_rw_intr_mask___bus3___width 1
155#define reg_ata_rw_intr_mask___bus3___bit 3
156#define reg_ata_rw_intr_mask_offset 28
157
158/* Register rw_ack_intr, scope ata, type rw */
159#define reg_ata_rw_ack_intr___bus0___lsb 0
160#define reg_ata_rw_ack_intr___bus0___width 1
161#define reg_ata_rw_ack_intr___bus0___bit 0
162#define reg_ata_rw_ack_intr___bus1___lsb 1
163#define reg_ata_rw_ack_intr___bus1___width 1
164#define reg_ata_rw_ack_intr___bus1___bit 1
165#define reg_ata_rw_ack_intr___bus2___lsb 2
166#define reg_ata_rw_ack_intr___bus2___width 1
167#define reg_ata_rw_ack_intr___bus2___bit 2
168#define reg_ata_rw_ack_intr___bus3___lsb 3
169#define reg_ata_rw_ack_intr___bus3___width 1
170#define reg_ata_rw_ack_intr___bus3___bit 3
171#define reg_ata_rw_ack_intr_offset 32
172
173/* Register r_intr, scope ata, type r */
174#define reg_ata_r_intr___bus0___lsb 0
175#define reg_ata_r_intr___bus0___width 1
176#define reg_ata_r_intr___bus0___bit 0
177#define reg_ata_r_intr___bus1___lsb 1
178#define reg_ata_r_intr___bus1___width 1
179#define reg_ata_r_intr___bus1___bit 1
180#define reg_ata_r_intr___bus2___lsb 2
181#define reg_ata_r_intr___bus2___width 1
182#define reg_ata_r_intr___bus2___bit 2
183#define reg_ata_r_intr___bus3___lsb 3
184#define reg_ata_r_intr___bus3___width 1
185#define reg_ata_r_intr___bus3___bit 3
186#define reg_ata_r_intr_offset 36
187
188/* Register r_masked_intr, scope ata, type r */
189#define reg_ata_r_masked_intr___bus0___lsb 0
190#define reg_ata_r_masked_intr___bus0___width 1
191#define reg_ata_r_masked_intr___bus0___bit 0
192#define reg_ata_r_masked_intr___bus1___lsb 1
193#define reg_ata_r_masked_intr___bus1___width 1
194#define reg_ata_r_masked_intr___bus1___bit 1
195#define reg_ata_r_masked_intr___bus2___lsb 2
196#define reg_ata_r_masked_intr___bus2___width 1
197#define reg_ata_r_masked_intr___bus2___bit 2
198#define reg_ata_r_masked_intr___bus3___lsb 3
199#define reg_ata_r_masked_intr___bus3___width 1
200#define reg_ata_r_masked_intr___bus3___bit 3
201#define reg_ata_r_masked_intr_offset 40
202
203
204/* Constants */
205#define regk_ata_active 0x00000001
206#define regk_ata_byte 0x00000001
207#define regk_ata_data 0x00000001
208#define regk_ata_dma 0x00000001
209#define regk_ata_inactive 0x00000000
210#define regk_ata_no 0x00000000
211#define regk_ata_nodata 0x00000000
212#define regk_ata_pio 0x00000000
213#define regk_ata_rd 0x00000001
214#define regk_ata_reg 0x00000000
215#define regk_ata_rw_ctrl0_default 0x00000000
216#define regk_ata_rw_ctrl2_default 0x00000000
217#define regk_ata_rw_intr_mask_default 0x00000000
218#define regk_ata_udma 0x00000002
219#define regk_ata_word 0x00000000
220#define regk_ata_wr 0x00000000
221#define regk_ata_yes 0x00000001
222#endif /* __ata_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h
new file mode 100644
index 000000000000..c686cb335621
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h
@@ -0,0 +1,319 @@
1#ifndef __bif_core_defs_asm_h
2#define __bif_core_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/bif/rtl/bif_core_regs.r
7 * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
8 * last modfied: Mon Apr 11 16:06:33 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r
11 * id: $Id: bif_core_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_grp1_cfg, scope bif_core, type rw */
57#define reg_bif_core_rw_grp1_cfg___lw___lsb 0
58#define reg_bif_core_rw_grp1_cfg___lw___width 6
59#define reg_bif_core_rw_grp1_cfg___ew___lsb 6
60#define reg_bif_core_rw_grp1_cfg___ew___width 3
61#define reg_bif_core_rw_grp1_cfg___zw___lsb 9
62#define reg_bif_core_rw_grp1_cfg___zw___width 3
63#define reg_bif_core_rw_grp1_cfg___aw___lsb 12
64#define reg_bif_core_rw_grp1_cfg___aw___width 2
65#define reg_bif_core_rw_grp1_cfg___dw___lsb 14
66#define reg_bif_core_rw_grp1_cfg___dw___width 2
67#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16
68#define reg_bif_core_rw_grp1_cfg___ewb___width 2
69#define reg_bif_core_rw_grp1_cfg___bw___lsb 18
70#define reg_bif_core_rw_grp1_cfg___bw___width 1
71#define reg_bif_core_rw_grp1_cfg___bw___bit 18
72#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19
73#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1
74#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19
75#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20
76#define reg_bif_core_rw_grp1_cfg___erc_en___width 1
77#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20
78#define reg_bif_core_rw_grp1_cfg___mode___lsb 21
79#define reg_bif_core_rw_grp1_cfg___mode___width 1
80#define reg_bif_core_rw_grp1_cfg___mode___bit 21
81#define reg_bif_core_rw_grp1_cfg_offset 0
82
83/* Register rw_grp2_cfg, scope bif_core, type rw */
84#define reg_bif_core_rw_grp2_cfg___lw___lsb 0
85#define reg_bif_core_rw_grp2_cfg___lw___width 6
86#define reg_bif_core_rw_grp2_cfg___ew___lsb 6
87#define reg_bif_core_rw_grp2_cfg___ew___width 3
88#define reg_bif_core_rw_grp2_cfg___zw___lsb 9
89#define reg_bif_core_rw_grp2_cfg___zw___width 3
90#define reg_bif_core_rw_grp2_cfg___aw___lsb 12
91#define reg_bif_core_rw_grp2_cfg___aw___width 2
92#define reg_bif_core_rw_grp2_cfg___dw___lsb 14
93#define reg_bif_core_rw_grp2_cfg___dw___width 2
94#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16
95#define reg_bif_core_rw_grp2_cfg___ewb___width 2
96#define reg_bif_core_rw_grp2_cfg___bw___lsb 18
97#define reg_bif_core_rw_grp2_cfg___bw___width 1
98#define reg_bif_core_rw_grp2_cfg___bw___bit 18
99#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19
100#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1
101#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19
102#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20
103#define reg_bif_core_rw_grp2_cfg___erc_en___width 1
104#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20
105#define reg_bif_core_rw_grp2_cfg___mode___lsb 21
106#define reg_bif_core_rw_grp2_cfg___mode___width 1
107#define reg_bif_core_rw_grp2_cfg___mode___bit 21
108#define reg_bif_core_rw_grp2_cfg_offset 4
109
110/* Register rw_grp3_cfg, scope bif_core, type rw */
111#define reg_bif_core_rw_grp3_cfg___lw___lsb 0
112#define reg_bif_core_rw_grp3_cfg___lw___width 6
113#define reg_bif_core_rw_grp3_cfg___ew___lsb 6
114#define reg_bif_core_rw_grp3_cfg___ew___width 3
115#define reg_bif_core_rw_grp3_cfg___zw___lsb 9
116#define reg_bif_core_rw_grp3_cfg___zw___width 3
117#define reg_bif_core_rw_grp3_cfg___aw___lsb 12
118#define reg_bif_core_rw_grp3_cfg___aw___width 2
119#define reg_bif_core_rw_grp3_cfg___dw___lsb 14
120#define reg_bif_core_rw_grp3_cfg___dw___width 2
121#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16
122#define reg_bif_core_rw_grp3_cfg___ewb___width 2
123#define reg_bif_core_rw_grp3_cfg___bw___lsb 18
124#define reg_bif_core_rw_grp3_cfg___bw___width 1
125#define reg_bif_core_rw_grp3_cfg___bw___bit 18
126#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19
127#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1
128#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19
129#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20
130#define reg_bif_core_rw_grp3_cfg___erc_en___width 1
131#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20
132#define reg_bif_core_rw_grp3_cfg___mode___lsb 21
133#define reg_bif_core_rw_grp3_cfg___mode___width 1
134#define reg_bif_core_rw_grp3_cfg___mode___bit 21
135#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24
136#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2
137#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26
138#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2
139#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28
140#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2
141#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30
142#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2
143#define reg_bif_core_rw_grp3_cfg_offset 8
144
145/* Register rw_grp4_cfg, scope bif_core, type rw */
146#define reg_bif_core_rw_grp4_cfg___lw___lsb 0
147#define reg_bif_core_rw_grp4_cfg___lw___width 6
148#define reg_bif_core_rw_grp4_cfg___ew___lsb 6
149#define reg_bif_core_rw_grp4_cfg___ew___width 3
150#define reg_bif_core_rw_grp4_cfg___zw___lsb 9
151#define reg_bif_core_rw_grp4_cfg___zw___width 3
152#define reg_bif_core_rw_grp4_cfg___aw___lsb 12
153#define reg_bif_core_rw_grp4_cfg___aw___width 2
154#define reg_bif_core_rw_grp4_cfg___dw___lsb 14
155#define reg_bif_core_rw_grp4_cfg___dw___width 2
156#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16
157#define reg_bif_core_rw_grp4_cfg___ewb___width 2
158#define reg_bif_core_rw_grp4_cfg___bw___lsb 18
159#define reg_bif_core_rw_grp4_cfg___bw___width 1
160#define reg_bif_core_rw_grp4_cfg___bw___bit 18
161#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19
162#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1
163#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19
164#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20
165#define reg_bif_core_rw_grp4_cfg___erc_en___width 1
166#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20
167#define reg_bif_core_rw_grp4_cfg___mode___lsb 21
168#define reg_bif_core_rw_grp4_cfg___mode___width 1
169#define reg_bif_core_rw_grp4_cfg___mode___bit 21
170#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26
171#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2
172#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28
173#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2
174#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30
175#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2
176#define reg_bif_core_rw_grp4_cfg_offset 12
177
178/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
179#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0
180#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5
181#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5
182#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3
183#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8
184#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1
185#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8
186#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9
187#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1
188#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9
189#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10
190#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3
191#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13
192#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1
193#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13
194#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14
195#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1
196#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14
197#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15
198#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5
199#define reg_bif_core_rw_sdram_cfg_grp0_offset 16
200
201/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
202#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0
203#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5
204#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5
205#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3
206#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8
207#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1
208#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8
209#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9
210#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1
211#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9
212#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10
213#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3
214#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13
215#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1
216#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13
217#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14
218#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1
219#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14
220#define reg_bif_core_rw_sdram_cfg_grp1_offset 20
221
222/* Register rw_sdram_timing, scope bif_core, type rw */
223#define reg_bif_core_rw_sdram_timing___cl___lsb 0
224#define reg_bif_core_rw_sdram_timing___cl___width 3
225#define reg_bif_core_rw_sdram_timing___rcd___lsb 3
226#define reg_bif_core_rw_sdram_timing___rcd___width 3
227#define reg_bif_core_rw_sdram_timing___rp___lsb 6
228#define reg_bif_core_rw_sdram_timing___rp___width 3
229#define reg_bif_core_rw_sdram_timing___rc___lsb 9
230#define reg_bif_core_rw_sdram_timing___rc___width 2
231#define reg_bif_core_rw_sdram_timing___dpl___lsb 11
232#define reg_bif_core_rw_sdram_timing___dpl___width 2
233#define reg_bif_core_rw_sdram_timing___pde___lsb 13
234#define reg_bif_core_rw_sdram_timing___pde___width 1
235#define reg_bif_core_rw_sdram_timing___pde___bit 13
236#define reg_bif_core_rw_sdram_timing___ref___lsb 14
237#define reg_bif_core_rw_sdram_timing___ref___width 2
238#define reg_bif_core_rw_sdram_timing___cpd___lsb 16
239#define reg_bif_core_rw_sdram_timing___cpd___width 1
240#define reg_bif_core_rw_sdram_timing___cpd___bit 16
241#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17
242#define reg_bif_core_rw_sdram_timing___sdcke___width 1
243#define reg_bif_core_rw_sdram_timing___sdcke___bit 17
244#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18
245#define reg_bif_core_rw_sdram_timing___sdclk___width 1
246#define reg_bif_core_rw_sdram_timing___sdclk___bit 18
247#define reg_bif_core_rw_sdram_timing_offset 24
248
249/* Register rw_sdram_cmd, scope bif_core, type rw */
250#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0
251#define reg_bif_core_rw_sdram_cmd___cmd___width 3
252#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3
253#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15
254#define reg_bif_core_rw_sdram_cmd_offset 28
255
256/* Register rs_sdram_ref_stat, scope bif_core, type rs */
257#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0
258#define reg_bif_core_rs_sdram_ref_stat___ok___width 1
259#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0
260#define reg_bif_core_rs_sdram_ref_stat_offset 32
261
262/* Register r_sdram_ref_stat, scope bif_core, type r */
263#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0
264#define reg_bif_core_r_sdram_ref_stat___ok___width 1
265#define reg_bif_core_r_sdram_ref_stat___ok___bit 0
266#define reg_bif_core_r_sdram_ref_stat_offset 36
267
268
269/* Constants */
270#define regk_bif_core_bank2 0x00000000
271#define regk_bif_core_bank4 0x00000001
272#define regk_bif_core_bit10 0x0000000a
273#define regk_bif_core_bit11 0x0000000b
274#define regk_bif_core_bit12 0x0000000c
275#define regk_bif_core_bit13 0x0000000d
276#define regk_bif_core_bit14 0x0000000e
277#define regk_bif_core_bit15 0x0000000f
278#define regk_bif_core_bit16 0x00000010
279#define regk_bif_core_bit17 0x00000011
280#define regk_bif_core_bit18 0x00000012
281#define regk_bif_core_bit19 0x00000013
282#define regk_bif_core_bit20 0x00000014
283#define regk_bif_core_bit21 0x00000015
284#define regk_bif_core_bit22 0x00000016
285#define regk_bif_core_bit23 0x00000017
286#define regk_bif_core_bit24 0x00000018
287#define regk_bif_core_bit25 0x00000019
288#define regk_bif_core_bit26 0x0000001a
289#define regk_bif_core_bit27 0x0000001b
290#define regk_bif_core_bit28 0x0000001c
291#define regk_bif_core_bit29 0x0000001d
292#define regk_bif_core_bit9 0x00000009
293#define regk_bif_core_bw16 0x00000001
294#define regk_bif_core_bw32 0x00000000
295#define regk_bif_core_bwe 0x00000000
296#define regk_bif_core_cwe 0x00000001
297#define regk_bif_core_e15us 0x00000001
298#define regk_bif_core_e7800ns 0x00000002
299#define regk_bif_core_grp0 0x00000000
300#define regk_bif_core_grp1 0x00000001
301#define regk_bif_core_mrs 0x00000003
302#define regk_bif_core_no 0x00000000
303#define regk_bif_core_none 0x00000000
304#define regk_bif_core_nop 0x00000000
305#define regk_bif_core_off 0x00000000
306#define regk_bif_core_pre 0x00000002
307#define regk_bif_core_r_sdram_ref_stat_default 0x00000001
308#define regk_bif_core_rd 0x00000002
309#define regk_bif_core_ref 0x00000001
310#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001
311#define regk_bif_core_rw_grp1_cfg_default 0x000006cf
312#define regk_bif_core_rw_grp2_cfg_default 0x000006cf
313#define regk_bif_core_rw_grp3_cfg_default 0x000006cf
314#define regk_bif_core_rw_grp4_cfg_default 0x000006cf
315#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000
316#define regk_bif_core_slf 0x00000004
317#define regk_bif_core_wr 0x00000001
318#define regk_bif_core_yes 0x00000001
319#endif /* __bif_core_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h
new file mode 100644
index 000000000000..71532aa18168
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h
@@ -0,0 +1,495 @@
1#ifndef __bif_dma_defs_asm_h
2#define __bif_dma_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/bif/rtl/bif_dma_regs.r
7 * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
8 * last modfied: Mon Apr 11 16:06:33 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r
11 * id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_ch0_ctrl, scope bif_dma, type rw */
57#define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0
58#define reg_bif_dma_rw_ch0_ctrl___bw___width 2
59#define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2
60#define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1
61#define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2
62#define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3
63#define reg_bif_dma_rw_ch0_ctrl___cont___width 1
64#define reg_bif_dma_rw_ch0_ctrl___cont___bit 3
65#define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4
66#define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1
67#define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4
68#define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5
69#define reg_bif_dma_rw_ch0_ctrl___cnt___width 1
70#define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5
71#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6
72#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3
73#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9
74#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2
75#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11
76#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3
77#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14
78#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2
79#define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16
80#define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2
81#define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18
82#define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1
83#define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18
84#define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19
85#define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1
86#define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19
87#define reg_bif_dma_rw_ch0_ctrl_offset 0
88
89/* Register rw_ch0_addr, scope bif_dma, type rw */
90#define reg_bif_dma_rw_ch0_addr___addr___lsb 0
91#define reg_bif_dma_rw_ch0_addr___addr___width 32
92#define reg_bif_dma_rw_ch0_addr_offset 4
93
94/* Register rw_ch0_start, scope bif_dma, type rw */
95#define reg_bif_dma_rw_ch0_start___run___lsb 0
96#define reg_bif_dma_rw_ch0_start___run___width 1
97#define reg_bif_dma_rw_ch0_start___run___bit 0
98#define reg_bif_dma_rw_ch0_start_offset 8
99
100/* Register rw_ch0_cnt, scope bif_dma, type rw */
101#define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0
102#define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16
103#define reg_bif_dma_rw_ch0_cnt_offset 12
104
105/* Register r_ch0_stat, scope bif_dma, type r */
106#define reg_bif_dma_r_ch0_stat___cnt___lsb 0
107#define reg_bif_dma_r_ch0_stat___cnt___width 16
108#define reg_bif_dma_r_ch0_stat___run___lsb 31
109#define reg_bif_dma_r_ch0_stat___run___width 1
110#define reg_bif_dma_r_ch0_stat___run___bit 31
111#define reg_bif_dma_r_ch0_stat_offset 16
112
113/* Register rw_ch1_ctrl, scope bif_dma, type rw */
114#define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0
115#define reg_bif_dma_rw_ch1_ctrl___bw___width 2
116#define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2
117#define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1
118#define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2
119#define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3
120#define reg_bif_dma_rw_ch1_ctrl___cont___width 1
121#define reg_bif_dma_rw_ch1_ctrl___cont___bit 3
122#define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4
123#define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1
124#define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4
125#define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5
126#define reg_bif_dma_rw_ch1_ctrl___cnt___width 1
127#define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5
128#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6
129#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3
130#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9
131#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2
132#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11
133#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3
134#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14
135#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2
136#define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16
137#define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2
138#define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18
139#define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1
140#define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18
141#define reg_bif_dma_rw_ch1_ctrl_offset 32
142
143/* Register rw_ch1_addr, scope bif_dma, type rw */
144#define reg_bif_dma_rw_ch1_addr___addr___lsb 0
145#define reg_bif_dma_rw_ch1_addr___addr___width 32
146#define reg_bif_dma_rw_ch1_addr_offset 36
147
148/* Register rw_ch1_start, scope bif_dma, type rw */
149#define reg_bif_dma_rw_ch1_start___run___lsb 0
150#define reg_bif_dma_rw_ch1_start___run___width 1
151#define reg_bif_dma_rw_ch1_start___run___bit 0
152#define reg_bif_dma_rw_ch1_start_offset 40
153
154/* Register rw_ch1_cnt, scope bif_dma, type rw */
155#define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0
156#define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16
157#define reg_bif_dma_rw_ch1_cnt_offset 44
158
159/* Register r_ch1_stat, scope bif_dma, type r */
160#define reg_bif_dma_r_ch1_stat___cnt___lsb 0
161#define reg_bif_dma_r_ch1_stat___cnt___width 16
162#define reg_bif_dma_r_ch1_stat___run___lsb 31
163#define reg_bif_dma_r_ch1_stat___run___width 1
164#define reg_bif_dma_r_ch1_stat___run___bit 31
165#define reg_bif_dma_r_ch1_stat_offset 48
166
167/* Register rw_ch2_ctrl, scope bif_dma, type rw */
168#define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0
169#define reg_bif_dma_rw_ch2_ctrl___bw___width 2
170#define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2
171#define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1
172#define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2
173#define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3
174#define reg_bif_dma_rw_ch2_ctrl___cont___width 1
175#define reg_bif_dma_rw_ch2_ctrl___cont___bit 3
176#define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4
177#define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1
178#define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4
179#define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5
180#define reg_bif_dma_rw_ch2_ctrl___cnt___width 1
181#define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5
182#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6
183#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3
184#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9
185#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2
186#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11
187#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3
188#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14
189#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2
190#define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16
191#define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2
192#define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18
193#define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1
194#define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18
195#define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19
196#define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1
197#define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19
198#define reg_bif_dma_rw_ch2_ctrl_offset 64
199
200/* Register rw_ch2_addr, scope bif_dma, type rw */
201#define reg_bif_dma_rw_ch2_addr___addr___lsb 0
202#define reg_bif_dma_rw_ch2_addr___addr___width 32
203#define reg_bif_dma_rw_ch2_addr_offset 68
204
205/* Register rw_ch2_start, scope bif_dma, type rw */
206#define reg_bif_dma_rw_ch2_start___run___lsb 0
207#define reg_bif_dma_rw_ch2_start___run___width 1
208#define reg_bif_dma_rw_ch2_start___run___bit 0
209#define reg_bif_dma_rw_ch2_start_offset 72
210
211/* Register rw_ch2_cnt, scope bif_dma, type rw */
212#define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0
213#define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16
214#define reg_bif_dma_rw_ch2_cnt_offset 76
215
216/* Register r_ch2_stat, scope bif_dma, type r */
217#define reg_bif_dma_r_ch2_stat___cnt___lsb 0
218#define reg_bif_dma_r_ch2_stat___cnt___width 16
219#define reg_bif_dma_r_ch2_stat___run___lsb 31
220#define reg_bif_dma_r_ch2_stat___run___width 1
221#define reg_bif_dma_r_ch2_stat___run___bit 31
222#define reg_bif_dma_r_ch2_stat_offset 80
223
224/* Register rw_ch3_ctrl, scope bif_dma, type rw */
225#define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0
226#define reg_bif_dma_rw_ch3_ctrl___bw___width 2
227#define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2
228#define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1
229#define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2
230#define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3
231#define reg_bif_dma_rw_ch3_ctrl___cont___width 1
232#define reg_bif_dma_rw_ch3_ctrl___cont___bit 3
233#define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4
234#define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1
235#define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4
236#define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5
237#define reg_bif_dma_rw_ch3_ctrl___cnt___width 1
238#define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5
239#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6
240#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3
241#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9
242#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2
243#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11
244#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3
245#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14
246#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2
247#define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16
248#define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2
249#define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18
250#define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1
251#define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18
252#define reg_bif_dma_rw_ch3_ctrl_offset 96
253
254/* Register rw_ch3_addr, scope bif_dma, type rw */
255#define reg_bif_dma_rw_ch3_addr___addr___lsb 0
256#define reg_bif_dma_rw_ch3_addr___addr___width 32
257#define reg_bif_dma_rw_ch3_addr_offset 100
258
259/* Register rw_ch3_start, scope bif_dma, type rw */
260#define reg_bif_dma_rw_ch3_start___run___lsb 0
261#define reg_bif_dma_rw_ch3_start___run___width 1
262#define reg_bif_dma_rw_ch3_start___run___bit 0
263#define reg_bif_dma_rw_ch3_start_offset 104
264
265/* Register rw_ch3_cnt, scope bif_dma, type rw */
266#define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0
267#define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16
268#define reg_bif_dma_rw_ch3_cnt_offset 108
269
270/* Register r_ch3_stat, scope bif_dma, type r */
271#define reg_bif_dma_r_ch3_stat___cnt___lsb 0
272#define reg_bif_dma_r_ch3_stat___cnt___width 16
273#define reg_bif_dma_r_ch3_stat___run___lsb 31
274#define reg_bif_dma_r_ch3_stat___run___width 1
275#define reg_bif_dma_r_ch3_stat___run___bit 31
276#define reg_bif_dma_r_ch3_stat_offset 112
277
278/* Register rw_intr_mask, scope bif_dma, type rw */
279#define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0
280#define reg_bif_dma_rw_intr_mask___ext_dma0___width 1
281#define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0
282#define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1
283#define reg_bif_dma_rw_intr_mask___ext_dma1___width 1
284#define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1
285#define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2
286#define reg_bif_dma_rw_intr_mask___ext_dma2___width 1
287#define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2
288#define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3
289#define reg_bif_dma_rw_intr_mask___ext_dma3___width 1
290#define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3
291#define reg_bif_dma_rw_intr_mask_offset 128
292
293/* Register rw_ack_intr, scope bif_dma, type rw */
294#define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0
295#define reg_bif_dma_rw_ack_intr___ext_dma0___width 1
296#define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0
297#define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1
298#define reg_bif_dma_rw_ack_intr___ext_dma1___width 1
299#define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1
300#define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2
301#define reg_bif_dma_rw_ack_intr___ext_dma2___width 1
302#define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2
303#define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3
304#define reg_bif_dma_rw_ack_intr___ext_dma3___width 1
305#define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3
306#define reg_bif_dma_rw_ack_intr_offset 132
307
308/* Register r_intr, scope bif_dma, type r */
309#define reg_bif_dma_r_intr___ext_dma0___lsb 0
310#define reg_bif_dma_r_intr___ext_dma0___width 1
311#define reg_bif_dma_r_intr___ext_dma0___bit 0
312#define reg_bif_dma_r_intr___ext_dma1___lsb 1
313#define reg_bif_dma_r_intr___ext_dma1___width 1
314#define reg_bif_dma_r_intr___ext_dma1___bit 1
315#define reg_bif_dma_r_intr___ext_dma2___lsb 2
316#define reg_bif_dma_r_intr___ext_dma2___width 1
317#define reg_bif_dma_r_intr___ext_dma2___bit 2
318#define reg_bif_dma_r_intr___ext_dma3___lsb 3
319#define reg_bif_dma_r_intr___ext_dma3___width 1
320#define reg_bif_dma_r_intr___ext_dma3___bit 3
321#define reg_bif_dma_r_intr_offset 136
322
323/* Register r_masked_intr, scope bif_dma, type r */
324#define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0
325#define reg_bif_dma_r_masked_intr___ext_dma0___width 1
326#define reg_bif_dma_r_masked_intr___ext_dma0___bit 0
327#define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1
328#define reg_bif_dma_r_masked_intr___ext_dma1___width 1
329#define reg_bif_dma_r_masked_intr___ext_dma1___bit 1
330#define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2
331#define reg_bif_dma_r_masked_intr___ext_dma2___width 1
332#define reg_bif_dma_r_masked_intr___ext_dma2___bit 2
333#define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3
334#define reg_bif_dma_r_masked_intr___ext_dma3___width 1
335#define reg_bif_dma_r_masked_intr___ext_dma3___bit 3
336#define reg_bif_dma_r_masked_intr_offset 140
337
338/* Register rw_pin0_cfg, scope bif_dma, type rw */
339#define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0
340#define reg_bif_dma_rw_pin0_cfg___master_ch___width 2
341#define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2
342#define reg_bif_dma_rw_pin0_cfg___master_mode___width 3
343#define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5
344#define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2
345#define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7
346#define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3
347#define reg_bif_dma_rw_pin0_cfg_offset 160
348
349/* Register rw_pin1_cfg, scope bif_dma, type rw */
350#define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0
351#define reg_bif_dma_rw_pin1_cfg___master_ch___width 2
352#define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2
353#define reg_bif_dma_rw_pin1_cfg___master_mode___width 3
354#define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5
355#define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2
356#define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7
357#define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3
358#define reg_bif_dma_rw_pin1_cfg_offset 164
359
360/* Register rw_pin2_cfg, scope bif_dma, type rw */
361#define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0
362#define reg_bif_dma_rw_pin2_cfg___master_ch___width 2
363#define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2
364#define reg_bif_dma_rw_pin2_cfg___master_mode___width 3
365#define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5
366#define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2
367#define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7
368#define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3
369#define reg_bif_dma_rw_pin2_cfg_offset 168
370
371/* Register rw_pin3_cfg, scope bif_dma, type rw */
372#define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0
373#define reg_bif_dma_rw_pin3_cfg___master_ch___width 2
374#define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2
375#define reg_bif_dma_rw_pin3_cfg___master_mode___width 3
376#define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5
377#define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2
378#define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7
379#define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3
380#define reg_bif_dma_rw_pin3_cfg_offset 172
381
382/* Register rw_pin4_cfg, scope bif_dma, type rw */
383#define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0
384#define reg_bif_dma_rw_pin4_cfg___master_ch___width 2
385#define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2
386#define reg_bif_dma_rw_pin4_cfg___master_mode___width 3
387#define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5
388#define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2
389#define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7
390#define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3
391#define reg_bif_dma_rw_pin4_cfg_offset 176
392
393/* Register rw_pin5_cfg, scope bif_dma, type rw */
394#define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0
395#define reg_bif_dma_rw_pin5_cfg___master_ch___width 2
396#define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2
397#define reg_bif_dma_rw_pin5_cfg___master_mode___width 3
398#define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5
399#define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2
400#define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7
401#define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3
402#define reg_bif_dma_rw_pin5_cfg_offset 180
403
404/* Register rw_pin6_cfg, scope bif_dma, type rw */
405#define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0
406#define reg_bif_dma_rw_pin6_cfg___master_ch___width 2
407#define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2
408#define reg_bif_dma_rw_pin6_cfg___master_mode___width 3
409#define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5
410#define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2
411#define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7
412#define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3
413#define reg_bif_dma_rw_pin6_cfg_offset 184
414
415/* Register rw_pin7_cfg, scope bif_dma, type rw */
416#define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0
417#define reg_bif_dma_rw_pin7_cfg___master_ch___width 2
418#define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2
419#define reg_bif_dma_rw_pin7_cfg___master_mode___width 3
420#define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5
421#define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2
422#define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7
423#define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3
424#define reg_bif_dma_rw_pin7_cfg_offset 188
425
426/* Register r_pin_stat, scope bif_dma, type r */
427#define reg_bif_dma_r_pin_stat___pin0___lsb 0
428#define reg_bif_dma_r_pin_stat___pin0___width 1
429#define reg_bif_dma_r_pin_stat___pin0___bit 0
430#define reg_bif_dma_r_pin_stat___pin1___lsb 1
431#define reg_bif_dma_r_pin_stat___pin1___width 1
432#define reg_bif_dma_r_pin_stat___pin1___bit 1
433#define reg_bif_dma_r_pin_stat___pin2___lsb 2
434#define reg_bif_dma_r_pin_stat___pin2___width 1
435#define reg_bif_dma_r_pin_stat___pin2___bit 2
436#define reg_bif_dma_r_pin_stat___pin3___lsb 3
437#define reg_bif_dma_r_pin_stat___pin3___width 1
438#define reg_bif_dma_r_pin_stat___pin3___bit 3
439#define reg_bif_dma_r_pin_stat___pin4___lsb 4
440#define reg_bif_dma_r_pin_stat___pin4___width 1
441#define reg_bif_dma_r_pin_stat___pin4___bit 4
442#define reg_bif_dma_r_pin_stat___pin5___lsb 5
443#define reg_bif_dma_r_pin_stat___pin5___width 1
444#define reg_bif_dma_r_pin_stat___pin5___bit 5
445#define reg_bif_dma_r_pin_stat___pin6___lsb 6
446#define reg_bif_dma_r_pin_stat___pin6___width 1
447#define reg_bif_dma_r_pin_stat___pin6___bit 6
448#define reg_bif_dma_r_pin_stat___pin7___lsb 7
449#define reg_bif_dma_r_pin_stat___pin7___width 1
450#define reg_bif_dma_r_pin_stat___pin7___bit 7
451#define reg_bif_dma_r_pin_stat_offset 192
452
453
454/* Constants */
455#define regk_bif_dma_as_master 0x00000001
456#define regk_bif_dma_as_slave 0x00000001
457#define regk_bif_dma_burst1 0x00000000
458#define regk_bif_dma_burst8 0x00000001
459#define regk_bif_dma_bw16 0x00000001
460#define regk_bif_dma_bw32 0x00000002
461#define regk_bif_dma_bw8 0x00000000
462#define regk_bif_dma_dack 0x00000006
463#define regk_bif_dma_dack_inv 0x00000007
464#define regk_bif_dma_force 0x00000001
465#define regk_bif_dma_hi 0x00000003
466#define regk_bif_dma_inv 0x00000003
467#define regk_bif_dma_lo 0x00000002
468#define regk_bif_dma_master 0x00000001
469#define regk_bif_dma_no 0x00000000
470#define regk_bif_dma_norm 0x00000002
471#define regk_bif_dma_off 0x00000000
472#define regk_bif_dma_rw_ch0_ctrl_default 0x00000000
473#define regk_bif_dma_rw_ch0_start_default 0x00000000
474#define regk_bif_dma_rw_ch1_ctrl_default 0x00000000
475#define regk_bif_dma_rw_ch1_start_default 0x00000000
476#define regk_bif_dma_rw_ch2_ctrl_default 0x00000000
477#define regk_bif_dma_rw_ch2_start_default 0x00000000
478#define regk_bif_dma_rw_ch3_ctrl_default 0x00000000
479#define regk_bif_dma_rw_ch3_start_default 0x00000000
480#define regk_bif_dma_rw_intr_mask_default 0x00000000
481#define regk_bif_dma_rw_pin0_cfg_default 0x00000000
482#define regk_bif_dma_rw_pin1_cfg_default 0x00000000
483#define regk_bif_dma_rw_pin2_cfg_default 0x00000000
484#define regk_bif_dma_rw_pin3_cfg_default 0x00000000
485#define regk_bif_dma_rw_pin4_cfg_default 0x00000000
486#define regk_bif_dma_rw_pin5_cfg_default 0x00000000
487#define regk_bif_dma_rw_pin6_cfg_default 0x00000000
488#define regk_bif_dma_rw_pin7_cfg_default 0x00000000
489#define regk_bif_dma_slave 0x00000002
490#define regk_bif_dma_sreq 0x00000006
491#define regk_bif_dma_sreq_inv 0x00000007
492#define regk_bif_dma_tc 0x00000004
493#define regk_bif_dma_tc_inv 0x00000005
494#define regk_bif_dma_yes 0x00000001
495#endif /* __bif_dma_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h
new file mode 100644
index 000000000000..031f33a365bb
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h
@@ -0,0 +1,249 @@
1#ifndef __bif_slave_defs_asm_h
2#define __bif_slave_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/bif/rtl/bif_slave_regs.r
7 * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
8 * last modfied: Mon Apr 11 16:06:34 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r
11 * id: $Id: bif_slave_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_slave_cfg, scope bif_slave, type rw */
57#define reg_bif_slave_rw_slave_cfg___slave_id___lsb 0
58#define reg_bif_slave_rw_slave_cfg___slave_id___width 3
59#define reg_bif_slave_rw_slave_cfg___use_slave_id___lsb 3
60#define reg_bif_slave_rw_slave_cfg___use_slave_id___width 1
61#define reg_bif_slave_rw_slave_cfg___use_slave_id___bit 3
62#define reg_bif_slave_rw_slave_cfg___boot_rdy___lsb 4
63#define reg_bif_slave_rw_slave_cfg___boot_rdy___width 1
64#define reg_bif_slave_rw_slave_cfg___boot_rdy___bit 4
65#define reg_bif_slave_rw_slave_cfg___loopback___lsb 5
66#define reg_bif_slave_rw_slave_cfg___loopback___width 1
67#define reg_bif_slave_rw_slave_cfg___loopback___bit 5
68#define reg_bif_slave_rw_slave_cfg___dis___lsb 6
69#define reg_bif_slave_rw_slave_cfg___dis___width 1
70#define reg_bif_slave_rw_slave_cfg___dis___bit 6
71#define reg_bif_slave_rw_slave_cfg_offset 0
72
73/* Register r_slave_mode, scope bif_slave, type r */
74#define reg_bif_slave_r_slave_mode___ch0_mode___lsb 0
75#define reg_bif_slave_r_slave_mode___ch0_mode___width 1
76#define reg_bif_slave_r_slave_mode___ch0_mode___bit 0
77#define reg_bif_slave_r_slave_mode___ch1_mode___lsb 1
78#define reg_bif_slave_r_slave_mode___ch1_mode___width 1
79#define reg_bif_slave_r_slave_mode___ch1_mode___bit 1
80#define reg_bif_slave_r_slave_mode___ch2_mode___lsb 2
81#define reg_bif_slave_r_slave_mode___ch2_mode___width 1
82#define reg_bif_slave_r_slave_mode___ch2_mode___bit 2
83#define reg_bif_slave_r_slave_mode___ch3_mode___lsb 3
84#define reg_bif_slave_r_slave_mode___ch3_mode___width 1
85#define reg_bif_slave_r_slave_mode___ch3_mode___bit 3
86#define reg_bif_slave_r_slave_mode_offset 4
87
88/* Register rw_ch0_cfg, scope bif_slave, type rw */
89#define reg_bif_slave_rw_ch0_cfg___rd_hold___lsb 0
90#define reg_bif_slave_rw_ch0_cfg___rd_hold___width 2
91#define reg_bif_slave_rw_ch0_cfg___access_mode___lsb 2
92#define reg_bif_slave_rw_ch0_cfg___access_mode___width 1
93#define reg_bif_slave_rw_ch0_cfg___access_mode___bit 2
94#define reg_bif_slave_rw_ch0_cfg___access_ctrl___lsb 3
95#define reg_bif_slave_rw_ch0_cfg___access_ctrl___width 1
96#define reg_bif_slave_rw_ch0_cfg___access_ctrl___bit 3
97#define reg_bif_slave_rw_ch0_cfg___data_cs___lsb 4
98#define reg_bif_slave_rw_ch0_cfg___data_cs___width 2
99#define reg_bif_slave_rw_ch0_cfg_offset 16
100
101/* Register rw_ch1_cfg, scope bif_slave, type rw */
102#define reg_bif_slave_rw_ch1_cfg___rd_hold___lsb 0
103#define reg_bif_slave_rw_ch1_cfg___rd_hold___width 2
104#define reg_bif_slave_rw_ch1_cfg___access_mode___lsb 2
105#define reg_bif_slave_rw_ch1_cfg___access_mode___width 1
106#define reg_bif_slave_rw_ch1_cfg___access_mode___bit 2
107#define reg_bif_slave_rw_ch1_cfg___access_ctrl___lsb 3
108#define reg_bif_slave_rw_ch1_cfg___access_ctrl___width 1
109#define reg_bif_slave_rw_ch1_cfg___access_ctrl___bit 3
110#define reg_bif_slave_rw_ch1_cfg___data_cs___lsb 4
111#define reg_bif_slave_rw_ch1_cfg___data_cs___width 2
112#define reg_bif_slave_rw_ch1_cfg_offset 20
113
114/* Register rw_ch2_cfg, scope bif_slave, type rw */
115#define reg_bif_slave_rw_ch2_cfg___rd_hold___lsb 0
116#define reg_bif_slave_rw_ch2_cfg___rd_hold___width 2
117#define reg_bif_slave_rw_ch2_cfg___access_mode___lsb 2
118#define reg_bif_slave_rw_ch2_cfg___access_mode___width 1
119#define reg_bif_slave_rw_ch2_cfg___access_mode___bit 2
120#define reg_bif_slave_rw_ch2_cfg___access_ctrl___lsb 3
121#define reg_bif_slave_rw_ch2_cfg___access_ctrl___width 1
122#define reg_bif_slave_rw_ch2_cfg___access_ctrl___bit 3
123#define reg_bif_slave_rw_ch2_cfg___data_cs___lsb 4
124#define reg_bif_slave_rw_ch2_cfg___data_cs___width 2
125#define reg_bif_slave_rw_ch2_cfg_offset 24
126
127/* Register rw_ch3_cfg, scope bif_slave, type rw */
128#define reg_bif_slave_rw_ch3_cfg___rd_hold___lsb 0
129#define reg_bif_slave_rw_ch3_cfg___rd_hold___width 2
130#define reg_bif_slave_rw_ch3_cfg___access_mode___lsb 2
131#define reg_bif_slave_rw_ch3_cfg___access_mode___width 1
132#define reg_bif_slave_rw_ch3_cfg___access_mode___bit 2
133#define reg_bif_slave_rw_ch3_cfg___access_ctrl___lsb 3
134#define reg_bif_slave_rw_ch3_cfg___access_ctrl___width 1
135#define reg_bif_slave_rw_ch3_cfg___access_ctrl___bit 3
136#define reg_bif_slave_rw_ch3_cfg___data_cs___lsb 4
137#define reg_bif_slave_rw_ch3_cfg___data_cs___width 2
138#define reg_bif_slave_rw_ch3_cfg_offset 28
139
140/* Register rw_arb_cfg, scope bif_slave, type rw */
141#define reg_bif_slave_rw_arb_cfg___brin_mode___lsb 0
142#define reg_bif_slave_rw_arb_cfg___brin_mode___width 1
143#define reg_bif_slave_rw_arb_cfg___brin_mode___bit 0
144#define reg_bif_slave_rw_arb_cfg___brout_mode___lsb 1
145#define reg_bif_slave_rw_arb_cfg___brout_mode___width 3
146#define reg_bif_slave_rw_arb_cfg___bg_mode___lsb 4
147#define reg_bif_slave_rw_arb_cfg___bg_mode___width 3
148#define reg_bif_slave_rw_arb_cfg___release___lsb 7
149#define reg_bif_slave_rw_arb_cfg___release___width 2
150#define reg_bif_slave_rw_arb_cfg___acquire___lsb 9
151#define reg_bif_slave_rw_arb_cfg___acquire___width 1
152#define reg_bif_slave_rw_arb_cfg___acquire___bit 9
153#define reg_bif_slave_rw_arb_cfg___settle_time___lsb 10
154#define reg_bif_slave_rw_arb_cfg___settle_time___width 2
155#define reg_bif_slave_rw_arb_cfg___dram_ctrl___lsb 12
156#define reg_bif_slave_rw_arb_cfg___dram_ctrl___width 1
157#define reg_bif_slave_rw_arb_cfg___dram_ctrl___bit 12
158#define reg_bif_slave_rw_arb_cfg_offset 32
159
160/* Register r_arb_stat, scope bif_slave, type r */
161#define reg_bif_slave_r_arb_stat___init_mode___lsb 0
162#define reg_bif_slave_r_arb_stat___init_mode___width 1
163#define reg_bif_slave_r_arb_stat___init_mode___bit 0
164#define reg_bif_slave_r_arb_stat___mode___lsb 1
165#define reg_bif_slave_r_arb_stat___mode___width 1
166#define reg_bif_slave_r_arb_stat___mode___bit 1
167#define reg_bif_slave_r_arb_stat___brin___lsb 2
168#define reg_bif_slave_r_arb_stat___brin___width 1
169#define reg_bif_slave_r_arb_stat___brin___bit 2
170#define reg_bif_slave_r_arb_stat___brout___lsb 3
171#define reg_bif_slave_r_arb_stat___brout___width 1
172#define reg_bif_slave_r_arb_stat___brout___bit 3
173#define reg_bif_slave_r_arb_stat___bg___lsb 4
174#define reg_bif_slave_r_arb_stat___bg___width 1
175#define reg_bif_slave_r_arb_stat___bg___bit 4
176#define reg_bif_slave_r_arb_stat_offset 36
177
178/* Register rw_intr_mask, scope bif_slave, type rw */
179#define reg_bif_slave_rw_intr_mask___bus_release___lsb 0
180#define reg_bif_slave_rw_intr_mask___bus_release___width 1
181#define reg_bif_slave_rw_intr_mask___bus_release___bit 0
182#define reg_bif_slave_rw_intr_mask___bus_acquire___lsb 1
183#define reg_bif_slave_rw_intr_mask___bus_acquire___width 1
184#define reg_bif_slave_rw_intr_mask___bus_acquire___bit 1
185#define reg_bif_slave_rw_intr_mask_offset 64
186
187/* Register rw_ack_intr, scope bif_slave, type rw */
188#define reg_bif_slave_rw_ack_intr___bus_release___lsb 0
189#define reg_bif_slave_rw_ack_intr___bus_release___width 1
190#define reg_bif_slave_rw_ack_intr___bus_release___bit 0
191#define reg_bif_slave_rw_ack_intr___bus_acquire___lsb 1
192#define reg_bif_slave_rw_ack_intr___bus_acquire___width 1
193#define reg_bif_slave_rw_ack_intr___bus_acquire___bit 1
194#define reg_bif_slave_rw_ack_intr_offset 68
195
196/* Register r_intr, scope bif_slave, type r */
197#define reg_bif_slave_r_intr___bus_release___lsb 0
198#define reg_bif_slave_r_intr___bus_release___width 1
199#define reg_bif_slave_r_intr___bus_release___bit 0
200#define reg_bif_slave_r_intr___bus_acquire___lsb 1
201#define reg_bif_slave_r_intr___bus_acquire___width 1
202#define reg_bif_slave_r_intr___bus_acquire___bit 1
203#define reg_bif_slave_r_intr_offset 72
204
205/* Register r_masked_intr, scope bif_slave, type r */
206#define reg_bif_slave_r_masked_intr___bus_release___lsb 0
207#define reg_bif_slave_r_masked_intr___bus_release___width 1
208#define reg_bif_slave_r_masked_intr___bus_release___bit 0
209#define reg_bif_slave_r_masked_intr___bus_acquire___lsb 1
210#define reg_bif_slave_r_masked_intr___bus_acquire___width 1
211#define reg_bif_slave_r_masked_intr___bus_acquire___bit 1
212#define reg_bif_slave_r_masked_intr_offset 76
213
214
215/* Constants */
216#define regk_bif_slave_active_hi 0x00000003
217#define regk_bif_slave_active_lo 0x00000002
218#define regk_bif_slave_addr 0x00000000
219#define regk_bif_slave_always 0x00000001
220#define regk_bif_slave_at_idle 0x00000002
221#define regk_bif_slave_burst_end 0x00000003
222#define regk_bif_slave_dma 0x00000001
223#define regk_bif_slave_hi 0x00000003
224#define regk_bif_slave_inv 0x00000001
225#define regk_bif_slave_lo 0x00000002
226#define regk_bif_slave_local 0x00000001
227#define regk_bif_slave_master 0x00000000
228#define regk_bif_slave_mode_reg 0x00000001
229#define regk_bif_slave_no 0x00000000
230#define regk_bif_slave_norm 0x00000000
231#define regk_bif_slave_on_access 0x00000000
232#define regk_bif_slave_rw_arb_cfg_default 0x00000000
233#define regk_bif_slave_rw_ch0_cfg_default 0x00000000
234#define regk_bif_slave_rw_ch1_cfg_default 0x00000000
235#define regk_bif_slave_rw_ch2_cfg_default 0x00000000
236#define regk_bif_slave_rw_ch3_cfg_default 0x00000000
237#define regk_bif_slave_rw_intr_mask_default 0x00000000
238#define regk_bif_slave_rw_slave_cfg_default 0x00000000
239#define regk_bif_slave_shared 0x00000000
240#define regk_bif_slave_slave 0x00000001
241#define regk_bif_slave_t0ns 0x00000003
242#define regk_bif_slave_t10ns 0x00000002
243#define regk_bif_slave_t20ns 0x00000003
244#define regk_bif_slave_t30ns 0x00000002
245#define regk_bif_slave_t40ns 0x00000001
246#define regk_bif_slave_t50ns 0x00000000
247#define regk_bif_slave_yes 0x00000001
248#define regk_bif_slave_z 0x00000004
249#endif /* __bif_slave_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h
new file mode 100644
index 000000000000..e98476332e1f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h
@@ -0,0 +1,131 @@
1#ifndef __config_defs_asm_h
2#define __config_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../rtl/config_regs.r
7 * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
8 * last modfied: Thu Mar 4 12:34:39 2004
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r
11 * id: $Id: config_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register r_bootsel, scope config, type r */
57#define reg_config_r_bootsel___boot_mode___lsb 0
58#define reg_config_r_bootsel___boot_mode___width 3
59#define reg_config_r_bootsel___full_duplex___lsb 3
60#define reg_config_r_bootsel___full_duplex___width 1
61#define reg_config_r_bootsel___full_duplex___bit 3
62#define reg_config_r_bootsel___user___lsb 4
63#define reg_config_r_bootsel___user___width 1
64#define reg_config_r_bootsel___user___bit 4
65#define reg_config_r_bootsel___pll___lsb 5
66#define reg_config_r_bootsel___pll___width 1
67#define reg_config_r_bootsel___pll___bit 5
68#define reg_config_r_bootsel___flash_bw___lsb 6
69#define reg_config_r_bootsel___flash_bw___width 1
70#define reg_config_r_bootsel___flash_bw___bit 6
71#define reg_config_r_bootsel_offset 0
72
73/* Register rw_clk_ctrl, scope config, type rw */
74#define reg_config_rw_clk_ctrl___pll___lsb 0
75#define reg_config_rw_clk_ctrl___pll___width 1
76#define reg_config_rw_clk_ctrl___pll___bit 0
77#define reg_config_rw_clk_ctrl___cpu___lsb 1
78#define reg_config_rw_clk_ctrl___cpu___width 1
79#define reg_config_rw_clk_ctrl___cpu___bit 1
80#define reg_config_rw_clk_ctrl___iop___lsb 2
81#define reg_config_rw_clk_ctrl___iop___width 1
82#define reg_config_rw_clk_ctrl___iop___bit 2
83#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3
84#define reg_config_rw_clk_ctrl___dma01_eth0___width 1
85#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3
86#define reg_config_rw_clk_ctrl___dma23___lsb 4
87#define reg_config_rw_clk_ctrl___dma23___width 1
88#define reg_config_rw_clk_ctrl___dma23___bit 4
89#define reg_config_rw_clk_ctrl___dma45___lsb 5
90#define reg_config_rw_clk_ctrl___dma45___width 1
91#define reg_config_rw_clk_ctrl___dma45___bit 5
92#define reg_config_rw_clk_ctrl___dma67___lsb 6
93#define reg_config_rw_clk_ctrl___dma67___width 1
94#define reg_config_rw_clk_ctrl___dma67___bit 6
95#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7
96#define reg_config_rw_clk_ctrl___dma89_strcop___width 1
97#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7
98#define reg_config_rw_clk_ctrl___bif___lsb 8
99#define reg_config_rw_clk_ctrl___bif___width 1
100#define reg_config_rw_clk_ctrl___bif___bit 8
101#define reg_config_rw_clk_ctrl___fix_io___lsb 9
102#define reg_config_rw_clk_ctrl___fix_io___width 1
103#define reg_config_rw_clk_ctrl___fix_io___bit 9
104#define reg_config_rw_clk_ctrl_offset 4
105
106/* Register rw_pad_ctrl, scope config, type rw */
107#define reg_config_rw_pad_ctrl___usb_susp___lsb 0
108#define reg_config_rw_pad_ctrl___usb_susp___width 1
109#define reg_config_rw_pad_ctrl___usb_susp___bit 0
110#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1
111#define reg_config_rw_pad_ctrl___phyrst_n___width 1
112#define reg_config_rw_pad_ctrl___phyrst_n___bit 1
113#define reg_config_rw_pad_ctrl_offset 8
114
115
116/* Constants */
117#define regk_config_bw16 0x00000000
118#define regk_config_bw32 0x00000001
119#define regk_config_master 0x00000005
120#define regk_config_nand 0x00000003
121#define regk_config_net_rx 0x00000001
122#define regk_config_net_tx_rx 0x00000002
123#define regk_config_no 0x00000000
124#define regk_config_none 0x00000007
125#define regk_config_nor 0x00000000
126#define regk_config_rw_clk_ctrl_default 0x00000002
127#define regk_config_rw_pad_ctrl_default 0x00000000
128#define regk_config_ser 0x00000004
129#define regk_config_slave 0x00000006
130#define regk_config_yes 0x00000001
131#endif /* __config_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h b/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h
new file mode 100644
index 000000000000..8370aee8a14a
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h
@@ -0,0 +1,41 @@
1/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
2 from ../../inst/crisp/doc/cpu_vect.r
3version . */
4
5#ifndef _______INST_CRISP_DOC_CPU_VECT_R
6#define _______INST_CRISP_DOC_CPU_VECT_R
7#define NMI_INTR_VECT 0x00
8#define RESERVED_1_INTR_VECT 0x01
9#define RESERVED_2_INTR_VECT 0x02
10#define SINGLE_STEP_INTR_VECT 0x03
11#define INSTR_TLB_REFILL_INTR_VECT 0x04
12#define INSTR_TLB_INV_INTR_VECT 0x05
13#define INSTR_TLB_ACC_INTR_VECT 0x06
14#define TLB_EX_INTR_VECT 0x07
15#define DATA_TLB_REFILL_INTR_VECT 0x08
16#define DATA_TLB_INV_INTR_VECT 0x09
17#define DATA_TLB_ACC_INTR_VECT 0x0a
18#define DATA_TLB_WE_INTR_VECT 0x0b
19#define HW_BP_INTR_VECT 0x0c
20#define RESERVED_D_INTR_VECT 0x0d
21#define RESERVED_E_INTR_VECT 0x0e
22#define RESERVED_F_INTR_VECT 0x0f
23#define BREAK_0_INTR_VECT 0x10
24#define BREAK_1_INTR_VECT 0x11
25#define BREAK_2_INTR_VECT 0x12
26#define BREAK_3_INTR_VECT 0x13
27#define BREAK_4_INTR_VECT 0x14
28#define BREAK_5_INTR_VECT 0x15
29#define BREAK_6_INTR_VECT 0x16
30#define BREAK_7_INTR_VECT 0x17
31#define BREAK_8_INTR_VECT 0x18
32#define BREAK_9_INTR_VECT 0x19
33#define BREAK_10_INTR_VECT 0x1a
34#define BREAK_11_INTR_VECT 0x1b
35#define BREAK_12_INTR_VECT 0x1c
36#define BREAK_13_INTR_VECT 0x1d
37#define BREAK_14_INTR_VECT 0x1e
38#define BREAK_15_INTR_VECT 0x1f
39#define MULTIPLE_INTR_VECT 0x30
40
41#endif
diff --git a/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h
new file mode 100644
index 000000000000..7f768db272e2
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h
@@ -0,0 +1,114 @@
1#ifndef __cris_defs_asm_h
2#define __cris_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/crisp/doc/cris.r
7 * id: cris.r,v 1.6 2004/05/05 07:41:12 perz Exp
8 * last modfied: Mon Apr 11 16:06:39 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r
11 * id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_gc_cfg, scope cris, type rw */
57#define reg_cris_rw_gc_cfg___ic___lsb 0
58#define reg_cris_rw_gc_cfg___ic___width 1
59#define reg_cris_rw_gc_cfg___ic___bit 0
60#define reg_cris_rw_gc_cfg___dc___lsb 1
61#define reg_cris_rw_gc_cfg___dc___width 1
62#define reg_cris_rw_gc_cfg___dc___bit 1
63#define reg_cris_rw_gc_cfg___im___lsb 2
64#define reg_cris_rw_gc_cfg___im___width 1
65#define reg_cris_rw_gc_cfg___im___bit 2
66#define reg_cris_rw_gc_cfg___dm___lsb 3
67#define reg_cris_rw_gc_cfg___dm___width 1
68#define reg_cris_rw_gc_cfg___dm___bit 3
69#define reg_cris_rw_gc_cfg___gb___lsb 4
70#define reg_cris_rw_gc_cfg___gb___width 1
71#define reg_cris_rw_gc_cfg___gb___bit 4
72#define reg_cris_rw_gc_cfg___gk___lsb 5
73#define reg_cris_rw_gc_cfg___gk___width 1
74#define reg_cris_rw_gc_cfg___gk___bit 5
75#define reg_cris_rw_gc_cfg___gp___lsb 6
76#define reg_cris_rw_gc_cfg___gp___width 1
77#define reg_cris_rw_gc_cfg___gp___bit 6
78#define reg_cris_rw_gc_cfg_offset 0
79
80/* Register rw_gc_ccs, scope cris, type rw */
81#define reg_cris_rw_gc_ccs_offset 4
82
83/* Register rw_gc_srs, scope cris, type rw */
84#define reg_cris_rw_gc_srs___srs___lsb 0
85#define reg_cris_rw_gc_srs___srs___width 8
86#define reg_cris_rw_gc_srs_offset 8
87
88/* Register rw_gc_nrp, scope cris, type rw */
89#define reg_cris_rw_gc_nrp_offset 12
90
91/* Register rw_gc_exs, scope cris, type rw */
92#define reg_cris_rw_gc_exs_offset 16
93
94/* Register rw_gc_eda, scope cris, type rw */
95#define reg_cris_rw_gc_eda_offset 20
96
97/* Register rw_gc_r0, scope cris, type rw */
98#define reg_cris_rw_gc_r0_offset 32
99
100/* Register rw_gc_r1, scope cris, type rw */
101#define reg_cris_rw_gc_r1_offset 36
102
103/* Register rw_gc_r2, scope cris, type rw */
104#define reg_cris_rw_gc_r2_offset 40
105
106/* Register rw_gc_r3, scope cris, type rw */
107#define reg_cris_rw_gc_r3_offset 44
108
109
110/* Constants */
111#define regk_cris_no 0x00000000
112#define regk_cris_rw_gc_cfg_default 0x00000000
113#define regk_cris_yes 0x00000001
114#endif /* __cris_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h b/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h
new file mode 100644
index 000000000000..7d3689a6f80d
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h
@@ -0,0 +1,10 @@
1#define RW_GC_CFG 0
2#define RW_GC_CCS 1
3#define RW_GC_SRS 2
4#define RW_GC_NRP 3
5#define RW_GC_EXS 4
6#define RW_GC_EDA 5
7#define RW_GC_R0 8
8#define RW_GC_R1 9
9#define RW_GC_R2 10
10#define RW_GC_R3 11
diff --git a/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h
new file mode 100644
index 000000000000..0cb71bc127ae
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h
@@ -0,0 +1,368 @@
1#ifndef __dma_defs_asm_h
2#define __dma_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
7 * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
8 * last modfied: Mon Apr 11 16:06:51 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
11 * id: $Id: dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_data, scope dma, type rw */
57#define reg_dma_rw_data_offset 0
58
59/* Register rw_data_next, scope dma, type rw */
60#define reg_dma_rw_data_next_offset 4
61
62/* Register rw_data_buf, scope dma, type rw */
63#define reg_dma_rw_data_buf_offset 8
64
65/* Register rw_data_ctrl, scope dma, type rw */
66#define reg_dma_rw_data_ctrl___eol___lsb 0
67#define reg_dma_rw_data_ctrl___eol___width 1
68#define reg_dma_rw_data_ctrl___eol___bit 0
69#define reg_dma_rw_data_ctrl___out_eop___lsb 3
70#define reg_dma_rw_data_ctrl___out_eop___width 1
71#define reg_dma_rw_data_ctrl___out_eop___bit 3
72#define reg_dma_rw_data_ctrl___intr___lsb 4
73#define reg_dma_rw_data_ctrl___intr___width 1
74#define reg_dma_rw_data_ctrl___intr___bit 4
75#define reg_dma_rw_data_ctrl___wait___lsb 5
76#define reg_dma_rw_data_ctrl___wait___width 1
77#define reg_dma_rw_data_ctrl___wait___bit 5
78#define reg_dma_rw_data_ctrl_offset 12
79
80/* Register rw_data_stat, scope dma, type rw */
81#define reg_dma_rw_data_stat___in_eop___lsb 3
82#define reg_dma_rw_data_stat___in_eop___width 1
83#define reg_dma_rw_data_stat___in_eop___bit 3
84#define reg_dma_rw_data_stat_offset 16
85
86/* Register rw_data_md, scope dma, type rw */
87#define reg_dma_rw_data_md___md___lsb 0
88#define reg_dma_rw_data_md___md___width 16
89#define reg_dma_rw_data_md_offset 20
90
91/* Register rw_data_md_s, scope dma, type rw */
92#define reg_dma_rw_data_md_s___md_s___lsb 0
93#define reg_dma_rw_data_md_s___md_s___width 16
94#define reg_dma_rw_data_md_s_offset 24
95
96/* Register rw_data_after, scope dma, type rw */
97#define reg_dma_rw_data_after_offset 28
98
99/* Register rw_ctxt, scope dma, type rw */
100#define reg_dma_rw_ctxt_offset 32
101
102/* Register rw_ctxt_next, scope dma, type rw */
103#define reg_dma_rw_ctxt_next_offset 36
104
105/* Register rw_ctxt_ctrl, scope dma, type rw */
106#define reg_dma_rw_ctxt_ctrl___eol___lsb 0
107#define reg_dma_rw_ctxt_ctrl___eol___width 1
108#define reg_dma_rw_ctxt_ctrl___eol___bit 0
109#define reg_dma_rw_ctxt_ctrl___intr___lsb 4
110#define reg_dma_rw_ctxt_ctrl___intr___width 1
111#define reg_dma_rw_ctxt_ctrl___intr___bit 4
112#define reg_dma_rw_ctxt_ctrl___store_mode___lsb 6
113#define reg_dma_rw_ctxt_ctrl___store_mode___width 1
114#define reg_dma_rw_ctxt_ctrl___store_mode___bit 6
115#define reg_dma_rw_ctxt_ctrl___en___lsb 7
116#define reg_dma_rw_ctxt_ctrl___en___width 1
117#define reg_dma_rw_ctxt_ctrl___en___bit 7
118#define reg_dma_rw_ctxt_ctrl_offset 40
119
120/* Register rw_ctxt_stat, scope dma, type rw */
121#define reg_dma_rw_ctxt_stat___dis___lsb 7
122#define reg_dma_rw_ctxt_stat___dis___width 1
123#define reg_dma_rw_ctxt_stat___dis___bit 7
124#define reg_dma_rw_ctxt_stat_offset 44
125
126/* Register rw_ctxt_md0, scope dma, type rw */
127#define reg_dma_rw_ctxt_md0___md0___lsb 0
128#define reg_dma_rw_ctxt_md0___md0___width 16
129#define reg_dma_rw_ctxt_md0_offset 48
130
131/* Register rw_ctxt_md0_s, scope dma, type rw */
132#define reg_dma_rw_ctxt_md0_s___md0_s___lsb 0
133#define reg_dma_rw_ctxt_md0_s___md0_s___width 16
134#define reg_dma_rw_ctxt_md0_s_offset 52
135
136/* Register rw_ctxt_md1, scope dma, type rw */
137#define reg_dma_rw_ctxt_md1_offset 56
138
139/* Register rw_ctxt_md1_s, scope dma, type rw */
140#define reg_dma_rw_ctxt_md1_s_offset 60
141
142/* Register rw_ctxt_md2, scope dma, type rw */
143#define reg_dma_rw_ctxt_md2_offset 64
144
145/* Register rw_ctxt_md2_s, scope dma, type rw */
146#define reg_dma_rw_ctxt_md2_s_offset 68
147
148/* Register rw_ctxt_md3, scope dma, type rw */
149#define reg_dma_rw_ctxt_md3_offset 72
150
151/* Register rw_ctxt_md3_s, scope dma, type rw */
152#define reg_dma_rw_ctxt_md3_s_offset 76
153
154/* Register rw_ctxt_md4, scope dma, type rw */
155#define reg_dma_rw_ctxt_md4_offset 80
156
157/* Register rw_ctxt_md4_s, scope dma, type rw */
158#define reg_dma_rw_ctxt_md4_s_offset 84
159
160/* Register rw_saved_data, scope dma, type rw */
161#define reg_dma_rw_saved_data_offset 88
162
163/* Register rw_saved_data_buf, scope dma, type rw */
164#define reg_dma_rw_saved_data_buf_offset 92
165
166/* Register rw_group, scope dma, type rw */
167#define reg_dma_rw_group_offset 96
168
169/* Register rw_group_next, scope dma, type rw */
170#define reg_dma_rw_group_next_offset 100
171
172/* Register rw_group_ctrl, scope dma, type rw */
173#define reg_dma_rw_group_ctrl___eol___lsb 0
174#define reg_dma_rw_group_ctrl___eol___width 1
175#define reg_dma_rw_group_ctrl___eol___bit 0
176#define reg_dma_rw_group_ctrl___tol___lsb 1
177#define reg_dma_rw_group_ctrl___tol___width 1
178#define reg_dma_rw_group_ctrl___tol___bit 1
179#define reg_dma_rw_group_ctrl___bol___lsb 2
180#define reg_dma_rw_group_ctrl___bol___width 1
181#define reg_dma_rw_group_ctrl___bol___bit 2
182#define reg_dma_rw_group_ctrl___intr___lsb 4
183#define reg_dma_rw_group_ctrl___intr___width 1
184#define reg_dma_rw_group_ctrl___intr___bit 4
185#define reg_dma_rw_group_ctrl___en___lsb 7
186#define reg_dma_rw_group_ctrl___en___width 1
187#define reg_dma_rw_group_ctrl___en___bit 7
188#define reg_dma_rw_group_ctrl_offset 104
189
190/* Register rw_group_stat, scope dma, type rw */
191#define reg_dma_rw_group_stat___dis___lsb 7
192#define reg_dma_rw_group_stat___dis___width 1
193#define reg_dma_rw_group_stat___dis___bit 7
194#define reg_dma_rw_group_stat_offset 108
195
196/* Register rw_group_md, scope dma, type rw */
197#define reg_dma_rw_group_md___md___lsb 0
198#define reg_dma_rw_group_md___md___width 16
199#define reg_dma_rw_group_md_offset 112
200
201/* Register rw_group_md_s, scope dma, type rw */
202#define reg_dma_rw_group_md_s___md_s___lsb 0
203#define reg_dma_rw_group_md_s___md_s___width 16
204#define reg_dma_rw_group_md_s_offset 116
205
206/* Register rw_group_up, scope dma, type rw */
207#define reg_dma_rw_group_up_offset 120
208
209/* Register rw_group_down, scope dma, type rw */
210#define reg_dma_rw_group_down_offset 124
211
212/* Register rw_cmd, scope dma, type rw */
213#define reg_dma_rw_cmd___cont_data___lsb 0
214#define reg_dma_rw_cmd___cont_data___width 1
215#define reg_dma_rw_cmd___cont_data___bit 0
216#define reg_dma_rw_cmd_offset 128
217
218/* Register rw_cfg, scope dma, type rw */
219#define reg_dma_rw_cfg___en___lsb 0
220#define reg_dma_rw_cfg___en___width 1
221#define reg_dma_rw_cfg___en___bit 0
222#define reg_dma_rw_cfg___stop___lsb 1
223#define reg_dma_rw_cfg___stop___width 1
224#define reg_dma_rw_cfg___stop___bit 1
225#define reg_dma_rw_cfg_offset 132
226
227/* Register rw_stat, scope dma, type rw */
228#define reg_dma_rw_stat___mode___lsb 0
229#define reg_dma_rw_stat___mode___width 5
230#define reg_dma_rw_stat___list_state___lsb 5
231#define reg_dma_rw_stat___list_state___width 3
232#define reg_dma_rw_stat___stream_cmd_src___lsb 8
233#define reg_dma_rw_stat___stream_cmd_src___width 8
234#define reg_dma_rw_stat___buf___lsb 24
235#define reg_dma_rw_stat___buf___width 8
236#define reg_dma_rw_stat_offset 136
237
238/* Register rw_intr_mask, scope dma, type rw */
239#define reg_dma_rw_intr_mask___group___lsb 0
240#define reg_dma_rw_intr_mask___group___width 1
241#define reg_dma_rw_intr_mask___group___bit 0
242#define reg_dma_rw_intr_mask___ctxt___lsb 1
243#define reg_dma_rw_intr_mask___ctxt___width 1
244#define reg_dma_rw_intr_mask___ctxt___bit 1
245#define reg_dma_rw_intr_mask___data___lsb 2
246#define reg_dma_rw_intr_mask___data___width 1
247#define reg_dma_rw_intr_mask___data___bit 2
248#define reg_dma_rw_intr_mask___in_eop___lsb 3
249#define reg_dma_rw_intr_mask___in_eop___width 1
250#define reg_dma_rw_intr_mask___in_eop___bit 3
251#define reg_dma_rw_intr_mask___stream_cmd___lsb 4
252#define reg_dma_rw_intr_mask___stream_cmd___width 1
253#define reg_dma_rw_intr_mask___stream_cmd___bit 4
254#define reg_dma_rw_intr_mask_offset 140
255
256/* Register rw_ack_intr, scope dma, type rw */
257#define reg_dma_rw_ack_intr___group___lsb 0
258#define reg_dma_rw_ack_intr___group___width 1
259#define reg_dma_rw_ack_intr___group___bit 0
260#define reg_dma_rw_ack_intr___ctxt___lsb 1
261#define reg_dma_rw_ack_intr___ctxt___width 1
262#define reg_dma_rw_ack_intr___ctxt___bit 1
263#define reg_dma_rw_ack_intr___data___lsb 2
264#define reg_dma_rw_ack_intr___data___width 1
265#define reg_dma_rw_ack_intr___data___bit 2
266#define reg_dma_rw_ack_intr___in_eop___lsb 3
267#define reg_dma_rw_ack_intr___in_eop___width 1
268#define reg_dma_rw_ack_intr___in_eop___bit 3
269#define reg_dma_rw_ack_intr___stream_cmd___lsb 4
270#define reg_dma_rw_ack_intr___stream_cmd___width 1
271#define reg_dma_rw_ack_intr___stream_cmd___bit 4
272#define reg_dma_rw_ack_intr_offset 144
273
274/* Register r_intr, scope dma, type r */
275#define reg_dma_r_intr___group___lsb 0
276#define reg_dma_r_intr___group___width 1
277#define reg_dma_r_intr___group___bit 0
278#define reg_dma_r_intr___ctxt___lsb 1
279#define reg_dma_r_intr___ctxt___width 1
280#define reg_dma_r_intr___ctxt___bit 1
281#define reg_dma_r_intr___data___lsb 2
282#define reg_dma_r_intr___data___width 1
283#define reg_dma_r_intr___data___bit 2
284#define reg_dma_r_intr___in_eop___lsb 3
285#define reg_dma_r_intr___in_eop___width 1
286#define reg_dma_r_intr___in_eop___bit 3
287#define reg_dma_r_intr___stream_cmd___lsb 4
288#define reg_dma_r_intr___stream_cmd___width 1
289#define reg_dma_r_intr___stream_cmd___bit 4
290#define reg_dma_r_intr_offset 148
291
292/* Register r_masked_intr, scope dma, type r */
293#define reg_dma_r_masked_intr___group___lsb 0
294#define reg_dma_r_masked_intr___group___width 1
295#define reg_dma_r_masked_intr___group___bit 0
296#define reg_dma_r_masked_intr___ctxt___lsb 1
297#define reg_dma_r_masked_intr___ctxt___width 1
298#define reg_dma_r_masked_intr___ctxt___bit 1
299#define reg_dma_r_masked_intr___data___lsb 2
300#define reg_dma_r_masked_intr___data___width 1
301#define reg_dma_r_masked_intr___data___bit 2
302#define reg_dma_r_masked_intr___in_eop___lsb 3
303#define reg_dma_r_masked_intr___in_eop___width 1
304#define reg_dma_r_masked_intr___in_eop___bit 3
305#define reg_dma_r_masked_intr___stream_cmd___lsb 4
306#define reg_dma_r_masked_intr___stream_cmd___width 1
307#define reg_dma_r_masked_intr___stream_cmd___bit 4
308#define reg_dma_r_masked_intr_offset 152
309
310/* Register rw_stream_cmd, scope dma, type rw */
311#define reg_dma_rw_stream_cmd___cmd___lsb 0
312#define reg_dma_rw_stream_cmd___cmd___width 10
313#define reg_dma_rw_stream_cmd___n___lsb 16
314#define reg_dma_rw_stream_cmd___n___width 8
315#define reg_dma_rw_stream_cmd___busy___lsb 31
316#define reg_dma_rw_stream_cmd___busy___width 1
317#define reg_dma_rw_stream_cmd___busy___bit 31
318#define reg_dma_rw_stream_cmd_offset 156
319
320
321/* Constants */
322#define regk_dma_ack_pkt 0x00000100
323#define regk_dma_anytime 0x00000001
324#define regk_dma_array 0x00000008
325#define regk_dma_burst 0x00000020
326#define regk_dma_client 0x00000002
327#define regk_dma_copy_next 0x00000010
328#define regk_dma_copy_up 0x00000020
329#define regk_dma_data_at_eol 0x00000001
330#define regk_dma_dis_c 0x00000010
331#define regk_dma_dis_g 0x00000020
332#define regk_dma_idle 0x00000001
333#define regk_dma_intern 0x00000004
334#define regk_dma_load_c 0x00000200
335#define regk_dma_load_c_n 0x00000280
336#define regk_dma_load_c_next 0x00000240
337#define regk_dma_load_d 0x00000140
338#define regk_dma_load_g 0x00000300
339#define regk_dma_load_g_down 0x000003c0
340#define regk_dma_load_g_next 0x00000340
341#define regk_dma_load_g_up 0x00000380
342#define regk_dma_next_en 0x00000010
343#define regk_dma_next_pkt 0x00000010
344#define regk_dma_no 0x00000000
345#define regk_dma_only_at_wait 0x00000000
346#define regk_dma_restore 0x00000020
347#define regk_dma_rst 0x00000001
348#define regk_dma_running 0x00000004
349#define regk_dma_rw_cfg_default 0x00000000
350#define regk_dma_rw_cmd_default 0x00000000
351#define regk_dma_rw_intr_mask_default 0x00000000
352#define regk_dma_rw_stat_default 0x00000101
353#define regk_dma_rw_stream_cmd_default 0x00000000
354#define regk_dma_save_down 0x00000020
355#define regk_dma_save_up 0x00000020
356#define regk_dma_set_reg 0x00000050
357#define regk_dma_set_w_size1 0x00000190
358#define regk_dma_set_w_size2 0x000001a0
359#define regk_dma_set_w_size4 0x000001c0
360#define regk_dma_stopped 0x00000002
361#define regk_dma_store_c 0x00000002
362#define regk_dma_store_descr 0x00000000
363#define regk_dma_store_g 0x00000004
364#define regk_dma_store_md 0x00000001
365#define regk_dma_sw 0x00000008
366#define regk_dma_update_down 0x00000020
367#define regk_dma_yes 0x00000001
368#endif /* __dma_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h
new file mode 100644
index 000000000000..c9f49864831b
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h
@@ -0,0 +1,498 @@
1#ifndef __eth_defs_asm_h
2#define __eth_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/eth/rtl/eth_regs.r
7 * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp
8 * last modfied: Mon Apr 11 16:07:03 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r
11 * id: $Id: eth_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_ma0_lo, scope eth, type rw */
57#define reg_eth_rw_ma0_lo___addr___lsb 0
58#define reg_eth_rw_ma0_lo___addr___width 32
59#define reg_eth_rw_ma0_lo_offset 0
60
61/* Register rw_ma0_hi, scope eth, type rw */
62#define reg_eth_rw_ma0_hi___addr___lsb 0
63#define reg_eth_rw_ma0_hi___addr___width 16
64#define reg_eth_rw_ma0_hi_offset 4
65
66/* Register rw_ma1_lo, scope eth, type rw */
67#define reg_eth_rw_ma1_lo___addr___lsb 0
68#define reg_eth_rw_ma1_lo___addr___width 32
69#define reg_eth_rw_ma1_lo_offset 8
70
71/* Register rw_ma1_hi, scope eth, type rw */
72#define reg_eth_rw_ma1_hi___addr___lsb 0
73#define reg_eth_rw_ma1_hi___addr___width 16
74#define reg_eth_rw_ma1_hi_offset 12
75
76/* Register rw_ga_lo, scope eth, type rw */
77#define reg_eth_rw_ga_lo___table___lsb 0
78#define reg_eth_rw_ga_lo___table___width 32
79#define reg_eth_rw_ga_lo_offset 16
80
81/* Register rw_ga_hi, scope eth, type rw */
82#define reg_eth_rw_ga_hi___table___lsb 0
83#define reg_eth_rw_ga_hi___table___width 32
84#define reg_eth_rw_ga_hi_offset 20
85
86/* Register rw_gen_ctrl, scope eth, type rw */
87#define reg_eth_rw_gen_ctrl___en___lsb 0
88#define reg_eth_rw_gen_ctrl___en___width 1
89#define reg_eth_rw_gen_ctrl___en___bit 0
90#define reg_eth_rw_gen_ctrl___phy___lsb 1
91#define reg_eth_rw_gen_ctrl___phy___width 2
92#define reg_eth_rw_gen_ctrl___protocol___lsb 3
93#define reg_eth_rw_gen_ctrl___protocol___width 1
94#define reg_eth_rw_gen_ctrl___protocol___bit 3
95#define reg_eth_rw_gen_ctrl___loopback___lsb 4
96#define reg_eth_rw_gen_ctrl___loopback___width 1
97#define reg_eth_rw_gen_ctrl___loopback___bit 4
98#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5
99#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1
100#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5
101#define reg_eth_rw_gen_ctrl_offset 24
102
103/* Register rw_rec_ctrl, scope eth, type rw */
104#define reg_eth_rw_rec_ctrl___ma0___lsb 0
105#define reg_eth_rw_rec_ctrl___ma0___width 1
106#define reg_eth_rw_rec_ctrl___ma0___bit 0
107#define reg_eth_rw_rec_ctrl___ma1___lsb 1
108#define reg_eth_rw_rec_ctrl___ma1___width 1
109#define reg_eth_rw_rec_ctrl___ma1___bit 1
110#define reg_eth_rw_rec_ctrl___individual___lsb 2
111#define reg_eth_rw_rec_ctrl___individual___width 1
112#define reg_eth_rw_rec_ctrl___individual___bit 2
113#define reg_eth_rw_rec_ctrl___broadcast___lsb 3
114#define reg_eth_rw_rec_ctrl___broadcast___width 1
115#define reg_eth_rw_rec_ctrl___broadcast___bit 3
116#define reg_eth_rw_rec_ctrl___undersize___lsb 4
117#define reg_eth_rw_rec_ctrl___undersize___width 1
118#define reg_eth_rw_rec_ctrl___undersize___bit 4
119#define reg_eth_rw_rec_ctrl___oversize___lsb 5
120#define reg_eth_rw_rec_ctrl___oversize___width 1
121#define reg_eth_rw_rec_ctrl___oversize___bit 5
122#define reg_eth_rw_rec_ctrl___bad_crc___lsb 6
123#define reg_eth_rw_rec_ctrl___bad_crc___width 1
124#define reg_eth_rw_rec_ctrl___bad_crc___bit 6
125#define reg_eth_rw_rec_ctrl___duplex___lsb 7
126#define reg_eth_rw_rec_ctrl___duplex___width 1
127#define reg_eth_rw_rec_ctrl___duplex___bit 7
128#define reg_eth_rw_rec_ctrl___max_size___lsb 8
129#define reg_eth_rw_rec_ctrl___max_size___width 1
130#define reg_eth_rw_rec_ctrl___max_size___bit 8
131#define reg_eth_rw_rec_ctrl_offset 28
132
133/* Register rw_tr_ctrl, scope eth, type rw */
134#define reg_eth_rw_tr_ctrl___crc___lsb 0
135#define reg_eth_rw_tr_ctrl___crc___width 1
136#define reg_eth_rw_tr_ctrl___crc___bit 0
137#define reg_eth_rw_tr_ctrl___pad___lsb 1
138#define reg_eth_rw_tr_ctrl___pad___width 1
139#define reg_eth_rw_tr_ctrl___pad___bit 1
140#define reg_eth_rw_tr_ctrl___retry___lsb 2
141#define reg_eth_rw_tr_ctrl___retry___width 1
142#define reg_eth_rw_tr_ctrl___retry___bit 2
143#define reg_eth_rw_tr_ctrl___ignore_col___lsb 3
144#define reg_eth_rw_tr_ctrl___ignore_col___width 1
145#define reg_eth_rw_tr_ctrl___ignore_col___bit 3
146#define reg_eth_rw_tr_ctrl___cancel___lsb 4
147#define reg_eth_rw_tr_ctrl___cancel___width 1
148#define reg_eth_rw_tr_ctrl___cancel___bit 4
149#define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5
150#define reg_eth_rw_tr_ctrl___hsh_delay___width 1
151#define reg_eth_rw_tr_ctrl___hsh_delay___bit 5
152#define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6
153#define reg_eth_rw_tr_ctrl___ignore_crs___width 1
154#define reg_eth_rw_tr_ctrl___ignore_crs___bit 6
155#define reg_eth_rw_tr_ctrl_offset 32
156
157/* Register rw_clr_err, scope eth, type rw */
158#define reg_eth_rw_clr_err___clr___lsb 0
159#define reg_eth_rw_clr_err___clr___width 1
160#define reg_eth_rw_clr_err___clr___bit 0
161#define reg_eth_rw_clr_err_offset 36
162
163/* Register rw_mgm_ctrl, scope eth, type rw */
164#define reg_eth_rw_mgm_ctrl___mdio___lsb 0
165#define reg_eth_rw_mgm_ctrl___mdio___width 1
166#define reg_eth_rw_mgm_ctrl___mdio___bit 0
167#define reg_eth_rw_mgm_ctrl___mdoe___lsb 1
168#define reg_eth_rw_mgm_ctrl___mdoe___width 1
169#define reg_eth_rw_mgm_ctrl___mdoe___bit 1
170#define reg_eth_rw_mgm_ctrl___mdc___lsb 2
171#define reg_eth_rw_mgm_ctrl___mdc___width 1
172#define reg_eth_rw_mgm_ctrl___mdc___bit 2
173#define reg_eth_rw_mgm_ctrl___phyclk___lsb 3
174#define reg_eth_rw_mgm_ctrl___phyclk___width 1
175#define reg_eth_rw_mgm_ctrl___phyclk___bit 3
176#define reg_eth_rw_mgm_ctrl___txdata___lsb 4
177#define reg_eth_rw_mgm_ctrl___txdata___width 4
178#define reg_eth_rw_mgm_ctrl___txen___lsb 8
179#define reg_eth_rw_mgm_ctrl___txen___width 1
180#define reg_eth_rw_mgm_ctrl___txen___bit 8
181#define reg_eth_rw_mgm_ctrl_offset 40
182
183/* Register r_stat, scope eth, type r */
184#define reg_eth_r_stat___mdio___lsb 0
185#define reg_eth_r_stat___mdio___width 1
186#define reg_eth_r_stat___mdio___bit 0
187#define reg_eth_r_stat___exc_col___lsb 1
188#define reg_eth_r_stat___exc_col___width 1
189#define reg_eth_r_stat___exc_col___bit 1
190#define reg_eth_r_stat___urun___lsb 2
191#define reg_eth_r_stat___urun___width 1
192#define reg_eth_r_stat___urun___bit 2
193#define reg_eth_r_stat___phyclk___lsb 3
194#define reg_eth_r_stat___phyclk___width 1
195#define reg_eth_r_stat___phyclk___bit 3
196#define reg_eth_r_stat___txdata___lsb 4
197#define reg_eth_r_stat___txdata___width 4
198#define reg_eth_r_stat___txen___lsb 8
199#define reg_eth_r_stat___txen___width 1
200#define reg_eth_r_stat___txen___bit 8
201#define reg_eth_r_stat___col___lsb 9
202#define reg_eth_r_stat___col___width 1
203#define reg_eth_r_stat___col___bit 9
204#define reg_eth_r_stat___crs___lsb 10
205#define reg_eth_r_stat___crs___width 1
206#define reg_eth_r_stat___crs___bit 10
207#define reg_eth_r_stat___txclk___lsb 11
208#define reg_eth_r_stat___txclk___width 1
209#define reg_eth_r_stat___txclk___bit 11
210#define reg_eth_r_stat___rxdata___lsb 12
211#define reg_eth_r_stat___rxdata___width 4
212#define reg_eth_r_stat___rxer___lsb 16
213#define reg_eth_r_stat___rxer___width 1
214#define reg_eth_r_stat___rxer___bit 16
215#define reg_eth_r_stat___rxdv___lsb 17
216#define reg_eth_r_stat___rxdv___width 1
217#define reg_eth_r_stat___rxdv___bit 17
218#define reg_eth_r_stat___rxclk___lsb 18
219#define reg_eth_r_stat___rxclk___width 1
220#define reg_eth_r_stat___rxclk___bit 18
221#define reg_eth_r_stat_offset 44
222
223/* Register rs_rec_cnt, scope eth, type rs */
224#define reg_eth_rs_rec_cnt___crc_err___lsb 0
225#define reg_eth_rs_rec_cnt___crc_err___width 8
226#define reg_eth_rs_rec_cnt___align_err___lsb 8
227#define reg_eth_rs_rec_cnt___align_err___width 8
228#define reg_eth_rs_rec_cnt___oversize___lsb 16
229#define reg_eth_rs_rec_cnt___oversize___width 8
230#define reg_eth_rs_rec_cnt___congestion___lsb 24
231#define reg_eth_rs_rec_cnt___congestion___width 8
232#define reg_eth_rs_rec_cnt_offset 48
233
234/* Register r_rec_cnt, scope eth, type r */
235#define reg_eth_r_rec_cnt___crc_err___lsb 0
236#define reg_eth_r_rec_cnt___crc_err___width 8
237#define reg_eth_r_rec_cnt___align_err___lsb 8
238#define reg_eth_r_rec_cnt___align_err___width 8
239#define reg_eth_r_rec_cnt___oversize___lsb 16
240#define reg_eth_r_rec_cnt___oversize___width 8
241#define reg_eth_r_rec_cnt___congestion___lsb 24
242#define reg_eth_r_rec_cnt___congestion___width 8
243#define reg_eth_r_rec_cnt_offset 52
244
245/* Register rs_tr_cnt, scope eth, type rs */
246#define reg_eth_rs_tr_cnt___single_col___lsb 0
247#define reg_eth_rs_tr_cnt___single_col___width 8
248#define reg_eth_rs_tr_cnt___mult_col___lsb 8
249#define reg_eth_rs_tr_cnt___mult_col___width 8
250#define reg_eth_rs_tr_cnt___late_col___lsb 16
251#define reg_eth_rs_tr_cnt___late_col___width 8
252#define reg_eth_rs_tr_cnt___deferred___lsb 24
253#define reg_eth_rs_tr_cnt___deferred___width 8
254#define reg_eth_rs_tr_cnt_offset 56
255
256/* Register r_tr_cnt, scope eth, type r */
257#define reg_eth_r_tr_cnt___single_col___lsb 0
258#define reg_eth_r_tr_cnt___single_col___width 8
259#define reg_eth_r_tr_cnt___mult_col___lsb 8
260#define reg_eth_r_tr_cnt___mult_col___width 8
261#define reg_eth_r_tr_cnt___late_col___lsb 16
262#define reg_eth_r_tr_cnt___late_col___width 8
263#define reg_eth_r_tr_cnt___deferred___lsb 24
264#define reg_eth_r_tr_cnt___deferred___width 8
265#define reg_eth_r_tr_cnt_offset 60
266
267/* Register rs_phy_cnt, scope eth, type rs */
268#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0
269#define reg_eth_rs_phy_cnt___carrier_loss___width 8
270#define reg_eth_rs_phy_cnt___sqe_err___lsb 8
271#define reg_eth_rs_phy_cnt___sqe_err___width 8
272#define reg_eth_rs_phy_cnt_offset 64
273
274/* Register r_phy_cnt, scope eth, type r */
275#define reg_eth_r_phy_cnt___carrier_loss___lsb 0
276#define reg_eth_r_phy_cnt___carrier_loss___width 8
277#define reg_eth_r_phy_cnt___sqe_err___lsb 8
278#define reg_eth_r_phy_cnt___sqe_err___width 8
279#define reg_eth_r_phy_cnt_offset 68
280
281/* Register rw_test_ctrl, scope eth, type rw */
282#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0
283#define reg_eth_rw_test_ctrl___snmp_inc___width 1
284#define reg_eth_rw_test_ctrl___snmp_inc___bit 0
285#define reg_eth_rw_test_ctrl___snmp___lsb 1
286#define reg_eth_rw_test_ctrl___snmp___width 1
287#define reg_eth_rw_test_ctrl___snmp___bit 1
288#define reg_eth_rw_test_ctrl___backoff___lsb 2
289#define reg_eth_rw_test_ctrl___backoff___width 1
290#define reg_eth_rw_test_ctrl___backoff___bit 2
291#define reg_eth_rw_test_ctrl_offset 72
292
293/* Register rw_intr_mask, scope eth, type rw */
294#define reg_eth_rw_intr_mask___crc___lsb 0
295#define reg_eth_rw_intr_mask___crc___width 1
296#define reg_eth_rw_intr_mask___crc___bit 0
297#define reg_eth_rw_intr_mask___align___lsb 1
298#define reg_eth_rw_intr_mask___align___width 1
299#define reg_eth_rw_intr_mask___align___bit 1
300#define reg_eth_rw_intr_mask___oversize___lsb 2
301#define reg_eth_rw_intr_mask___oversize___width 1
302#define reg_eth_rw_intr_mask___oversize___bit 2
303#define reg_eth_rw_intr_mask___congestion___lsb 3
304#define reg_eth_rw_intr_mask___congestion___width 1
305#define reg_eth_rw_intr_mask___congestion___bit 3
306#define reg_eth_rw_intr_mask___single_col___lsb 4
307#define reg_eth_rw_intr_mask___single_col___width 1
308#define reg_eth_rw_intr_mask___single_col___bit 4
309#define reg_eth_rw_intr_mask___mult_col___lsb 5
310#define reg_eth_rw_intr_mask___mult_col___width 1
311#define reg_eth_rw_intr_mask___mult_col___bit 5
312#define reg_eth_rw_intr_mask___late_col___lsb 6
313#define reg_eth_rw_intr_mask___late_col___width 1
314#define reg_eth_rw_intr_mask___late_col___bit 6
315#define reg_eth_rw_intr_mask___deferred___lsb 7
316#define reg_eth_rw_intr_mask___deferred___width 1
317#define reg_eth_rw_intr_mask___deferred___bit 7
318#define reg_eth_rw_intr_mask___carrier_loss___lsb 8
319#define reg_eth_rw_intr_mask___carrier_loss___width 1
320#define reg_eth_rw_intr_mask___carrier_loss___bit 8
321#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9
322#define reg_eth_rw_intr_mask___sqe_test_err___width 1
323#define reg_eth_rw_intr_mask___sqe_test_err___bit 9
324#define reg_eth_rw_intr_mask___orun___lsb 10
325#define reg_eth_rw_intr_mask___orun___width 1
326#define reg_eth_rw_intr_mask___orun___bit 10
327#define reg_eth_rw_intr_mask___urun___lsb 11
328#define reg_eth_rw_intr_mask___urun___width 1
329#define reg_eth_rw_intr_mask___urun___bit 11
330#define reg_eth_rw_intr_mask___excessive_col___lsb 12
331#define reg_eth_rw_intr_mask___excessive_col___width 1
332#define reg_eth_rw_intr_mask___excessive_col___bit 12
333#define reg_eth_rw_intr_mask___mdio___lsb 13
334#define reg_eth_rw_intr_mask___mdio___width 1
335#define reg_eth_rw_intr_mask___mdio___bit 13
336#define reg_eth_rw_intr_mask_offset 76
337
338/* Register rw_ack_intr, scope eth, type rw */
339#define reg_eth_rw_ack_intr___crc___lsb 0
340#define reg_eth_rw_ack_intr___crc___width 1
341#define reg_eth_rw_ack_intr___crc___bit 0
342#define reg_eth_rw_ack_intr___align___lsb 1
343#define reg_eth_rw_ack_intr___align___width 1
344#define reg_eth_rw_ack_intr___align___bit 1
345#define reg_eth_rw_ack_intr___oversize___lsb 2
346#define reg_eth_rw_ack_intr___oversize___width 1
347#define reg_eth_rw_ack_intr___oversize___bit 2
348#define reg_eth_rw_ack_intr___congestion___lsb 3
349#define reg_eth_rw_ack_intr___congestion___width 1
350#define reg_eth_rw_ack_intr___congestion___bit 3
351#define reg_eth_rw_ack_intr___single_col___lsb 4
352#define reg_eth_rw_ack_intr___single_col___width 1
353#define reg_eth_rw_ack_intr___single_col___bit 4
354#define reg_eth_rw_ack_intr___mult_col___lsb 5
355#define reg_eth_rw_ack_intr___mult_col___width 1
356#define reg_eth_rw_ack_intr___mult_col___bit 5
357#define reg_eth_rw_ack_intr___late_col___lsb 6
358#define reg_eth_rw_ack_intr___late_col___width 1
359#define reg_eth_rw_ack_intr___late_col___bit 6
360#define reg_eth_rw_ack_intr___deferred___lsb 7
361#define reg_eth_rw_ack_intr___deferred___width 1
362#define reg_eth_rw_ack_intr___deferred___bit 7
363#define reg_eth_rw_ack_intr___carrier_loss___lsb 8
364#define reg_eth_rw_ack_intr___carrier_loss___width 1
365#define reg_eth_rw_ack_intr___carrier_loss___bit 8
366#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9
367#define reg_eth_rw_ack_intr___sqe_test_err___width 1
368#define reg_eth_rw_ack_intr___sqe_test_err___bit 9
369#define reg_eth_rw_ack_intr___orun___lsb 10
370#define reg_eth_rw_ack_intr___orun___width 1
371#define reg_eth_rw_ack_intr___orun___bit 10
372#define reg_eth_rw_ack_intr___urun___lsb 11
373#define reg_eth_rw_ack_intr___urun___width 1
374#define reg_eth_rw_ack_intr___urun___bit 11
375#define reg_eth_rw_ack_intr___excessive_col___lsb 12
376#define reg_eth_rw_ack_intr___excessive_col___width 1
377#define reg_eth_rw_ack_intr___excessive_col___bit 12
378#define reg_eth_rw_ack_intr___mdio___lsb 13
379#define reg_eth_rw_ack_intr___mdio___width 1
380#define reg_eth_rw_ack_intr___mdio___bit 13
381#define reg_eth_rw_ack_intr_offset 80
382
383/* Register r_intr, scope eth, type r */
384#define reg_eth_r_intr___crc___lsb 0
385#define reg_eth_r_intr___crc___width 1
386#define reg_eth_r_intr___crc___bit 0
387#define reg_eth_r_intr___align___lsb 1
388#define reg_eth_r_intr___align___width 1
389#define reg_eth_r_intr___align___bit 1
390#define reg_eth_r_intr___oversize___lsb 2
391#define reg_eth_r_intr___oversize___width 1
392#define reg_eth_r_intr___oversize___bit 2
393#define reg_eth_r_intr___congestion___lsb 3
394#define reg_eth_r_intr___congestion___width 1
395#define reg_eth_r_intr___congestion___bit 3
396#define reg_eth_r_intr___single_col___lsb 4
397#define reg_eth_r_intr___single_col___width 1
398#define reg_eth_r_intr___single_col___bit 4
399#define reg_eth_r_intr___mult_col___lsb 5
400#define reg_eth_r_intr___mult_col___width 1
401#define reg_eth_r_intr___mult_col___bit 5
402#define reg_eth_r_intr___late_col___lsb 6
403#define reg_eth_r_intr___late_col___width 1
404#define reg_eth_r_intr___late_col___bit 6
405#define reg_eth_r_intr___deferred___lsb 7
406#define reg_eth_r_intr___deferred___width 1
407#define reg_eth_r_intr___deferred___bit 7
408#define reg_eth_r_intr___carrier_loss___lsb 8
409#define reg_eth_r_intr___carrier_loss___width 1
410#define reg_eth_r_intr___carrier_loss___bit 8
411#define reg_eth_r_intr___sqe_test_err___lsb 9
412#define reg_eth_r_intr___sqe_test_err___width 1
413#define reg_eth_r_intr___sqe_test_err___bit 9
414#define reg_eth_r_intr___orun___lsb 10
415#define reg_eth_r_intr___orun___width 1
416#define reg_eth_r_intr___orun___bit 10
417#define reg_eth_r_intr___urun___lsb 11
418#define reg_eth_r_intr___urun___width 1
419#define reg_eth_r_intr___urun___bit 11
420#define reg_eth_r_intr___excessive_col___lsb 12
421#define reg_eth_r_intr___excessive_col___width 1
422#define reg_eth_r_intr___excessive_col___bit 12
423#define reg_eth_r_intr___mdio___lsb 13
424#define reg_eth_r_intr___mdio___width 1
425#define reg_eth_r_intr___mdio___bit 13
426#define reg_eth_r_intr_offset 84
427
428/* Register r_masked_intr, scope eth, type r */
429#define reg_eth_r_masked_intr___crc___lsb 0
430#define reg_eth_r_masked_intr___crc___width 1
431#define reg_eth_r_masked_intr___crc___bit 0
432#define reg_eth_r_masked_intr___align___lsb 1
433#define reg_eth_r_masked_intr___align___width 1
434#define reg_eth_r_masked_intr___align___bit 1
435#define reg_eth_r_masked_intr___oversize___lsb 2
436#define reg_eth_r_masked_intr___oversize___width 1
437#define reg_eth_r_masked_intr___oversize___bit 2
438#define reg_eth_r_masked_intr___congestion___lsb 3
439#define reg_eth_r_masked_intr___congestion___width 1
440#define reg_eth_r_masked_intr___congestion___bit 3
441#define reg_eth_r_masked_intr___single_col___lsb 4
442#define reg_eth_r_masked_intr___single_col___width 1
443#define reg_eth_r_masked_intr___single_col___bit 4
444#define reg_eth_r_masked_intr___mult_col___lsb 5
445#define reg_eth_r_masked_intr___mult_col___width 1
446#define reg_eth_r_masked_intr___mult_col___bit 5
447#define reg_eth_r_masked_intr___late_col___lsb 6
448#define reg_eth_r_masked_intr___late_col___width 1
449#define reg_eth_r_masked_intr___late_col___bit 6
450#define reg_eth_r_masked_intr___deferred___lsb 7
451#define reg_eth_r_masked_intr___deferred___width 1
452#define reg_eth_r_masked_intr___deferred___bit 7
453#define reg_eth_r_masked_intr___carrier_loss___lsb 8
454#define reg_eth_r_masked_intr___carrier_loss___width 1
455#define reg_eth_r_masked_intr___carrier_loss___bit 8
456#define reg_eth_r_masked_intr___sqe_test_err___lsb 9
457#define reg_eth_r_masked_intr___sqe_test_err___width 1
458#define reg_eth_r_masked_intr___sqe_test_err___bit 9
459#define reg_eth_r_masked_intr___orun___lsb 10
460#define reg_eth_r_masked_intr___orun___width 1
461#define reg_eth_r_masked_intr___orun___bit 10
462#define reg_eth_r_masked_intr___urun___lsb 11
463#define reg_eth_r_masked_intr___urun___width 1
464#define reg_eth_r_masked_intr___urun___bit 11
465#define reg_eth_r_masked_intr___excessive_col___lsb 12
466#define reg_eth_r_masked_intr___excessive_col___width 1
467#define reg_eth_r_masked_intr___excessive_col___bit 12
468#define reg_eth_r_masked_intr___mdio___lsb 13
469#define reg_eth_r_masked_intr___mdio___width 1
470#define reg_eth_r_masked_intr___mdio___bit 13
471#define reg_eth_r_masked_intr_offset 88
472
473
474/* Constants */
475#define regk_eth_discard 0x00000000
476#define regk_eth_ether 0x00000000
477#define regk_eth_full 0x00000001
478#define regk_eth_half 0x00000000
479#define regk_eth_hsh 0x00000001
480#define regk_eth_mii 0x00000001
481#define regk_eth_mii_clk 0x00000000
482#define regk_eth_mii_rec 0x00000002
483#define regk_eth_no 0x00000000
484#define regk_eth_rec 0x00000001
485#define regk_eth_rw_ga_hi_default 0x00000000
486#define regk_eth_rw_ga_lo_default 0x00000000
487#define regk_eth_rw_gen_ctrl_default 0x00000000
488#define regk_eth_rw_intr_mask_default 0x00000000
489#define regk_eth_rw_ma0_hi_default 0x00000000
490#define regk_eth_rw_ma0_lo_default 0x00000000
491#define regk_eth_rw_ma1_hi_default 0x00000000
492#define regk_eth_rw_ma1_lo_default 0x00000000
493#define regk_eth_rw_mgm_ctrl_default 0x00000000
494#define regk_eth_rw_test_ctrl_default 0x00000000
495#define regk_eth_size1518 0x00000000
496#define regk_eth_size1522 0x00000001
497#define regk_eth_yes 0x00000001
498#endif /* __eth_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h
new file mode 100644
index 000000000000..35356bc08629
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h
@@ -0,0 +1,276 @@
1#ifndef __gio_defs_asm_h
2#define __gio_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/gio/rtl/gio_regs.r
7 * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
8 * last modfied: Mon Apr 11 16:07:47 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r
11 * id: $Id: gio_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_pa_dout, scope gio, type rw */
57#define reg_gio_rw_pa_dout___data___lsb 0
58#define reg_gio_rw_pa_dout___data___width 8
59#define reg_gio_rw_pa_dout_offset 0
60
61/* Register r_pa_din, scope gio, type r */
62#define reg_gio_r_pa_din___data___lsb 0
63#define reg_gio_r_pa_din___data___width 8
64#define reg_gio_r_pa_din_offset 4
65
66/* Register rw_pa_oe, scope gio, type rw */
67#define reg_gio_rw_pa_oe___oe___lsb 0
68#define reg_gio_rw_pa_oe___oe___width 8
69#define reg_gio_rw_pa_oe_offset 8
70
71/* Register rw_intr_cfg, scope gio, type rw */
72#define reg_gio_rw_intr_cfg___pa0___lsb 0
73#define reg_gio_rw_intr_cfg___pa0___width 3
74#define reg_gio_rw_intr_cfg___pa1___lsb 3
75#define reg_gio_rw_intr_cfg___pa1___width 3
76#define reg_gio_rw_intr_cfg___pa2___lsb 6
77#define reg_gio_rw_intr_cfg___pa2___width 3
78#define reg_gio_rw_intr_cfg___pa3___lsb 9
79#define reg_gio_rw_intr_cfg___pa3___width 3
80#define reg_gio_rw_intr_cfg___pa4___lsb 12
81#define reg_gio_rw_intr_cfg___pa4___width 3
82#define reg_gio_rw_intr_cfg___pa5___lsb 15
83#define reg_gio_rw_intr_cfg___pa5___width 3
84#define reg_gio_rw_intr_cfg___pa6___lsb 18
85#define reg_gio_rw_intr_cfg___pa6___width 3
86#define reg_gio_rw_intr_cfg___pa7___lsb 21
87#define reg_gio_rw_intr_cfg___pa7___width 3
88#define reg_gio_rw_intr_cfg_offset 12
89
90/* Register rw_intr_mask, scope gio, type rw */
91#define reg_gio_rw_intr_mask___pa0___lsb 0
92#define reg_gio_rw_intr_mask___pa0___width 1
93#define reg_gio_rw_intr_mask___pa0___bit 0
94#define reg_gio_rw_intr_mask___pa1___lsb 1
95#define reg_gio_rw_intr_mask___pa1___width 1
96#define reg_gio_rw_intr_mask___pa1___bit 1
97#define reg_gio_rw_intr_mask___pa2___lsb 2
98#define reg_gio_rw_intr_mask___pa2___width 1
99#define reg_gio_rw_intr_mask___pa2___bit 2
100#define reg_gio_rw_intr_mask___pa3___lsb 3
101#define reg_gio_rw_intr_mask___pa3___width 1
102#define reg_gio_rw_intr_mask___pa3___bit 3
103#define reg_gio_rw_intr_mask___pa4___lsb 4
104#define reg_gio_rw_intr_mask___pa4___width 1
105#define reg_gio_rw_intr_mask___pa4___bit 4
106#define reg_gio_rw_intr_mask___pa5___lsb 5
107#define reg_gio_rw_intr_mask___pa5___width 1
108#define reg_gio_rw_intr_mask___pa5___bit 5
109#define reg_gio_rw_intr_mask___pa6___lsb 6
110#define reg_gio_rw_intr_mask___pa6___width 1
111#define reg_gio_rw_intr_mask___pa6___bit 6
112#define reg_gio_rw_intr_mask___pa7___lsb 7
113#define reg_gio_rw_intr_mask___pa7___width 1
114#define reg_gio_rw_intr_mask___pa7___bit 7
115#define reg_gio_rw_intr_mask_offset 16
116
117/* Register rw_ack_intr, scope gio, type rw */
118#define reg_gio_rw_ack_intr___pa0___lsb 0
119#define reg_gio_rw_ack_intr___pa0___width 1
120#define reg_gio_rw_ack_intr___pa0___bit 0
121#define reg_gio_rw_ack_intr___pa1___lsb 1
122#define reg_gio_rw_ack_intr___pa1___width 1
123#define reg_gio_rw_ack_intr___pa1___bit 1
124#define reg_gio_rw_ack_intr___pa2___lsb 2
125#define reg_gio_rw_ack_intr___pa2___width 1
126#define reg_gio_rw_ack_intr___pa2___bit 2
127#define reg_gio_rw_ack_intr___pa3___lsb 3
128#define reg_gio_rw_ack_intr___pa3___width 1
129#define reg_gio_rw_ack_intr___pa3___bit 3
130#define reg_gio_rw_ack_intr___pa4___lsb 4
131#define reg_gio_rw_ack_intr___pa4___width 1
132#define reg_gio_rw_ack_intr___pa4___bit 4
133#define reg_gio_rw_ack_intr___pa5___lsb 5
134#define reg_gio_rw_ack_intr___pa5___width 1
135#define reg_gio_rw_ack_intr___pa5___bit 5
136#define reg_gio_rw_ack_intr___pa6___lsb 6
137#define reg_gio_rw_ack_intr___pa6___width 1
138#define reg_gio_rw_ack_intr___pa6___bit 6
139#define reg_gio_rw_ack_intr___pa7___lsb 7
140#define reg_gio_rw_ack_intr___pa7___width 1
141#define reg_gio_rw_ack_intr___pa7___bit 7
142#define reg_gio_rw_ack_intr_offset 20
143
144/* Register r_intr, scope gio, type r */
145#define reg_gio_r_intr___pa0___lsb 0
146#define reg_gio_r_intr___pa0___width 1
147#define reg_gio_r_intr___pa0___bit 0
148#define reg_gio_r_intr___pa1___lsb 1
149#define reg_gio_r_intr___pa1___width 1
150#define reg_gio_r_intr___pa1___bit 1
151#define reg_gio_r_intr___pa2___lsb 2
152#define reg_gio_r_intr___pa2___width 1
153#define reg_gio_r_intr___pa2___bit 2
154#define reg_gio_r_intr___pa3___lsb 3
155#define reg_gio_r_intr___pa3___width 1
156#define reg_gio_r_intr___pa3___bit 3
157#define reg_gio_r_intr___pa4___lsb 4
158#define reg_gio_r_intr___pa4___width 1
159#define reg_gio_r_intr___pa4___bit 4
160#define reg_gio_r_intr___pa5___lsb 5
161#define reg_gio_r_intr___pa5___width 1
162#define reg_gio_r_intr___pa5___bit 5
163#define reg_gio_r_intr___pa6___lsb 6
164#define reg_gio_r_intr___pa6___width 1
165#define reg_gio_r_intr___pa6___bit 6
166#define reg_gio_r_intr___pa7___lsb 7
167#define reg_gio_r_intr___pa7___width 1
168#define reg_gio_r_intr___pa7___bit 7
169#define reg_gio_r_intr_offset 24
170
171/* Register r_masked_intr, scope gio, type r */
172#define reg_gio_r_masked_intr___pa0___lsb 0
173#define reg_gio_r_masked_intr___pa0___width 1
174#define reg_gio_r_masked_intr___pa0___bit 0
175#define reg_gio_r_masked_intr___pa1___lsb 1
176#define reg_gio_r_masked_intr___pa1___width 1
177#define reg_gio_r_masked_intr___pa1___bit 1
178#define reg_gio_r_masked_intr___pa2___lsb 2
179#define reg_gio_r_masked_intr___pa2___width 1
180#define reg_gio_r_masked_intr___pa2___bit 2
181#define reg_gio_r_masked_intr___pa3___lsb 3
182#define reg_gio_r_masked_intr___pa3___width 1
183#define reg_gio_r_masked_intr___pa3___bit 3
184#define reg_gio_r_masked_intr___pa4___lsb 4
185#define reg_gio_r_masked_intr___pa4___width 1
186#define reg_gio_r_masked_intr___pa4___bit 4
187#define reg_gio_r_masked_intr___pa5___lsb 5
188#define reg_gio_r_masked_intr___pa5___width 1
189#define reg_gio_r_masked_intr___pa5___bit 5
190#define reg_gio_r_masked_intr___pa6___lsb 6
191#define reg_gio_r_masked_intr___pa6___width 1
192#define reg_gio_r_masked_intr___pa6___bit 6
193#define reg_gio_r_masked_intr___pa7___lsb 7
194#define reg_gio_r_masked_intr___pa7___width 1
195#define reg_gio_r_masked_intr___pa7___bit 7
196#define reg_gio_r_masked_intr_offset 28
197
198/* Register rw_pb_dout, scope gio, type rw */
199#define reg_gio_rw_pb_dout___data___lsb 0
200#define reg_gio_rw_pb_dout___data___width 18
201#define reg_gio_rw_pb_dout_offset 32
202
203/* Register r_pb_din, scope gio, type r */
204#define reg_gio_r_pb_din___data___lsb 0
205#define reg_gio_r_pb_din___data___width 18
206#define reg_gio_r_pb_din_offset 36
207
208/* Register rw_pb_oe, scope gio, type rw */
209#define reg_gio_rw_pb_oe___oe___lsb 0
210#define reg_gio_rw_pb_oe___oe___width 18
211#define reg_gio_rw_pb_oe_offset 40
212
213/* Register rw_pc_dout, scope gio, type rw */
214#define reg_gio_rw_pc_dout___data___lsb 0
215#define reg_gio_rw_pc_dout___data___width 18
216#define reg_gio_rw_pc_dout_offset 48
217
218/* Register r_pc_din, scope gio, type r */
219#define reg_gio_r_pc_din___data___lsb 0
220#define reg_gio_r_pc_din___data___width 18
221#define reg_gio_r_pc_din_offset 52
222
223/* Register rw_pc_oe, scope gio, type rw */
224#define reg_gio_rw_pc_oe___oe___lsb 0
225#define reg_gio_rw_pc_oe___oe___width 18
226#define reg_gio_rw_pc_oe_offset 56
227
228/* Register rw_pd_dout, scope gio, type rw */
229#define reg_gio_rw_pd_dout___data___lsb 0
230#define reg_gio_rw_pd_dout___data___width 18
231#define reg_gio_rw_pd_dout_offset 64
232
233/* Register r_pd_din, scope gio, type r */
234#define reg_gio_r_pd_din___data___lsb 0
235#define reg_gio_r_pd_din___data___width 18
236#define reg_gio_r_pd_din_offset 68
237
238/* Register rw_pd_oe, scope gio, type rw */
239#define reg_gio_rw_pd_oe___oe___lsb 0
240#define reg_gio_rw_pd_oe___oe___width 18
241#define reg_gio_rw_pd_oe_offset 72
242
243/* Register rw_pe_dout, scope gio, type rw */
244#define reg_gio_rw_pe_dout___data___lsb 0
245#define reg_gio_rw_pe_dout___data___width 18
246#define reg_gio_rw_pe_dout_offset 80
247
248/* Register r_pe_din, scope gio, type r */
249#define reg_gio_r_pe_din___data___lsb 0
250#define reg_gio_r_pe_din___data___width 18
251#define reg_gio_r_pe_din_offset 84
252
253/* Register rw_pe_oe, scope gio, type rw */
254#define reg_gio_rw_pe_oe___oe___lsb 0
255#define reg_gio_rw_pe_oe___oe___width 18
256#define reg_gio_rw_pe_oe_offset 88
257
258
259/* Constants */
260#define regk_gio_anyedge 0x00000007
261#define regk_gio_hi 0x00000001
262#define regk_gio_lo 0x00000002
263#define regk_gio_negedge 0x00000006
264#define regk_gio_no 0x00000000
265#define regk_gio_off 0x00000000
266#define regk_gio_posedge 0x00000005
267#define regk_gio_rw_intr_cfg_default 0x00000000
268#define regk_gio_rw_intr_mask_default 0x00000000
269#define regk_gio_rw_pa_oe_default 0x00000000
270#define regk_gio_rw_pb_oe_default 0x00000000
271#define regk_gio_rw_pc_oe_default 0x00000000
272#define regk_gio_rw_pd_oe_default 0x00000000
273#define regk_gio_rw_pe_oe_default 0x00000000
274#define regk_gio_set 0x00000003
275#define regk_gio_yes 0x00000001
276#endif /* __gio_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h b/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h
new file mode 100644
index 000000000000..c8315905c571
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h
@@ -0,0 +1,38 @@
1/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
2 from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
3version . */
4
5#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
6#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
7#define MEMARB_INTR_VECT 0x31
8#define GEN_IO_INTR_VECT 0x32
9#define IOP0_INTR_VECT 0x33
10#define IOP1_INTR_VECT 0x34
11#define IOP2_INTR_VECT 0x35
12#define IOP3_INTR_VECT 0x36
13#define DMA0_INTR_VECT 0x37
14#define DMA1_INTR_VECT 0x38
15#define DMA2_INTR_VECT 0x39
16#define DMA3_INTR_VECT 0x3a
17#define DMA4_INTR_VECT 0x3b
18#define DMA5_INTR_VECT 0x3c
19#define DMA6_INTR_VECT 0x3d
20#define DMA7_INTR_VECT 0x3e
21#define DMA8_INTR_VECT 0x3f
22#define DMA9_INTR_VECT 0x40
23#define ATA_INTR_VECT 0x41
24#define SSER0_INTR_VECT 0x42
25#define SSER1_INTR_VECT 0x43
26#define SER0_INTR_VECT 0x44
27#define SER1_INTR_VECT 0x45
28#define SER2_INTR_VECT 0x46
29#define SER3_INTR_VECT 0x47
30#define P21_INTR_VECT 0x48
31#define ETH0_INTR_VECT 0x49
32#define ETH1_INTR_VECT 0x4a
33#define TIMER_INTR_VECT 0x4b
34#define BIF_ARB_INTR_VECT 0x4c
35#define BIF_DMA_INTR_VECT 0x4d
36#define EXT_INTR_VECT 0x4e
37
38#endif
diff --git a/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h
new file mode 100644
index 000000000000..6df2a433b02d
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h
@@ -0,0 +1,355 @@
1#ifndef __intr_vect_defs_asm_h
2#define __intr_vect_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r
7 * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
8 * last modfied: Mon Apr 11 16:08:03 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
11 * id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_mask, scope intr_vect, type rw */
57#define reg_intr_vect_rw_mask___memarb___lsb 0
58#define reg_intr_vect_rw_mask___memarb___width 1
59#define reg_intr_vect_rw_mask___memarb___bit 0
60#define reg_intr_vect_rw_mask___gen_io___lsb 1
61#define reg_intr_vect_rw_mask___gen_io___width 1
62#define reg_intr_vect_rw_mask___gen_io___bit 1
63#define reg_intr_vect_rw_mask___iop0___lsb 2
64#define reg_intr_vect_rw_mask___iop0___width 1
65#define reg_intr_vect_rw_mask___iop0___bit 2
66#define reg_intr_vect_rw_mask___iop1___lsb 3
67#define reg_intr_vect_rw_mask___iop1___width 1
68#define reg_intr_vect_rw_mask___iop1___bit 3
69#define reg_intr_vect_rw_mask___iop2___lsb 4
70#define reg_intr_vect_rw_mask___iop2___width 1
71#define reg_intr_vect_rw_mask___iop2___bit 4
72#define reg_intr_vect_rw_mask___iop3___lsb 5
73#define reg_intr_vect_rw_mask___iop3___width 1
74#define reg_intr_vect_rw_mask___iop3___bit 5
75#define reg_intr_vect_rw_mask___dma0___lsb 6
76#define reg_intr_vect_rw_mask___dma0___width 1
77#define reg_intr_vect_rw_mask___dma0___bit 6
78#define reg_intr_vect_rw_mask___dma1___lsb 7
79#define reg_intr_vect_rw_mask___dma1___width 1
80#define reg_intr_vect_rw_mask___dma1___bit 7
81#define reg_intr_vect_rw_mask___dma2___lsb 8
82#define reg_intr_vect_rw_mask___dma2___width 1
83#define reg_intr_vect_rw_mask___dma2___bit 8
84#define reg_intr_vect_rw_mask___dma3___lsb 9
85#define reg_intr_vect_rw_mask___dma3___width 1
86#define reg_intr_vect_rw_mask___dma3___bit 9
87#define reg_intr_vect_rw_mask___dma4___lsb 10
88#define reg_intr_vect_rw_mask___dma4___width 1
89#define reg_intr_vect_rw_mask___dma4___bit 10
90#define reg_intr_vect_rw_mask___dma5___lsb 11
91#define reg_intr_vect_rw_mask___dma5___width 1
92#define reg_intr_vect_rw_mask___dma5___bit 11
93#define reg_intr_vect_rw_mask___dma6___lsb 12
94#define reg_intr_vect_rw_mask___dma6___width 1
95#define reg_intr_vect_rw_mask___dma6___bit 12
96#define reg_intr_vect_rw_mask___dma7___lsb 13
97#define reg_intr_vect_rw_mask___dma7___width 1
98#define reg_intr_vect_rw_mask___dma7___bit 13
99#define reg_intr_vect_rw_mask___dma8___lsb 14
100#define reg_intr_vect_rw_mask___dma8___width 1
101#define reg_intr_vect_rw_mask___dma8___bit 14
102#define reg_intr_vect_rw_mask___dma9___lsb 15
103#define reg_intr_vect_rw_mask___dma9___width 1
104#define reg_intr_vect_rw_mask___dma9___bit 15
105#define reg_intr_vect_rw_mask___ata___lsb 16
106#define reg_intr_vect_rw_mask___ata___width 1
107#define reg_intr_vect_rw_mask___ata___bit 16
108#define reg_intr_vect_rw_mask___sser0___lsb 17
109#define reg_intr_vect_rw_mask___sser0___width 1
110#define reg_intr_vect_rw_mask___sser0___bit 17
111#define reg_intr_vect_rw_mask___sser1___lsb 18
112#define reg_intr_vect_rw_mask___sser1___width 1
113#define reg_intr_vect_rw_mask___sser1___bit 18
114#define reg_intr_vect_rw_mask___ser0___lsb 19
115#define reg_intr_vect_rw_mask___ser0___width 1
116#define reg_intr_vect_rw_mask___ser0___bit 19
117#define reg_intr_vect_rw_mask___ser1___lsb 20
118#define reg_intr_vect_rw_mask___ser1___width 1
119#define reg_intr_vect_rw_mask___ser1___bit 20
120#define reg_intr_vect_rw_mask___ser2___lsb 21
121#define reg_intr_vect_rw_mask___ser2___width 1
122#define reg_intr_vect_rw_mask___ser2___bit 21
123#define reg_intr_vect_rw_mask___ser3___lsb 22
124#define reg_intr_vect_rw_mask___ser3___width 1
125#define reg_intr_vect_rw_mask___ser3___bit 22
126#define reg_intr_vect_rw_mask___p21___lsb 23
127#define reg_intr_vect_rw_mask___p21___width 1
128#define reg_intr_vect_rw_mask___p21___bit 23
129#define reg_intr_vect_rw_mask___eth0___lsb 24
130#define reg_intr_vect_rw_mask___eth0___width 1
131#define reg_intr_vect_rw_mask___eth0___bit 24
132#define reg_intr_vect_rw_mask___eth1___lsb 25
133#define reg_intr_vect_rw_mask___eth1___width 1
134#define reg_intr_vect_rw_mask___eth1___bit 25
135#define reg_intr_vect_rw_mask___timer___lsb 26
136#define reg_intr_vect_rw_mask___timer___width 1
137#define reg_intr_vect_rw_mask___timer___bit 26
138#define reg_intr_vect_rw_mask___bif_arb___lsb 27
139#define reg_intr_vect_rw_mask___bif_arb___width 1
140#define reg_intr_vect_rw_mask___bif_arb___bit 27
141#define reg_intr_vect_rw_mask___bif_dma___lsb 28
142#define reg_intr_vect_rw_mask___bif_dma___width 1
143#define reg_intr_vect_rw_mask___bif_dma___bit 28
144#define reg_intr_vect_rw_mask___ext___lsb 29
145#define reg_intr_vect_rw_mask___ext___width 1
146#define reg_intr_vect_rw_mask___ext___bit 29
147#define reg_intr_vect_rw_mask_offset 0
148
149/* Register r_vect, scope intr_vect, type r */
150#define reg_intr_vect_r_vect___memarb___lsb 0
151#define reg_intr_vect_r_vect___memarb___width 1
152#define reg_intr_vect_r_vect___memarb___bit 0
153#define reg_intr_vect_r_vect___gen_io___lsb 1
154#define reg_intr_vect_r_vect___gen_io___width 1
155#define reg_intr_vect_r_vect___gen_io___bit 1
156#define reg_intr_vect_r_vect___iop0___lsb 2
157#define reg_intr_vect_r_vect___iop0___width 1
158#define reg_intr_vect_r_vect___iop0___bit 2
159#define reg_intr_vect_r_vect___iop1___lsb 3
160#define reg_intr_vect_r_vect___iop1___width 1
161#define reg_intr_vect_r_vect___iop1___bit 3
162#define reg_intr_vect_r_vect___iop2___lsb 4
163#define reg_intr_vect_r_vect___iop2___width 1
164#define reg_intr_vect_r_vect___iop2___bit 4
165#define reg_intr_vect_r_vect___iop3___lsb 5
166#define reg_intr_vect_r_vect___iop3___width 1
167#define reg_intr_vect_r_vect___iop3___bit 5
168#define reg_intr_vect_r_vect___dma0___lsb 6
169#define reg_intr_vect_r_vect___dma0___width 1
170#define reg_intr_vect_r_vect___dma0___bit 6
171#define reg_intr_vect_r_vect___dma1___lsb 7
172#define reg_intr_vect_r_vect___dma1___width 1
173#define reg_intr_vect_r_vect___dma1___bit 7
174#define reg_intr_vect_r_vect___dma2___lsb 8
175#define reg_intr_vect_r_vect___dma2___width 1
176#define reg_intr_vect_r_vect___dma2___bit 8
177#define reg_intr_vect_r_vect___dma3___lsb 9
178#define reg_intr_vect_r_vect___dma3___width 1
179#define reg_intr_vect_r_vect___dma3___bit 9
180#define reg_intr_vect_r_vect___dma4___lsb 10
181#define reg_intr_vect_r_vect___dma4___width 1
182#define reg_intr_vect_r_vect___dma4___bit 10
183#define reg_intr_vect_r_vect___dma5___lsb 11
184#define reg_intr_vect_r_vect___dma5___width 1
185#define reg_intr_vect_r_vect___dma5___bit 11
186#define reg_intr_vect_r_vect___dma6___lsb 12
187#define reg_intr_vect_r_vect___dma6___width 1
188#define reg_intr_vect_r_vect___dma6___bit 12
189#define reg_intr_vect_r_vect___dma7___lsb 13
190#define reg_intr_vect_r_vect___dma7___width 1
191#define reg_intr_vect_r_vect___dma7___bit 13
192#define reg_intr_vect_r_vect___dma8___lsb 14
193#define reg_intr_vect_r_vect___dma8___width 1
194#define reg_intr_vect_r_vect___dma8___bit 14
195#define reg_intr_vect_r_vect___dma9___lsb 15
196#define reg_intr_vect_r_vect___dma9___width 1
197#define reg_intr_vect_r_vect___dma9___bit 15
198#define reg_intr_vect_r_vect___ata___lsb 16
199#define reg_intr_vect_r_vect___ata___width 1
200#define reg_intr_vect_r_vect___ata___bit 16
201#define reg_intr_vect_r_vect___sser0___lsb 17
202#define reg_intr_vect_r_vect___sser0___width 1
203#define reg_intr_vect_r_vect___sser0___bit 17
204#define reg_intr_vect_r_vect___sser1___lsb 18
205#define reg_intr_vect_r_vect___sser1___width 1
206#define reg_intr_vect_r_vect___sser1___bit 18
207#define reg_intr_vect_r_vect___ser0___lsb 19
208#define reg_intr_vect_r_vect___ser0___width 1
209#define reg_intr_vect_r_vect___ser0___bit 19
210#define reg_intr_vect_r_vect___ser1___lsb 20
211#define reg_intr_vect_r_vect___ser1___width 1
212#define reg_intr_vect_r_vect___ser1___bit 20
213#define reg_intr_vect_r_vect___ser2___lsb 21
214#define reg_intr_vect_r_vect___ser2___width 1
215#define reg_intr_vect_r_vect___ser2___bit 21
216#define reg_intr_vect_r_vect___ser3___lsb 22
217#define reg_intr_vect_r_vect___ser3___width 1
218#define reg_intr_vect_r_vect___ser3___bit 22
219#define reg_intr_vect_r_vect___p21___lsb 23
220#define reg_intr_vect_r_vect___p21___width 1
221#define reg_intr_vect_r_vect___p21___bit 23
222#define reg_intr_vect_r_vect___eth0___lsb 24
223#define reg_intr_vect_r_vect___eth0___width 1
224#define reg_intr_vect_r_vect___eth0___bit 24
225#define reg_intr_vect_r_vect___eth1___lsb 25
226#define reg_intr_vect_r_vect___eth1___width 1
227#define reg_intr_vect_r_vect___eth1___bit 25
228#define reg_intr_vect_r_vect___timer___lsb 26
229#define reg_intr_vect_r_vect___timer___width 1
230#define reg_intr_vect_r_vect___timer___bit 26
231#define reg_intr_vect_r_vect___bif_arb___lsb 27
232#define reg_intr_vect_r_vect___bif_arb___width 1
233#define reg_intr_vect_r_vect___bif_arb___bit 27
234#define reg_intr_vect_r_vect___bif_dma___lsb 28
235#define reg_intr_vect_r_vect___bif_dma___width 1
236#define reg_intr_vect_r_vect___bif_dma___bit 28
237#define reg_intr_vect_r_vect___ext___lsb 29
238#define reg_intr_vect_r_vect___ext___width 1
239#define reg_intr_vect_r_vect___ext___bit 29
240#define reg_intr_vect_r_vect_offset 4
241
242/* Register r_masked_vect, scope intr_vect, type r */
243#define reg_intr_vect_r_masked_vect___memarb___lsb 0
244#define reg_intr_vect_r_masked_vect___memarb___width 1
245#define reg_intr_vect_r_masked_vect___memarb___bit 0
246#define reg_intr_vect_r_masked_vect___gen_io___lsb 1
247#define reg_intr_vect_r_masked_vect___gen_io___width 1
248#define reg_intr_vect_r_masked_vect___gen_io___bit 1
249#define reg_intr_vect_r_masked_vect___iop0___lsb 2
250#define reg_intr_vect_r_masked_vect___iop0___width 1
251#define reg_intr_vect_r_masked_vect___iop0___bit 2
252#define reg_intr_vect_r_masked_vect___iop1___lsb 3
253#define reg_intr_vect_r_masked_vect___iop1___width 1
254#define reg_intr_vect_r_masked_vect___iop1___bit 3
255#define reg_intr_vect_r_masked_vect___iop2___lsb 4
256#define reg_intr_vect_r_masked_vect___iop2___width 1
257#define reg_intr_vect_r_masked_vect___iop2___bit 4
258#define reg_intr_vect_r_masked_vect___iop3___lsb 5
259#define reg_intr_vect_r_masked_vect___iop3___width 1
260#define reg_intr_vect_r_masked_vect___iop3___bit 5
261#define reg_intr_vect_r_masked_vect___dma0___lsb 6
262#define reg_intr_vect_r_masked_vect___dma0___width 1
263#define reg_intr_vect_r_masked_vect___dma0___bit 6
264#define reg_intr_vect_r_masked_vect___dma1___lsb 7
265#define reg_intr_vect_r_masked_vect___dma1___width 1
266#define reg_intr_vect_r_masked_vect___dma1___bit 7
267#define reg_intr_vect_r_masked_vect___dma2___lsb 8
268#define reg_intr_vect_r_masked_vect___dma2___width 1
269#define reg_intr_vect_r_masked_vect___dma2___bit 8
270#define reg_intr_vect_r_masked_vect___dma3___lsb 9
271#define reg_intr_vect_r_masked_vect___dma3___width 1
272#define reg_intr_vect_r_masked_vect___dma3___bit 9
273#define reg_intr_vect_r_masked_vect___dma4___lsb 10
274#define reg_intr_vect_r_masked_vect___dma4___width 1
275#define reg_intr_vect_r_masked_vect___dma4___bit 10
276#define reg_intr_vect_r_masked_vect___dma5___lsb 11
277#define reg_intr_vect_r_masked_vect___dma5___width 1
278#define reg_intr_vect_r_masked_vect___dma5___bit 11
279#define reg_intr_vect_r_masked_vect___dma6___lsb 12
280#define reg_intr_vect_r_masked_vect___dma6___width 1
281#define reg_intr_vect_r_masked_vect___dma6___bit 12
282#define reg_intr_vect_r_masked_vect___dma7___lsb 13
283#define reg_intr_vect_r_masked_vect___dma7___width 1
284#define reg_intr_vect_r_masked_vect___dma7___bit 13
285#define reg_intr_vect_r_masked_vect___dma8___lsb 14
286#define reg_intr_vect_r_masked_vect___dma8___width 1
287#define reg_intr_vect_r_masked_vect___dma8___bit 14
288#define reg_intr_vect_r_masked_vect___dma9___lsb 15
289#define reg_intr_vect_r_masked_vect___dma9___width 1
290#define reg_intr_vect_r_masked_vect___dma9___bit 15
291#define reg_intr_vect_r_masked_vect___ata___lsb 16
292#define reg_intr_vect_r_masked_vect___ata___width 1
293#define reg_intr_vect_r_masked_vect___ata___bit 16
294#define reg_intr_vect_r_masked_vect___sser0___lsb 17
295#define reg_intr_vect_r_masked_vect___sser0___width 1
296#define reg_intr_vect_r_masked_vect___sser0___bit 17
297#define reg_intr_vect_r_masked_vect___sser1___lsb 18
298#define reg_intr_vect_r_masked_vect___sser1___width 1
299#define reg_intr_vect_r_masked_vect___sser1___bit 18
300#define reg_intr_vect_r_masked_vect___ser0___lsb 19
301#define reg_intr_vect_r_masked_vect___ser0___width 1
302#define reg_intr_vect_r_masked_vect___ser0___bit 19
303#define reg_intr_vect_r_masked_vect___ser1___lsb 20
304#define reg_intr_vect_r_masked_vect___ser1___width 1
305#define reg_intr_vect_r_masked_vect___ser1___bit 20
306#define reg_intr_vect_r_masked_vect___ser2___lsb 21
307#define reg_intr_vect_r_masked_vect___ser2___width 1
308#define reg_intr_vect_r_masked_vect___ser2___bit 21
309#define reg_intr_vect_r_masked_vect___ser3___lsb 22
310#define reg_intr_vect_r_masked_vect___ser3___width 1
311#define reg_intr_vect_r_masked_vect___ser3___bit 22
312#define reg_intr_vect_r_masked_vect___p21___lsb 23
313#define reg_intr_vect_r_masked_vect___p21___width 1
314#define reg_intr_vect_r_masked_vect___p21___bit 23
315#define reg_intr_vect_r_masked_vect___eth0___lsb 24
316#define reg_intr_vect_r_masked_vect___eth0___width 1
317#define reg_intr_vect_r_masked_vect___eth0___bit 24
318#define reg_intr_vect_r_masked_vect___eth1___lsb 25
319#define reg_intr_vect_r_masked_vect___eth1___width 1
320#define reg_intr_vect_r_masked_vect___eth1___bit 25
321#define reg_intr_vect_r_masked_vect___timer___lsb 26
322#define reg_intr_vect_r_masked_vect___timer___width 1
323#define reg_intr_vect_r_masked_vect___timer___bit 26
324#define reg_intr_vect_r_masked_vect___bif_arb___lsb 27
325#define reg_intr_vect_r_masked_vect___bif_arb___width 1
326#define reg_intr_vect_r_masked_vect___bif_arb___bit 27
327#define reg_intr_vect_r_masked_vect___bif_dma___lsb 28
328#define reg_intr_vect_r_masked_vect___bif_dma___width 1
329#define reg_intr_vect_r_masked_vect___bif_dma___bit 28
330#define reg_intr_vect_r_masked_vect___ext___lsb 29
331#define reg_intr_vect_r_masked_vect___ext___width 1
332#define reg_intr_vect_r_masked_vect___ext___bit 29
333#define reg_intr_vect_r_masked_vect_offset 8
334
335/* Register r_nmi, scope intr_vect, type r */
336#define reg_intr_vect_r_nmi___ext___lsb 0
337#define reg_intr_vect_r_nmi___ext___width 1
338#define reg_intr_vect_r_nmi___ext___bit 0
339#define reg_intr_vect_r_nmi___watchdog___lsb 1
340#define reg_intr_vect_r_nmi___watchdog___width 1
341#define reg_intr_vect_r_nmi___watchdog___bit 1
342#define reg_intr_vect_r_nmi_offset 12
343
344/* Register r_guru, scope intr_vect, type r */
345#define reg_intr_vect_r_guru___jtag___lsb 0
346#define reg_intr_vect_r_guru___jtag___width 1
347#define reg_intr_vect_r_guru___jtag___bit 0
348#define reg_intr_vect_r_guru_offset 16
349
350
351/* Constants */
352#define regk_intr_vect_off 0x00000000
353#define regk_intr_vect_on 0x00000001
354#define regk_intr_vect_rw_mask_default 0x00000000
355#endif /* __intr_vect_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h
new file mode 100644
index 000000000000..0c8084054840
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h
@@ -0,0 +1,69 @@
1#ifndef __irq_nmi_defs_asm_h
2#define __irq_nmi_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../mod/irq_nmi.r
7 * id: <not found>
8 * last modfied: Thu Jan 22 09:22:43 2004
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r
11 * id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_cmd, scope irq_nmi, type rw */
57#define reg_irq_nmi_rw_cmd___delay___lsb 0
58#define reg_irq_nmi_rw_cmd___delay___width 16
59#define reg_irq_nmi_rw_cmd___op___lsb 16
60#define reg_irq_nmi_rw_cmd___op___width 2
61#define reg_irq_nmi_rw_cmd_offset 0
62
63
64/* Constants */
65#define regk_irq_nmi_ack_irq 0x00000002
66#define regk_irq_nmi_ack_nmi 0x00000003
67#define regk_irq_nmi_irq 0x00000000
68#define regk_irq_nmi_nmi 0x00000001
69#endif /* __irq_nmi_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h
new file mode 100644
index 000000000000..45400eb8d389
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h
@@ -0,0 +1,579 @@
1#ifndef __marb_defs_asm_h
2#define __marb_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/memarb/rtl/guinness/marb_top.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:12:16 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
11 * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56#define STRIDE_marb_rw_int_slots 4
57/* Register rw_int_slots, scope marb, type rw */
58#define reg_marb_rw_int_slots___owner___lsb 0
59#define reg_marb_rw_int_slots___owner___width 4
60#define reg_marb_rw_int_slots_offset 0
61
62#define STRIDE_marb_rw_ext_slots 4
63/* Register rw_ext_slots, scope marb, type rw */
64#define reg_marb_rw_ext_slots___owner___lsb 0
65#define reg_marb_rw_ext_slots___owner___width 4
66#define reg_marb_rw_ext_slots_offset 256
67
68#define STRIDE_marb_rw_regs_slots 4
69/* Register rw_regs_slots, scope marb, type rw */
70#define reg_marb_rw_regs_slots___owner___lsb 0
71#define reg_marb_rw_regs_slots___owner___width 4
72#define reg_marb_rw_regs_slots_offset 512
73
74/* Register rw_intr_mask, scope marb, type rw */
75#define reg_marb_rw_intr_mask___bp0___lsb 0
76#define reg_marb_rw_intr_mask___bp0___width 1
77#define reg_marb_rw_intr_mask___bp0___bit 0
78#define reg_marb_rw_intr_mask___bp1___lsb 1
79#define reg_marb_rw_intr_mask___bp1___width 1
80#define reg_marb_rw_intr_mask___bp1___bit 1
81#define reg_marb_rw_intr_mask___bp2___lsb 2
82#define reg_marb_rw_intr_mask___bp2___width 1
83#define reg_marb_rw_intr_mask___bp2___bit 2
84#define reg_marb_rw_intr_mask___bp3___lsb 3
85#define reg_marb_rw_intr_mask___bp3___width 1
86#define reg_marb_rw_intr_mask___bp3___bit 3
87#define reg_marb_rw_intr_mask_offset 528
88
89/* Register rw_ack_intr, scope marb, type rw */
90#define reg_marb_rw_ack_intr___bp0___lsb 0
91#define reg_marb_rw_ack_intr___bp0___width 1
92#define reg_marb_rw_ack_intr___bp0___bit 0
93#define reg_marb_rw_ack_intr___bp1___lsb 1
94#define reg_marb_rw_ack_intr___bp1___width 1
95#define reg_marb_rw_ack_intr___bp1___bit 1
96#define reg_marb_rw_ack_intr___bp2___lsb 2
97#define reg_marb_rw_ack_intr___bp2___width 1
98#define reg_marb_rw_ack_intr___bp2___bit 2
99#define reg_marb_rw_ack_intr___bp3___lsb 3
100#define reg_marb_rw_ack_intr___bp3___width 1
101#define reg_marb_rw_ack_intr___bp3___bit 3
102#define reg_marb_rw_ack_intr_offset 532
103
104/* Register r_intr, scope marb, type r */
105#define reg_marb_r_intr___bp0___lsb 0
106#define reg_marb_r_intr___bp0___width 1
107#define reg_marb_r_intr___bp0___bit 0
108#define reg_marb_r_intr___bp1___lsb 1
109#define reg_marb_r_intr___bp1___width 1
110#define reg_marb_r_intr___bp1___bit 1
111#define reg_marb_r_intr___bp2___lsb 2
112#define reg_marb_r_intr___bp2___width 1
113#define reg_marb_r_intr___bp2___bit 2
114#define reg_marb_r_intr___bp3___lsb 3
115#define reg_marb_r_intr___bp3___width 1
116#define reg_marb_r_intr___bp3___bit 3
117#define reg_marb_r_intr_offset 536
118
119/* Register r_masked_intr, scope marb, type r */
120#define reg_marb_r_masked_intr___bp0___lsb 0
121#define reg_marb_r_masked_intr___bp0___width 1
122#define reg_marb_r_masked_intr___bp0___bit 0
123#define reg_marb_r_masked_intr___bp1___lsb 1
124#define reg_marb_r_masked_intr___bp1___width 1
125#define reg_marb_r_masked_intr___bp1___bit 1
126#define reg_marb_r_masked_intr___bp2___lsb 2
127#define reg_marb_r_masked_intr___bp2___width 1
128#define reg_marb_r_masked_intr___bp2___bit 2
129#define reg_marb_r_masked_intr___bp3___lsb 3
130#define reg_marb_r_masked_intr___bp3___width 1
131#define reg_marb_r_masked_intr___bp3___bit 3
132#define reg_marb_r_masked_intr_offset 540
133
134/* Register rw_stop_mask, scope marb, type rw */
135#define reg_marb_rw_stop_mask___dma0___lsb 0
136#define reg_marb_rw_stop_mask___dma0___width 1
137#define reg_marb_rw_stop_mask___dma0___bit 0
138#define reg_marb_rw_stop_mask___dma1___lsb 1
139#define reg_marb_rw_stop_mask___dma1___width 1
140#define reg_marb_rw_stop_mask___dma1___bit 1
141#define reg_marb_rw_stop_mask___dma2___lsb 2
142#define reg_marb_rw_stop_mask___dma2___width 1
143#define reg_marb_rw_stop_mask___dma2___bit 2
144#define reg_marb_rw_stop_mask___dma3___lsb 3
145#define reg_marb_rw_stop_mask___dma3___width 1
146#define reg_marb_rw_stop_mask___dma3___bit 3
147#define reg_marb_rw_stop_mask___dma4___lsb 4
148#define reg_marb_rw_stop_mask___dma4___width 1
149#define reg_marb_rw_stop_mask___dma4___bit 4
150#define reg_marb_rw_stop_mask___dma5___lsb 5
151#define reg_marb_rw_stop_mask___dma5___width 1
152#define reg_marb_rw_stop_mask___dma5___bit 5
153#define reg_marb_rw_stop_mask___dma6___lsb 6
154#define reg_marb_rw_stop_mask___dma6___width 1
155#define reg_marb_rw_stop_mask___dma6___bit 6
156#define reg_marb_rw_stop_mask___dma7___lsb 7
157#define reg_marb_rw_stop_mask___dma7___width 1
158#define reg_marb_rw_stop_mask___dma7___bit 7
159#define reg_marb_rw_stop_mask___dma8___lsb 8
160#define reg_marb_rw_stop_mask___dma8___width 1
161#define reg_marb_rw_stop_mask___dma8___bit 8
162#define reg_marb_rw_stop_mask___dma9___lsb 9
163#define reg_marb_rw_stop_mask___dma9___width 1
164#define reg_marb_rw_stop_mask___dma9___bit 9
165#define reg_marb_rw_stop_mask___cpui___lsb 10
166#define reg_marb_rw_stop_mask___cpui___width 1
167#define reg_marb_rw_stop_mask___cpui___bit 10
168#define reg_marb_rw_stop_mask___cpud___lsb 11
169#define reg_marb_rw_stop_mask___cpud___width 1
170#define reg_marb_rw_stop_mask___cpud___bit 11
171#define reg_marb_rw_stop_mask___iop___lsb 12
172#define reg_marb_rw_stop_mask___iop___width 1
173#define reg_marb_rw_stop_mask___iop___bit 12
174#define reg_marb_rw_stop_mask___slave___lsb 13
175#define reg_marb_rw_stop_mask___slave___width 1
176#define reg_marb_rw_stop_mask___slave___bit 13
177#define reg_marb_rw_stop_mask_offset 544
178
179/* Register r_stopped, scope marb, type r */
180#define reg_marb_r_stopped___dma0___lsb 0
181#define reg_marb_r_stopped___dma0___width 1
182#define reg_marb_r_stopped___dma0___bit 0
183#define reg_marb_r_stopped___dma1___lsb 1
184#define reg_marb_r_stopped___dma1___width 1
185#define reg_marb_r_stopped___dma1___bit 1
186#define reg_marb_r_stopped___dma2___lsb 2
187#define reg_marb_r_stopped___dma2___width 1
188#define reg_marb_r_stopped___dma2___bit 2
189#define reg_marb_r_stopped___dma3___lsb 3
190#define reg_marb_r_stopped___dma3___width 1
191#define reg_marb_r_stopped___dma3___bit 3
192#define reg_marb_r_stopped___dma4___lsb 4
193#define reg_marb_r_stopped___dma4___width 1
194#define reg_marb_r_stopped___dma4___bit 4
195#define reg_marb_r_stopped___dma5___lsb 5
196#define reg_marb_r_stopped___dma5___width 1
197#define reg_marb_r_stopped___dma5___bit 5
198#define reg_marb_r_stopped___dma6___lsb 6
199#define reg_marb_r_stopped___dma6___width 1
200#define reg_marb_r_stopped___dma6___bit 6
201#define reg_marb_r_stopped___dma7___lsb 7
202#define reg_marb_r_stopped___dma7___width 1
203#define reg_marb_r_stopped___dma7___bit 7
204#define reg_marb_r_stopped___dma8___lsb 8
205#define reg_marb_r_stopped___dma8___width 1
206#define reg_marb_r_stopped___dma8___bit 8
207#define reg_marb_r_stopped___dma9___lsb 9
208#define reg_marb_r_stopped___dma9___width 1
209#define reg_marb_r_stopped___dma9___bit 9
210#define reg_marb_r_stopped___cpui___lsb 10
211#define reg_marb_r_stopped___cpui___width 1
212#define reg_marb_r_stopped___cpui___bit 10
213#define reg_marb_r_stopped___cpud___lsb 11
214#define reg_marb_r_stopped___cpud___width 1
215#define reg_marb_r_stopped___cpud___bit 11
216#define reg_marb_r_stopped___iop___lsb 12
217#define reg_marb_r_stopped___iop___width 1
218#define reg_marb_r_stopped___iop___bit 12
219#define reg_marb_r_stopped___slave___lsb 13
220#define reg_marb_r_stopped___slave___width 1
221#define reg_marb_r_stopped___slave___bit 13
222#define reg_marb_r_stopped_offset 548
223
224/* Register rw_no_snoop, scope marb, type rw */
225#define reg_marb_rw_no_snoop___dma0___lsb 0
226#define reg_marb_rw_no_snoop___dma0___width 1
227#define reg_marb_rw_no_snoop___dma0___bit 0
228#define reg_marb_rw_no_snoop___dma1___lsb 1
229#define reg_marb_rw_no_snoop___dma1___width 1
230#define reg_marb_rw_no_snoop___dma1___bit 1
231#define reg_marb_rw_no_snoop___dma2___lsb 2
232#define reg_marb_rw_no_snoop___dma2___width 1
233#define reg_marb_rw_no_snoop___dma2___bit 2
234#define reg_marb_rw_no_snoop___dma3___lsb 3
235#define reg_marb_rw_no_snoop___dma3___width 1
236#define reg_marb_rw_no_snoop___dma3___bit 3
237#define reg_marb_rw_no_snoop___dma4___lsb 4
238#define reg_marb_rw_no_snoop___dma4___width 1
239#define reg_marb_rw_no_snoop___dma4___bit 4
240#define reg_marb_rw_no_snoop___dma5___lsb 5
241#define reg_marb_rw_no_snoop___dma5___width 1
242#define reg_marb_rw_no_snoop___dma5___bit 5
243#define reg_marb_rw_no_snoop___dma6___lsb 6
244#define reg_marb_rw_no_snoop___dma6___width 1
245#define reg_marb_rw_no_snoop___dma6___bit 6
246#define reg_marb_rw_no_snoop___dma7___lsb 7
247#define reg_marb_rw_no_snoop___dma7___width 1
248#define reg_marb_rw_no_snoop___dma7___bit 7
249#define reg_marb_rw_no_snoop___dma8___lsb 8
250#define reg_marb_rw_no_snoop___dma8___width 1
251#define reg_marb_rw_no_snoop___dma8___bit 8
252#define reg_marb_rw_no_snoop___dma9___lsb 9
253#define reg_marb_rw_no_snoop___dma9___width 1
254#define reg_marb_rw_no_snoop___dma9___bit 9
255#define reg_marb_rw_no_snoop___cpui___lsb 10
256#define reg_marb_rw_no_snoop___cpui___width 1
257#define reg_marb_rw_no_snoop___cpui___bit 10
258#define reg_marb_rw_no_snoop___cpud___lsb 11
259#define reg_marb_rw_no_snoop___cpud___width 1
260#define reg_marb_rw_no_snoop___cpud___bit 11
261#define reg_marb_rw_no_snoop___iop___lsb 12
262#define reg_marb_rw_no_snoop___iop___width 1
263#define reg_marb_rw_no_snoop___iop___bit 12
264#define reg_marb_rw_no_snoop___slave___lsb 13
265#define reg_marb_rw_no_snoop___slave___width 1
266#define reg_marb_rw_no_snoop___slave___bit 13
267#define reg_marb_rw_no_snoop_offset 832
268
269/* Register rw_no_snoop_rq, scope marb, type rw */
270#define reg_marb_rw_no_snoop_rq___cpui___lsb 10
271#define reg_marb_rw_no_snoop_rq___cpui___width 1
272#define reg_marb_rw_no_snoop_rq___cpui___bit 10
273#define reg_marb_rw_no_snoop_rq___cpud___lsb 11
274#define reg_marb_rw_no_snoop_rq___cpud___width 1
275#define reg_marb_rw_no_snoop_rq___cpud___bit 11
276#define reg_marb_rw_no_snoop_rq_offset 836
277
278
279/* Constants */
280#define regk_marb_cpud 0x0000000b
281#define regk_marb_cpui 0x0000000a
282#define regk_marb_dma0 0x00000000
283#define regk_marb_dma1 0x00000001
284#define regk_marb_dma2 0x00000002
285#define regk_marb_dma3 0x00000003
286#define regk_marb_dma4 0x00000004
287#define regk_marb_dma5 0x00000005
288#define regk_marb_dma6 0x00000006
289#define regk_marb_dma7 0x00000007
290#define regk_marb_dma8 0x00000008
291#define regk_marb_dma9 0x00000009
292#define regk_marb_iop 0x0000000c
293#define regk_marb_no 0x00000000
294#define regk_marb_r_stopped_default 0x00000000
295#define regk_marb_rw_ext_slots_default 0x00000000
296#define regk_marb_rw_ext_slots_size 0x00000040
297#define regk_marb_rw_int_slots_default 0x00000000
298#define regk_marb_rw_int_slots_size 0x00000040
299#define regk_marb_rw_intr_mask_default 0x00000000
300#define regk_marb_rw_no_snoop_default 0x00000000
301#define regk_marb_rw_no_snoop_rq_default 0x00000000
302#define regk_marb_rw_regs_slots_default 0x00000000
303#define regk_marb_rw_regs_slots_size 0x00000004
304#define regk_marb_rw_stop_mask_default 0x00000000
305#define regk_marb_slave 0x0000000d
306#define regk_marb_yes 0x00000001
307#endif /* __marb_defs_asm_h */
308#ifndef __marb_bp_defs_asm_h
309#define __marb_bp_defs_asm_h
310
311/*
312 * This file is autogenerated from
313 * file: ../../inst/memarb/rtl/guinness/marb_top.r
314 * id: <not found>
315 * last modfied: Mon Apr 11 16:12:16 2005
316 *
317 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
318 * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
319 * Any changes here will be lost.
320 *
321 * -*- buffer-read-only: t -*-
322 */
323
324#ifndef REG_FIELD
325#define REG_FIELD( scope, reg, field, value ) \
326 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
327#define REG_FIELD_X_( value, shift ) ((value) << shift)
328#endif
329
330#ifndef REG_STATE
331#define REG_STATE( scope, reg, field, symbolic_value ) \
332 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
333#define REG_STATE_X_( k, shift ) (k << shift)
334#endif
335
336#ifndef REG_MASK
337#define REG_MASK( scope, reg, field ) \
338 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
339#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
340#endif
341
342#ifndef REG_LSB
343#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
344#endif
345
346#ifndef REG_BIT
347#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
348#endif
349
350#ifndef REG_ADDR
351#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
352#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
353#endif
354
355#ifndef REG_ADDR_VECT
356#define REG_ADDR_VECT( scope, inst, reg, index ) \
357 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
358 STRIDE_##scope##_##reg )
359#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
360 ((inst) + offs + (index) * stride)
361#endif
362
363/* Register rw_first_addr, scope marb_bp, type rw */
364#define reg_marb_bp_rw_first_addr_offset 0
365
366/* Register rw_last_addr, scope marb_bp, type rw */
367#define reg_marb_bp_rw_last_addr_offset 4
368
369/* Register rw_op, scope marb_bp, type rw */
370#define reg_marb_bp_rw_op___rd___lsb 0
371#define reg_marb_bp_rw_op___rd___width 1
372#define reg_marb_bp_rw_op___rd___bit 0
373#define reg_marb_bp_rw_op___wr___lsb 1
374#define reg_marb_bp_rw_op___wr___width 1
375#define reg_marb_bp_rw_op___wr___bit 1
376#define reg_marb_bp_rw_op___rd_excl___lsb 2
377#define reg_marb_bp_rw_op___rd_excl___width 1
378#define reg_marb_bp_rw_op___rd_excl___bit 2
379#define reg_marb_bp_rw_op___pri_wr___lsb 3
380#define reg_marb_bp_rw_op___pri_wr___width 1
381#define reg_marb_bp_rw_op___pri_wr___bit 3
382#define reg_marb_bp_rw_op___us_rd___lsb 4
383#define reg_marb_bp_rw_op___us_rd___width 1
384#define reg_marb_bp_rw_op___us_rd___bit 4
385#define reg_marb_bp_rw_op___us_wr___lsb 5
386#define reg_marb_bp_rw_op___us_wr___width 1
387#define reg_marb_bp_rw_op___us_wr___bit 5
388#define reg_marb_bp_rw_op___us_rd_excl___lsb 6
389#define reg_marb_bp_rw_op___us_rd_excl___width 1
390#define reg_marb_bp_rw_op___us_rd_excl___bit 6
391#define reg_marb_bp_rw_op___us_pri_wr___lsb 7
392#define reg_marb_bp_rw_op___us_pri_wr___width 1
393#define reg_marb_bp_rw_op___us_pri_wr___bit 7
394#define reg_marb_bp_rw_op_offset 8
395
396/* Register rw_clients, scope marb_bp, type rw */
397#define reg_marb_bp_rw_clients___dma0___lsb 0
398#define reg_marb_bp_rw_clients___dma0___width 1
399#define reg_marb_bp_rw_clients___dma0___bit 0
400#define reg_marb_bp_rw_clients___dma1___lsb 1
401#define reg_marb_bp_rw_clients___dma1___width 1
402#define reg_marb_bp_rw_clients___dma1___bit 1
403#define reg_marb_bp_rw_clients___dma2___lsb 2
404#define reg_marb_bp_rw_clients___dma2___width 1
405#define reg_marb_bp_rw_clients___dma2___bit 2
406#define reg_marb_bp_rw_clients___dma3___lsb 3
407#define reg_marb_bp_rw_clients___dma3___width 1
408#define reg_marb_bp_rw_clients___dma3___bit 3
409#define reg_marb_bp_rw_clients___dma4___lsb 4
410#define reg_marb_bp_rw_clients___dma4___width 1
411#define reg_marb_bp_rw_clients___dma4___bit 4
412#define reg_marb_bp_rw_clients___dma5___lsb 5
413#define reg_marb_bp_rw_clients___dma5___width 1
414#define reg_marb_bp_rw_clients___dma5___bit 5
415#define reg_marb_bp_rw_clients___dma6___lsb 6
416#define reg_marb_bp_rw_clients___dma6___width 1
417#define reg_marb_bp_rw_clients___dma6___bit 6
418#define reg_marb_bp_rw_clients___dma7___lsb 7
419#define reg_marb_bp_rw_clients___dma7___width 1
420#define reg_marb_bp_rw_clients___dma7___bit 7
421#define reg_marb_bp_rw_clients___dma8___lsb 8
422#define reg_marb_bp_rw_clients___dma8___width 1
423#define reg_marb_bp_rw_clients___dma8___bit 8
424#define reg_marb_bp_rw_clients___dma9___lsb 9
425#define reg_marb_bp_rw_clients___dma9___width 1
426#define reg_marb_bp_rw_clients___dma9___bit 9
427#define reg_marb_bp_rw_clients___cpui___lsb 10
428#define reg_marb_bp_rw_clients___cpui___width 1
429#define reg_marb_bp_rw_clients___cpui___bit 10
430#define reg_marb_bp_rw_clients___cpud___lsb 11
431#define reg_marb_bp_rw_clients___cpud___width 1
432#define reg_marb_bp_rw_clients___cpud___bit 11
433#define reg_marb_bp_rw_clients___iop___lsb 12
434#define reg_marb_bp_rw_clients___iop___width 1
435#define reg_marb_bp_rw_clients___iop___bit 12
436#define reg_marb_bp_rw_clients___slave___lsb 13
437#define reg_marb_bp_rw_clients___slave___width 1
438#define reg_marb_bp_rw_clients___slave___bit 13
439#define reg_marb_bp_rw_clients_offset 12
440
441/* Register rw_options, scope marb_bp, type rw */
442#define reg_marb_bp_rw_options___wrap___lsb 0
443#define reg_marb_bp_rw_options___wrap___width 1
444#define reg_marb_bp_rw_options___wrap___bit 0
445#define reg_marb_bp_rw_options_offset 16
446
447/* Register r_brk_addr, scope marb_bp, type r */
448#define reg_marb_bp_r_brk_addr_offset 20
449
450/* Register r_brk_op, scope marb_bp, type r */
451#define reg_marb_bp_r_brk_op___rd___lsb 0
452#define reg_marb_bp_r_brk_op___rd___width 1
453#define reg_marb_bp_r_brk_op___rd___bit 0
454#define reg_marb_bp_r_brk_op___wr___lsb 1
455#define reg_marb_bp_r_brk_op___wr___width 1
456#define reg_marb_bp_r_brk_op___wr___bit 1
457#define reg_marb_bp_r_brk_op___rd_excl___lsb 2
458#define reg_marb_bp_r_brk_op___rd_excl___width 1
459#define reg_marb_bp_r_brk_op___rd_excl___bit 2
460#define reg_marb_bp_r_brk_op___pri_wr___lsb 3
461#define reg_marb_bp_r_brk_op___pri_wr___width 1
462#define reg_marb_bp_r_brk_op___pri_wr___bit 3
463#define reg_marb_bp_r_brk_op___us_rd___lsb 4
464#define reg_marb_bp_r_brk_op___us_rd___width 1
465#define reg_marb_bp_r_brk_op___us_rd___bit 4
466#define reg_marb_bp_r_brk_op___us_wr___lsb 5
467#define reg_marb_bp_r_brk_op___us_wr___width 1
468#define reg_marb_bp_r_brk_op___us_wr___bit 5
469#define reg_marb_bp_r_brk_op___us_rd_excl___lsb 6
470#define reg_marb_bp_r_brk_op___us_rd_excl___width 1
471#define reg_marb_bp_r_brk_op___us_rd_excl___bit 6
472#define reg_marb_bp_r_brk_op___us_pri_wr___lsb 7
473#define reg_marb_bp_r_brk_op___us_pri_wr___width 1
474#define reg_marb_bp_r_brk_op___us_pri_wr___bit 7
475#define reg_marb_bp_r_brk_op_offset 24
476
477/* Register r_brk_clients, scope marb_bp, type r */
478#define reg_marb_bp_r_brk_clients___dma0___lsb 0
479#define reg_marb_bp_r_brk_clients___dma0___width 1
480#define reg_marb_bp_r_brk_clients___dma0___bit 0
481#define reg_marb_bp_r_brk_clients___dma1___lsb 1
482#define reg_marb_bp_r_brk_clients___dma1___width 1
483#define reg_marb_bp_r_brk_clients___dma1___bit 1
484#define reg_marb_bp_r_brk_clients___dma2___lsb 2
485#define reg_marb_bp_r_brk_clients___dma2___width 1
486#define reg_marb_bp_r_brk_clients___dma2___bit 2
487#define reg_marb_bp_r_brk_clients___dma3___lsb 3
488#define reg_marb_bp_r_brk_clients___dma3___width 1
489#define reg_marb_bp_r_brk_clients___dma3___bit 3
490#define reg_marb_bp_r_brk_clients___dma4___lsb 4
491#define reg_marb_bp_r_brk_clients___dma4___width 1
492#define reg_marb_bp_r_brk_clients___dma4___bit 4
493#define reg_marb_bp_r_brk_clients___dma5___lsb 5
494#define reg_marb_bp_r_brk_clients___dma5___width 1
495#define reg_marb_bp_r_brk_clients___dma5___bit 5
496#define reg_marb_bp_r_brk_clients___dma6___lsb 6
497#define reg_marb_bp_r_brk_clients___dma6___width 1
498#define reg_marb_bp_r_brk_clients___dma6___bit 6
499#define reg_marb_bp_r_brk_clients___dma7___lsb 7
500#define reg_marb_bp_r_brk_clients___dma7___width 1
501#define reg_marb_bp_r_brk_clients___dma7___bit 7
502#define reg_marb_bp_r_brk_clients___dma8___lsb 8
503#define reg_marb_bp_r_brk_clients___dma8___width 1
504#define reg_marb_bp_r_brk_clients___dma8___bit 8
505#define reg_marb_bp_r_brk_clients___dma9___lsb 9
506#define reg_marb_bp_r_brk_clients___dma9___width 1
507#define reg_marb_bp_r_brk_clients___dma9___bit 9
508#define reg_marb_bp_r_brk_clients___cpui___lsb 10
509#define reg_marb_bp_r_brk_clients___cpui___width 1
510#define reg_marb_bp_r_brk_clients___cpui___bit 10
511#define reg_marb_bp_r_brk_clients___cpud___lsb 11
512#define reg_marb_bp_r_brk_clients___cpud___width 1
513#define reg_marb_bp_r_brk_clients___cpud___bit 11
514#define reg_marb_bp_r_brk_clients___iop___lsb 12
515#define reg_marb_bp_r_brk_clients___iop___width 1
516#define reg_marb_bp_r_brk_clients___iop___bit 12
517#define reg_marb_bp_r_brk_clients___slave___lsb 13
518#define reg_marb_bp_r_brk_clients___slave___width 1
519#define reg_marb_bp_r_brk_clients___slave___bit 13
520#define reg_marb_bp_r_brk_clients_offset 28
521
522/* Register r_brk_first_client, scope marb_bp, type r */
523#define reg_marb_bp_r_brk_first_client___dma0___lsb 0
524#define reg_marb_bp_r_brk_first_client___dma0___width 1
525#define reg_marb_bp_r_brk_first_client___dma0___bit 0
526#define reg_marb_bp_r_brk_first_client___dma1___lsb 1
527#define reg_marb_bp_r_brk_first_client___dma1___width 1
528#define reg_marb_bp_r_brk_first_client___dma1___bit 1
529#define reg_marb_bp_r_brk_first_client___dma2___lsb 2
530#define reg_marb_bp_r_brk_first_client___dma2___width 1
531#define reg_marb_bp_r_brk_first_client___dma2___bit 2
532#define reg_marb_bp_r_brk_first_client___dma3___lsb 3
533#define reg_marb_bp_r_brk_first_client___dma3___width 1
534#define reg_marb_bp_r_brk_first_client___dma3___bit 3
535#define reg_marb_bp_r_brk_first_client___dma4___lsb 4
536#define reg_marb_bp_r_brk_first_client___dma4___width 1
537#define reg_marb_bp_r_brk_first_client___dma4___bit 4
538#define reg_marb_bp_r_brk_first_client___dma5___lsb 5
539#define reg_marb_bp_r_brk_first_client___dma5___width 1
540#define reg_marb_bp_r_brk_first_client___dma5___bit 5
541#define reg_marb_bp_r_brk_first_client___dma6___lsb 6
542#define reg_marb_bp_r_brk_first_client___dma6___width 1
543#define reg_marb_bp_r_brk_first_client___dma6___bit 6
544#define reg_marb_bp_r_brk_first_client___dma7___lsb 7
545#define reg_marb_bp_r_brk_first_client___dma7___width 1
546#define reg_marb_bp_r_brk_first_client___dma7___bit 7
547#define reg_marb_bp_r_brk_first_client___dma8___lsb 8
548#define reg_marb_bp_r_brk_first_client___dma8___width 1
549#define reg_marb_bp_r_brk_first_client___dma8___bit 8
550#define reg_marb_bp_r_brk_first_client___dma9___lsb 9
551#define reg_marb_bp_r_brk_first_client___dma9___width 1
552#define reg_marb_bp_r_brk_first_client___dma9___bit 9
553#define reg_marb_bp_r_brk_first_client___cpui___lsb 10
554#define reg_marb_bp_r_brk_first_client___cpui___width 1
555#define reg_marb_bp_r_brk_first_client___cpui___bit 10
556#define reg_marb_bp_r_brk_first_client___cpud___lsb 11
557#define reg_marb_bp_r_brk_first_client___cpud___width 1
558#define reg_marb_bp_r_brk_first_client___cpud___bit 11
559#define reg_marb_bp_r_brk_first_client___iop___lsb 12
560#define reg_marb_bp_r_brk_first_client___iop___width 1
561#define reg_marb_bp_r_brk_first_client___iop___bit 12
562#define reg_marb_bp_r_brk_first_client___slave___lsb 13
563#define reg_marb_bp_r_brk_first_client___slave___width 1
564#define reg_marb_bp_r_brk_first_client___slave___bit 13
565#define reg_marb_bp_r_brk_first_client_offset 32
566
567/* Register r_brk_size, scope marb_bp, type r */
568#define reg_marb_bp_r_brk_size_offset 36
569
570/* Register rw_ack, scope marb_bp, type rw */
571#define reg_marb_bp_rw_ack_offset 40
572
573
574/* Constants */
575#define regk_marb_bp_no 0x00000000
576#define regk_marb_bp_rw_op_default 0x00000000
577#define regk_marb_bp_rw_options_default 0x00000000
578#define regk_marb_bp_yes 0x00000001
579#endif /* __marb_bp_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h
new file mode 100644
index 000000000000..505b7a16d878
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h
@@ -0,0 +1,212 @@
1#ifndef __mmu_defs_asm_h
2#define __mmu_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/mmu/doc/mmu_regs.r
7 * id: mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp
8 * last modfied: Mon Apr 11 17:03:20 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r
11 * id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_mm_cfg, scope mmu, type rw */
57#define reg_mmu_rw_mm_cfg___seg_0___lsb 0
58#define reg_mmu_rw_mm_cfg___seg_0___width 1
59#define reg_mmu_rw_mm_cfg___seg_0___bit 0
60#define reg_mmu_rw_mm_cfg___seg_1___lsb 1
61#define reg_mmu_rw_mm_cfg___seg_1___width 1
62#define reg_mmu_rw_mm_cfg___seg_1___bit 1
63#define reg_mmu_rw_mm_cfg___seg_2___lsb 2
64#define reg_mmu_rw_mm_cfg___seg_2___width 1
65#define reg_mmu_rw_mm_cfg___seg_2___bit 2
66#define reg_mmu_rw_mm_cfg___seg_3___lsb 3
67#define reg_mmu_rw_mm_cfg___seg_3___width 1
68#define reg_mmu_rw_mm_cfg___seg_3___bit 3
69#define reg_mmu_rw_mm_cfg___seg_4___lsb 4
70#define reg_mmu_rw_mm_cfg___seg_4___width 1
71#define reg_mmu_rw_mm_cfg___seg_4___bit 4
72#define reg_mmu_rw_mm_cfg___seg_5___lsb 5
73#define reg_mmu_rw_mm_cfg___seg_5___width 1
74#define reg_mmu_rw_mm_cfg___seg_5___bit 5
75#define reg_mmu_rw_mm_cfg___seg_6___lsb 6
76#define reg_mmu_rw_mm_cfg___seg_6___width 1
77#define reg_mmu_rw_mm_cfg___seg_6___bit 6
78#define reg_mmu_rw_mm_cfg___seg_7___lsb 7
79#define reg_mmu_rw_mm_cfg___seg_7___width 1
80#define reg_mmu_rw_mm_cfg___seg_7___bit 7
81#define reg_mmu_rw_mm_cfg___seg_8___lsb 8
82#define reg_mmu_rw_mm_cfg___seg_8___width 1
83#define reg_mmu_rw_mm_cfg___seg_8___bit 8
84#define reg_mmu_rw_mm_cfg___seg_9___lsb 9
85#define reg_mmu_rw_mm_cfg___seg_9___width 1
86#define reg_mmu_rw_mm_cfg___seg_9___bit 9
87#define reg_mmu_rw_mm_cfg___seg_a___lsb 10
88#define reg_mmu_rw_mm_cfg___seg_a___width 1
89#define reg_mmu_rw_mm_cfg___seg_a___bit 10
90#define reg_mmu_rw_mm_cfg___seg_b___lsb 11
91#define reg_mmu_rw_mm_cfg___seg_b___width 1
92#define reg_mmu_rw_mm_cfg___seg_b___bit 11
93#define reg_mmu_rw_mm_cfg___seg_c___lsb 12
94#define reg_mmu_rw_mm_cfg___seg_c___width 1
95#define reg_mmu_rw_mm_cfg___seg_c___bit 12
96#define reg_mmu_rw_mm_cfg___seg_d___lsb 13
97#define reg_mmu_rw_mm_cfg___seg_d___width 1
98#define reg_mmu_rw_mm_cfg___seg_d___bit 13
99#define reg_mmu_rw_mm_cfg___seg_e___lsb 14
100#define reg_mmu_rw_mm_cfg___seg_e___width 1
101#define reg_mmu_rw_mm_cfg___seg_e___bit 14
102#define reg_mmu_rw_mm_cfg___seg_f___lsb 15
103#define reg_mmu_rw_mm_cfg___seg_f___width 1
104#define reg_mmu_rw_mm_cfg___seg_f___bit 15
105#define reg_mmu_rw_mm_cfg___inv___lsb 16
106#define reg_mmu_rw_mm_cfg___inv___width 1
107#define reg_mmu_rw_mm_cfg___inv___bit 16
108#define reg_mmu_rw_mm_cfg___ex___lsb 17
109#define reg_mmu_rw_mm_cfg___ex___width 1
110#define reg_mmu_rw_mm_cfg___ex___bit 17
111#define reg_mmu_rw_mm_cfg___acc___lsb 18
112#define reg_mmu_rw_mm_cfg___acc___width 1
113#define reg_mmu_rw_mm_cfg___acc___bit 18
114#define reg_mmu_rw_mm_cfg___we___lsb 19
115#define reg_mmu_rw_mm_cfg___we___width 1
116#define reg_mmu_rw_mm_cfg___we___bit 19
117#define reg_mmu_rw_mm_cfg_offset 0
118
119/* Register rw_mm_kbase_lo, scope mmu, type rw */
120#define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0
121#define reg_mmu_rw_mm_kbase_lo___base_0___width 4
122#define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4
123#define reg_mmu_rw_mm_kbase_lo___base_1___width 4
124#define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8
125#define reg_mmu_rw_mm_kbase_lo___base_2___width 4
126#define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12
127#define reg_mmu_rw_mm_kbase_lo___base_3___width 4
128#define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16
129#define reg_mmu_rw_mm_kbase_lo___base_4___width 4
130#define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20
131#define reg_mmu_rw_mm_kbase_lo___base_5___width 4
132#define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24
133#define reg_mmu_rw_mm_kbase_lo___base_6___width 4
134#define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28
135#define reg_mmu_rw_mm_kbase_lo___base_7___width 4
136#define reg_mmu_rw_mm_kbase_lo_offset 4
137
138/* Register rw_mm_kbase_hi, scope mmu, type rw */
139#define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0
140#define reg_mmu_rw_mm_kbase_hi___base_8___width 4
141#define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4
142#define reg_mmu_rw_mm_kbase_hi___base_9___width 4
143#define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8
144#define reg_mmu_rw_mm_kbase_hi___base_a___width 4
145#define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12
146#define reg_mmu_rw_mm_kbase_hi___base_b___width 4
147#define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16
148#define reg_mmu_rw_mm_kbase_hi___base_c___width 4
149#define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20
150#define reg_mmu_rw_mm_kbase_hi___base_d___width 4
151#define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24
152#define reg_mmu_rw_mm_kbase_hi___base_e___width 4
153#define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28
154#define reg_mmu_rw_mm_kbase_hi___base_f___width 4
155#define reg_mmu_rw_mm_kbase_hi_offset 8
156
157/* Register r_mm_cause, scope mmu, type r */
158#define reg_mmu_r_mm_cause___pid___lsb 0
159#define reg_mmu_r_mm_cause___pid___width 8
160#define reg_mmu_r_mm_cause___op___lsb 8
161#define reg_mmu_r_mm_cause___op___width 2
162#define reg_mmu_r_mm_cause___vpn___lsb 13
163#define reg_mmu_r_mm_cause___vpn___width 19
164#define reg_mmu_r_mm_cause_offset 12
165
166/* Register rw_mm_tlb_sel, scope mmu, type rw */
167#define reg_mmu_rw_mm_tlb_sel___idx___lsb 0
168#define reg_mmu_rw_mm_tlb_sel___idx___width 4
169#define reg_mmu_rw_mm_tlb_sel___set___lsb 4
170#define reg_mmu_rw_mm_tlb_sel___set___width 2
171#define reg_mmu_rw_mm_tlb_sel_offset 16
172
173/* Register rw_mm_tlb_lo, scope mmu, type rw */
174#define reg_mmu_rw_mm_tlb_lo___x___lsb 0
175#define reg_mmu_rw_mm_tlb_lo___x___width 1
176#define reg_mmu_rw_mm_tlb_lo___x___bit 0
177#define reg_mmu_rw_mm_tlb_lo___w___lsb 1
178#define reg_mmu_rw_mm_tlb_lo___w___width 1
179#define reg_mmu_rw_mm_tlb_lo___w___bit 1
180#define reg_mmu_rw_mm_tlb_lo___k___lsb 2
181#define reg_mmu_rw_mm_tlb_lo___k___width 1
182#define reg_mmu_rw_mm_tlb_lo___k___bit 2
183#define reg_mmu_rw_mm_tlb_lo___v___lsb 3
184#define reg_mmu_rw_mm_tlb_lo___v___width 1
185#define reg_mmu_rw_mm_tlb_lo___v___bit 3
186#define reg_mmu_rw_mm_tlb_lo___g___lsb 4
187#define reg_mmu_rw_mm_tlb_lo___g___width 1
188#define reg_mmu_rw_mm_tlb_lo___g___bit 4
189#define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13
190#define reg_mmu_rw_mm_tlb_lo___pfn___width 19
191#define reg_mmu_rw_mm_tlb_lo_offset 20
192
193/* Register rw_mm_tlb_hi, scope mmu, type rw */
194#define reg_mmu_rw_mm_tlb_hi___pid___lsb 0
195#define reg_mmu_rw_mm_tlb_hi___pid___width 8
196#define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13
197#define reg_mmu_rw_mm_tlb_hi___vpn___width 19
198#define reg_mmu_rw_mm_tlb_hi_offset 24
199
200
201/* Constants */
202#define regk_mmu_execute 0x00000000
203#define regk_mmu_flush 0x00000003
204#define regk_mmu_linear 0x00000001
205#define regk_mmu_no 0x00000000
206#define regk_mmu_off 0x00000000
207#define regk_mmu_on 0x00000001
208#define regk_mmu_page 0x00000000
209#define regk_mmu_read 0x00000001
210#define regk_mmu_write 0x00000002
211#define regk_mmu_yes 0x00000001
212#endif /* __mmu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h b/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h
new file mode 100644
index 000000000000..339500bf3bc0
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h
@@ -0,0 +1,7 @@
1#define RW_MM_CFG 0
2#define RW_MM_KBASE_LO 1
3#define RW_MM_KBASE_HI 2
4#define R_MM_CAUSE 3
5#define RW_MM_TLB_SEL 4
6#define RW_MM_TLB_LO 5
7#define RW_MM_TLB_HI 6
diff --git a/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h
new file mode 100644
index 000000000000..13c725e4c774
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h
@@ -0,0 +1,632 @@
1#ifndef __pinmux_defs_asm_h
2#define __pinmux_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r
7 * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
8 * last modfied: Mon Apr 11 16:09:11 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
11 * id: $Id: pinmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_pa, scope pinmux, type rw */
57#define reg_pinmux_rw_pa___pa0___lsb 0
58#define reg_pinmux_rw_pa___pa0___width 1
59#define reg_pinmux_rw_pa___pa0___bit 0
60#define reg_pinmux_rw_pa___pa1___lsb 1
61#define reg_pinmux_rw_pa___pa1___width 1
62#define reg_pinmux_rw_pa___pa1___bit 1
63#define reg_pinmux_rw_pa___pa2___lsb 2
64#define reg_pinmux_rw_pa___pa2___width 1
65#define reg_pinmux_rw_pa___pa2___bit 2
66#define reg_pinmux_rw_pa___pa3___lsb 3
67#define reg_pinmux_rw_pa___pa3___width 1
68#define reg_pinmux_rw_pa___pa3___bit 3
69#define reg_pinmux_rw_pa___pa4___lsb 4
70#define reg_pinmux_rw_pa___pa4___width 1
71#define reg_pinmux_rw_pa___pa4___bit 4
72#define reg_pinmux_rw_pa___pa5___lsb 5
73#define reg_pinmux_rw_pa___pa5___width 1
74#define reg_pinmux_rw_pa___pa5___bit 5
75#define reg_pinmux_rw_pa___pa6___lsb 6
76#define reg_pinmux_rw_pa___pa6___width 1
77#define reg_pinmux_rw_pa___pa6___bit 6
78#define reg_pinmux_rw_pa___pa7___lsb 7
79#define reg_pinmux_rw_pa___pa7___width 1
80#define reg_pinmux_rw_pa___pa7___bit 7
81#define reg_pinmux_rw_pa___csp2_n___lsb 8
82#define reg_pinmux_rw_pa___csp2_n___width 1
83#define reg_pinmux_rw_pa___csp2_n___bit 8
84#define reg_pinmux_rw_pa___csp3_n___lsb 9
85#define reg_pinmux_rw_pa___csp3_n___width 1
86#define reg_pinmux_rw_pa___csp3_n___bit 9
87#define reg_pinmux_rw_pa___csp5_n___lsb 10
88#define reg_pinmux_rw_pa___csp5_n___width 1
89#define reg_pinmux_rw_pa___csp5_n___bit 10
90#define reg_pinmux_rw_pa___csp6_n___lsb 11
91#define reg_pinmux_rw_pa___csp6_n___width 1
92#define reg_pinmux_rw_pa___csp6_n___bit 11
93#define reg_pinmux_rw_pa___hsh4___lsb 12
94#define reg_pinmux_rw_pa___hsh4___width 1
95#define reg_pinmux_rw_pa___hsh4___bit 12
96#define reg_pinmux_rw_pa___hsh5___lsb 13
97#define reg_pinmux_rw_pa___hsh5___width 1
98#define reg_pinmux_rw_pa___hsh5___bit 13
99#define reg_pinmux_rw_pa___hsh6___lsb 14
100#define reg_pinmux_rw_pa___hsh6___width 1
101#define reg_pinmux_rw_pa___hsh6___bit 14
102#define reg_pinmux_rw_pa___hsh7___lsb 15
103#define reg_pinmux_rw_pa___hsh7___width 1
104#define reg_pinmux_rw_pa___hsh7___bit 15
105#define reg_pinmux_rw_pa_offset 0
106
107/* Register rw_hwprot, scope pinmux, type rw */
108#define reg_pinmux_rw_hwprot___ser1___lsb 0
109#define reg_pinmux_rw_hwprot___ser1___width 1
110#define reg_pinmux_rw_hwprot___ser1___bit 0
111#define reg_pinmux_rw_hwprot___ser2___lsb 1
112#define reg_pinmux_rw_hwprot___ser2___width 1
113#define reg_pinmux_rw_hwprot___ser2___bit 1
114#define reg_pinmux_rw_hwprot___ser3___lsb 2
115#define reg_pinmux_rw_hwprot___ser3___width 1
116#define reg_pinmux_rw_hwprot___ser3___bit 2
117#define reg_pinmux_rw_hwprot___sser0___lsb 3
118#define reg_pinmux_rw_hwprot___sser0___width 1
119#define reg_pinmux_rw_hwprot___sser0___bit 3
120#define reg_pinmux_rw_hwprot___sser1___lsb 4
121#define reg_pinmux_rw_hwprot___sser1___width 1
122#define reg_pinmux_rw_hwprot___sser1___bit 4
123#define reg_pinmux_rw_hwprot___ata0___lsb 5
124#define reg_pinmux_rw_hwprot___ata0___width 1
125#define reg_pinmux_rw_hwprot___ata0___bit 5
126#define reg_pinmux_rw_hwprot___ata1___lsb 6
127#define reg_pinmux_rw_hwprot___ata1___width 1
128#define reg_pinmux_rw_hwprot___ata1___bit 6
129#define reg_pinmux_rw_hwprot___ata2___lsb 7
130#define reg_pinmux_rw_hwprot___ata2___width 1
131#define reg_pinmux_rw_hwprot___ata2___bit 7
132#define reg_pinmux_rw_hwprot___ata3___lsb 8
133#define reg_pinmux_rw_hwprot___ata3___width 1
134#define reg_pinmux_rw_hwprot___ata3___bit 8
135#define reg_pinmux_rw_hwprot___ata___lsb 9
136#define reg_pinmux_rw_hwprot___ata___width 1
137#define reg_pinmux_rw_hwprot___ata___bit 9
138#define reg_pinmux_rw_hwprot___eth1___lsb 10
139#define reg_pinmux_rw_hwprot___eth1___width 1
140#define reg_pinmux_rw_hwprot___eth1___bit 10
141#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11
142#define reg_pinmux_rw_hwprot___eth1_mgm___width 1
143#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11
144#define reg_pinmux_rw_hwprot___timer___lsb 12
145#define reg_pinmux_rw_hwprot___timer___width 1
146#define reg_pinmux_rw_hwprot___timer___bit 12
147#define reg_pinmux_rw_hwprot___p21___lsb 13
148#define reg_pinmux_rw_hwprot___p21___width 1
149#define reg_pinmux_rw_hwprot___p21___bit 13
150#define reg_pinmux_rw_hwprot_offset 4
151
152/* Register rw_pb_gio, scope pinmux, type rw */
153#define reg_pinmux_rw_pb_gio___pb0___lsb 0
154#define reg_pinmux_rw_pb_gio___pb0___width 1
155#define reg_pinmux_rw_pb_gio___pb0___bit 0
156#define reg_pinmux_rw_pb_gio___pb1___lsb 1
157#define reg_pinmux_rw_pb_gio___pb1___width 1
158#define reg_pinmux_rw_pb_gio___pb1___bit 1
159#define reg_pinmux_rw_pb_gio___pb2___lsb 2
160#define reg_pinmux_rw_pb_gio___pb2___width 1
161#define reg_pinmux_rw_pb_gio___pb2___bit 2
162#define reg_pinmux_rw_pb_gio___pb3___lsb 3
163#define reg_pinmux_rw_pb_gio___pb3___width 1
164#define reg_pinmux_rw_pb_gio___pb3___bit 3
165#define reg_pinmux_rw_pb_gio___pb4___lsb 4
166#define reg_pinmux_rw_pb_gio___pb4___width 1
167#define reg_pinmux_rw_pb_gio___pb4___bit 4
168#define reg_pinmux_rw_pb_gio___pb5___lsb 5
169#define reg_pinmux_rw_pb_gio___pb5___width 1
170#define reg_pinmux_rw_pb_gio___pb5___bit 5
171#define reg_pinmux_rw_pb_gio___pb6___lsb 6
172#define reg_pinmux_rw_pb_gio___pb6___width 1
173#define reg_pinmux_rw_pb_gio___pb6___bit 6
174#define reg_pinmux_rw_pb_gio___pb7___lsb 7
175#define reg_pinmux_rw_pb_gio___pb7___width 1
176#define reg_pinmux_rw_pb_gio___pb7___bit 7
177#define reg_pinmux_rw_pb_gio___pb8___lsb 8
178#define reg_pinmux_rw_pb_gio___pb8___width 1
179#define reg_pinmux_rw_pb_gio___pb8___bit 8
180#define reg_pinmux_rw_pb_gio___pb9___lsb 9
181#define reg_pinmux_rw_pb_gio___pb9___width 1
182#define reg_pinmux_rw_pb_gio___pb9___bit 9
183#define reg_pinmux_rw_pb_gio___pb10___lsb 10
184#define reg_pinmux_rw_pb_gio___pb10___width 1
185#define reg_pinmux_rw_pb_gio___pb10___bit 10
186#define reg_pinmux_rw_pb_gio___pb11___lsb 11
187#define reg_pinmux_rw_pb_gio___pb11___width 1
188#define reg_pinmux_rw_pb_gio___pb11___bit 11
189#define reg_pinmux_rw_pb_gio___pb12___lsb 12
190#define reg_pinmux_rw_pb_gio___pb12___width 1
191#define reg_pinmux_rw_pb_gio___pb12___bit 12
192#define reg_pinmux_rw_pb_gio___pb13___lsb 13
193#define reg_pinmux_rw_pb_gio___pb13___width 1
194#define reg_pinmux_rw_pb_gio___pb13___bit 13
195#define reg_pinmux_rw_pb_gio___pb14___lsb 14
196#define reg_pinmux_rw_pb_gio___pb14___width 1
197#define reg_pinmux_rw_pb_gio___pb14___bit 14
198#define reg_pinmux_rw_pb_gio___pb15___lsb 15
199#define reg_pinmux_rw_pb_gio___pb15___width 1
200#define reg_pinmux_rw_pb_gio___pb15___bit 15
201#define reg_pinmux_rw_pb_gio___pb16___lsb 16
202#define reg_pinmux_rw_pb_gio___pb16___width 1
203#define reg_pinmux_rw_pb_gio___pb16___bit 16
204#define reg_pinmux_rw_pb_gio___pb17___lsb 17
205#define reg_pinmux_rw_pb_gio___pb17___width 1
206#define reg_pinmux_rw_pb_gio___pb17___bit 17
207#define reg_pinmux_rw_pb_gio_offset 8
208
209/* Register rw_pb_iop, scope pinmux, type rw */
210#define reg_pinmux_rw_pb_iop___pb0___lsb 0
211#define reg_pinmux_rw_pb_iop___pb0___width 1
212#define reg_pinmux_rw_pb_iop___pb0___bit 0
213#define reg_pinmux_rw_pb_iop___pb1___lsb 1
214#define reg_pinmux_rw_pb_iop___pb1___width 1
215#define reg_pinmux_rw_pb_iop___pb1___bit 1
216#define reg_pinmux_rw_pb_iop___pb2___lsb 2
217#define reg_pinmux_rw_pb_iop___pb2___width 1
218#define reg_pinmux_rw_pb_iop___pb2___bit 2
219#define reg_pinmux_rw_pb_iop___pb3___lsb 3
220#define reg_pinmux_rw_pb_iop___pb3___width 1
221#define reg_pinmux_rw_pb_iop___pb3___bit 3
222#define reg_pinmux_rw_pb_iop___pb4___lsb 4
223#define reg_pinmux_rw_pb_iop___pb4___width 1
224#define reg_pinmux_rw_pb_iop___pb4___bit 4
225#define reg_pinmux_rw_pb_iop___pb5___lsb 5
226#define reg_pinmux_rw_pb_iop___pb5___width 1
227#define reg_pinmux_rw_pb_iop___pb5___bit 5
228#define reg_pinmux_rw_pb_iop___pb6___lsb 6
229#define reg_pinmux_rw_pb_iop___pb6___width 1
230#define reg_pinmux_rw_pb_iop___pb6___bit 6
231#define reg_pinmux_rw_pb_iop___pb7___lsb 7
232#define reg_pinmux_rw_pb_iop___pb7___width 1
233#define reg_pinmux_rw_pb_iop___pb7___bit 7
234#define reg_pinmux_rw_pb_iop___pb8___lsb 8
235#define reg_pinmux_rw_pb_iop___pb8___width 1
236#define reg_pinmux_rw_pb_iop___pb8___bit 8
237#define reg_pinmux_rw_pb_iop___pb9___lsb 9
238#define reg_pinmux_rw_pb_iop___pb9___width 1
239#define reg_pinmux_rw_pb_iop___pb9___bit 9
240#define reg_pinmux_rw_pb_iop___pb10___lsb 10
241#define reg_pinmux_rw_pb_iop___pb10___width 1
242#define reg_pinmux_rw_pb_iop___pb10___bit 10
243#define reg_pinmux_rw_pb_iop___pb11___lsb 11
244#define reg_pinmux_rw_pb_iop___pb11___width 1
245#define reg_pinmux_rw_pb_iop___pb11___bit 11
246#define reg_pinmux_rw_pb_iop___pb12___lsb 12
247#define reg_pinmux_rw_pb_iop___pb12___width 1
248#define reg_pinmux_rw_pb_iop___pb12___bit 12
249#define reg_pinmux_rw_pb_iop___pb13___lsb 13
250#define reg_pinmux_rw_pb_iop___pb13___width 1
251#define reg_pinmux_rw_pb_iop___pb13___bit 13
252#define reg_pinmux_rw_pb_iop___pb14___lsb 14
253#define reg_pinmux_rw_pb_iop___pb14___width 1
254#define reg_pinmux_rw_pb_iop___pb14___bit 14
255#define reg_pinmux_rw_pb_iop___pb15___lsb 15
256#define reg_pinmux_rw_pb_iop___pb15___width 1
257#define reg_pinmux_rw_pb_iop___pb15___bit 15
258#define reg_pinmux_rw_pb_iop___pb16___lsb 16
259#define reg_pinmux_rw_pb_iop___pb16___width 1
260#define reg_pinmux_rw_pb_iop___pb16___bit 16
261#define reg_pinmux_rw_pb_iop___pb17___lsb 17
262#define reg_pinmux_rw_pb_iop___pb17___width 1
263#define reg_pinmux_rw_pb_iop___pb17___bit 17
264#define reg_pinmux_rw_pb_iop_offset 12
265
266/* Register rw_pc_gio, scope pinmux, type rw */
267#define reg_pinmux_rw_pc_gio___pc0___lsb 0
268#define reg_pinmux_rw_pc_gio___pc0___width 1
269#define reg_pinmux_rw_pc_gio___pc0___bit 0
270#define reg_pinmux_rw_pc_gio___pc1___lsb 1
271#define reg_pinmux_rw_pc_gio___pc1___width 1
272#define reg_pinmux_rw_pc_gio___pc1___bit 1
273#define reg_pinmux_rw_pc_gio___pc2___lsb 2
274#define reg_pinmux_rw_pc_gio___pc2___width 1
275#define reg_pinmux_rw_pc_gio___pc2___bit 2
276#define reg_pinmux_rw_pc_gio___pc3___lsb 3
277#define reg_pinmux_rw_pc_gio___pc3___width 1
278#define reg_pinmux_rw_pc_gio___pc3___bit 3
279#define reg_pinmux_rw_pc_gio___pc4___lsb 4
280#define reg_pinmux_rw_pc_gio___pc4___width 1
281#define reg_pinmux_rw_pc_gio___pc4___bit 4
282#define reg_pinmux_rw_pc_gio___pc5___lsb 5
283#define reg_pinmux_rw_pc_gio___pc5___width 1
284#define reg_pinmux_rw_pc_gio___pc5___bit 5
285#define reg_pinmux_rw_pc_gio___pc6___lsb 6
286#define reg_pinmux_rw_pc_gio___pc6___width 1
287#define reg_pinmux_rw_pc_gio___pc6___bit 6
288#define reg_pinmux_rw_pc_gio___pc7___lsb 7
289#define reg_pinmux_rw_pc_gio___pc7___width 1
290#define reg_pinmux_rw_pc_gio___pc7___bit 7
291#define reg_pinmux_rw_pc_gio___pc8___lsb 8
292#define reg_pinmux_rw_pc_gio___pc8___width 1
293#define reg_pinmux_rw_pc_gio___pc8___bit 8
294#define reg_pinmux_rw_pc_gio___pc9___lsb 9
295#define reg_pinmux_rw_pc_gio___pc9___width 1
296#define reg_pinmux_rw_pc_gio___pc9___bit 9
297#define reg_pinmux_rw_pc_gio___pc10___lsb 10
298#define reg_pinmux_rw_pc_gio___pc10___width 1
299#define reg_pinmux_rw_pc_gio___pc10___bit 10
300#define reg_pinmux_rw_pc_gio___pc11___lsb 11
301#define reg_pinmux_rw_pc_gio___pc11___width 1
302#define reg_pinmux_rw_pc_gio___pc11___bit 11
303#define reg_pinmux_rw_pc_gio___pc12___lsb 12
304#define reg_pinmux_rw_pc_gio___pc12___width 1
305#define reg_pinmux_rw_pc_gio___pc12___bit 12
306#define reg_pinmux_rw_pc_gio___pc13___lsb 13
307#define reg_pinmux_rw_pc_gio___pc13___width 1
308#define reg_pinmux_rw_pc_gio___pc13___bit 13
309#define reg_pinmux_rw_pc_gio___pc14___lsb 14
310#define reg_pinmux_rw_pc_gio___pc14___width 1
311#define reg_pinmux_rw_pc_gio___pc14___bit 14
312#define reg_pinmux_rw_pc_gio___pc15___lsb 15
313#define reg_pinmux_rw_pc_gio___pc15___width 1
314#define reg_pinmux_rw_pc_gio___pc15___bit 15
315#define reg_pinmux_rw_pc_gio___pc16___lsb 16
316#define reg_pinmux_rw_pc_gio___pc16___width 1
317#define reg_pinmux_rw_pc_gio___pc16___bit 16
318#define reg_pinmux_rw_pc_gio___pc17___lsb 17
319#define reg_pinmux_rw_pc_gio___pc17___width 1
320#define reg_pinmux_rw_pc_gio___pc17___bit 17
321#define reg_pinmux_rw_pc_gio_offset 16
322
323/* Register rw_pc_iop, scope pinmux, type rw */
324#define reg_pinmux_rw_pc_iop___pc0___lsb 0
325#define reg_pinmux_rw_pc_iop___pc0___width 1
326#define reg_pinmux_rw_pc_iop___pc0___bit 0
327#define reg_pinmux_rw_pc_iop___pc1___lsb 1
328#define reg_pinmux_rw_pc_iop___pc1___width 1
329#define reg_pinmux_rw_pc_iop___pc1___bit 1
330#define reg_pinmux_rw_pc_iop___pc2___lsb 2
331#define reg_pinmux_rw_pc_iop___pc2___width 1
332#define reg_pinmux_rw_pc_iop___pc2___bit 2
333#define reg_pinmux_rw_pc_iop___pc3___lsb 3
334#define reg_pinmux_rw_pc_iop___pc3___width 1
335#define reg_pinmux_rw_pc_iop___pc3___bit 3
336#define reg_pinmux_rw_pc_iop___pc4___lsb 4
337#define reg_pinmux_rw_pc_iop___pc4___width 1
338#define reg_pinmux_rw_pc_iop___pc4___bit 4
339#define reg_pinmux_rw_pc_iop___pc5___lsb 5
340#define reg_pinmux_rw_pc_iop___pc5___width 1
341#define reg_pinmux_rw_pc_iop___pc5___bit 5
342#define reg_pinmux_rw_pc_iop___pc6___lsb 6
343#define reg_pinmux_rw_pc_iop___pc6___width 1
344#define reg_pinmux_rw_pc_iop___pc6___bit 6
345#define reg_pinmux_rw_pc_iop___pc7___lsb 7
346#define reg_pinmux_rw_pc_iop___pc7___width 1
347#define reg_pinmux_rw_pc_iop___pc7___bit 7
348#define reg_pinmux_rw_pc_iop___pc8___lsb 8
349#define reg_pinmux_rw_pc_iop___pc8___width 1
350#define reg_pinmux_rw_pc_iop___pc8___bit 8
351#define reg_pinmux_rw_pc_iop___pc9___lsb 9
352#define reg_pinmux_rw_pc_iop___pc9___width 1
353#define reg_pinmux_rw_pc_iop___pc9___bit 9
354#define reg_pinmux_rw_pc_iop___pc10___lsb 10
355#define reg_pinmux_rw_pc_iop___pc10___width 1
356#define reg_pinmux_rw_pc_iop___pc10___bit 10
357#define reg_pinmux_rw_pc_iop___pc11___lsb 11
358#define reg_pinmux_rw_pc_iop___pc11___width 1
359#define reg_pinmux_rw_pc_iop___pc11___bit 11
360#define reg_pinmux_rw_pc_iop___pc12___lsb 12
361#define reg_pinmux_rw_pc_iop___pc12___width 1
362#define reg_pinmux_rw_pc_iop___pc12___bit 12
363#define reg_pinmux_rw_pc_iop___pc13___lsb 13
364#define reg_pinmux_rw_pc_iop___pc13___width 1
365#define reg_pinmux_rw_pc_iop___pc13___bit 13
366#define reg_pinmux_rw_pc_iop___pc14___lsb 14
367#define reg_pinmux_rw_pc_iop___pc14___width 1
368#define reg_pinmux_rw_pc_iop___pc14___bit 14
369#define reg_pinmux_rw_pc_iop___pc15___lsb 15
370#define reg_pinmux_rw_pc_iop___pc15___width 1
371#define reg_pinmux_rw_pc_iop___pc15___bit 15
372#define reg_pinmux_rw_pc_iop___pc16___lsb 16
373#define reg_pinmux_rw_pc_iop___pc16___width 1
374#define reg_pinmux_rw_pc_iop___pc16___bit 16
375#define reg_pinmux_rw_pc_iop___pc17___lsb 17
376#define reg_pinmux_rw_pc_iop___pc17___width 1
377#define reg_pinmux_rw_pc_iop___pc17___bit 17
378#define reg_pinmux_rw_pc_iop_offset 20
379
380/* Register rw_pd_gio, scope pinmux, type rw */
381#define reg_pinmux_rw_pd_gio___pd0___lsb 0
382#define reg_pinmux_rw_pd_gio___pd0___width 1
383#define reg_pinmux_rw_pd_gio___pd0___bit 0
384#define reg_pinmux_rw_pd_gio___pd1___lsb 1
385#define reg_pinmux_rw_pd_gio___pd1___width 1
386#define reg_pinmux_rw_pd_gio___pd1___bit 1
387#define reg_pinmux_rw_pd_gio___pd2___lsb 2
388#define reg_pinmux_rw_pd_gio___pd2___width 1
389#define reg_pinmux_rw_pd_gio___pd2___bit 2
390#define reg_pinmux_rw_pd_gio___pd3___lsb 3
391#define reg_pinmux_rw_pd_gio___pd3___width 1
392#define reg_pinmux_rw_pd_gio___pd3___bit 3
393#define reg_pinmux_rw_pd_gio___pd4___lsb 4
394#define reg_pinmux_rw_pd_gio___pd4___width 1
395#define reg_pinmux_rw_pd_gio___pd4___bit 4
396#define reg_pinmux_rw_pd_gio___pd5___lsb 5
397#define reg_pinmux_rw_pd_gio___pd5___width 1
398#define reg_pinmux_rw_pd_gio___pd5___bit 5
399#define reg_pinmux_rw_pd_gio___pd6___lsb 6
400#define reg_pinmux_rw_pd_gio___pd6___width 1
401#define reg_pinmux_rw_pd_gio___pd6___bit 6
402#define reg_pinmux_rw_pd_gio___pd7___lsb 7
403#define reg_pinmux_rw_pd_gio___pd7___width 1
404#define reg_pinmux_rw_pd_gio___pd7___bit 7
405#define reg_pinmux_rw_pd_gio___pd8___lsb 8
406#define reg_pinmux_rw_pd_gio___pd8___width 1
407#define reg_pinmux_rw_pd_gio___pd8___bit 8
408#define reg_pinmux_rw_pd_gio___pd9___lsb 9
409#define reg_pinmux_rw_pd_gio___pd9___width 1
410#define reg_pinmux_rw_pd_gio___pd9___bit 9
411#define reg_pinmux_rw_pd_gio___pd10___lsb 10
412#define reg_pinmux_rw_pd_gio___pd10___width 1
413#define reg_pinmux_rw_pd_gio___pd10___bit 10
414#define reg_pinmux_rw_pd_gio___pd11___lsb 11
415#define reg_pinmux_rw_pd_gio___pd11___width 1
416#define reg_pinmux_rw_pd_gio___pd11___bit 11
417#define reg_pinmux_rw_pd_gio___pd12___lsb 12
418#define reg_pinmux_rw_pd_gio___pd12___width 1
419#define reg_pinmux_rw_pd_gio___pd12___bit 12
420#define reg_pinmux_rw_pd_gio___pd13___lsb 13
421#define reg_pinmux_rw_pd_gio___pd13___width 1
422#define reg_pinmux_rw_pd_gio___pd13___bit 13
423#define reg_pinmux_rw_pd_gio___pd14___lsb 14
424#define reg_pinmux_rw_pd_gio___pd14___width 1
425#define reg_pinmux_rw_pd_gio___pd14___bit 14
426#define reg_pinmux_rw_pd_gio___pd15___lsb 15
427#define reg_pinmux_rw_pd_gio___pd15___width 1
428#define reg_pinmux_rw_pd_gio___pd15___bit 15
429#define reg_pinmux_rw_pd_gio___pd16___lsb 16
430#define reg_pinmux_rw_pd_gio___pd16___width 1
431#define reg_pinmux_rw_pd_gio___pd16___bit 16
432#define reg_pinmux_rw_pd_gio___pd17___lsb 17
433#define reg_pinmux_rw_pd_gio___pd17___width 1
434#define reg_pinmux_rw_pd_gio___pd17___bit 17
435#define reg_pinmux_rw_pd_gio_offset 24
436
437/* Register rw_pd_iop, scope pinmux, type rw */
438#define reg_pinmux_rw_pd_iop___pd0___lsb 0
439#define reg_pinmux_rw_pd_iop___pd0___width 1
440#define reg_pinmux_rw_pd_iop___pd0___bit 0
441#define reg_pinmux_rw_pd_iop___pd1___lsb 1
442#define reg_pinmux_rw_pd_iop___pd1___width 1
443#define reg_pinmux_rw_pd_iop___pd1___bit 1
444#define reg_pinmux_rw_pd_iop___pd2___lsb 2
445#define reg_pinmux_rw_pd_iop___pd2___width 1
446#define reg_pinmux_rw_pd_iop___pd2___bit 2
447#define reg_pinmux_rw_pd_iop___pd3___lsb 3
448#define reg_pinmux_rw_pd_iop___pd3___width 1
449#define reg_pinmux_rw_pd_iop___pd3___bit 3
450#define reg_pinmux_rw_pd_iop___pd4___lsb 4
451#define reg_pinmux_rw_pd_iop___pd4___width 1
452#define reg_pinmux_rw_pd_iop___pd4___bit 4
453#define reg_pinmux_rw_pd_iop___pd5___lsb 5
454#define reg_pinmux_rw_pd_iop___pd5___width 1
455#define reg_pinmux_rw_pd_iop___pd5___bit 5
456#define reg_pinmux_rw_pd_iop___pd6___lsb 6
457#define reg_pinmux_rw_pd_iop___pd6___width 1
458#define reg_pinmux_rw_pd_iop___pd6___bit 6
459#define reg_pinmux_rw_pd_iop___pd7___lsb 7
460#define reg_pinmux_rw_pd_iop___pd7___width 1
461#define reg_pinmux_rw_pd_iop___pd7___bit 7
462#define reg_pinmux_rw_pd_iop___pd8___lsb 8
463#define reg_pinmux_rw_pd_iop___pd8___width 1
464#define reg_pinmux_rw_pd_iop___pd8___bit 8
465#define reg_pinmux_rw_pd_iop___pd9___lsb 9
466#define reg_pinmux_rw_pd_iop___pd9___width 1
467#define reg_pinmux_rw_pd_iop___pd9___bit 9
468#define reg_pinmux_rw_pd_iop___pd10___lsb 10
469#define reg_pinmux_rw_pd_iop___pd10___width 1
470#define reg_pinmux_rw_pd_iop___pd10___bit 10
471#define reg_pinmux_rw_pd_iop___pd11___lsb 11
472#define reg_pinmux_rw_pd_iop___pd11___width 1
473#define reg_pinmux_rw_pd_iop___pd11___bit 11
474#define reg_pinmux_rw_pd_iop___pd12___lsb 12
475#define reg_pinmux_rw_pd_iop___pd12___width 1
476#define reg_pinmux_rw_pd_iop___pd12___bit 12
477#define reg_pinmux_rw_pd_iop___pd13___lsb 13
478#define reg_pinmux_rw_pd_iop___pd13___width 1
479#define reg_pinmux_rw_pd_iop___pd13___bit 13
480#define reg_pinmux_rw_pd_iop___pd14___lsb 14
481#define reg_pinmux_rw_pd_iop___pd14___width 1
482#define reg_pinmux_rw_pd_iop___pd14___bit 14
483#define reg_pinmux_rw_pd_iop___pd15___lsb 15
484#define reg_pinmux_rw_pd_iop___pd15___width 1
485#define reg_pinmux_rw_pd_iop___pd15___bit 15
486#define reg_pinmux_rw_pd_iop___pd16___lsb 16
487#define reg_pinmux_rw_pd_iop___pd16___width 1
488#define reg_pinmux_rw_pd_iop___pd16___bit 16
489#define reg_pinmux_rw_pd_iop___pd17___lsb 17
490#define reg_pinmux_rw_pd_iop___pd17___width 1
491#define reg_pinmux_rw_pd_iop___pd17___bit 17
492#define reg_pinmux_rw_pd_iop_offset 28
493
494/* Register rw_pe_gio, scope pinmux, type rw */
495#define reg_pinmux_rw_pe_gio___pe0___lsb 0
496#define reg_pinmux_rw_pe_gio___pe0___width 1
497#define reg_pinmux_rw_pe_gio___pe0___bit 0
498#define reg_pinmux_rw_pe_gio___pe1___lsb 1
499#define reg_pinmux_rw_pe_gio___pe1___width 1
500#define reg_pinmux_rw_pe_gio___pe1___bit 1
501#define reg_pinmux_rw_pe_gio___pe2___lsb 2
502#define reg_pinmux_rw_pe_gio___pe2___width 1
503#define reg_pinmux_rw_pe_gio___pe2___bit 2
504#define reg_pinmux_rw_pe_gio___pe3___lsb 3
505#define reg_pinmux_rw_pe_gio___pe3___width 1
506#define reg_pinmux_rw_pe_gio___pe3___bit 3
507#define reg_pinmux_rw_pe_gio___pe4___lsb 4
508#define reg_pinmux_rw_pe_gio___pe4___width 1
509#define reg_pinmux_rw_pe_gio___pe4___bit 4
510#define reg_pinmux_rw_pe_gio___pe5___lsb 5
511#define reg_pinmux_rw_pe_gio___pe5___width 1
512#define reg_pinmux_rw_pe_gio___pe5___bit 5
513#define reg_pinmux_rw_pe_gio___pe6___lsb 6
514#define reg_pinmux_rw_pe_gio___pe6___width 1
515#define reg_pinmux_rw_pe_gio___pe6___bit 6
516#define reg_pinmux_rw_pe_gio___pe7___lsb 7
517#define reg_pinmux_rw_pe_gio___pe7___width 1
518#define reg_pinmux_rw_pe_gio___pe7___bit 7
519#define reg_pinmux_rw_pe_gio___pe8___lsb 8
520#define reg_pinmux_rw_pe_gio___pe8___width 1
521#define reg_pinmux_rw_pe_gio___pe8___bit 8
522#define reg_pinmux_rw_pe_gio___pe9___lsb 9
523#define reg_pinmux_rw_pe_gio___pe9___width 1
524#define reg_pinmux_rw_pe_gio___pe9___bit 9
525#define reg_pinmux_rw_pe_gio___pe10___lsb 10
526#define reg_pinmux_rw_pe_gio___pe10___width 1
527#define reg_pinmux_rw_pe_gio___pe10___bit 10
528#define reg_pinmux_rw_pe_gio___pe11___lsb 11
529#define reg_pinmux_rw_pe_gio___pe11___width 1
530#define reg_pinmux_rw_pe_gio___pe11___bit 11
531#define reg_pinmux_rw_pe_gio___pe12___lsb 12
532#define reg_pinmux_rw_pe_gio___pe12___width 1
533#define reg_pinmux_rw_pe_gio___pe12___bit 12
534#define reg_pinmux_rw_pe_gio___pe13___lsb 13
535#define reg_pinmux_rw_pe_gio___pe13___width 1
536#define reg_pinmux_rw_pe_gio___pe13___bit 13
537#define reg_pinmux_rw_pe_gio___pe14___lsb 14
538#define reg_pinmux_rw_pe_gio___pe14___width 1
539#define reg_pinmux_rw_pe_gio___pe14___bit 14
540#define reg_pinmux_rw_pe_gio___pe15___lsb 15
541#define reg_pinmux_rw_pe_gio___pe15___width 1
542#define reg_pinmux_rw_pe_gio___pe15___bit 15
543#define reg_pinmux_rw_pe_gio___pe16___lsb 16
544#define reg_pinmux_rw_pe_gio___pe16___width 1
545#define reg_pinmux_rw_pe_gio___pe16___bit 16
546#define reg_pinmux_rw_pe_gio___pe17___lsb 17
547#define reg_pinmux_rw_pe_gio___pe17___width 1
548#define reg_pinmux_rw_pe_gio___pe17___bit 17
549#define reg_pinmux_rw_pe_gio_offset 32
550
551/* Register rw_pe_iop, scope pinmux, type rw */
552#define reg_pinmux_rw_pe_iop___pe0___lsb 0
553#define reg_pinmux_rw_pe_iop___pe0___width 1
554#define reg_pinmux_rw_pe_iop___pe0___bit 0
555#define reg_pinmux_rw_pe_iop___pe1___lsb 1
556#define reg_pinmux_rw_pe_iop___pe1___width 1
557#define reg_pinmux_rw_pe_iop___pe1___bit 1
558#define reg_pinmux_rw_pe_iop___pe2___lsb 2
559#define reg_pinmux_rw_pe_iop___pe2___width 1
560#define reg_pinmux_rw_pe_iop___pe2___bit 2
561#define reg_pinmux_rw_pe_iop___pe3___lsb 3
562#define reg_pinmux_rw_pe_iop___pe3___width 1
563#define reg_pinmux_rw_pe_iop___pe3___bit 3
564#define reg_pinmux_rw_pe_iop___pe4___lsb 4
565#define reg_pinmux_rw_pe_iop___pe4___width 1
566#define reg_pinmux_rw_pe_iop___pe4___bit 4
567#define reg_pinmux_rw_pe_iop___pe5___lsb 5
568#define reg_pinmux_rw_pe_iop___pe5___width 1
569#define reg_pinmux_rw_pe_iop___pe5___bit 5
570#define reg_pinmux_rw_pe_iop___pe6___lsb 6
571#define reg_pinmux_rw_pe_iop___pe6___width 1
572#define reg_pinmux_rw_pe_iop___pe6___bit 6
573#define reg_pinmux_rw_pe_iop___pe7___lsb 7
574#define reg_pinmux_rw_pe_iop___pe7___width 1
575#define reg_pinmux_rw_pe_iop___pe7___bit 7
576#define reg_pinmux_rw_pe_iop___pe8___lsb 8
577#define reg_pinmux_rw_pe_iop___pe8___width 1
578#define reg_pinmux_rw_pe_iop___pe8___bit 8
579#define reg_pinmux_rw_pe_iop___pe9___lsb 9
580#define reg_pinmux_rw_pe_iop___pe9___width 1
581#define reg_pinmux_rw_pe_iop___pe9___bit 9
582#define reg_pinmux_rw_pe_iop___pe10___lsb 10
583#define reg_pinmux_rw_pe_iop___pe10___width 1
584#define reg_pinmux_rw_pe_iop___pe10___bit 10
585#define reg_pinmux_rw_pe_iop___pe11___lsb 11
586#define reg_pinmux_rw_pe_iop___pe11___width 1
587#define reg_pinmux_rw_pe_iop___pe11___bit 11
588#define reg_pinmux_rw_pe_iop___pe12___lsb 12
589#define reg_pinmux_rw_pe_iop___pe12___width 1
590#define reg_pinmux_rw_pe_iop___pe12___bit 12
591#define reg_pinmux_rw_pe_iop___pe13___lsb 13
592#define reg_pinmux_rw_pe_iop___pe13___width 1
593#define reg_pinmux_rw_pe_iop___pe13___bit 13
594#define reg_pinmux_rw_pe_iop___pe14___lsb 14
595#define reg_pinmux_rw_pe_iop___pe14___width 1
596#define reg_pinmux_rw_pe_iop___pe14___bit 14
597#define reg_pinmux_rw_pe_iop___pe15___lsb 15
598#define reg_pinmux_rw_pe_iop___pe15___width 1
599#define reg_pinmux_rw_pe_iop___pe15___bit 15
600#define reg_pinmux_rw_pe_iop___pe16___lsb 16
601#define reg_pinmux_rw_pe_iop___pe16___width 1
602#define reg_pinmux_rw_pe_iop___pe16___bit 16
603#define reg_pinmux_rw_pe_iop___pe17___lsb 17
604#define reg_pinmux_rw_pe_iop___pe17___width 1
605#define reg_pinmux_rw_pe_iop___pe17___bit 17
606#define reg_pinmux_rw_pe_iop_offset 36
607
608/* Register rw_usb_phy, scope pinmux, type rw */
609#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0
610#define reg_pinmux_rw_usb_phy___en_usb0___width 1
611#define reg_pinmux_rw_usb_phy___en_usb0___bit 0
612#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1
613#define reg_pinmux_rw_usb_phy___en_usb1___width 1
614#define reg_pinmux_rw_usb_phy___en_usb1___bit 1
615#define reg_pinmux_rw_usb_phy_offset 40
616
617
618/* Constants */
619#define regk_pinmux_no 0x00000000
620#define regk_pinmux_rw_hwprot_default 0x00000000
621#define regk_pinmux_rw_pa_default 0x00000000
622#define regk_pinmux_rw_pb_gio_default 0x00000000
623#define regk_pinmux_rw_pb_iop_default 0x00000000
624#define regk_pinmux_rw_pc_gio_default 0x00000000
625#define regk_pinmux_rw_pc_iop_default 0x00000000
626#define regk_pinmux_rw_pd_gio_default 0x00000000
627#define regk_pinmux_rw_pd_iop_default 0x00000000
628#define regk_pinmux_rw_pe_gio_default 0x00000000
629#define regk_pinmux_rw_pe_iop_default 0x00000000
630#define regk_pinmux_rw_usb_phy_default 0x00000000
631#define regk_pinmux_yes 0x00000001
632#endif /* __pinmux_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h
new file mode 100644
index 000000000000..76959b70cd2c
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h
@@ -0,0 +1,96 @@
1#ifndef __reg_map_h
2#define __reg_map_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../mod/fakereg.rmap
7 * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
8 * last modified: Wed Feb 11 20:53:25 2004
9 * file: ../../rtl/global.rmap
10 * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
11 * last modified: Mon Aug 18 17:08:23 2003
12 * file: ../../mod/modreg.rmap
13 * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
14 * last modified: Fri Feb 20 16:40:04 2004
15 *
16 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
17 * id: $Id: reg_map_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
18 * Any changes here will be lost.
19 *
20 * -*- buffer-read-only: t -*-
21 */
22#define regi_artpec_mod 0xb7044000
23#define regi_ata 0xb0032000
24#define regi_ata_mod 0xb7006000
25#define regi_barber 0xb701a000
26#define regi_bif_core 0xb0014000
27#define regi_bif_dma 0xb0016000
28#define regi_bif_slave 0xb0018000
29#define regi_bif_slave_ext 0xac000000
30#define regi_bus_master 0xb703c000
31#define regi_config 0xb003c000
32#define regi_dma0 0xb0000000
33#define regi_dma1 0xb0002000
34#define regi_dma2 0xb0004000
35#define regi_dma3 0xb0006000
36#define regi_dma4 0xb0008000
37#define regi_dma5 0xb000a000
38#define regi_dma6 0xb000c000
39#define regi_dma7 0xb000e000
40#define regi_dma8 0xb0010000
41#define regi_dma9 0xb0012000
42#define regi_eth0 0xb0034000
43#define regi_eth1 0xb0036000
44#define regi_eth_mod 0xb7004000
45#define regi_eth_mod1 0xb701c000
46#define regi_eth_strmod 0xb7008000
47#define regi_eth_strmod1 0xb7032000
48#define regi_ext_dma 0xb703a000
49#define regi_ext_mem 0xb7046000
50#define regi_gen_io 0xb7016000
51#define regi_gio 0xb001a000
52#define regi_hook 0xb7000000
53#define regi_iop 0xb0020000
54#define regi_irq 0xb001c000
55#define regi_irq_nmi 0xb701e000
56#define regi_marb 0xb003e000
57#define regi_marb_bp0 0xb003e240
58#define regi_marb_bp1 0xb003e280
59#define regi_marb_bp2 0xb003e2c0
60#define regi_marb_bp3 0xb003e300
61#define regi_nand_mod 0xb7014000
62#define regi_p21 0xb002e000
63#define regi_p21_mod 0xb7042000
64#define regi_pci_mod 0xb7010000
65#define regi_pin_test 0xb7018000
66#define regi_pinmux 0xb0038000
67#define regi_sdram_chk 0xb703e000
68#define regi_sdram_mod 0xb7012000
69#define regi_ser0 0xb0026000
70#define regi_ser1 0xb0028000
71#define regi_ser2 0xb002a000
72#define regi_ser3 0xb002c000
73#define regi_ser_mod0 0xb7020000
74#define regi_ser_mod1 0xb7022000
75#define regi_ser_mod2 0xb7024000
76#define regi_ser_mod3 0xb7026000
77#define regi_smif_stat 0xb700e000
78#define regi_sser0 0xb0022000
79#define regi_sser1 0xb0024000
80#define regi_sser_mod0 0xb700a000
81#define regi_sser_mod1 0xb700c000
82#define regi_strcop 0xb0030000
83#define regi_strmux 0xb003a000
84#define regi_strmux_tst 0xb7040000
85#define regi_tap 0xb7002000
86#define regi_timer 0xb001e000
87#define regi_timer_mod 0xb7034000
88#define regi_trace 0xb0040000
89#define regi_usb0 0xb7028000
90#define regi_usb1 0xb702a000
91#define regi_usb2 0xb702c000
92#define regi_usb3 0xb702e000
93#define regi_usb_dev 0xb7030000
94#define regi_utmi_mod0 0xb7036000
95#define regi_utmi_mod1 0xb7038000
96#endif /* __reg_map_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h
new file mode 100644
index 000000000000..10246f49fb28
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h
@@ -0,0 +1,142 @@
1#ifndef __rt_trace_defs_asm_h
2#define __rt_trace_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/rt_trace/rtl/rt_regs.r
7 * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp
8 * last modfied: Mon Apr 11 16:09:14 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/rt_trace_defs_asm.h ../../inst/rt_trace/rtl/rt_regs.r
11 * id: $Id: rt_trace_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_cfg, scope rt_trace, type rw */
57#define reg_rt_trace_rw_cfg___en___lsb 0
58#define reg_rt_trace_rw_cfg___en___width 1
59#define reg_rt_trace_rw_cfg___en___bit 0
60#define reg_rt_trace_rw_cfg___mode___lsb 1
61#define reg_rt_trace_rw_cfg___mode___width 1
62#define reg_rt_trace_rw_cfg___mode___bit 1
63#define reg_rt_trace_rw_cfg___owner___lsb 2
64#define reg_rt_trace_rw_cfg___owner___width 1
65#define reg_rt_trace_rw_cfg___owner___bit 2
66#define reg_rt_trace_rw_cfg___wp___lsb 3
67#define reg_rt_trace_rw_cfg___wp___width 1
68#define reg_rt_trace_rw_cfg___wp___bit 3
69#define reg_rt_trace_rw_cfg___stall___lsb 4
70#define reg_rt_trace_rw_cfg___stall___width 1
71#define reg_rt_trace_rw_cfg___stall___bit 4
72#define reg_rt_trace_rw_cfg___wp_start___lsb 8
73#define reg_rt_trace_rw_cfg___wp_start___width 7
74#define reg_rt_trace_rw_cfg___wp_stop___lsb 16
75#define reg_rt_trace_rw_cfg___wp_stop___width 7
76#define reg_rt_trace_rw_cfg_offset 0
77
78/* Register rw_tap_ctrl, scope rt_trace, type rw */
79#define reg_rt_trace_rw_tap_ctrl___ack_data___lsb 0
80#define reg_rt_trace_rw_tap_ctrl___ack_data___width 1
81#define reg_rt_trace_rw_tap_ctrl___ack_data___bit 0
82#define reg_rt_trace_rw_tap_ctrl___ack_guru___lsb 1
83#define reg_rt_trace_rw_tap_ctrl___ack_guru___width 1
84#define reg_rt_trace_rw_tap_ctrl___ack_guru___bit 1
85#define reg_rt_trace_rw_tap_ctrl_offset 4
86
87/* Register r_tap_stat, scope rt_trace, type r */
88#define reg_rt_trace_r_tap_stat___dav___lsb 0
89#define reg_rt_trace_r_tap_stat___dav___width 1
90#define reg_rt_trace_r_tap_stat___dav___bit 0
91#define reg_rt_trace_r_tap_stat___empty___lsb 1
92#define reg_rt_trace_r_tap_stat___empty___width 1
93#define reg_rt_trace_r_tap_stat___empty___bit 1
94#define reg_rt_trace_r_tap_stat_offset 8
95
96/* Register rw_tap_data, scope rt_trace, type rw */
97#define reg_rt_trace_rw_tap_data_offset 12
98
99/* Register rw_tap_hdata, scope rt_trace, type rw */
100#define reg_rt_trace_rw_tap_hdata___op___lsb 0
101#define reg_rt_trace_rw_tap_hdata___op___width 4
102#define reg_rt_trace_rw_tap_hdata___sub_op___lsb 4
103#define reg_rt_trace_rw_tap_hdata___sub_op___width 4
104#define reg_rt_trace_rw_tap_hdata_offset 16
105
106/* Register r_redir, scope rt_trace, type r */
107#define reg_rt_trace_r_redir_offset 20
108
109
110/* Constants */
111#define regk_rt_trace_brk 0x0000000c
112#define regk_rt_trace_dbg 0x00000003
113#define regk_rt_trace_dbgdi 0x00000004
114#define regk_rt_trace_dbgdo 0x00000005
115#define regk_rt_trace_gmode 0x00000000
116#define regk_rt_trace_no 0x00000000
117#define regk_rt_trace_nop 0x00000000
118#define regk_rt_trace_normal 0x00000000
119#define regk_rt_trace_rdmem 0x00000007
120#define regk_rt_trace_rdmemb 0x00000009
121#define regk_rt_trace_rdpreg 0x00000002
122#define regk_rt_trace_rdreg 0x00000001
123#define regk_rt_trace_rdsreg 0x00000003
124#define regk_rt_trace_redir 0x00000006
125#define regk_rt_trace_ret 0x0000000b
126#define regk_rt_trace_rw_cfg_default 0x00000000
127#define regk_rt_trace_trcfg 0x00000001
128#define regk_rt_trace_wp 0x00000001
129#define regk_rt_trace_wp0 0x00000001
130#define regk_rt_trace_wp1 0x00000002
131#define regk_rt_trace_wp2 0x00000004
132#define regk_rt_trace_wp3 0x00000008
133#define regk_rt_trace_wp4 0x00000010
134#define regk_rt_trace_wp5 0x00000020
135#define regk_rt_trace_wp6 0x00000040
136#define regk_rt_trace_wrmem 0x00000008
137#define regk_rt_trace_wrmemb 0x0000000a
138#define regk_rt_trace_wrpreg 0x00000005
139#define regk_rt_trace_wrreg 0x00000004
140#define regk_rt_trace_wrsreg 0x00000006
141#define regk_rt_trace_yes 0x00000001
142#endif /* __rt_trace_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h
new file mode 100644
index 000000000000..4a2808bdf390
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h
@@ -0,0 +1,359 @@
1#ifndef __ser_defs_asm_h
2#define __ser_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/ser/rtl/ser_regs.r
7 * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp
8 * last modfied: Mon Apr 11 16:09:21 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r
11 * id: $Id: ser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_tr_ctrl, scope ser, type rw */
57#define reg_ser_rw_tr_ctrl___base_freq___lsb 0
58#define reg_ser_rw_tr_ctrl___base_freq___width 3
59#define reg_ser_rw_tr_ctrl___en___lsb 3
60#define reg_ser_rw_tr_ctrl___en___width 1
61#define reg_ser_rw_tr_ctrl___en___bit 3
62#define reg_ser_rw_tr_ctrl___par___lsb 4
63#define reg_ser_rw_tr_ctrl___par___width 2
64#define reg_ser_rw_tr_ctrl___par_en___lsb 6
65#define reg_ser_rw_tr_ctrl___par_en___width 1
66#define reg_ser_rw_tr_ctrl___par_en___bit 6
67#define reg_ser_rw_tr_ctrl___data_bits___lsb 7
68#define reg_ser_rw_tr_ctrl___data_bits___width 1
69#define reg_ser_rw_tr_ctrl___data_bits___bit 7
70#define reg_ser_rw_tr_ctrl___stop_bits___lsb 8
71#define reg_ser_rw_tr_ctrl___stop_bits___width 1
72#define reg_ser_rw_tr_ctrl___stop_bits___bit 8
73#define reg_ser_rw_tr_ctrl___stop___lsb 9
74#define reg_ser_rw_tr_ctrl___stop___width 1
75#define reg_ser_rw_tr_ctrl___stop___bit 9
76#define reg_ser_rw_tr_ctrl___rts_delay___lsb 10
77#define reg_ser_rw_tr_ctrl___rts_delay___width 3
78#define reg_ser_rw_tr_ctrl___rts_setup___lsb 13
79#define reg_ser_rw_tr_ctrl___rts_setup___width 1
80#define reg_ser_rw_tr_ctrl___rts_setup___bit 13
81#define reg_ser_rw_tr_ctrl___auto_rts___lsb 14
82#define reg_ser_rw_tr_ctrl___auto_rts___width 1
83#define reg_ser_rw_tr_ctrl___auto_rts___bit 14
84#define reg_ser_rw_tr_ctrl___txd___lsb 15
85#define reg_ser_rw_tr_ctrl___txd___width 1
86#define reg_ser_rw_tr_ctrl___txd___bit 15
87#define reg_ser_rw_tr_ctrl___auto_cts___lsb 16
88#define reg_ser_rw_tr_ctrl___auto_cts___width 1
89#define reg_ser_rw_tr_ctrl___auto_cts___bit 16
90#define reg_ser_rw_tr_ctrl_offset 0
91
92/* Register rw_tr_dma_en, scope ser, type rw */
93#define reg_ser_rw_tr_dma_en___en___lsb 0
94#define reg_ser_rw_tr_dma_en___en___width 1
95#define reg_ser_rw_tr_dma_en___en___bit 0
96#define reg_ser_rw_tr_dma_en_offset 4
97
98/* Register rw_rec_ctrl, scope ser, type rw */
99#define reg_ser_rw_rec_ctrl___base_freq___lsb 0
100#define reg_ser_rw_rec_ctrl___base_freq___width 3
101#define reg_ser_rw_rec_ctrl___en___lsb 3
102#define reg_ser_rw_rec_ctrl___en___width 1
103#define reg_ser_rw_rec_ctrl___en___bit 3
104#define reg_ser_rw_rec_ctrl___par___lsb 4
105#define reg_ser_rw_rec_ctrl___par___width 2
106#define reg_ser_rw_rec_ctrl___par_en___lsb 6
107#define reg_ser_rw_rec_ctrl___par_en___width 1
108#define reg_ser_rw_rec_ctrl___par_en___bit 6
109#define reg_ser_rw_rec_ctrl___data_bits___lsb 7
110#define reg_ser_rw_rec_ctrl___data_bits___width 1
111#define reg_ser_rw_rec_ctrl___data_bits___bit 7
112#define reg_ser_rw_rec_ctrl___dma_mode___lsb 8
113#define reg_ser_rw_rec_ctrl___dma_mode___width 1
114#define reg_ser_rw_rec_ctrl___dma_mode___bit 8
115#define reg_ser_rw_rec_ctrl___dma_err___lsb 9
116#define reg_ser_rw_rec_ctrl___dma_err___width 1
117#define reg_ser_rw_rec_ctrl___dma_err___bit 9
118#define reg_ser_rw_rec_ctrl___sampling___lsb 10
119#define reg_ser_rw_rec_ctrl___sampling___width 1
120#define reg_ser_rw_rec_ctrl___sampling___bit 10
121#define reg_ser_rw_rec_ctrl___timeout___lsb 11
122#define reg_ser_rw_rec_ctrl___timeout___width 3
123#define reg_ser_rw_rec_ctrl___auto_eop___lsb 14
124#define reg_ser_rw_rec_ctrl___auto_eop___width 1
125#define reg_ser_rw_rec_ctrl___auto_eop___bit 14
126#define reg_ser_rw_rec_ctrl___half_duplex___lsb 15
127#define reg_ser_rw_rec_ctrl___half_duplex___width 1
128#define reg_ser_rw_rec_ctrl___half_duplex___bit 15
129#define reg_ser_rw_rec_ctrl___rts_n___lsb 16
130#define reg_ser_rw_rec_ctrl___rts_n___width 1
131#define reg_ser_rw_rec_ctrl___rts_n___bit 16
132#define reg_ser_rw_rec_ctrl___loopback___lsb 17
133#define reg_ser_rw_rec_ctrl___loopback___width 1
134#define reg_ser_rw_rec_ctrl___loopback___bit 17
135#define reg_ser_rw_rec_ctrl_offset 8
136
137/* Register rw_tr_baud_div, scope ser, type rw */
138#define reg_ser_rw_tr_baud_div___div___lsb 0
139#define reg_ser_rw_tr_baud_div___div___width 16
140#define reg_ser_rw_tr_baud_div_offset 12
141
142/* Register rw_rec_baud_div, scope ser, type rw */
143#define reg_ser_rw_rec_baud_div___div___lsb 0
144#define reg_ser_rw_rec_baud_div___div___width 16
145#define reg_ser_rw_rec_baud_div_offset 16
146
147/* Register rw_xoff, scope ser, type rw */
148#define reg_ser_rw_xoff___chr___lsb 0
149#define reg_ser_rw_xoff___chr___width 8
150#define reg_ser_rw_xoff___automatic___lsb 8
151#define reg_ser_rw_xoff___automatic___width 1
152#define reg_ser_rw_xoff___automatic___bit 8
153#define reg_ser_rw_xoff_offset 20
154
155/* Register rw_xoff_clr, scope ser, type rw */
156#define reg_ser_rw_xoff_clr___clr___lsb 0
157#define reg_ser_rw_xoff_clr___clr___width 1
158#define reg_ser_rw_xoff_clr___clr___bit 0
159#define reg_ser_rw_xoff_clr_offset 24
160
161/* Register rw_dout, scope ser, type rw */
162#define reg_ser_rw_dout___data___lsb 0
163#define reg_ser_rw_dout___data___width 8
164#define reg_ser_rw_dout_offset 28
165
166/* Register rs_stat_din, scope ser, type rs */
167#define reg_ser_rs_stat_din___data___lsb 0
168#define reg_ser_rs_stat_din___data___width 8
169#define reg_ser_rs_stat_din___dav___lsb 16
170#define reg_ser_rs_stat_din___dav___width 1
171#define reg_ser_rs_stat_din___dav___bit 16
172#define reg_ser_rs_stat_din___framing_err___lsb 17
173#define reg_ser_rs_stat_din___framing_err___width 1
174#define reg_ser_rs_stat_din___framing_err___bit 17
175#define reg_ser_rs_stat_din___par_err___lsb 18
176#define reg_ser_rs_stat_din___par_err___width 1
177#define reg_ser_rs_stat_din___par_err___bit 18
178#define reg_ser_rs_stat_din___orun___lsb 19
179#define reg_ser_rs_stat_din___orun___width 1
180#define reg_ser_rs_stat_din___orun___bit 19
181#define reg_ser_rs_stat_din___rec_err___lsb 20
182#define reg_ser_rs_stat_din___rec_err___width 1
183#define reg_ser_rs_stat_din___rec_err___bit 20
184#define reg_ser_rs_stat_din___rxd___lsb 21
185#define reg_ser_rs_stat_din___rxd___width 1
186#define reg_ser_rs_stat_din___rxd___bit 21
187#define reg_ser_rs_stat_din___tr_idle___lsb 22
188#define reg_ser_rs_stat_din___tr_idle___width 1
189#define reg_ser_rs_stat_din___tr_idle___bit 22
190#define reg_ser_rs_stat_din___tr_empty___lsb 23
191#define reg_ser_rs_stat_din___tr_empty___width 1
192#define reg_ser_rs_stat_din___tr_empty___bit 23
193#define reg_ser_rs_stat_din___tr_rdy___lsb 24
194#define reg_ser_rs_stat_din___tr_rdy___width 1
195#define reg_ser_rs_stat_din___tr_rdy___bit 24
196#define reg_ser_rs_stat_din___cts_n___lsb 25
197#define reg_ser_rs_stat_din___cts_n___width 1
198#define reg_ser_rs_stat_din___cts_n___bit 25
199#define reg_ser_rs_stat_din___xoff_detect___lsb 26
200#define reg_ser_rs_stat_din___xoff_detect___width 1
201#define reg_ser_rs_stat_din___xoff_detect___bit 26
202#define reg_ser_rs_stat_din___rts_n___lsb 27
203#define reg_ser_rs_stat_din___rts_n___width 1
204#define reg_ser_rs_stat_din___rts_n___bit 27
205#define reg_ser_rs_stat_din___txd___lsb 28
206#define reg_ser_rs_stat_din___txd___width 1
207#define reg_ser_rs_stat_din___txd___bit 28
208#define reg_ser_rs_stat_din_offset 32
209
210/* Register r_stat_din, scope ser, type r */
211#define reg_ser_r_stat_din___data___lsb 0
212#define reg_ser_r_stat_din___data___width 8
213#define reg_ser_r_stat_din___dav___lsb 16
214#define reg_ser_r_stat_din___dav___width 1
215#define reg_ser_r_stat_din___dav___bit 16
216#define reg_ser_r_stat_din___framing_err___lsb 17
217#define reg_ser_r_stat_din___framing_err___width 1
218#define reg_ser_r_stat_din___framing_err___bit 17
219#define reg_ser_r_stat_din___par_err___lsb 18
220#define reg_ser_r_stat_din___par_err___width 1
221#define reg_ser_r_stat_din___par_err___bit 18
222#define reg_ser_r_stat_din___orun___lsb 19
223#define reg_ser_r_stat_din___orun___width 1
224#define reg_ser_r_stat_din___orun___bit 19
225#define reg_ser_r_stat_din___rec_err___lsb 20
226#define reg_ser_r_stat_din___rec_err___width 1
227#define reg_ser_r_stat_din___rec_err___bit 20
228#define reg_ser_r_stat_din___rxd___lsb 21
229#define reg_ser_r_stat_din___rxd___width 1
230#define reg_ser_r_stat_din___rxd___bit 21
231#define reg_ser_r_stat_din___tr_idle___lsb 22
232#define reg_ser_r_stat_din___tr_idle___width 1
233#define reg_ser_r_stat_din___tr_idle___bit 22
234#define reg_ser_r_stat_din___tr_empty___lsb 23
235#define reg_ser_r_stat_din___tr_empty___width 1
236#define reg_ser_r_stat_din___tr_empty___bit 23
237#define reg_ser_r_stat_din___tr_rdy___lsb 24
238#define reg_ser_r_stat_din___tr_rdy___width 1
239#define reg_ser_r_stat_din___tr_rdy___bit 24
240#define reg_ser_r_stat_din___cts_n___lsb 25
241#define reg_ser_r_stat_din___cts_n___width 1
242#define reg_ser_r_stat_din___cts_n___bit 25
243#define reg_ser_r_stat_din___xoff_detect___lsb 26
244#define reg_ser_r_stat_din___xoff_detect___width 1
245#define reg_ser_r_stat_din___xoff_detect___bit 26
246#define reg_ser_r_stat_din___rts_n___lsb 27
247#define reg_ser_r_stat_din___rts_n___width 1
248#define reg_ser_r_stat_din___rts_n___bit 27
249#define reg_ser_r_stat_din___txd___lsb 28
250#define reg_ser_r_stat_din___txd___width 1
251#define reg_ser_r_stat_din___txd___bit 28
252#define reg_ser_r_stat_din_offset 36
253
254/* Register rw_rec_eop, scope ser, type rw */
255#define reg_ser_rw_rec_eop___set___lsb 0
256#define reg_ser_rw_rec_eop___set___width 1
257#define reg_ser_rw_rec_eop___set___bit 0
258#define reg_ser_rw_rec_eop_offset 40
259
260/* Register rw_intr_mask, scope ser, type rw */
261#define reg_ser_rw_intr_mask___tr_rdy___lsb 0
262#define reg_ser_rw_intr_mask___tr_rdy___width 1
263#define reg_ser_rw_intr_mask___tr_rdy___bit 0
264#define reg_ser_rw_intr_mask___tr_empty___lsb 1
265#define reg_ser_rw_intr_mask___tr_empty___width 1
266#define reg_ser_rw_intr_mask___tr_empty___bit 1
267#define reg_ser_rw_intr_mask___tr_idle___lsb 2
268#define reg_ser_rw_intr_mask___tr_idle___width 1
269#define reg_ser_rw_intr_mask___tr_idle___bit 2
270#define reg_ser_rw_intr_mask___dav___lsb 3
271#define reg_ser_rw_intr_mask___dav___width 1
272#define reg_ser_rw_intr_mask___dav___bit 3
273#define reg_ser_rw_intr_mask_offset 44
274
275/* Register rw_ack_intr, scope ser, type rw */
276#define reg_ser_rw_ack_intr___tr_rdy___lsb 0
277#define reg_ser_rw_ack_intr___tr_rdy___width 1
278#define reg_ser_rw_ack_intr___tr_rdy___bit 0
279#define reg_ser_rw_ack_intr___tr_empty___lsb 1
280#define reg_ser_rw_ack_intr___tr_empty___width 1
281#define reg_ser_rw_ack_intr___tr_empty___bit 1
282#define reg_ser_rw_ack_intr___tr_idle___lsb 2
283#define reg_ser_rw_ack_intr___tr_idle___width 1
284#define reg_ser_rw_ack_intr___tr_idle___bit 2
285#define reg_ser_rw_ack_intr___dav___lsb 3
286#define reg_ser_rw_ack_intr___dav___width 1
287#define reg_ser_rw_ack_intr___dav___bit 3
288#define reg_ser_rw_ack_intr_offset 48
289
290/* Register r_intr, scope ser, type r */
291#define reg_ser_r_intr___tr_rdy___lsb 0
292#define reg_ser_r_intr___tr_rdy___width 1
293#define reg_ser_r_intr___tr_rdy___bit 0
294#define reg_ser_r_intr___tr_empty___lsb 1
295#define reg_ser_r_intr___tr_empty___width 1
296#define reg_ser_r_intr___tr_empty___bit 1
297#define reg_ser_r_intr___tr_idle___lsb 2
298#define reg_ser_r_intr___tr_idle___width 1
299#define reg_ser_r_intr___tr_idle___bit 2
300#define reg_ser_r_intr___dav___lsb 3
301#define reg_ser_r_intr___dav___width 1
302#define reg_ser_r_intr___dav___bit 3
303#define reg_ser_r_intr_offset 52
304
305/* Register r_masked_intr, scope ser, type r */
306#define reg_ser_r_masked_intr___tr_rdy___lsb 0
307#define reg_ser_r_masked_intr___tr_rdy___width 1
308#define reg_ser_r_masked_intr___tr_rdy___bit 0
309#define reg_ser_r_masked_intr___tr_empty___lsb 1
310#define reg_ser_r_masked_intr___tr_empty___width 1
311#define reg_ser_r_masked_intr___tr_empty___bit 1
312#define reg_ser_r_masked_intr___tr_idle___lsb 2
313#define reg_ser_r_masked_intr___tr_idle___width 1
314#define reg_ser_r_masked_intr___tr_idle___bit 2
315#define reg_ser_r_masked_intr___dav___lsb 3
316#define reg_ser_r_masked_intr___dav___width 1
317#define reg_ser_r_masked_intr___dav___bit 3
318#define reg_ser_r_masked_intr_offset 56
319
320
321/* Constants */
322#define regk_ser_active 0x00000000
323#define regk_ser_bits1 0x00000000
324#define regk_ser_bits2 0x00000001
325#define regk_ser_bits7 0x00000001
326#define regk_ser_bits8 0x00000000
327#define regk_ser_del0_5 0x00000000
328#define regk_ser_del1 0x00000001
329#define regk_ser_del1_5 0x00000002
330#define regk_ser_del2 0x00000003
331#define regk_ser_del2_5 0x00000004
332#define regk_ser_del3 0x00000005
333#define regk_ser_del3_5 0x00000006
334#define regk_ser_del4 0x00000007
335#define regk_ser_even 0x00000000
336#define regk_ser_ext 0x00000001
337#define regk_ser_f100 0x00000007
338#define regk_ser_f29_493 0x00000004
339#define regk_ser_f32 0x00000005
340#define regk_ser_f32_768 0x00000006
341#define regk_ser_ignore 0x00000001
342#define regk_ser_inactive 0x00000001
343#define regk_ser_majority 0x00000001
344#define regk_ser_mark 0x00000002
345#define regk_ser_middle 0x00000000
346#define regk_ser_no 0x00000000
347#define regk_ser_odd 0x00000001
348#define regk_ser_off 0x00000000
349#define regk_ser_rw_intr_mask_default 0x00000000
350#define regk_ser_rw_rec_baud_div_default 0x00000000
351#define regk_ser_rw_rec_ctrl_default 0x00010000
352#define regk_ser_rw_tr_baud_div_default 0x00000000
353#define regk_ser_rw_tr_ctrl_default 0x00008000
354#define regk_ser_rw_tr_dma_en_default 0x00000000
355#define regk_ser_rw_xoff_default 0x00000000
356#define regk_ser_space 0x00000003
357#define regk_ser_stop 0x00000000
358#define regk_ser_yes 0x00000001
359#endif /* __ser_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h
new file mode 100644
index 000000000000..27d4d91b3abd
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h
@@ -0,0 +1,462 @@
1#ifndef __sser_defs_asm_h
2#define __sser_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/syncser/rtl/sser_regs.r
7 * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp
8 * last modfied: Mon Apr 11 16:09:48 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r
11 * id: $Id: sser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_cfg, scope sser, type rw */
57#define reg_sser_rw_cfg___clk_div___lsb 0
58#define reg_sser_rw_cfg___clk_div___width 16
59#define reg_sser_rw_cfg___base_freq___lsb 16
60#define reg_sser_rw_cfg___base_freq___width 3
61#define reg_sser_rw_cfg___gate_clk___lsb 19
62#define reg_sser_rw_cfg___gate_clk___width 1
63#define reg_sser_rw_cfg___gate_clk___bit 19
64#define reg_sser_rw_cfg___clkgate_ctrl___lsb 20
65#define reg_sser_rw_cfg___clkgate_ctrl___width 1
66#define reg_sser_rw_cfg___clkgate_ctrl___bit 20
67#define reg_sser_rw_cfg___clkgate_in___lsb 21
68#define reg_sser_rw_cfg___clkgate_in___width 1
69#define reg_sser_rw_cfg___clkgate_in___bit 21
70#define reg_sser_rw_cfg___clk_dir___lsb 22
71#define reg_sser_rw_cfg___clk_dir___width 1
72#define reg_sser_rw_cfg___clk_dir___bit 22
73#define reg_sser_rw_cfg___clk_od_mode___lsb 23
74#define reg_sser_rw_cfg___clk_od_mode___width 1
75#define reg_sser_rw_cfg___clk_od_mode___bit 23
76#define reg_sser_rw_cfg___out_clk_pol___lsb 24
77#define reg_sser_rw_cfg___out_clk_pol___width 1
78#define reg_sser_rw_cfg___out_clk_pol___bit 24
79#define reg_sser_rw_cfg___out_clk_src___lsb 25
80#define reg_sser_rw_cfg___out_clk_src___width 2
81#define reg_sser_rw_cfg___clk_in_sel___lsb 27
82#define reg_sser_rw_cfg___clk_in_sel___width 1
83#define reg_sser_rw_cfg___clk_in_sel___bit 27
84#define reg_sser_rw_cfg___hold_pol___lsb 28
85#define reg_sser_rw_cfg___hold_pol___width 1
86#define reg_sser_rw_cfg___hold_pol___bit 28
87#define reg_sser_rw_cfg___prepare___lsb 29
88#define reg_sser_rw_cfg___prepare___width 1
89#define reg_sser_rw_cfg___prepare___bit 29
90#define reg_sser_rw_cfg___en___lsb 30
91#define reg_sser_rw_cfg___en___width 1
92#define reg_sser_rw_cfg___en___bit 30
93#define reg_sser_rw_cfg_offset 0
94
95/* Register rw_frm_cfg, scope sser, type rw */
96#define reg_sser_rw_frm_cfg___wordrate___lsb 0
97#define reg_sser_rw_frm_cfg___wordrate___width 10
98#define reg_sser_rw_frm_cfg___rec_delay___lsb 10
99#define reg_sser_rw_frm_cfg___rec_delay___width 3
100#define reg_sser_rw_frm_cfg___tr_delay___lsb 13
101#define reg_sser_rw_frm_cfg___tr_delay___width 3
102#define reg_sser_rw_frm_cfg___early_wend___lsb 16
103#define reg_sser_rw_frm_cfg___early_wend___width 1
104#define reg_sser_rw_frm_cfg___early_wend___bit 16
105#define reg_sser_rw_frm_cfg___level___lsb 17
106#define reg_sser_rw_frm_cfg___level___width 2
107#define reg_sser_rw_frm_cfg___type___lsb 19
108#define reg_sser_rw_frm_cfg___type___width 1
109#define reg_sser_rw_frm_cfg___type___bit 19
110#define reg_sser_rw_frm_cfg___clk_pol___lsb 20
111#define reg_sser_rw_frm_cfg___clk_pol___width 1
112#define reg_sser_rw_frm_cfg___clk_pol___bit 20
113#define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21
114#define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1
115#define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21
116#define reg_sser_rw_frm_cfg___clk_src___lsb 22
117#define reg_sser_rw_frm_cfg___clk_src___width 1
118#define reg_sser_rw_frm_cfg___clk_src___bit 22
119#define reg_sser_rw_frm_cfg___out_off___lsb 23
120#define reg_sser_rw_frm_cfg___out_off___width 1
121#define reg_sser_rw_frm_cfg___out_off___bit 23
122#define reg_sser_rw_frm_cfg___out_on___lsb 24
123#define reg_sser_rw_frm_cfg___out_on___width 1
124#define reg_sser_rw_frm_cfg___out_on___bit 24
125#define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25
126#define reg_sser_rw_frm_cfg___frame_pin_dir___width 1
127#define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25
128#define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26
129#define reg_sser_rw_frm_cfg___frame_pin_use___width 2
130#define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28
131#define reg_sser_rw_frm_cfg___status_pin_dir___width 1
132#define reg_sser_rw_frm_cfg___status_pin_dir___bit 28
133#define reg_sser_rw_frm_cfg___status_pin_use___lsb 29
134#define reg_sser_rw_frm_cfg___status_pin_use___width 2
135#define reg_sser_rw_frm_cfg_offset 4
136
137/* Register rw_tr_cfg, scope sser, type rw */
138#define reg_sser_rw_tr_cfg___tr_en___lsb 0
139#define reg_sser_rw_tr_cfg___tr_en___width 1
140#define reg_sser_rw_tr_cfg___tr_en___bit 0
141#define reg_sser_rw_tr_cfg___stop___lsb 1
142#define reg_sser_rw_tr_cfg___stop___width 1
143#define reg_sser_rw_tr_cfg___stop___bit 1
144#define reg_sser_rw_tr_cfg___urun_stop___lsb 2
145#define reg_sser_rw_tr_cfg___urun_stop___width 1
146#define reg_sser_rw_tr_cfg___urun_stop___bit 2
147#define reg_sser_rw_tr_cfg___eop_stop___lsb 3
148#define reg_sser_rw_tr_cfg___eop_stop___width 1
149#define reg_sser_rw_tr_cfg___eop_stop___bit 3
150#define reg_sser_rw_tr_cfg___sample_size___lsb 4
151#define reg_sser_rw_tr_cfg___sample_size___width 6
152#define reg_sser_rw_tr_cfg___sh_dir___lsb 10
153#define reg_sser_rw_tr_cfg___sh_dir___width 1
154#define reg_sser_rw_tr_cfg___sh_dir___bit 10
155#define reg_sser_rw_tr_cfg___clk_pol___lsb 11
156#define reg_sser_rw_tr_cfg___clk_pol___width 1
157#define reg_sser_rw_tr_cfg___clk_pol___bit 11
158#define reg_sser_rw_tr_cfg___clk_src___lsb 12
159#define reg_sser_rw_tr_cfg___clk_src___width 1
160#define reg_sser_rw_tr_cfg___clk_src___bit 12
161#define reg_sser_rw_tr_cfg___use_dma___lsb 13
162#define reg_sser_rw_tr_cfg___use_dma___width 1
163#define reg_sser_rw_tr_cfg___use_dma___bit 13
164#define reg_sser_rw_tr_cfg___mode___lsb 14
165#define reg_sser_rw_tr_cfg___mode___width 2
166#define reg_sser_rw_tr_cfg___frm_src___lsb 16
167#define reg_sser_rw_tr_cfg___frm_src___width 1
168#define reg_sser_rw_tr_cfg___frm_src___bit 16
169#define reg_sser_rw_tr_cfg___use60958___lsb 17
170#define reg_sser_rw_tr_cfg___use60958___width 1
171#define reg_sser_rw_tr_cfg___use60958___bit 17
172#define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18
173#define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2
174#define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20
175#define reg_sser_rw_tr_cfg___rate_ctrl___width 1
176#define reg_sser_rw_tr_cfg___rate_ctrl___bit 20
177#define reg_sser_rw_tr_cfg___use_md___lsb 21
178#define reg_sser_rw_tr_cfg___use_md___width 1
179#define reg_sser_rw_tr_cfg___use_md___bit 21
180#define reg_sser_rw_tr_cfg___dual_i2s___lsb 22
181#define reg_sser_rw_tr_cfg___dual_i2s___width 1
182#define reg_sser_rw_tr_cfg___dual_i2s___bit 22
183#define reg_sser_rw_tr_cfg___data_pin_use___lsb 23
184#define reg_sser_rw_tr_cfg___data_pin_use___width 2
185#define reg_sser_rw_tr_cfg___od_mode___lsb 25
186#define reg_sser_rw_tr_cfg___od_mode___width 1
187#define reg_sser_rw_tr_cfg___od_mode___bit 25
188#define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26
189#define reg_sser_rw_tr_cfg___bulk_wspace___width 2
190#define reg_sser_rw_tr_cfg_offset 8
191
192/* Register rw_rec_cfg, scope sser, type rw */
193#define reg_sser_rw_rec_cfg___rec_en___lsb 0
194#define reg_sser_rw_rec_cfg___rec_en___width 1
195#define reg_sser_rw_rec_cfg___rec_en___bit 0
196#define reg_sser_rw_rec_cfg___force_eop___lsb 1
197#define reg_sser_rw_rec_cfg___force_eop___width 1
198#define reg_sser_rw_rec_cfg___force_eop___bit 1
199#define reg_sser_rw_rec_cfg___stop___lsb 2
200#define reg_sser_rw_rec_cfg___stop___width 1
201#define reg_sser_rw_rec_cfg___stop___bit 2
202#define reg_sser_rw_rec_cfg___orun_stop___lsb 3
203#define reg_sser_rw_rec_cfg___orun_stop___width 1
204#define reg_sser_rw_rec_cfg___orun_stop___bit 3
205#define reg_sser_rw_rec_cfg___eop_stop___lsb 4
206#define reg_sser_rw_rec_cfg___eop_stop___width 1
207#define reg_sser_rw_rec_cfg___eop_stop___bit 4
208#define reg_sser_rw_rec_cfg___sample_size___lsb 5
209#define reg_sser_rw_rec_cfg___sample_size___width 6
210#define reg_sser_rw_rec_cfg___sh_dir___lsb 11
211#define reg_sser_rw_rec_cfg___sh_dir___width 1
212#define reg_sser_rw_rec_cfg___sh_dir___bit 11
213#define reg_sser_rw_rec_cfg___clk_pol___lsb 12
214#define reg_sser_rw_rec_cfg___clk_pol___width 1
215#define reg_sser_rw_rec_cfg___clk_pol___bit 12
216#define reg_sser_rw_rec_cfg___clk_src___lsb 13
217#define reg_sser_rw_rec_cfg___clk_src___width 1
218#define reg_sser_rw_rec_cfg___clk_src___bit 13
219#define reg_sser_rw_rec_cfg___use_dma___lsb 14
220#define reg_sser_rw_rec_cfg___use_dma___width 1
221#define reg_sser_rw_rec_cfg___use_dma___bit 14
222#define reg_sser_rw_rec_cfg___mode___lsb 15
223#define reg_sser_rw_rec_cfg___mode___width 2
224#define reg_sser_rw_rec_cfg___frm_src___lsb 17
225#define reg_sser_rw_rec_cfg___frm_src___width 2
226#define reg_sser_rw_rec_cfg___use60958___lsb 19
227#define reg_sser_rw_rec_cfg___use60958___width 1
228#define reg_sser_rw_rec_cfg___use60958___bit 19
229#define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20
230#define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5
231#define reg_sser_rw_rec_cfg___slave2_en___lsb 25
232#define reg_sser_rw_rec_cfg___slave2_en___width 1
233#define reg_sser_rw_rec_cfg___slave2_en___bit 25
234#define reg_sser_rw_rec_cfg___slave3_en___lsb 26
235#define reg_sser_rw_rec_cfg___slave3_en___width 1
236#define reg_sser_rw_rec_cfg___slave3_en___bit 26
237#define reg_sser_rw_rec_cfg___fifo_thr___lsb 27
238#define reg_sser_rw_rec_cfg___fifo_thr___width 2
239#define reg_sser_rw_rec_cfg_offset 12
240
241/* Register rw_tr_data, scope sser, type rw */
242#define reg_sser_rw_tr_data___data___lsb 0
243#define reg_sser_rw_tr_data___data___width 16
244#define reg_sser_rw_tr_data___md___lsb 16
245#define reg_sser_rw_tr_data___md___width 1
246#define reg_sser_rw_tr_data___md___bit 16
247#define reg_sser_rw_tr_data_offset 16
248
249/* Register r_rec_data, scope sser, type r */
250#define reg_sser_r_rec_data___data___lsb 0
251#define reg_sser_r_rec_data___data___width 16
252#define reg_sser_r_rec_data___md___lsb 16
253#define reg_sser_r_rec_data___md___width 1
254#define reg_sser_r_rec_data___md___bit 16
255#define reg_sser_r_rec_data___ext_clk___lsb 17
256#define reg_sser_r_rec_data___ext_clk___width 1
257#define reg_sser_r_rec_data___ext_clk___bit 17
258#define reg_sser_r_rec_data___status_in___lsb 18
259#define reg_sser_r_rec_data___status_in___width 1
260#define reg_sser_r_rec_data___status_in___bit 18
261#define reg_sser_r_rec_data___frame_in___lsb 19
262#define reg_sser_r_rec_data___frame_in___width 1
263#define reg_sser_r_rec_data___frame_in___bit 19
264#define reg_sser_r_rec_data___din___lsb 20
265#define reg_sser_r_rec_data___din___width 1
266#define reg_sser_r_rec_data___din___bit 20
267#define reg_sser_r_rec_data___data_in___lsb 21
268#define reg_sser_r_rec_data___data_in___width 1
269#define reg_sser_r_rec_data___data_in___bit 21
270#define reg_sser_r_rec_data___clk_in___lsb 22
271#define reg_sser_r_rec_data___clk_in___width 1
272#define reg_sser_r_rec_data___clk_in___bit 22
273#define reg_sser_r_rec_data_offset 20
274
275/* Register rw_extra, scope sser, type rw */
276#define reg_sser_rw_extra___clkoff_cycles___lsb 0
277#define reg_sser_rw_extra___clkoff_cycles___width 20
278#define reg_sser_rw_extra___clkoff_en___lsb 20
279#define reg_sser_rw_extra___clkoff_en___width 1
280#define reg_sser_rw_extra___clkoff_en___bit 20
281#define reg_sser_rw_extra___clkon_en___lsb 21
282#define reg_sser_rw_extra___clkon_en___width 1
283#define reg_sser_rw_extra___clkon_en___bit 21
284#define reg_sser_rw_extra___dout_delay___lsb 22
285#define reg_sser_rw_extra___dout_delay___width 5
286#define reg_sser_rw_extra_offset 24
287
288/* Register rw_intr_mask, scope sser, type rw */
289#define reg_sser_rw_intr_mask___trdy___lsb 0
290#define reg_sser_rw_intr_mask___trdy___width 1
291#define reg_sser_rw_intr_mask___trdy___bit 0
292#define reg_sser_rw_intr_mask___rdav___lsb 1
293#define reg_sser_rw_intr_mask___rdav___width 1
294#define reg_sser_rw_intr_mask___rdav___bit 1
295#define reg_sser_rw_intr_mask___tidle___lsb 2
296#define reg_sser_rw_intr_mask___tidle___width 1
297#define reg_sser_rw_intr_mask___tidle___bit 2
298#define reg_sser_rw_intr_mask___rstop___lsb 3
299#define reg_sser_rw_intr_mask___rstop___width 1
300#define reg_sser_rw_intr_mask___rstop___bit 3
301#define reg_sser_rw_intr_mask___urun___lsb 4
302#define reg_sser_rw_intr_mask___urun___width 1
303#define reg_sser_rw_intr_mask___urun___bit 4
304#define reg_sser_rw_intr_mask___orun___lsb 5
305#define reg_sser_rw_intr_mask___orun___width 1
306#define reg_sser_rw_intr_mask___orun___bit 5
307#define reg_sser_rw_intr_mask___md_rec___lsb 6
308#define reg_sser_rw_intr_mask___md_rec___width 1
309#define reg_sser_rw_intr_mask___md_rec___bit 6
310#define reg_sser_rw_intr_mask___md_sent___lsb 7
311#define reg_sser_rw_intr_mask___md_sent___width 1
312#define reg_sser_rw_intr_mask___md_sent___bit 7
313#define reg_sser_rw_intr_mask___r958err___lsb 8
314#define reg_sser_rw_intr_mask___r958err___width 1
315#define reg_sser_rw_intr_mask___r958err___bit 8
316#define reg_sser_rw_intr_mask_offset 28
317
318/* Register rw_ack_intr, scope sser, type rw */
319#define reg_sser_rw_ack_intr___trdy___lsb 0
320#define reg_sser_rw_ack_intr___trdy___width 1
321#define reg_sser_rw_ack_intr___trdy___bit 0
322#define reg_sser_rw_ack_intr___rdav___lsb 1
323#define reg_sser_rw_ack_intr___rdav___width 1
324#define reg_sser_rw_ack_intr___rdav___bit 1
325#define reg_sser_rw_ack_intr___tidle___lsb 2
326#define reg_sser_rw_ack_intr___tidle___width 1
327#define reg_sser_rw_ack_intr___tidle___bit 2
328#define reg_sser_rw_ack_intr___rstop___lsb 3
329#define reg_sser_rw_ack_intr___rstop___width 1
330#define reg_sser_rw_ack_intr___rstop___bit 3
331#define reg_sser_rw_ack_intr___urun___lsb 4
332#define reg_sser_rw_ack_intr___urun___width 1
333#define reg_sser_rw_ack_intr___urun___bit 4
334#define reg_sser_rw_ack_intr___orun___lsb 5
335#define reg_sser_rw_ack_intr___orun___width 1
336#define reg_sser_rw_ack_intr___orun___bit 5
337#define reg_sser_rw_ack_intr___md_rec___lsb 6
338#define reg_sser_rw_ack_intr___md_rec___width 1
339#define reg_sser_rw_ack_intr___md_rec___bit 6
340#define reg_sser_rw_ack_intr___md_sent___lsb 7
341#define reg_sser_rw_ack_intr___md_sent___width 1
342#define reg_sser_rw_ack_intr___md_sent___bit 7
343#define reg_sser_rw_ack_intr___r958err___lsb 8
344#define reg_sser_rw_ack_intr___r958err___width 1
345#define reg_sser_rw_ack_intr___r958err___bit 8
346#define reg_sser_rw_ack_intr_offset 32
347
348/* Register r_intr, scope sser, type r */
349#define reg_sser_r_intr___trdy___lsb 0
350#define reg_sser_r_intr___trdy___width 1
351#define reg_sser_r_intr___trdy___bit 0
352#define reg_sser_r_intr___rdav___lsb 1
353#define reg_sser_r_intr___rdav___width 1
354#define reg_sser_r_intr___rdav___bit 1
355#define reg_sser_r_intr___tidle___lsb 2
356#define reg_sser_r_intr___tidle___width 1
357#define reg_sser_r_intr___tidle___bit 2
358#define reg_sser_r_intr___rstop___lsb 3
359#define reg_sser_r_intr___rstop___width 1
360#define reg_sser_r_intr___rstop___bit 3
361#define reg_sser_r_intr___urun___lsb 4
362#define reg_sser_r_intr___urun___width 1
363#define reg_sser_r_intr___urun___bit 4
364#define reg_sser_r_intr___orun___lsb 5
365#define reg_sser_r_intr___orun___width 1
366#define reg_sser_r_intr___orun___bit 5
367#define reg_sser_r_intr___md_rec___lsb 6
368#define reg_sser_r_intr___md_rec___width 1
369#define reg_sser_r_intr___md_rec___bit 6
370#define reg_sser_r_intr___md_sent___lsb 7
371#define reg_sser_r_intr___md_sent___width 1
372#define reg_sser_r_intr___md_sent___bit 7
373#define reg_sser_r_intr___r958err___lsb 8
374#define reg_sser_r_intr___r958err___width 1
375#define reg_sser_r_intr___r958err___bit 8
376#define reg_sser_r_intr_offset 36
377
378/* Register r_masked_intr, scope sser, type r */
379#define reg_sser_r_masked_intr___trdy___lsb 0
380#define reg_sser_r_masked_intr___trdy___width 1
381#define reg_sser_r_masked_intr___trdy___bit 0
382#define reg_sser_r_masked_intr___rdav___lsb 1
383#define reg_sser_r_masked_intr___rdav___width 1
384#define reg_sser_r_masked_intr___rdav___bit 1
385#define reg_sser_r_masked_intr___tidle___lsb 2
386#define reg_sser_r_masked_intr___tidle___width 1
387#define reg_sser_r_masked_intr___tidle___bit 2
388#define reg_sser_r_masked_intr___rstop___lsb 3
389#define reg_sser_r_masked_intr___rstop___width 1
390#define reg_sser_r_masked_intr___rstop___bit 3
391#define reg_sser_r_masked_intr___urun___lsb 4
392#define reg_sser_r_masked_intr___urun___width 1
393#define reg_sser_r_masked_intr___urun___bit 4
394#define reg_sser_r_masked_intr___orun___lsb 5
395#define reg_sser_r_masked_intr___orun___width 1
396#define reg_sser_r_masked_intr___orun___bit 5
397#define reg_sser_r_masked_intr___md_rec___lsb 6
398#define reg_sser_r_masked_intr___md_rec___width 1
399#define reg_sser_r_masked_intr___md_rec___bit 6
400#define reg_sser_r_masked_intr___md_sent___lsb 7
401#define reg_sser_r_masked_intr___md_sent___width 1
402#define reg_sser_r_masked_intr___md_sent___bit 7
403#define reg_sser_r_masked_intr___r958err___lsb 8
404#define reg_sser_r_masked_intr___r958err___width 1
405#define reg_sser_r_masked_intr___r958err___bit 8
406#define reg_sser_r_masked_intr_offset 40
407
408
409/* Constants */
410#define regk_sser_both 0x00000002
411#define regk_sser_bulk 0x00000001
412#define regk_sser_clk100 0x00000000
413#define regk_sser_clk_in 0x00000000
414#define regk_sser_const0 0x00000003
415#define regk_sser_dout 0x00000002
416#define regk_sser_edge 0x00000000
417#define regk_sser_ext 0x00000001
418#define regk_sser_ext_clk 0x00000001
419#define regk_sser_f100 0x00000000
420#define regk_sser_f29_493 0x00000004
421#define regk_sser_f32 0x00000005
422#define regk_sser_f32_768 0x00000006
423#define regk_sser_frm 0x00000003
424#define regk_sser_gio0 0x00000000
425#define regk_sser_gio1 0x00000001
426#define regk_sser_hispeed 0x00000001
427#define regk_sser_hold 0x00000002
428#define regk_sser_in 0x00000000
429#define regk_sser_inf 0x00000003
430#define regk_sser_intern 0x00000000
431#define regk_sser_intern_clk 0x00000001
432#define regk_sser_intern_tb 0x00000000
433#define regk_sser_iso 0x00000000
434#define regk_sser_level 0x00000001
435#define regk_sser_lospeed 0x00000000
436#define regk_sser_lsbfirst 0x00000000
437#define regk_sser_msbfirst 0x00000001
438#define regk_sser_neg 0x00000001
439#define regk_sser_neg_lo 0x00000000
440#define regk_sser_no 0x00000000
441#define regk_sser_no_clk 0x00000007
442#define regk_sser_nojitter 0x00000002
443#define regk_sser_out 0x00000001
444#define regk_sser_pos 0x00000000
445#define regk_sser_pos_hi 0x00000001
446#define regk_sser_rec 0x00000000
447#define regk_sser_rw_cfg_default 0x00000000
448#define regk_sser_rw_extra_default 0x00000000
449#define regk_sser_rw_frm_cfg_default 0x00000000
450#define regk_sser_rw_intr_mask_default 0x00000000
451#define regk_sser_rw_rec_cfg_default 0x00000000
452#define regk_sser_rw_tr_cfg_default 0x01800000
453#define regk_sser_rw_tr_data_default 0x00000000
454#define regk_sser_thr16 0x00000001
455#define regk_sser_thr32 0x00000002
456#define regk_sser_thr8 0x00000000
457#define regk_sser_tr 0x00000001
458#define regk_sser_ts_out 0x00000003
459#define regk_sser_tx_bulk 0x00000002
460#define regk_sser_wiresave 0x00000002
461#define regk_sser_yes 0x00000001
462#endif /* __sser_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h
new file mode 100644
index 000000000000..55083e6aec93
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h
@@ -0,0 +1,84 @@
1#ifndef __strcop_defs_asm_h
2#define __strcop_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/strcop/rtl/strcop_regs.r
7 * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp
8 * last modfied: Mon Apr 11 16:09:38 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r
11 * id: $Id: strcop_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_cfg, scope strcop, type rw */
57#define reg_strcop_rw_cfg___td3___lsb 0
58#define reg_strcop_rw_cfg___td3___width 1
59#define reg_strcop_rw_cfg___td3___bit 0
60#define reg_strcop_rw_cfg___td2___lsb 1
61#define reg_strcop_rw_cfg___td2___width 1
62#define reg_strcop_rw_cfg___td2___bit 1
63#define reg_strcop_rw_cfg___td1___lsb 2
64#define reg_strcop_rw_cfg___td1___width 1
65#define reg_strcop_rw_cfg___td1___bit 2
66#define reg_strcop_rw_cfg___ipend___lsb 3
67#define reg_strcop_rw_cfg___ipend___width 1
68#define reg_strcop_rw_cfg___ipend___bit 3
69#define reg_strcop_rw_cfg___ignore_sync___lsb 4
70#define reg_strcop_rw_cfg___ignore_sync___width 1
71#define reg_strcop_rw_cfg___ignore_sync___bit 4
72#define reg_strcop_rw_cfg___en___lsb 5
73#define reg_strcop_rw_cfg___en___width 1
74#define reg_strcop_rw_cfg___en___bit 5
75#define reg_strcop_rw_cfg_offset 0
76
77
78/* Constants */
79#define regk_strcop_big 0x00000001
80#define regk_strcop_d 0x00000001
81#define regk_strcop_e 0x00000000
82#define regk_strcop_little 0x00000000
83#define regk_strcop_rw_cfg_default 0x00000002
84#endif /* __strcop_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h
new file mode 100644
index 000000000000..69b299920f71
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h
@@ -0,0 +1,100 @@
1#ifndef __strmux_defs_asm_h
2#define __strmux_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/strmux/rtl/guinness/strmux_regs.r
7 * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
8 * last modfied: Mon Apr 11 16:09:43 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strmux_defs_asm.h ../../inst/strmux/rtl/guinness/strmux_regs.r
11 * id: $Id: strmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_cfg, scope strmux, type rw */
57#define reg_strmux_rw_cfg___dma0___lsb 0
58#define reg_strmux_rw_cfg___dma0___width 3
59#define reg_strmux_rw_cfg___dma1___lsb 3
60#define reg_strmux_rw_cfg___dma1___width 3
61#define reg_strmux_rw_cfg___dma2___lsb 6
62#define reg_strmux_rw_cfg___dma2___width 3
63#define reg_strmux_rw_cfg___dma3___lsb 9
64#define reg_strmux_rw_cfg___dma3___width 3
65#define reg_strmux_rw_cfg___dma4___lsb 12
66#define reg_strmux_rw_cfg___dma4___width 3
67#define reg_strmux_rw_cfg___dma5___lsb 15
68#define reg_strmux_rw_cfg___dma5___width 3
69#define reg_strmux_rw_cfg___dma6___lsb 18
70#define reg_strmux_rw_cfg___dma6___width 3
71#define reg_strmux_rw_cfg___dma7___lsb 21
72#define reg_strmux_rw_cfg___dma7___width 3
73#define reg_strmux_rw_cfg___dma8___lsb 24
74#define reg_strmux_rw_cfg___dma8___width 3
75#define reg_strmux_rw_cfg___dma9___lsb 27
76#define reg_strmux_rw_cfg___dma9___width 3
77#define reg_strmux_rw_cfg_offset 0
78
79
80/* Constants */
81#define regk_strmux_ata 0x00000003
82#define regk_strmux_eth0 0x00000001
83#define regk_strmux_eth1 0x00000004
84#define regk_strmux_ext0 0x00000001
85#define regk_strmux_ext1 0x00000001
86#define regk_strmux_ext2 0x00000001
87#define regk_strmux_ext3 0x00000001
88#define regk_strmux_iop0 0x00000002
89#define regk_strmux_iop1 0x00000001
90#define regk_strmux_off 0x00000000
91#define regk_strmux_p21 0x00000004
92#define regk_strmux_rw_cfg_default 0x00000000
93#define regk_strmux_ser0 0x00000002
94#define regk_strmux_ser1 0x00000002
95#define regk_strmux_ser2 0x00000004
96#define regk_strmux_ser3 0x00000003
97#define regk_strmux_sser0 0x00000003
98#define regk_strmux_sser1 0x00000003
99#define regk_strmux_strcop 0x00000002
100#endif /* __strmux_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h
new file mode 100644
index 000000000000..43146021fc16
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h
@@ -0,0 +1,229 @@
1#ifndef __timer_defs_asm_h
2#define __timer_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/timer/rtl/timer_regs.r
7 * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
8 * last modfied: Mon Apr 11 16:09:53 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
11 * id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_tmr0_div, scope timer, type rw */
57#define reg_timer_rw_tmr0_div_offset 0
58
59/* Register r_tmr0_data, scope timer, type r */
60#define reg_timer_r_tmr0_data_offset 4
61
62/* Register rw_tmr0_ctrl, scope timer, type rw */
63#define reg_timer_rw_tmr0_ctrl___op___lsb 0
64#define reg_timer_rw_tmr0_ctrl___op___width 2
65#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
66#define reg_timer_rw_tmr0_ctrl___freq___width 3
67#define reg_timer_rw_tmr0_ctrl_offset 8
68
69/* Register rw_tmr1_div, scope timer, type rw */
70#define reg_timer_rw_tmr1_div_offset 16
71
72/* Register r_tmr1_data, scope timer, type r */
73#define reg_timer_r_tmr1_data_offset 20
74
75/* Register rw_tmr1_ctrl, scope timer, type rw */
76#define reg_timer_rw_tmr1_ctrl___op___lsb 0
77#define reg_timer_rw_tmr1_ctrl___op___width 2
78#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
79#define reg_timer_rw_tmr1_ctrl___freq___width 3
80#define reg_timer_rw_tmr1_ctrl_offset 24
81
82/* Register rs_cnt_data, scope timer, type rs */
83#define reg_timer_rs_cnt_data___tmr___lsb 0
84#define reg_timer_rs_cnt_data___tmr___width 24
85#define reg_timer_rs_cnt_data___cnt___lsb 24
86#define reg_timer_rs_cnt_data___cnt___width 8
87#define reg_timer_rs_cnt_data_offset 32
88
89/* Register r_cnt_data, scope timer, type r */
90#define reg_timer_r_cnt_data___tmr___lsb 0
91#define reg_timer_r_cnt_data___tmr___width 24
92#define reg_timer_r_cnt_data___cnt___lsb 24
93#define reg_timer_r_cnt_data___cnt___width 8
94#define reg_timer_r_cnt_data_offset 36
95
96/* Register rw_cnt_cfg, scope timer, type rw */
97#define reg_timer_rw_cnt_cfg___clk___lsb 0
98#define reg_timer_rw_cnt_cfg___clk___width 2
99#define reg_timer_rw_cnt_cfg_offset 40
100
101/* Register rw_trig, scope timer, type rw */
102#define reg_timer_rw_trig_offset 48
103
104/* Register rw_trig_cfg, scope timer, type rw */
105#define reg_timer_rw_trig_cfg___tmr___lsb 0
106#define reg_timer_rw_trig_cfg___tmr___width 2
107#define reg_timer_rw_trig_cfg_offset 52
108
109/* Register r_time, scope timer, type r */
110#define reg_timer_r_time_offset 56
111
112/* Register rw_out, scope timer, type rw */
113#define reg_timer_rw_out___tmr___lsb 0
114#define reg_timer_rw_out___tmr___width 2
115#define reg_timer_rw_out_offset 60
116
117/* Register rw_wd_ctrl, scope timer, type rw */
118#define reg_timer_rw_wd_ctrl___cnt___lsb 0
119#define reg_timer_rw_wd_ctrl___cnt___width 8
120#define reg_timer_rw_wd_ctrl___cmd___lsb 8
121#define reg_timer_rw_wd_ctrl___cmd___width 1
122#define reg_timer_rw_wd_ctrl___cmd___bit 8
123#define reg_timer_rw_wd_ctrl___key___lsb 9
124#define reg_timer_rw_wd_ctrl___key___width 7
125#define reg_timer_rw_wd_ctrl_offset 64
126
127/* Register r_wd_stat, scope timer, type r */
128#define reg_timer_r_wd_stat___cnt___lsb 0
129#define reg_timer_r_wd_stat___cnt___width 8
130#define reg_timer_r_wd_stat___cmd___lsb 8
131#define reg_timer_r_wd_stat___cmd___width 1
132#define reg_timer_r_wd_stat___cmd___bit 8
133#define reg_timer_r_wd_stat_offset 68
134
135/* Register rw_intr_mask, scope timer, type rw */
136#define reg_timer_rw_intr_mask___tmr0___lsb 0
137#define reg_timer_rw_intr_mask___tmr0___width 1
138#define reg_timer_rw_intr_mask___tmr0___bit 0
139#define reg_timer_rw_intr_mask___tmr1___lsb 1
140#define reg_timer_rw_intr_mask___tmr1___width 1
141#define reg_timer_rw_intr_mask___tmr1___bit 1
142#define reg_timer_rw_intr_mask___cnt___lsb 2
143#define reg_timer_rw_intr_mask___cnt___width 1
144#define reg_timer_rw_intr_mask___cnt___bit 2
145#define reg_timer_rw_intr_mask___trig___lsb 3
146#define reg_timer_rw_intr_mask___trig___width 1
147#define reg_timer_rw_intr_mask___trig___bit 3
148#define reg_timer_rw_intr_mask_offset 72
149
150/* Register rw_ack_intr, scope timer, type rw */
151#define reg_timer_rw_ack_intr___tmr0___lsb 0
152#define reg_timer_rw_ack_intr___tmr0___width 1
153#define reg_timer_rw_ack_intr___tmr0___bit 0
154#define reg_timer_rw_ack_intr___tmr1___lsb 1
155#define reg_timer_rw_ack_intr___tmr1___width 1
156#define reg_timer_rw_ack_intr___tmr1___bit 1
157#define reg_timer_rw_ack_intr___cnt___lsb 2
158#define reg_timer_rw_ack_intr___cnt___width 1
159#define reg_timer_rw_ack_intr___cnt___bit 2
160#define reg_timer_rw_ack_intr___trig___lsb 3
161#define reg_timer_rw_ack_intr___trig___width 1
162#define reg_timer_rw_ack_intr___trig___bit 3
163#define reg_timer_rw_ack_intr_offset 76
164
165/* Register r_intr, scope timer, type r */
166#define reg_timer_r_intr___tmr0___lsb 0
167#define reg_timer_r_intr___tmr0___width 1
168#define reg_timer_r_intr___tmr0___bit 0
169#define reg_timer_r_intr___tmr1___lsb 1
170#define reg_timer_r_intr___tmr1___width 1
171#define reg_timer_r_intr___tmr1___bit 1
172#define reg_timer_r_intr___cnt___lsb 2
173#define reg_timer_r_intr___cnt___width 1
174#define reg_timer_r_intr___cnt___bit 2
175#define reg_timer_r_intr___trig___lsb 3
176#define reg_timer_r_intr___trig___width 1
177#define reg_timer_r_intr___trig___bit 3
178#define reg_timer_r_intr_offset 80
179
180/* Register r_masked_intr, scope timer, type r */
181#define reg_timer_r_masked_intr___tmr0___lsb 0
182#define reg_timer_r_masked_intr___tmr0___width 1
183#define reg_timer_r_masked_intr___tmr0___bit 0
184#define reg_timer_r_masked_intr___tmr1___lsb 1
185#define reg_timer_r_masked_intr___tmr1___width 1
186#define reg_timer_r_masked_intr___tmr1___bit 1
187#define reg_timer_r_masked_intr___cnt___lsb 2
188#define reg_timer_r_masked_intr___cnt___width 1
189#define reg_timer_r_masked_intr___cnt___bit 2
190#define reg_timer_r_masked_intr___trig___lsb 3
191#define reg_timer_r_masked_intr___trig___width 1
192#define reg_timer_r_masked_intr___trig___bit 3
193#define reg_timer_r_masked_intr_offset 84
194
195/* Register rw_test, scope timer, type rw */
196#define reg_timer_rw_test___dis___lsb 0
197#define reg_timer_rw_test___dis___width 1
198#define reg_timer_rw_test___dis___bit 0
199#define reg_timer_rw_test___en___lsb 1
200#define reg_timer_rw_test___en___width 1
201#define reg_timer_rw_test___en___bit 1
202#define reg_timer_rw_test_offset 88
203
204
205/* Constants */
206#define regk_timer_ext 0x00000001
207#define regk_timer_f100 0x00000007
208#define regk_timer_f29_493 0x00000004
209#define regk_timer_f32 0x00000005
210#define regk_timer_f32_768 0x00000006
211#define regk_timer_hold 0x00000001
212#define regk_timer_ld 0x00000000
213#define regk_timer_no 0x00000000
214#define regk_timer_off 0x00000000
215#define regk_timer_run 0x00000002
216#define regk_timer_rw_cnt_cfg_default 0x00000000
217#define regk_timer_rw_intr_mask_default 0x00000000
218#define regk_timer_rw_out_default 0x00000000
219#define regk_timer_rw_test_default 0x00000000
220#define regk_timer_rw_tmr0_ctrl_default 0x00000000
221#define regk_timer_rw_tmr1_ctrl_default 0x00000000
222#define regk_timer_rw_trig_cfg_default 0x00000000
223#define regk_timer_start 0x00000001
224#define regk_timer_stop 0x00000000
225#define regk_timer_time 0x00000001
226#define regk_timer_tmr0 0x00000002
227#define regk_timer_tmr1 0x00000003
228#define regk_timer_yes 0x00000001
229#endif /* __timer_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/ata_defs.h b/include/asm-cris/arch-v32/hwregs/ata_defs.h
new file mode 100644
index 000000000000..43b6643ff0d3
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/ata_defs.h
@@ -0,0 +1,222 @@
1#ifndef __ata_defs_h
2#define __ata_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/ata/rtl/ata_regs.r
7 * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
8 * last modfied: Mon Apr 11 16:06:25 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r
11 * id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope ata */
86
87/* Register rw_ctrl0, scope ata, type rw */
88typedef struct {
89 unsigned int pio_hold : 6;
90 unsigned int pio_strb : 6;
91 unsigned int pio_setup : 6;
92 unsigned int dma_hold : 6;
93 unsigned int dma_strb : 6;
94 unsigned int rst : 1;
95 unsigned int en : 1;
96} reg_ata_rw_ctrl0;
97#define REG_RD_ADDR_ata_rw_ctrl0 12
98#define REG_WR_ADDR_ata_rw_ctrl0 12
99
100/* Register rw_ctrl1, scope ata, type rw */
101typedef struct {
102 unsigned int udma_tcyc : 4;
103 unsigned int udma_tdvs : 4;
104 unsigned int dummy1 : 24;
105} reg_ata_rw_ctrl1;
106#define REG_RD_ADDR_ata_rw_ctrl1 16
107#define REG_WR_ADDR_ata_rw_ctrl1 16
108
109/* Register rw_ctrl2, scope ata, type rw */
110typedef struct {
111 unsigned int data : 16;
112 unsigned int dummy1 : 3;
113 unsigned int dma_size : 1;
114 unsigned int multi : 1;
115 unsigned int hsh : 2;
116 unsigned int trf_mode : 1;
117 unsigned int rw : 1;
118 unsigned int addr : 3;
119 unsigned int cs0 : 1;
120 unsigned int cs1 : 1;
121 unsigned int sel : 2;
122} reg_ata_rw_ctrl2;
123#define REG_RD_ADDR_ata_rw_ctrl2 0
124#define REG_WR_ADDR_ata_rw_ctrl2 0
125
126/* Register rs_stat_data, scope ata, type rs */
127typedef struct {
128 unsigned int data : 16;
129 unsigned int dav : 1;
130 unsigned int busy : 1;
131 unsigned int dummy1 : 14;
132} reg_ata_rs_stat_data;
133#define REG_RD_ADDR_ata_rs_stat_data 4
134
135/* Register r_stat_data, scope ata, type r */
136typedef struct {
137 unsigned int data : 16;
138 unsigned int dav : 1;
139 unsigned int busy : 1;
140 unsigned int dummy1 : 14;
141} reg_ata_r_stat_data;
142#define REG_RD_ADDR_ata_r_stat_data 8
143
144/* Register rw_trf_cnt, scope ata, type rw */
145typedef struct {
146 unsigned int cnt : 17;
147 unsigned int dummy1 : 15;
148} reg_ata_rw_trf_cnt;
149#define REG_RD_ADDR_ata_rw_trf_cnt 20
150#define REG_WR_ADDR_ata_rw_trf_cnt 20
151
152/* Register r_stat_misc, scope ata, type r */
153typedef struct {
154 unsigned int crc : 16;
155 unsigned int dummy1 : 16;
156} reg_ata_r_stat_misc;
157#define REG_RD_ADDR_ata_r_stat_misc 24
158
159/* Register rw_intr_mask, scope ata, type rw */
160typedef struct {
161 unsigned int bus0 : 1;
162 unsigned int bus1 : 1;
163 unsigned int bus2 : 1;
164 unsigned int bus3 : 1;
165 unsigned int dummy1 : 28;
166} reg_ata_rw_intr_mask;
167#define REG_RD_ADDR_ata_rw_intr_mask 28
168#define REG_WR_ADDR_ata_rw_intr_mask 28
169
170/* Register rw_ack_intr, scope ata, type rw */
171typedef struct {
172 unsigned int bus0 : 1;
173 unsigned int bus1 : 1;
174 unsigned int bus2 : 1;
175 unsigned int bus3 : 1;
176 unsigned int dummy1 : 28;
177} reg_ata_rw_ack_intr;
178#define REG_RD_ADDR_ata_rw_ack_intr 32
179#define REG_WR_ADDR_ata_rw_ack_intr 32
180
181/* Register r_intr, scope ata, type r */
182typedef struct {
183 unsigned int bus0 : 1;
184 unsigned int bus1 : 1;
185 unsigned int bus2 : 1;
186 unsigned int bus3 : 1;
187 unsigned int dummy1 : 28;
188} reg_ata_r_intr;
189#define REG_RD_ADDR_ata_r_intr 36
190
191/* Register r_masked_intr, scope ata, type r */
192typedef struct {
193 unsigned int bus0 : 1;
194 unsigned int bus1 : 1;
195 unsigned int bus2 : 1;
196 unsigned int bus3 : 1;
197 unsigned int dummy1 : 28;
198} reg_ata_r_masked_intr;
199#define REG_RD_ADDR_ata_r_masked_intr 40
200
201
202/* Constants */
203enum {
204 regk_ata_active = 0x00000001,
205 regk_ata_byte = 0x00000001,
206 regk_ata_data = 0x00000001,
207 regk_ata_dma = 0x00000001,
208 regk_ata_inactive = 0x00000000,
209 regk_ata_no = 0x00000000,
210 regk_ata_nodata = 0x00000000,
211 regk_ata_pio = 0x00000000,
212 regk_ata_rd = 0x00000001,
213 regk_ata_reg = 0x00000000,
214 regk_ata_rw_ctrl0_default = 0x00000000,
215 regk_ata_rw_ctrl2_default = 0x00000000,
216 regk_ata_rw_intr_mask_default = 0x00000000,
217 regk_ata_udma = 0x00000002,
218 regk_ata_word = 0x00000000,
219 regk_ata_wr = 0x00000000,
220 regk_ata_yes = 0x00000001
221};
222#endif /* __ata_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/bif_core_defs.h b/include/asm-cris/arch-v32/hwregs/bif_core_defs.h
new file mode 100644
index 000000000000..a56608b50359
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/bif_core_defs.h
@@ -0,0 +1,284 @@
1#ifndef __bif_core_defs_h
2#define __bif_core_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/bif/rtl/bif_core_regs.r
7 * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
8 * last modfied: Mon Apr 11 16:06:33 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
11 * id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope bif_core */
86
87/* Register rw_grp1_cfg, scope bif_core, type rw */
88typedef struct {
89 unsigned int lw : 6;
90 unsigned int ew : 3;
91 unsigned int zw : 3;
92 unsigned int aw : 2;
93 unsigned int dw : 2;
94 unsigned int ewb : 2;
95 unsigned int bw : 1;
96 unsigned int wr_extend : 1;
97 unsigned int erc_en : 1;
98 unsigned int mode : 1;
99 unsigned int dummy1 : 10;
100} reg_bif_core_rw_grp1_cfg;
101#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0
102#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0
103
104/* Register rw_grp2_cfg, scope bif_core, type rw */
105typedef struct {
106 unsigned int lw : 6;
107 unsigned int ew : 3;
108 unsigned int zw : 3;
109 unsigned int aw : 2;
110 unsigned int dw : 2;
111 unsigned int ewb : 2;
112 unsigned int bw : 1;
113 unsigned int wr_extend : 1;
114 unsigned int erc_en : 1;
115 unsigned int mode : 1;
116 unsigned int dummy1 : 10;
117} reg_bif_core_rw_grp2_cfg;
118#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
119#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
120
121/* Register rw_grp3_cfg, scope bif_core, type rw */
122typedef struct {
123 unsigned int lw : 6;
124 unsigned int ew : 3;
125 unsigned int zw : 3;
126 unsigned int aw : 2;
127 unsigned int dw : 2;
128 unsigned int ewb : 2;
129 unsigned int bw : 1;
130 unsigned int wr_extend : 1;
131 unsigned int erc_en : 1;
132 unsigned int mode : 1;
133 unsigned int dummy1 : 2;
134 unsigned int gated_csp0 : 2;
135 unsigned int gated_csp1 : 2;
136 unsigned int gated_csp2 : 2;
137 unsigned int gated_csp3 : 2;
138} reg_bif_core_rw_grp3_cfg;
139#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8
140#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8
141
142/* Register rw_grp4_cfg, scope bif_core, type rw */
143typedef struct {
144 unsigned int lw : 6;
145 unsigned int ew : 3;
146 unsigned int zw : 3;
147 unsigned int aw : 2;
148 unsigned int dw : 2;
149 unsigned int ewb : 2;
150 unsigned int bw : 1;
151 unsigned int wr_extend : 1;
152 unsigned int erc_en : 1;
153 unsigned int mode : 1;
154 unsigned int dummy1 : 4;
155 unsigned int gated_csp4 : 2;
156 unsigned int gated_csp5 : 2;
157 unsigned int gated_csp6 : 2;
158} reg_bif_core_rw_grp4_cfg;
159#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12
160#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12
161
162/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
163typedef struct {
164 unsigned int bank_sel : 5;
165 unsigned int ca : 3;
166 unsigned int type : 1;
167 unsigned int bw : 1;
168 unsigned int sh : 3;
169 unsigned int wmm : 1;
170 unsigned int sh16 : 1;
171 unsigned int grp_sel : 5;
172 unsigned int dummy1 : 12;
173} reg_bif_core_rw_sdram_cfg_grp0;
174#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16
175#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16
176
177/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
178typedef struct {
179 unsigned int bank_sel : 5;
180 unsigned int ca : 3;
181 unsigned int type : 1;
182 unsigned int bw : 1;
183 unsigned int sh : 3;
184 unsigned int wmm : 1;
185 unsigned int sh16 : 1;
186 unsigned int dummy1 : 17;
187} reg_bif_core_rw_sdram_cfg_grp1;
188#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20
189#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20
190
191/* Register rw_sdram_timing, scope bif_core, type rw */
192typedef struct {
193 unsigned int cl : 3;
194 unsigned int rcd : 3;
195 unsigned int rp : 3;
196 unsigned int rc : 2;
197 unsigned int dpl : 2;
198 unsigned int pde : 1;
199 unsigned int ref : 2;
200 unsigned int cpd : 1;
201 unsigned int sdcke : 1;
202 unsigned int sdclk : 1;
203 unsigned int dummy1 : 13;
204} reg_bif_core_rw_sdram_timing;
205#define REG_RD_ADDR_bif_core_rw_sdram_timing 24
206#define REG_WR_ADDR_bif_core_rw_sdram_timing 24
207
208/* Register rw_sdram_cmd, scope bif_core, type rw */
209typedef struct {
210 unsigned int cmd : 3;
211 unsigned int mrs_data : 15;
212 unsigned int dummy1 : 14;
213} reg_bif_core_rw_sdram_cmd;
214#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28
215#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28
216
217/* Register rs_sdram_ref_stat, scope bif_core, type rs */
218typedef struct {
219 unsigned int ok : 1;
220 unsigned int dummy1 : 31;
221} reg_bif_core_rs_sdram_ref_stat;
222#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32
223
224/* Register r_sdram_ref_stat, scope bif_core, type r */
225typedef struct {
226 unsigned int ok : 1;
227 unsigned int dummy1 : 31;
228} reg_bif_core_r_sdram_ref_stat;
229#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36
230
231
232/* Constants */
233enum {
234 regk_bif_core_bank2 = 0x00000000,
235 regk_bif_core_bank4 = 0x00000001,
236 regk_bif_core_bit10 = 0x0000000a,
237 regk_bif_core_bit11 = 0x0000000b,
238 regk_bif_core_bit12 = 0x0000000c,
239 regk_bif_core_bit13 = 0x0000000d,
240 regk_bif_core_bit14 = 0x0000000e,
241 regk_bif_core_bit15 = 0x0000000f,
242 regk_bif_core_bit16 = 0x00000010,
243 regk_bif_core_bit17 = 0x00000011,
244 regk_bif_core_bit18 = 0x00000012,
245 regk_bif_core_bit19 = 0x00000013,
246 regk_bif_core_bit20 = 0x00000014,
247 regk_bif_core_bit21 = 0x00000015,
248 regk_bif_core_bit22 = 0x00000016,
249 regk_bif_core_bit23 = 0x00000017,
250 regk_bif_core_bit24 = 0x00000018,
251 regk_bif_core_bit25 = 0x00000019,
252 regk_bif_core_bit26 = 0x0000001a,
253 regk_bif_core_bit27 = 0x0000001b,
254 regk_bif_core_bit28 = 0x0000001c,
255 regk_bif_core_bit29 = 0x0000001d,
256 regk_bif_core_bit9 = 0x00000009,
257 regk_bif_core_bw16 = 0x00000001,
258 regk_bif_core_bw32 = 0x00000000,
259 regk_bif_core_bwe = 0x00000000,
260 regk_bif_core_cwe = 0x00000001,
261 regk_bif_core_e15us = 0x00000001,
262 regk_bif_core_e7800ns = 0x00000002,
263 regk_bif_core_grp0 = 0x00000000,
264 regk_bif_core_grp1 = 0x00000001,
265 regk_bif_core_mrs = 0x00000003,
266 regk_bif_core_no = 0x00000000,
267 regk_bif_core_none = 0x00000000,
268 regk_bif_core_nop = 0x00000000,
269 regk_bif_core_off = 0x00000000,
270 regk_bif_core_pre = 0x00000002,
271 regk_bif_core_r_sdram_ref_stat_default = 0x00000001,
272 regk_bif_core_rd = 0x00000002,
273 regk_bif_core_ref = 0x00000001,
274 regk_bif_core_rs_sdram_ref_stat_default = 0x00000001,
275 regk_bif_core_rw_grp1_cfg_default = 0x000006cf,
276 regk_bif_core_rw_grp2_cfg_default = 0x000006cf,
277 regk_bif_core_rw_grp3_cfg_default = 0x000006cf,
278 regk_bif_core_rw_grp4_cfg_default = 0x000006cf,
279 regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000,
280 regk_bif_core_slf = 0x00000004,
281 regk_bif_core_wr = 0x00000001,
282 regk_bif_core_yes = 0x00000001
283};
284#endif /* __bif_core_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h b/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h
new file mode 100644
index 000000000000..b931c1aab679
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h
@@ -0,0 +1,473 @@
1#ifndef __bif_dma_defs_h
2#define __bif_dma_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/bif/rtl/bif_dma_regs.r
7 * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
8 * last modfied: Mon Apr 11 16:06:33 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
11 * id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope bif_dma */
86
87/* Register rw_ch0_ctrl, scope bif_dma, type rw */
88typedef struct {
89 unsigned int bw : 2;
90 unsigned int burst_len : 1;
91 unsigned int cont : 1;
92 unsigned int end_pad : 1;
93 unsigned int cnt : 1;
94 unsigned int dreq_pin : 3;
95 unsigned int dreq_mode : 2;
96 unsigned int tc_in_pin : 3;
97 unsigned int tc_in_mode : 2;
98 unsigned int bus_mode : 2;
99 unsigned int rate_en : 1;
100 unsigned int wr_all : 1;
101 unsigned int dummy1 : 12;
102} reg_bif_dma_rw_ch0_ctrl;
103#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0
104#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0
105
106/* Register rw_ch0_addr, scope bif_dma, type rw */
107typedef struct {
108 unsigned int addr : 32;
109} reg_bif_dma_rw_ch0_addr;
110#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4
111#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4
112
113/* Register rw_ch0_start, scope bif_dma, type rw */
114typedef struct {
115 unsigned int run : 1;
116 unsigned int dummy1 : 31;
117} reg_bif_dma_rw_ch0_start;
118#define REG_RD_ADDR_bif_dma_rw_ch0_start 8
119#define REG_WR_ADDR_bif_dma_rw_ch0_start 8
120
121/* Register rw_ch0_cnt, scope bif_dma, type rw */
122typedef struct {
123 unsigned int start_cnt : 16;
124 unsigned int dummy1 : 16;
125} reg_bif_dma_rw_ch0_cnt;
126#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12
127#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12
128
129/* Register r_ch0_stat, scope bif_dma, type r */
130typedef struct {
131 unsigned int cnt : 16;
132 unsigned int dummy1 : 15;
133 unsigned int run : 1;
134} reg_bif_dma_r_ch0_stat;
135#define REG_RD_ADDR_bif_dma_r_ch0_stat 16
136
137/* Register rw_ch1_ctrl, scope bif_dma, type rw */
138typedef struct {
139 unsigned int bw : 2;
140 unsigned int burst_len : 1;
141 unsigned int cont : 1;
142 unsigned int end_discard : 1;
143 unsigned int cnt : 1;
144 unsigned int dreq_pin : 3;
145 unsigned int dreq_mode : 2;
146 unsigned int tc_in_pin : 3;
147 unsigned int tc_in_mode : 2;
148 unsigned int bus_mode : 2;
149 unsigned int rate_en : 1;
150 unsigned int dummy1 : 13;
151} reg_bif_dma_rw_ch1_ctrl;
152#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32
153#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32
154
155/* Register rw_ch1_addr, scope bif_dma, type rw */
156typedef struct {
157 unsigned int addr : 32;
158} reg_bif_dma_rw_ch1_addr;
159#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36
160#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36
161
162/* Register rw_ch1_start, scope bif_dma, type rw */
163typedef struct {
164 unsigned int run : 1;
165 unsigned int dummy1 : 31;
166} reg_bif_dma_rw_ch1_start;
167#define REG_RD_ADDR_bif_dma_rw_ch1_start 40
168#define REG_WR_ADDR_bif_dma_rw_ch1_start 40
169
170/* Register rw_ch1_cnt, scope bif_dma, type rw */
171typedef struct {
172 unsigned int start_cnt : 16;
173 unsigned int dummy1 : 16;
174} reg_bif_dma_rw_ch1_cnt;
175#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44
176#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44
177
178/* Register r_ch1_stat, scope bif_dma, type r */
179typedef struct {
180 unsigned int cnt : 16;
181 unsigned int dummy1 : 15;
182 unsigned int run : 1;
183} reg_bif_dma_r_ch1_stat;
184#define REG_RD_ADDR_bif_dma_r_ch1_stat 48
185
186/* Register rw_ch2_ctrl, scope bif_dma, type rw */
187typedef struct {
188 unsigned int bw : 2;
189 unsigned int burst_len : 1;
190 unsigned int cont : 1;
191 unsigned int end_pad : 1;
192 unsigned int cnt : 1;
193 unsigned int dreq_pin : 3;
194 unsigned int dreq_mode : 2;
195 unsigned int tc_in_pin : 3;
196 unsigned int tc_in_mode : 2;
197 unsigned int bus_mode : 2;
198 unsigned int rate_en : 1;
199 unsigned int wr_all : 1;
200 unsigned int dummy1 : 12;
201} reg_bif_dma_rw_ch2_ctrl;
202#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64
203#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64
204
205/* Register rw_ch2_addr, scope bif_dma, type rw */
206typedef struct {
207 unsigned int addr : 32;
208} reg_bif_dma_rw_ch2_addr;
209#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68
210#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68
211
212/* Register rw_ch2_start, scope bif_dma, type rw */
213typedef struct {
214 unsigned int run : 1;
215 unsigned int dummy1 : 31;
216} reg_bif_dma_rw_ch2_start;
217#define REG_RD_ADDR_bif_dma_rw_ch2_start 72
218#define REG_WR_ADDR_bif_dma_rw_ch2_start 72
219
220/* Register rw_ch2_cnt, scope bif_dma, type rw */
221typedef struct {
222 unsigned int start_cnt : 16;
223 unsigned int dummy1 : 16;
224} reg_bif_dma_rw_ch2_cnt;
225#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76
226#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76
227
228/* Register r_ch2_stat, scope bif_dma, type r */
229typedef struct {
230 unsigned int cnt : 16;
231 unsigned int dummy1 : 15;
232 unsigned int run : 1;
233} reg_bif_dma_r_ch2_stat;
234#define REG_RD_ADDR_bif_dma_r_ch2_stat 80
235
236/* Register rw_ch3_ctrl, scope bif_dma, type rw */
237typedef struct {
238 unsigned int bw : 2;
239 unsigned int burst_len : 1;
240 unsigned int cont : 1;
241 unsigned int end_discard : 1;
242 unsigned int cnt : 1;
243 unsigned int dreq_pin : 3;
244 unsigned int dreq_mode : 2;
245 unsigned int tc_in_pin : 3;
246 unsigned int tc_in_mode : 2;
247 unsigned int bus_mode : 2;
248 unsigned int rate_en : 1;
249 unsigned int dummy1 : 13;
250} reg_bif_dma_rw_ch3_ctrl;
251#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96
252#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96
253
254/* Register rw_ch3_addr, scope bif_dma, type rw */
255typedef struct {
256 unsigned int addr : 32;
257} reg_bif_dma_rw_ch3_addr;
258#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100
259#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100
260
261/* Register rw_ch3_start, scope bif_dma, type rw */
262typedef struct {
263 unsigned int run : 1;
264 unsigned int dummy1 : 31;
265} reg_bif_dma_rw_ch3_start;
266#define REG_RD_ADDR_bif_dma_rw_ch3_start 104
267#define REG_WR_ADDR_bif_dma_rw_ch3_start 104
268
269/* Register rw_ch3_cnt, scope bif_dma, type rw */
270typedef struct {
271 unsigned int start_cnt : 16;
272 unsigned int dummy1 : 16;
273} reg_bif_dma_rw_ch3_cnt;
274#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108
275#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108
276
277/* Register r_ch3_stat, scope bif_dma, type r */
278typedef struct {
279 unsigned int cnt : 16;
280 unsigned int dummy1 : 15;
281 unsigned int run : 1;
282} reg_bif_dma_r_ch3_stat;
283#define REG_RD_ADDR_bif_dma_r_ch3_stat 112
284
285/* Register rw_intr_mask, scope bif_dma, type rw */
286typedef struct {
287 unsigned int ext_dma0 : 1;
288 unsigned int ext_dma1 : 1;
289 unsigned int ext_dma2 : 1;
290 unsigned int ext_dma3 : 1;
291 unsigned int dummy1 : 28;
292} reg_bif_dma_rw_intr_mask;
293#define REG_RD_ADDR_bif_dma_rw_intr_mask 128
294#define REG_WR_ADDR_bif_dma_rw_intr_mask 128
295
296/* Register rw_ack_intr, scope bif_dma, type rw */
297typedef struct {
298 unsigned int ext_dma0 : 1;
299 unsigned int ext_dma1 : 1;
300 unsigned int ext_dma2 : 1;
301 unsigned int ext_dma3 : 1;
302 unsigned int dummy1 : 28;
303} reg_bif_dma_rw_ack_intr;
304#define REG_RD_ADDR_bif_dma_rw_ack_intr 132
305#define REG_WR_ADDR_bif_dma_rw_ack_intr 132
306
307/* Register r_intr, scope bif_dma, type r */
308typedef struct {
309 unsigned int ext_dma0 : 1;
310 unsigned int ext_dma1 : 1;
311 unsigned int ext_dma2 : 1;
312 unsigned int ext_dma3 : 1;
313 unsigned int dummy1 : 28;
314} reg_bif_dma_r_intr;
315#define REG_RD_ADDR_bif_dma_r_intr 136
316
317/* Register r_masked_intr, scope bif_dma, type r */
318typedef struct {
319 unsigned int ext_dma0 : 1;
320 unsigned int ext_dma1 : 1;
321 unsigned int ext_dma2 : 1;
322 unsigned int ext_dma3 : 1;
323 unsigned int dummy1 : 28;
324} reg_bif_dma_r_masked_intr;
325#define REG_RD_ADDR_bif_dma_r_masked_intr 140
326
327/* Register rw_pin0_cfg, scope bif_dma, type rw */
328typedef struct {
329 unsigned int master_ch : 2;
330 unsigned int master_mode : 3;
331 unsigned int slave_ch : 2;
332 unsigned int slave_mode : 3;
333 unsigned int dummy1 : 22;
334} reg_bif_dma_rw_pin0_cfg;
335#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160
336#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160
337
338/* Register rw_pin1_cfg, scope bif_dma, type rw */
339typedef struct {
340 unsigned int master_ch : 2;
341 unsigned int master_mode : 3;
342 unsigned int slave_ch : 2;
343 unsigned int slave_mode : 3;
344 unsigned int dummy1 : 22;
345} reg_bif_dma_rw_pin1_cfg;
346#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164
347#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164
348
349/* Register rw_pin2_cfg, scope bif_dma, type rw */
350typedef struct {
351 unsigned int master_ch : 2;
352 unsigned int master_mode : 3;
353 unsigned int slave_ch : 2;
354 unsigned int slave_mode : 3;
355 unsigned int dummy1 : 22;
356} reg_bif_dma_rw_pin2_cfg;
357#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168
358#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168
359
360/* Register rw_pin3_cfg, scope bif_dma, type rw */
361typedef struct {
362 unsigned int master_ch : 2;
363 unsigned int master_mode : 3;
364 unsigned int slave_ch : 2;
365 unsigned int slave_mode : 3;
366 unsigned int dummy1 : 22;
367} reg_bif_dma_rw_pin3_cfg;
368#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172
369#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172
370
371/* Register rw_pin4_cfg, scope bif_dma, type rw */
372typedef struct {
373 unsigned int master_ch : 2;
374 unsigned int master_mode : 3;
375 unsigned int slave_ch : 2;
376 unsigned int slave_mode : 3;
377 unsigned int dummy1 : 22;
378} reg_bif_dma_rw_pin4_cfg;
379#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176
380#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176
381
382/* Register rw_pin5_cfg, scope bif_dma, type rw */
383typedef struct {
384 unsigned int master_ch : 2;
385 unsigned int master_mode : 3;
386 unsigned int slave_ch : 2;
387 unsigned int slave_mode : 3;
388 unsigned int dummy1 : 22;
389} reg_bif_dma_rw_pin5_cfg;
390#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180
391#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180
392
393/* Register rw_pin6_cfg, scope bif_dma, type rw */
394typedef struct {
395 unsigned int master_ch : 2;
396 unsigned int master_mode : 3;
397 unsigned int slave_ch : 2;
398 unsigned int slave_mode : 3;
399 unsigned int dummy1 : 22;
400} reg_bif_dma_rw_pin6_cfg;
401#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184
402#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184
403
404/* Register rw_pin7_cfg, scope bif_dma, type rw */
405typedef struct {
406 unsigned int master_ch : 2;
407 unsigned int master_mode : 3;
408 unsigned int slave_ch : 2;
409 unsigned int slave_mode : 3;
410 unsigned int dummy1 : 22;
411} reg_bif_dma_rw_pin7_cfg;
412#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188
413#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188
414
415/* Register r_pin_stat, scope bif_dma, type r */
416typedef struct {
417 unsigned int pin0 : 1;
418 unsigned int pin1 : 1;
419 unsigned int pin2 : 1;
420 unsigned int pin3 : 1;
421 unsigned int pin4 : 1;
422 unsigned int pin5 : 1;
423 unsigned int pin6 : 1;
424 unsigned int pin7 : 1;
425 unsigned int dummy1 : 24;
426} reg_bif_dma_r_pin_stat;
427#define REG_RD_ADDR_bif_dma_r_pin_stat 192
428
429
430/* Constants */
431enum {
432 regk_bif_dma_as_master = 0x00000001,
433 regk_bif_dma_as_slave = 0x00000001,
434 regk_bif_dma_burst1 = 0x00000000,
435 regk_bif_dma_burst8 = 0x00000001,
436 regk_bif_dma_bw16 = 0x00000001,
437 regk_bif_dma_bw32 = 0x00000002,
438 regk_bif_dma_bw8 = 0x00000000,
439 regk_bif_dma_dack = 0x00000006,
440 regk_bif_dma_dack_inv = 0x00000007,
441 regk_bif_dma_force = 0x00000001,
442 regk_bif_dma_hi = 0x00000003,
443 regk_bif_dma_inv = 0x00000003,
444 regk_bif_dma_lo = 0x00000002,
445 regk_bif_dma_master = 0x00000001,
446 regk_bif_dma_no = 0x00000000,
447 regk_bif_dma_norm = 0x00000002,
448 regk_bif_dma_off = 0x00000000,
449 regk_bif_dma_rw_ch0_ctrl_default = 0x00000000,
450 regk_bif_dma_rw_ch0_start_default = 0x00000000,
451 regk_bif_dma_rw_ch1_ctrl_default = 0x00000000,
452 regk_bif_dma_rw_ch1_start_default = 0x00000000,
453 regk_bif_dma_rw_ch2_ctrl_default = 0x00000000,
454 regk_bif_dma_rw_ch2_start_default = 0x00000000,
455 regk_bif_dma_rw_ch3_ctrl_default = 0x00000000,
456 regk_bif_dma_rw_ch3_start_default = 0x00000000,
457 regk_bif_dma_rw_intr_mask_default = 0x00000000,
458 regk_bif_dma_rw_pin0_cfg_default = 0x00000000,
459 regk_bif_dma_rw_pin1_cfg_default = 0x00000000,
460 regk_bif_dma_rw_pin2_cfg_default = 0x00000000,
461 regk_bif_dma_rw_pin3_cfg_default = 0x00000000,
462 regk_bif_dma_rw_pin4_cfg_default = 0x00000000,
463 regk_bif_dma_rw_pin5_cfg_default = 0x00000000,
464 regk_bif_dma_rw_pin6_cfg_default = 0x00000000,
465 regk_bif_dma_rw_pin7_cfg_default = 0x00000000,
466 regk_bif_dma_slave = 0x00000002,
467 regk_bif_dma_sreq = 0x00000006,
468 regk_bif_dma_sreq_inv = 0x00000007,
469 regk_bif_dma_tc = 0x00000004,
470 regk_bif_dma_tc_inv = 0x00000005,
471 regk_bif_dma_yes = 0x00000001
472};
473#endif /* __bif_dma_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h b/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h
new file mode 100644
index 000000000000..d18fc3c9f569
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h
@@ -0,0 +1,249 @@
1#ifndef __bif_slave_defs_h
2#define __bif_slave_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/bif/rtl/bif_slave_regs.r
7 * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
8 * last modfied: Mon Apr 11 16:06:34 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r
11 * id: $Id: bif_slave_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope bif_slave */
86
87/* Register rw_slave_cfg, scope bif_slave, type rw */
88typedef struct {
89 unsigned int slave_id : 3;
90 unsigned int use_slave_id : 1;
91 unsigned int boot_rdy : 1;
92 unsigned int loopback : 1;
93 unsigned int dis : 1;
94 unsigned int dummy1 : 25;
95} reg_bif_slave_rw_slave_cfg;
96#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0
97#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0
98
99/* Register r_slave_mode, scope bif_slave, type r */
100typedef struct {
101 unsigned int ch0_mode : 1;
102 unsigned int ch1_mode : 1;
103 unsigned int ch2_mode : 1;
104 unsigned int ch3_mode : 1;
105 unsigned int dummy1 : 28;
106} reg_bif_slave_r_slave_mode;
107#define REG_RD_ADDR_bif_slave_r_slave_mode 4
108
109/* Register rw_ch0_cfg, scope bif_slave, type rw */
110typedef struct {
111 unsigned int rd_hold : 2;
112 unsigned int access_mode : 1;
113 unsigned int access_ctrl : 1;
114 unsigned int data_cs : 2;
115 unsigned int dummy1 : 26;
116} reg_bif_slave_rw_ch0_cfg;
117#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16
118#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16
119
120/* Register rw_ch1_cfg, scope bif_slave, type rw */
121typedef struct {
122 unsigned int rd_hold : 2;
123 unsigned int access_mode : 1;
124 unsigned int access_ctrl : 1;
125 unsigned int data_cs : 2;
126 unsigned int dummy1 : 26;
127} reg_bif_slave_rw_ch1_cfg;
128#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20
129#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20
130
131/* Register rw_ch2_cfg, scope bif_slave, type rw */
132typedef struct {
133 unsigned int rd_hold : 2;
134 unsigned int access_mode : 1;
135 unsigned int access_ctrl : 1;
136 unsigned int data_cs : 2;
137 unsigned int dummy1 : 26;
138} reg_bif_slave_rw_ch2_cfg;
139#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24
140#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24
141
142/* Register rw_ch3_cfg, scope bif_slave, type rw */
143typedef struct {
144 unsigned int rd_hold : 2;
145 unsigned int access_mode : 1;
146 unsigned int access_ctrl : 1;
147 unsigned int data_cs : 2;
148 unsigned int dummy1 : 26;
149} reg_bif_slave_rw_ch3_cfg;
150#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28
151#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28
152
153/* Register rw_arb_cfg, scope bif_slave, type rw */
154typedef struct {
155 unsigned int brin_mode : 1;
156 unsigned int brout_mode : 3;
157 unsigned int bg_mode : 3;
158 unsigned int release : 2;
159 unsigned int acquire : 1;
160 unsigned int settle_time : 2;
161 unsigned int dram_ctrl : 1;
162 unsigned int dummy1 : 19;
163} reg_bif_slave_rw_arb_cfg;
164#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32
165#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32
166
167/* Register r_arb_stat, scope bif_slave, type r */
168typedef struct {
169 unsigned int init_mode : 1;
170 unsigned int mode : 1;
171 unsigned int brin : 1;
172 unsigned int brout : 1;
173 unsigned int bg : 1;
174 unsigned int dummy1 : 27;
175} reg_bif_slave_r_arb_stat;
176#define REG_RD_ADDR_bif_slave_r_arb_stat 36
177
178/* Register rw_intr_mask, scope bif_slave, type rw */
179typedef struct {
180 unsigned int bus_release : 1;
181 unsigned int bus_acquire : 1;
182 unsigned int dummy1 : 30;
183} reg_bif_slave_rw_intr_mask;
184#define REG_RD_ADDR_bif_slave_rw_intr_mask 64
185#define REG_WR_ADDR_bif_slave_rw_intr_mask 64
186
187/* Register rw_ack_intr, scope bif_slave, type rw */
188typedef struct {
189 unsigned int bus_release : 1;
190 unsigned int bus_acquire : 1;
191 unsigned int dummy1 : 30;
192} reg_bif_slave_rw_ack_intr;
193#define REG_RD_ADDR_bif_slave_rw_ack_intr 68
194#define REG_WR_ADDR_bif_slave_rw_ack_intr 68
195
196/* Register r_intr, scope bif_slave, type r */
197typedef struct {
198 unsigned int bus_release : 1;
199 unsigned int bus_acquire : 1;
200 unsigned int dummy1 : 30;
201} reg_bif_slave_r_intr;
202#define REG_RD_ADDR_bif_slave_r_intr 72
203
204/* Register r_masked_intr, scope bif_slave, type r */
205typedef struct {
206 unsigned int bus_release : 1;
207 unsigned int bus_acquire : 1;
208 unsigned int dummy1 : 30;
209} reg_bif_slave_r_masked_intr;
210#define REG_RD_ADDR_bif_slave_r_masked_intr 76
211
212
213/* Constants */
214enum {
215 regk_bif_slave_active_hi = 0x00000003,
216 regk_bif_slave_active_lo = 0x00000002,
217 regk_bif_slave_addr = 0x00000000,
218 regk_bif_slave_always = 0x00000001,
219 regk_bif_slave_at_idle = 0x00000002,
220 regk_bif_slave_burst_end = 0x00000003,
221 regk_bif_slave_dma = 0x00000001,
222 regk_bif_slave_hi = 0x00000003,
223 regk_bif_slave_inv = 0x00000001,
224 regk_bif_slave_lo = 0x00000002,
225 regk_bif_slave_local = 0x00000001,
226 regk_bif_slave_master = 0x00000000,
227 regk_bif_slave_mode_reg = 0x00000001,
228 regk_bif_slave_no = 0x00000000,
229 regk_bif_slave_norm = 0x00000000,
230 regk_bif_slave_on_access = 0x00000000,
231 regk_bif_slave_rw_arb_cfg_default = 0x00000000,
232 regk_bif_slave_rw_ch0_cfg_default = 0x00000000,
233 regk_bif_slave_rw_ch1_cfg_default = 0x00000000,
234 regk_bif_slave_rw_ch2_cfg_default = 0x00000000,
235 regk_bif_slave_rw_ch3_cfg_default = 0x00000000,
236 regk_bif_slave_rw_intr_mask_default = 0x00000000,
237 regk_bif_slave_rw_slave_cfg_default = 0x00000000,
238 regk_bif_slave_shared = 0x00000000,
239 regk_bif_slave_slave = 0x00000001,
240 regk_bif_slave_t0ns = 0x00000003,
241 regk_bif_slave_t10ns = 0x00000002,
242 regk_bif_slave_t20ns = 0x00000003,
243 regk_bif_slave_t30ns = 0x00000002,
244 regk_bif_slave_t40ns = 0x00000001,
245 regk_bif_slave_t50ns = 0x00000000,
246 regk_bif_slave_yes = 0x00000001,
247 regk_bif_slave_z = 0x00000004
248};
249#endif /* __bif_slave_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/config_defs.h b/include/asm-cris/arch-v32/hwregs/config_defs.h
new file mode 100644
index 000000000000..45457a4e3817
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/config_defs.h
@@ -0,0 +1,142 @@
1#ifndef __config_defs_h
2#define __config_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../rtl/config_regs.r
7 * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
8 * last modfied: Thu Mar 4 12:34:39 2004
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r
11 * id: $Id: config_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope config */
86
87/* Register r_bootsel, scope config, type r */
88typedef struct {
89 unsigned int boot_mode : 3;
90 unsigned int full_duplex : 1;
91 unsigned int user : 1;
92 unsigned int pll : 1;
93 unsigned int flash_bw : 1;
94 unsigned int dummy1 : 25;
95} reg_config_r_bootsel;
96#define REG_RD_ADDR_config_r_bootsel 0
97
98/* Register rw_clk_ctrl, scope config, type rw */
99typedef struct {
100 unsigned int pll : 1;
101 unsigned int cpu : 1;
102 unsigned int iop : 1;
103 unsigned int dma01_eth0 : 1;
104 unsigned int dma23 : 1;
105 unsigned int dma45 : 1;
106 unsigned int dma67 : 1;
107 unsigned int dma89_strcop : 1;
108 unsigned int bif : 1;
109 unsigned int fix_io : 1;
110 unsigned int dummy1 : 22;
111} reg_config_rw_clk_ctrl;
112#define REG_RD_ADDR_config_rw_clk_ctrl 4
113#define REG_WR_ADDR_config_rw_clk_ctrl 4
114
115/* Register rw_pad_ctrl, scope config, type rw */
116typedef struct {
117 unsigned int usb_susp : 1;
118 unsigned int phyrst_n : 1;
119 unsigned int dummy1 : 30;
120} reg_config_rw_pad_ctrl;
121#define REG_RD_ADDR_config_rw_pad_ctrl 8
122#define REG_WR_ADDR_config_rw_pad_ctrl 8
123
124
125/* Constants */
126enum {
127 regk_config_bw16 = 0x00000000,
128 regk_config_bw32 = 0x00000001,
129 regk_config_master = 0x00000005,
130 regk_config_nand = 0x00000003,
131 regk_config_net_rx = 0x00000001,
132 regk_config_net_tx_rx = 0x00000002,
133 regk_config_no = 0x00000000,
134 regk_config_none = 0x00000007,
135 regk_config_nor = 0x00000000,
136 regk_config_rw_clk_ctrl_default = 0x00000002,
137 regk_config_rw_pad_ctrl_default = 0x00000000,
138 regk_config_ser = 0x00000004,
139 regk_config_slave = 0x00000006,
140 regk_config_yes = 0x00000001
141};
142#endif /* __config_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/cpu_vect.h b/include/asm-cris/arch-v32/hwregs/cpu_vect.h
new file mode 100644
index 000000000000..8370aee8a14a
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/cpu_vect.h
@@ -0,0 +1,41 @@
1/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
2 from ../../inst/crisp/doc/cpu_vect.r
3version . */
4
5#ifndef _______INST_CRISP_DOC_CPU_VECT_R
6#define _______INST_CRISP_DOC_CPU_VECT_R
7#define NMI_INTR_VECT 0x00
8#define RESERVED_1_INTR_VECT 0x01
9#define RESERVED_2_INTR_VECT 0x02
10#define SINGLE_STEP_INTR_VECT 0x03
11#define INSTR_TLB_REFILL_INTR_VECT 0x04
12#define INSTR_TLB_INV_INTR_VECT 0x05
13#define INSTR_TLB_ACC_INTR_VECT 0x06
14#define TLB_EX_INTR_VECT 0x07
15#define DATA_TLB_REFILL_INTR_VECT 0x08
16#define DATA_TLB_INV_INTR_VECT 0x09
17#define DATA_TLB_ACC_INTR_VECT 0x0a
18#define DATA_TLB_WE_INTR_VECT 0x0b
19#define HW_BP_INTR_VECT 0x0c
20#define RESERVED_D_INTR_VECT 0x0d
21#define RESERVED_E_INTR_VECT 0x0e
22#define RESERVED_F_INTR_VECT 0x0f
23#define BREAK_0_INTR_VECT 0x10
24#define BREAK_1_INTR_VECT 0x11
25#define BREAK_2_INTR_VECT 0x12
26#define BREAK_3_INTR_VECT 0x13
27#define BREAK_4_INTR_VECT 0x14
28#define BREAK_5_INTR_VECT 0x15
29#define BREAK_6_INTR_VECT 0x16
30#define BREAK_7_INTR_VECT 0x17
31#define BREAK_8_INTR_VECT 0x18
32#define BREAK_9_INTR_VECT 0x19
33#define BREAK_10_INTR_VECT 0x1a
34#define BREAK_11_INTR_VECT 0x1b
35#define BREAK_12_INTR_VECT 0x1c
36#define BREAK_13_INTR_VECT 0x1d
37#define BREAK_14_INTR_VECT 0x1e
38#define BREAK_15_INTR_VECT 0x1f
39#define MULTIPLE_INTR_VECT 0x30
40
41#endif
diff --git a/include/asm-cris/arch-v32/hwregs/dma.h b/include/asm-cris/arch-v32/hwregs/dma.h
new file mode 100644
index 000000000000..c31832d3d6be
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/dma.h
@@ -0,0 +1,128 @@
1/* $Id: dma.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
2 *
3 * DMA C definitions and help macros
4 *
5 */
6
7#ifndef dma_h
8#define dma_h
9
10/* registers */ /* Really needed, since both are listed in sw.list? */
11#include "dma_defs.h"
12
13
14/* descriptors */
15
16// ------------------------------------------------------------ dma_descr_group
17typedef struct dma_descr_group {
18 struct dma_descr_group *next;
19 unsigned eol : 1;
20 unsigned tol : 1;
21 unsigned bol : 1;
22 unsigned : 1;
23 unsigned intr : 1;
24 unsigned : 2;
25 unsigned en : 1;
26 unsigned : 7;
27 unsigned dis : 1;
28 unsigned md : 16;
29 struct dma_descr_group *up;
30 union {
31 struct dma_descr_context *context;
32 struct dma_descr_group *group;
33 } down;
34} dma_descr_group;
35
36// ---------------------------------------------------------- dma_descr_context
37typedef struct dma_descr_context {
38 struct dma_descr_context *next;
39 unsigned eol : 1;
40 unsigned : 3;
41 unsigned intr : 1;
42 unsigned : 1;
43 unsigned store_mode : 1;
44 unsigned en : 1;
45 unsigned : 7;
46 unsigned dis : 1;
47 unsigned md0 : 16;
48 unsigned md1;
49 unsigned md2;
50 unsigned md3;
51 unsigned md4;
52 struct dma_descr_data *saved_data;
53 char *saved_data_buf;
54} dma_descr_context;
55
56// ------------------------------------------------------------- dma_descr_data
57typedef struct dma_descr_data {
58 struct dma_descr_data *next;
59 char *buf;
60 unsigned eol : 1;
61 unsigned : 2;
62 unsigned out_eop : 1;
63 unsigned intr : 1;
64 unsigned wait : 1;
65 unsigned : 2;
66 unsigned : 3;
67 unsigned in_eop : 1;
68 unsigned : 4;
69 unsigned md : 16;
70 char *after;
71} dma_descr_data;
72
73// --------------------------------------------------------------------- macros
74
75// enable DMA channel
76#define DMA_ENABLE( inst ) \
77 do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\
78 e.en = regk_dma_yes; \
79 REG_WR( dma, inst, rw_cfg, e); } while( 0 )
80
81// reset DMA channel
82#define DMA_RESET( inst ) \
83 do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\
84 r.en = regk_dma_no; \
85 REG_WR( dma, inst, rw_cfg, r); } while( 0 )
86
87// stop DMA channel
88#define DMA_STOP( inst ) \
89 do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\
90 s.stop = regk_dma_yes; \
91 REG_WR( dma, inst, rw_cfg, s); } while( 0 )
92
93// continue DMA channel operation
94#define DMA_CONTINUE( inst ) \
95 do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\
96 c.stop = regk_dma_no; \
97 REG_WR( dma, inst, rw_cfg, c); } while( 0 )
98
99// give stream command
100#define DMA_WR_CMD( inst, cmd_par ) \
101 do { reg_dma_rw_stream_cmd r = {0}; \
102 do { r = REG_RD( dma, inst, rw_stream_cmd ); } while( r.busy ); \
103 r.cmd = (cmd_par); \
104 REG_WR( dma, inst, rw_stream_cmd, r ); \
105 } while( 0 )
106
107// load: g,c,d:burst
108#define DMA_START_GROUP( inst, group_descr ) \
109 do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \
110 DMA_WR_CMD( inst, regk_dma_load_g ); \
111 DMA_WR_CMD( inst, regk_dma_load_c ); \
112 DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
113 } while( 0 )
114
115// load: c,d:burst
116#define DMA_START_CONTEXT( inst, ctx_descr ) \
117 do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \
118 DMA_WR_CMD( inst, regk_dma_load_c ); \
119 DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
120 } while( 0 )
121
122// if the DMA is at the end of the data list, the last data descr is reloaded
123#define DMA_CONTINUE_DATA( inst ) \
124do { reg_dma_rw_cmd c = {0}; \
125 c.cont_data = regk_dma_yes;\
126 REG_WR( dma, inst, rw_cmd, c ); } while( 0 )
127
128#endif
diff --git a/include/asm-cris/arch-v32/hwregs/dma_defs.h b/include/asm-cris/arch-v32/hwregs/dma_defs.h
new file mode 100644
index 000000000000..48ac8cef7ebe
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/dma_defs.h
@@ -0,0 +1,436 @@
1#ifndef __dma_defs_h
2#define __dma_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
7 * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
8 * last modfied: Mon Apr 11 16:06:51 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
11 * id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope dma */
86
87/* Register rw_data, scope dma, type rw */
88typedef unsigned int reg_dma_rw_data;
89#define REG_RD_ADDR_dma_rw_data 0
90#define REG_WR_ADDR_dma_rw_data 0
91
92/* Register rw_data_next, scope dma, type rw */
93typedef unsigned int reg_dma_rw_data_next;
94#define REG_RD_ADDR_dma_rw_data_next 4
95#define REG_WR_ADDR_dma_rw_data_next 4
96
97/* Register rw_data_buf, scope dma, type rw */
98typedef unsigned int reg_dma_rw_data_buf;
99#define REG_RD_ADDR_dma_rw_data_buf 8
100#define REG_WR_ADDR_dma_rw_data_buf 8
101
102/* Register rw_data_ctrl, scope dma, type rw */
103typedef struct {
104 unsigned int eol : 1;
105 unsigned int dummy1 : 2;
106 unsigned int out_eop : 1;
107 unsigned int intr : 1;
108 unsigned int wait : 1;
109 unsigned int dummy2 : 26;
110} reg_dma_rw_data_ctrl;
111#define REG_RD_ADDR_dma_rw_data_ctrl 12
112#define REG_WR_ADDR_dma_rw_data_ctrl 12
113
114/* Register rw_data_stat, scope dma, type rw */
115typedef struct {
116 unsigned int dummy1 : 3;
117 unsigned int in_eop : 1;
118 unsigned int dummy2 : 28;
119} reg_dma_rw_data_stat;
120#define REG_RD_ADDR_dma_rw_data_stat 16
121#define REG_WR_ADDR_dma_rw_data_stat 16
122
123/* Register rw_data_md, scope dma, type rw */
124typedef struct {
125 unsigned int md : 16;
126 unsigned int dummy1 : 16;
127} reg_dma_rw_data_md;
128#define REG_RD_ADDR_dma_rw_data_md 20
129#define REG_WR_ADDR_dma_rw_data_md 20
130
131/* Register rw_data_md_s, scope dma, type rw */
132typedef struct {
133 unsigned int md_s : 16;
134 unsigned int dummy1 : 16;
135} reg_dma_rw_data_md_s;
136#define REG_RD_ADDR_dma_rw_data_md_s 24
137#define REG_WR_ADDR_dma_rw_data_md_s 24
138
139/* Register rw_data_after, scope dma, type rw */
140typedef unsigned int reg_dma_rw_data_after;
141#define REG_RD_ADDR_dma_rw_data_after 28
142#define REG_WR_ADDR_dma_rw_data_after 28
143
144/* Register rw_ctxt, scope dma, type rw */
145typedef unsigned int reg_dma_rw_ctxt;
146#define REG_RD_ADDR_dma_rw_ctxt 32
147#define REG_WR_ADDR_dma_rw_ctxt 32
148
149/* Register rw_ctxt_next, scope dma, type rw */
150typedef unsigned int reg_dma_rw_ctxt_next;
151#define REG_RD_ADDR_dma_rw_ctxt_next 36
152#define REG_WR_ADDR_dma_rw_ctxt_next 36
153
154/* Register rw_ctxt_ctrl, scope dma, type rw */
155typedef struct {
156 unsigned int eol : 1;
157 unsigned int dummy1 : 3;
158 unsigned int intr : 1;
159 unsigned int dummy2 : 1;
160 unsigned int store_mode : 1;
161 unsigned int en : 1;
162 unsigned int dummy3 : 24;
163} reg_dma_rw_ctxt_ctrl;
164#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40
165#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40
166
167/* Register rw_ctxt_stat, scope dma, type rw */
168typedef struct {
169 unsigned int dummy1 : 7;
170 unsigned int dis : 1;
171 unsigned int dummy2 : 24;
172} reg_dma_rw_ctxt_stat;
173#define REG_RD_ADDR_dma_rw_ctxt_stat 44
174#define REG_WR_ADDR_dma_rw_ctxt_stat 44
175
176/* Register rw_ctxt_md0, scope dma, type rw */
177typedef struct {
178 unsigned int md0 : 16;
179 unsigned int dummy1 : 16;
180} reg_dma_rw_ctxt_md0;
181#define REG_RD_ADDR_dma_rw_ctxt_md0 48
182#define REG_WR_ADDR_dma_rw_ctxt_md0 48
183
184/* Register rw_ctxt_md0_s, scope dma, type rw */
185typedef struct {
186 unsigned int md0_s : 16;
187 unsigned int dummy1 : 16;
188} reg_dma_rw_ctxt_md0_s;
189#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52
190#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52
191
192/* Register rw_ctxt_md1, scope dma, type rw */
193typedef unsigned int reg_dma_rw_ctxt_md1;
194#define REG_RD_ADDR_dma_rw_ctxt_md1 56
195#define REG_WR_ADDR_dma_rw_ctxt_md1 56
196
197/* Register rw_ctxt_md1_s, scope dma, type rw */
198typedef unsigned int reg_dma_rw_ctxt_md1_s;
199#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60
200#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60
201
202/* Register rw_ctxt_md2, scope dma, type rw */
203typedef unsigned int reg_dma_rw_ctxt_md2;
204#define REG_RD_ADDR_dma_rw_ctxt_md2 64
205#define REG_WR_ADDR_dma_rw_ctxt_md2 64
206
207/* Register rw_ctxt_md2_s, scope dma, type rw */
208typedef unsigned int reg_dma_rw_ctxt_md2_s;
209#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68
210#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68
211
212/* Register rw_ctxt_md3, scope dma, type rw */
213typedef unsigned int reg_dma_rw_ctxt_md3;
214#define REG_RD_ADDR_dma_rw_ctxt_md3 72
215#define REG_WR_ADDR_dma_rw_ctxt_md3 72
216
217/* Register rw_ctxt_md3_s, scope dma, type rw */
218typedef unsigned int reg_dma_rw_ctxt_md3_s;
219#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76
220#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76
221
222/* Register rw_ctxt_md4, scope dma, type rw */
223typedef unsigned int reg_dma_rw_ctxt_md4;
224#define REG_RD_ADDR_dma_rw_ctxt_md4 80
225#define REG_WR_ADDR_dma_rw_ctxt_md4 80
226
227/* Register rw_ctxt_md4_s, scope dma, type rw */
228typedef unsigned int reg_dma_rw_ctxt_md4_s;
229#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84
230#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84
231
232/* Register rw_saved_data, scope dma, type rw */
233typedef unsigned int reg_dma_rw_saved_data;
234#define REG_RD_ADDR_dma_rw_saved_data 88
235#define REG_WR_ADDR_dma_rw_saved_data 88
236
237/* Register rw_saved_data_buf, scope dma, type rw */
238typedef unsigned int reg_dma_rw_saved_data_buf;
239#define REG_RD_ADDR_dma_rw_saved_data_buf 92
240#define REG_WR_ADDR_dma_rw_saved_data_buf 92
241
242/* Register rw_group, scope dma, type rw */
243typedef unsigned int reg_dma_rw_group;
244#define REG_RD_ADDR_dma_rw_group 96
245#define REG_WR_ADDR_dma_rw_group 96
246
247/* Register rw_group_next, scope dma, type rw */
248typedef unsigned int reg_dma_rw_group_next;
249#define REG_RD_ADDR_dma_rw_group_next 100
250#define REG_WR_ADDR_dma_rw_group_next 100
251
252/* Register rw_group_ctrl, scope dma, type rw */
253typedef struct {
254 unsigned int eol : 1;
255 unsigned int tol : 1;
256 unsigned int bol : 1;
257 unsigned int dummy1 : 1;
258 unsigned int intr : 1;
259 unsigned int dummy2 : 2;
260 unsigned int en : 1;
261 unsigned int dummy3 : 24;
262} reg_dma_rw_group_ctrl;
263#define REG_RD_ADDR_dma_rw_group_ctrl 104
264#define REG_WR_ADDR_dma_rw_group_ctrl 104
265
266/* Register rw_group_stat, scope dma, type rw */
267typedef struct {
268 unsigned int dummy1 : 7;
269 unsigned int dis : 1;
270 unsigned int dummy2 : 24;
271} reg_dma_rw_group_stat;
272#define REG_RD_ADDR_dma_rw_group_stat 108
273#define REG_WR_ADDR_dma_rw_group_stat 108
274
275/* Register rw_group_md, scope dma, type rw */
276typedef struct {
277 unsigned int md : 16;
278 unsigned int dummy1 : 16;
279} reg_dma_rw_group_md;
280#define REG_RD_ADDR_dma_rw_group_md 112
281#define REG_WR_ADDR_dma_rw_group_md 112
282
283/* Register rw_group_md_s, scope dma, type rw */
284typedef struct {
285 unsigned int md_s : 16;
286 unsigned int dummy1 : 16;
287} reg_dma_rw_group_md_s;
288#define REG_RD_ADDR_dma_rw_group_md_s 116
289#define REG_WR_ADDR_dma_rw_group_md_s 116
290
291/* Register rw_group_up, scope dma, type rw */
292typedef unsigned int reg_dma_rw_group_up;
293#define REG_RD_ADDR_dma_rw_group_up 120
294#define REG_WR_ADDR_dma_rw_group_up 120
295
296/* Register rw_group_down, scope dma, type rw */
297typedef unsigned int reg_dma_rw_group_down;
298#define REG_RD_ADDR_dma_rw_group_down 124
299#define REG_WR_ADDR_dma_rw_group_down 124
300
301/* Register rw_cmd, scope dma, type rw */
302typedef struct {
303 unsigned int cont_data : 1;
304 unsigned int dummy1 : 31;
305} reg_dma_rw_cmd;
306#define REG_RD_ADDR_dma_rw_cmd 128
307#define REG_WR_ADDR_dma_rw_cmd 128
308
309/* Register rw_cfg, scope dma, type rw */
310typedef struct {
311 unsigned int en : 1;
312 unsigned int stop : 1;
313 unsigned int dummy1 : 30;
314} reg_dma_rw_cfg;
315#define REG_RD_ADDR_dma_rw_cfg 132
316#define REG_WR_ADDR_dma_rw_cfg 132
317
318/* Register rw_stat, scope dma, type rw */
319typedef struct {
320 unsigned int mode : 5;
321 unsigned int list_state : 3;
322 unsigned int stream_cmd_src : 8;
323 unsigned int dummy1 : 8;
324 unsigned int buf : 8;
325} reg_dma_rw_stat;
326#define REG_RD_ADDR_dma_rw_stat 136
327#define REG_WR_ADDR_dma_rw_stat 136
328
329/* Register rw_intr_mask, scope dma, type rw */
330typedef struct {
331 unsigned int group : 1;
332 unsigned int ctxt : 1;
333 unsigned int data : 1;
334 unsigned int in_eop : 1;
335 unsigned int stream_cmd : 1;
336 unsigned int dummy1 : 27;
337} reg_dma_rw_intr_mask;
338#define REG_RD_ADDR_dma_rw_intr_mask 140
339#define REG_WR_ADDR_dma_rw_intr_mask 140
340
341/* Register rw_ack_intr, scope dma, type rw */
342typedef struct {
343 unsigned int group : 1;
344 unsigned int ctxt : 1;
345 unsigned int data : 1;
346 unsigned int in_eop : 1;
347 unsigned int stream_cmd : 1;
348 unsigned int dummy1 : 27;
349} reg_dma_rw_ack_intr;
350#define REG_RD_ADDR_dma_rw_ack_intr 144
351#define REG_WR_ADDR_dma_rw_ack_intr 144
352
353/* Register r_intr, scope dma, type r */
354typedef struct {
355 unsigned int group : 1;
356 unsigned int ctxt : 1;
357 unsigned int data : 1;
358 unsigned int in_eop : 1;
359 unsigned int stream_cmd : 1;
360 unsigned int dummy1 : 27;
361} reg_dma_r_intr;
362#define REG_RD_ADDR_dma_r_intr 148
363
364/* Register r_masked_intr, scope dma, type r */
365typedef struct {
366 unsigned int group : 1;
367 unsigned int ctxt : 1;
368 unsigned int data : 1;
369 unsigned int in_eop : 1;
370 unsigned int stream_cmd : 1;
371 unsigned int dummy1 : 27;
372} reg_dma_r_masked_intr;
373#define REG_RD_ADDR_dma_r_masked_intr 152
374
375/* Register rw_stream_cmd, scope dma, type rw */
376typedef struct {
377 unsigned int cmd : 10;
378 unsigned int dummy1 : 6;
379 unsigned int n : 8;
380 unsigned int dummy2 : 7;
381 unsigned int busy : 1;
382} reg_dma_rw_stream_cmd;
383#define REG_RD_ADDR_dma_rw_stream_cmd 156
384#define REG_WR_ADDR_dma_rw_stream_cmd 156
385
386
387/* Constants */
388enum {
389 regk_dma_ack_pkt = 0x00000100,
390 regk_dma_anytime = 0x00000001,
391 regk_dma_array = 0x00000008,
392 regk_dma_burst = 0x00000020,
393 regk_dma_client = 0x00000002,
394 regk_dma_copy_next = 0x00000010,
395 regk_dma_copy_up = 0x00000020,
396 regk_dma_data_at_eol = 0x00000001,
397 regk_dma_dis_c = 0x00000010,
398 regk_dma_dis_g = 0x00000020,
399 regk_dma_idle = 0x00000001,
400 regk_dma_intern = 0x00000004,
401 regk_dma_load_c = 0x00000200,
402 regk_dma_load_c_n = 0x00000280,
403 regk_dma_load_c_next = 0x00000240,
404 regk_dma_load_d = 0x00000140,
405 regk_dma_load_g = 0x00000300,
406 regk_dma_load_g_down = 0x000003c0,
407 regk_dma_load_g_next = 0x00000340,
408 regk_dma_load_g_up = 0x00000380,
409 regk_dma_next_en = 0x00000010,
410 regk_dma_next_pkt = 0x00000010,
411 regk_dma_no = 0x00000000,
412 regk_dma_only_at_wait = 0x00000000,
413 regk_dma_restore = 0x00000020,
414 regk_dma_rst = 0x00000001,
415 regk_dma_running = 0x00000004,
416 regk_dma_rw_cfg_default = 0x00000000,
417 regk_dma_rw_cmd_default = 0x00000000,
418 regk_dma_rw_intr_mask_default = 0x00000000,
419 regk_dma_rw_stat_default = 0x00000101,
420 regk_dma_rw_stream_cmd_default = 0x00000000,
421 regk_dma_save_down = 0x00000020,
422 regk_dma_save_up = 0x00000020,
423 regk_dma_set_reg = 0x00000050,
424 regk_dma_set_w_size1 = 0x00000190,
425 regk_dma_set_w_size2 = 0x000001a0,
426 regk_dma_set_w_size4 = 0x000001c0,
427 regk_dma_stopped = 0x00000002,
428 regk_dma_store_c = 0x00000002,
429 regk_dma_store_descr = 0x00000000,
430 regk_dma_store_g = 0x00000004,
431 regk_dma_store_md = 0x00000001,
432 regk_dma_sw = 0x00000008,
433 regk_dma_update_down = 0x00000020,
434 regk_dma_yes = 0x00000001
435};
436#endif /* __dma_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/eth_defs.h b/include/asm-cris/arch-v32/hwregs/eth_defs.h
new file mode 100644
index 000000000000..1196d7cc783f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/eth_defs.h
@@ -0,0 +1,384 @@
1#ifndef __eth_defs_h
2#define __eth_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/eth/rtl/eth_regs.r
7 * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp
8 * last modfied: Mon Apr 11 16:07:03 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile eth_defs.h ../../inst/eth/rtl/eth_regs.r
11 * id: $Id: eth_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope eth */
86
87/* Register rw_ma0_lo, scope eth, type rw */
88typedef struct {
89 unsigned int addr : 32;
90} reg_eth_rw_ma0_lo;
91#define REG_RD_ADDR_eth_rw_ma0_lo 0
92#define REG_WR_ADDR_eth_rw_ma0_lo 0
93
94/* Register rw_ma0_hi, scope eth, type rw */
95typedef struct {
96 unsigned int addr : 16;
97 unsigned int dummy1 : 16;
98} reg_eth_rw_ma0_hi;
99#define REG_RD_ADDR_eth_rw_ma0_hi 4
100#define REG_WR_ADDR_eth_rw_ma0_hi 4
101
102/* Register rw_ma1_lo, scope eth, type rw */
103typedef struct {
104 unsigned int addr : 32;
105} reg_eth_rw_ma1_lo;
106#define REG_RD_ADDR_eth_rw_ma1_lo 8
107#define REG_WR_ADDR_eth_rw_ma1_lo 8
108
109/* Register rw_ma1_hi, scope eth, type rw */
110typedef struct {
111 unsigned int addr : 16;
112 unsigned int dummy1 : 16;
113} reg_eth_rw_ma1_hi;
114#define REG_RD_ADDR_eth_rw_ma1_hi 12
115#define REG_WR_ADDR_eth_rw_ma1_hi 12
116
117/* Register rw_ga_lo, scope eth, type rw */
118typedef struct {
119 unsigned int table : 32;
120} reg_eth_rw_ga_lo;
121#define REG_RD_ADDR_eth_rw_ga_lo 16
122#define REG_WR_ADDR_eth_rw_ga_lo 16
123
124/* Register rw_ga_hi, scope eth, type rw */
125typedef struct {
126 unsigned int table : 32;
127} reg_eth_rw_ga_hi;
128#define REG_RD_ADDR_eth_rw_ga_hi 20
129#define REG_WR_ADDR_eth_rw_ga_hi 20
130
131/* Register rw_gen_ctrl, scope eth, type rw */
132typedef struct {
133 unsigned int en : 1;
134 unsigned int phy : 2;
135 unsigned int protocol : 1;
136 unsigned int loopback : 1;
137 unsigned int flow_ctrl_dis : 1;
138 unsigned int dummy1 : 26;
139} reg_eth_rw_gen_ctrl;
140#define REG_RD_ADDR_eth_rw_gen_ctrl 24
141#define REG_WR_ADDR_eth_rw_gen_ctrl 24
142
143/* Register rw_rec_ctrl, scope eth, type rw */
144typedef struct {
145 unsigned int ma0 : 1;
146 unsigned int ma1 : 1;
147 unsigned int individual : 1;
148 unsigned int broadcast : 1;
149 unsigned int undersize : 1;
150 unsigned int oversize : 1;
151 unsigned int bad_crc : 1;
152 unsigned int duplex : 1;
153 unsigned int max_size : 1;
154 unsigned int dummy1 : 23;
155} reg_eth_rw_rec_ctrl;
156#define REG_RD_ADDR_eth_rw_rec_ctrl 28
157#define REG_WR_ADDR_eth_rw_rec_ctrl 28
158
159/* Register rw_tr_ctrl, scope eth, type rw */
160typedef struct {
161 unsigned int crc : 1;
162 unsigned int pad : 1;
163 unsigned int retry : 1;
164 unsigned int ignore_col : 1;
165 unsigned int cancel : 1;
166 unsigned int hsh_delay : 1;
167 unsigned int ignore_crs : 1;
168 unsigned int dummy1 : 25;
169} reg_eth_rw_tr_ctrl;
170#define REG_RD_ADDR_eth_rw_tr_ctrl 32
171#define REG_WR_ADDR_eth_rw_tr_ctrl 32
172
173/* Register rw_clr_err, scope eth, type rw */
174typedef struct {
175 unsigned int clr : 1;
176 unsigned int dummy1 : 31;
177} reg_eth_rw_clr_err;
178#define REG_RD_ADDR_eth_rw_clr_err 36
179#define REG_WR_ADDR_eth_rw_clr_err 36
180
181/* Register rw_mgm_ctrl, scope eth, type rw */
182typedef struct {
183 unsigned int mdio : 1;
184 unsigned int mdoe : 1;
185 unsigned int mdc : 1;
186 unsigned int phyclk : 1;
187 unsigned int txdata : 4;
188 unsigned int txen : 1;
189 unsigned int dummy1 : 23;
190} reg_eth_rw_mgm_ctrl;
191#define REG_RD_ADDR_eth_rw_mgm_ctrl 40
192#define REG_WR_ADDR_eth_rw_mgm_ctrl 40
193
194/* Register r_stat, scope eth, type r */
195typedef struct {
196 unsigned int mdio : 1;
197 unsigned int exc_col : 1;
198 unsigned int urun : 1;
199 unsigned int phyclk : 1;
200 unsigned int txdata : 4;
201 unsigned int txen : 1;
202 unsigned int col : 1;
203 unsigned int crs : 1;
204 unsigned int txclk : 1;
205 unsigned int rxdata : 4;
206 unsigned int rxer : 1;
207 unsigned int rxdv : 1;
208 unsigned int rxclk : 1;
209 unsigned int dummy1 : 13;
210} reg_eth_r_stat;
211#define REG_RD_ADDR_eth_r_stat 44
212
213/* Register rs_rec_cnt, scope eth, type rs */
214typedef struct {
215 unsigned int crc_err : 8;
216 unsigned int align_err : 8;
217 unsigned int oversize : 8;
218 unsigned int congestion : 8;
219} reg_eth_rs_rec_cnt;
220#define REG_RD_ADDR_eth_rs_rec_cnt 48
221
222/* Register r_rec_cnt, scope eth, type r */
223typedef struct {
224 unsigned int crc_err : 8;
225 unsigned int align_err : 8;
226 unsigned int oversize : 8;
227 unsigned int congestion : 8;
228} reg_eth_r_rec_cnt;
229#define REG_RD_ADDR_eth_r_rec_cnt 52
230
231/* Register rs_tr_cnt, scope eth, type rs */
232typedef struct {
233 unsigned int single_col : 8;
234 unsigned int mult_col : 8;
235 unsigned int late_col : 8;
236 unsigned int deferred : 8;
237} reg_eth_rs_tr_cnt;
238#define REG_RD_ADDR_eth_rs_tr_cnt 56
239
240/* Register r_tr_cnt, scope eth, type r */
241typedef struct {
242 unsigned int single_col : 8;
243 unsigned int mult_col : 8;
244 unsigned int late_col : 8;
245 unsigned int deferred : 8;
246} reg_eth_r_tr_cnt;
247#define REG_RD_ADDR_eth_r_tr_cnt 60
248
249/* Register rs_phy_cnt, scope eth, type rs */
250typedef struct {
251 unsigned int carrier_loss : 8;
252 unsigned int sqe_err : 8;
253 unsigned int dummy1 : 16;
254} reg_eth_rs_phy_cnt;
255#define REG_RD_ADDR_eth_rs_phy_cnt 64
256
257/* Register r_phy_cnt, scope eth, type r */
258typedef struct {
259 unsigned int carrier_loss : 8;
260 unsigned int sqe_err : 8;
261 unsigned int dummy1 : 16;
262} reg_eth_r_phy_cnt;
263#define REG_RD_ADDR_eth_r_phy_cnt 68
264
265/* Register rw_test_ctrl, scope eth, type rw */
266typedef struct {
267 unsigned int snmp_inc : 1;
268 unsigned int snmp : 1;
269 unsigned int backoff : 1;
270 unsigned int dummy1 : 29;
271} reg_eth_rw_test_ctrl;
272#define REG_RD_ADDR_eth_rw_test_ctrl 72
273#define REG_WR_ADDR_eth_rw_test_ctrl 72
274
275/* Register rw_intr_mask, scope eth, type rw */
276typedef struct {
277 unsigned int crc : 1;
278 unsigned int align : 1;
279 unsigned int oversize : 1;
280 unsigned int congestion : 1;
281 unsigned int single_col : 1;
282 unsigned int mult_col : 1;
283 unsigned int late_col : 1;
284 unsigned int deferred : 1;
285 unsigned int carrier_loss : 1;
286 unsigned int sqe_test_err : 1;
287 unsigned int orun : 1;
288 unsigned int urun : 1;
289 unsigned int excessive_col : 1;
290 unsigned int mdio : 1;
291 unsigned int dummy1 : 18;
292} reg_eth_rw_intr_mask;
293#define REG_RD_ADDR_eth_rw_intr_mask 76
294#define REG_WR_ADDR_eth_rw_intr_mask 76
295
296/* Register rw_ack_intr, scope eth, type rw */
297typedef struct {
298 unsigned int crc : 1;
299 unsigned int align : 1;
300 unsigned int oversize : 1;
301 unsigned int congestion : 1;
302 unsigned int single_col : 1;
303 unsigned int mult_col : 1;
304 unsigned int late_col : 1;
305 unsigned int deferred : 1;
306 unsigned int carrier_loss : 1;
307 unsigned int sqe_test_err : 1;
308 unsigned int orun : 1;
309 unsigned int urun : 1;
310 unsigned int excessive_col : 1;
311 unsigned int mdio : 1;
312 unsigned int dummy1 : 18;
313} reg_eth_rw_ack_intr;
314#define REG_RD_ADDR_eth_rw_ack_intr 80
315#define REG_WR_ADDR_eth_rw_ack_intr 80
316
317/* Register r_intr, scope eth, type r */
318typedef struct {
319 unsigned int crc : 1;
320 unsigned int align : 1;
321 unsigned int oversize : 1;
322 unsigned int congestion : 1;
323 unsigned int single_col : 1;
324 unsigned int mult_col : 1;
325 unsigned int late_col : 1;
326 unsigned int deferred : 1;
327 unsigned int carrier_loss : 1;
328 unsigned int sqe_test_err : 1;
329 unsigned int orun : 1;
330 unsigned int urun : 1;
331 unsigned int excessive_col : 1;
332 unsigned int mdio : 1;
333 unsigned int dummy1 : 18;
334} reg_eth_r_intr;
335#define REG_RD_ADDR_eth_r_intr 84
336
337/* Register r_masked_intr, scope eth, type r */
338typedef struct {
339 unsigned int crc : 1;
340 unsigned int align : 1;
341 unsigned int oversize : 1;
342 unsigned int congestion : 1;
343 unsigned int single_col : 1;
344 unsigned int mult_col : 1;
345 unsigned int late_col : 1;
346 unsigned int deferred : 1;
347 unsigned int carrier_loss : 1;
348 unsigned int sqe_test_err : 1;
349 unsigned int orun : 1;
350 unsigned int urun : 1;
351 unsigned int excessive_col : 1;
352 unsigned int mdio : 1;
353 unsigned int dummy1 : 18;
354} reg_eth_r_masked_intr;
355#define REG_RD_ADDR_eth_r_masked_intr 88
356
357
358/* Constants */
359enum {
360 regk_eth_discard = 0x00000000,
361 regk_eth_ether = 0x00000000,
362 regk_eth_full = 0x00000001,
363 regk_eth_half = 0x00000000,
364 regk_eth_hsh = 0x00000001,
365 regk_eth_mii = 0x00000001,
366 regk_eth_mii_clk = 0x00000000,
367 regk_eth_mii_rec = 0x00000002,
368 regk_eth_no = 0x00000000,
369 regk_eth_rec = 0x00000001,
370 regk_eth_rw_ga_hi_default = 0x00000000,
371 regk_eth_rw_ga_lo_default = 0x00000000,
372 regk_eth_rw_gen_ctrl_default = 0x00000000,
373 regk_eth_rw_intr_mask_default = 0x00000000,
374 regk_eth_rw_ma0_hi_default = 0x00000000,
375 regk_eth_rw_ma0_lo_default = 0x00000000,
376 regk_eth_rw_ma1_hi_default = 0x00000000,
377 regk_eth_rw_ma1_lo_default = 0x00000000,
378 regk_eth_rw_mgm_ctrl_default = 0x00000000,
379 regk_eth_rw_test_ctrl_default = 0x00000000,
380 regk_eth_size1518 = 0x00000000,
381 regk_eth_size1522 = 0x00000001,
382 regk_eth_yes = 0x00000001
383};
384#endif /* __eth_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/extmem_defs.h b/include/asm-cris/arch-v32/hwregs/extmem_defs.h
new file mode 100644
index 000000000000..c47b5ca48ece
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/extmem_defs.h
@@ -0,0 +1,369 @@
1#ifndef __extmem_defs_h
2#define __extmem_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/ext_mem/mod/extmem_regs.r
7 * id: extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp
8 * last modfied: Tue Mar 30 22:26:21 2004
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r
11 * id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope extmem */
86
87/* Register rw_cse0_cfg, scope extmem, type rw */
88typedef struct {
89 unsigned int lw : 6;
90 unsigned int ew : 3;
91 unsigned int zw : 3;
92 unsigned int aw : 2;
93 unsigned int dw : 2;
94 unsigned int ewb : 2;
95 unsigned int bw : 1;
96 unsigned int mode : 1;
97 unsigned int erc_en : 1;
98 unsigned int dummy1 : 6;
99 unsigned int size : 3;
100 unsigned int log : 1;
101 unsigned int en : 1;
102} reg_extmem_rw_cse0_cfg;
103#define REG_RD_ADDR_extmem_rw_cse0_cfg 0
104#define REG_WR_ADDR_extmem_rw_cse0_cfg 0
105
106/* Register rw_cse1_cfg, scope extmem, type rw */
107typedef struct {
108 unsigned int lw : 6;
109 unsigned int ew : 3;
110 unsigned int zw : 3;
111 unsigned int aw : 2;
112 unsigned int dw : 2;
113 unsigned int ewb : 2;
114 unsigned int bw : 1;
115 unsigned int mode : 1;
116 unsigned int erc_en : 1;
117 unsigned int dummy1 : 6;
118 unsigned int size : 3;
119 unsigned int log : 1;
120 unsigned int en : 1;
121} reg_extmem_rw_cse1_cfg;
122#define REG_RD_ADDR_extmem_rw_cse1_cfg 4
123#define REG_WR_ADDR_extmem_rw_cse1_cfg 4
124
125/* Register rw_csr0_cfg, scope extmem, type rw */
126typedef struct {
127 unsigned int lw : 6;
128 unsigned int ew : 3;
129 unsigned int zw : 3;
130 unsigned int aw : 2;
131 unsigned int dw : 2;
132 unsigned int ewb : 2;
133 unsigned int bw : 1;
134 unsigned int mode : 1;
135 unsigned int erc_en : 1;
136 unsigned int dummy1 : 6;
137 unsigned int size : 3;
138 unsigned int log : 1;
139 unsigned int en : 1;
140} reg_extmem_rw_csr0_cfg;
141#define REG_RD_ADDR_extmem_rw_csr0_cfg 8
142#define REG_WR_ADDR_extmem_rw_csr0_cfg 8
143
144/* Register rw_csr1_cfg, scope extmem, type rw */
145typedef struct {
146 unsigned int lw : 6;
147 unsigned int ew : 3;
148 unsigned int zw : 3;
149 unsigned int aw : 2;
150 unsigned int dw : 2;
151 unsigned int ewb : 2;
152 unsigned int bw : 1;
153 unsigned int mode : 1;
154 unsigned int erc_en : 1;
155 unsigned int dummy1 : 6;
156 unsigned int size : 3;
157 unsigned int log : 1;
158 unsigned int en : 1;
159} reg_extmem_rw_csr1_cfg;
160#define REG_RD_ADDR_extmem_rw_csr1_cfg 12
161#define REG_WR_ADDR_extmem_rw_csr1_cfg 12
162
163/* Register rw_csp0_cfg, scope extmem, type rw */
164typedef struct {
165 unsigned int lw : 6;
166 unsigned int ew : 3;
167 unsigned int zw : 3;
168 unsigned int aw : 2;
169 unsigned int dw : 2;
170 unsigned int ewb : 2;
171 unsigned int bw : 1;
172 unsigned int mode : 1;
173 unsigned int erc_en : 1;
174 unsigned int dummy1 : 6;
175 unsigned int size : 3;
176 unsigned int log : 1;
177 unsigned int en : 1;
178} reg_extmem_rw_csp0_cfg;
179#define REG_RD_ADDR_extmem_rw_csp0_cfg 16
180#define REG_WR_ADDR_extmem_rw_csp0_cfg 16
181
182/* Register rw_csp1_cfg, scope extmem, type rw */
183typedef struct {
184 unsigned int lw : 6;
185 unsigned int ew : 3;
186 unsigned int zw : 3;
187 unsigned int aw : 2;
188 unsigned int dw : 2;
189 unsigned int ewb : 2;
190 unsigned int bw : 1;
191 unsigned int mode : 1;
192 unsigned int erc_en : 1;
193 unsigned int dummy1 : 6;
194 unsigned int size : 3;
195 unsigned int log : 1;
196 unsigned int en : 1;
197} reg_extmem_rw_csp1_cfg;
198#define REG_RD_ADDR_extmem_rw_csp1_cfg 20
199#define REG_WR_ADDR_extmem_rw_csp1_cfg 20
200
201/* Register rw_csp2_cfg, scope extmem, type rw */
202typedef struct {
203 unsigned int lw : 6;
204 unsigned int ew : 3;
205 unsigned int zw : 3;
206 unsigned int aw : 2;
207 unsigned int dw : 2;
208 unsigned int ewb : 2;
209 unsigned int bw : 1;
210 unsigned int mode : 1;
211 unsigned int erc_en : 1;
212 unsigned int dummy1 : 6;
213 unsigned int size : 3;
214 unsigned int log : 1;
215 unsigned int en : 1;
216} reg_extmem_rw_csp2_cfg;
217#define REG_RD_ADDR_extmem_rw_csp2_cfg 24
218#define REG_WR_ADDR_extmem_rw_csp2_cfg 24
219
220/* Register rw_csp3_cfg, scope extmem, type rw */
221typedef struct {
222 unsigned int lw : 6;
223 unsigned int ew : 3;
224 unsigned int zw : 3;
225 unsigned int aw : 2;
226 unsigned int dw : 2;
227 unsigned int ewb : 2;
228 unsigned int bw : 1;
229 unsigned int mode : 1;
230 unsigned int erc_en : 1;
231 unsigned int dummy1 : 6;
232 unsigned int size : 3;
233 unsigned int log : 1;
234 unsigned int en : 1;
235} reg_extmem_rw_csp3_cfg;
236#define REG_RD_ADDR_extmem_rw_csp3_cfg 28
237#define REG_WR_ADDR_extmem_rw_csp3_cfg 28
238
239/* Register rw_csp4_cfg, scope extmem, type rw */
240typedef struct {
241 unsigned int lw : 6;
242 unsigned int ew : 3;
243 unsigned int zw : 3;
244 unsigned int aw : 2;
245 unsigned int dw : 2;
246 unsigned int ewb : 2;
247 unsigned int bw : 1;
248 unsigned int mode : 1;
249 unsigned int erc_en : 1;
250 unsigned int dummy1 : 6;
251 unsigned int size : 3;
252 unsigned int log : 1;
253 unsigned int en : 1;
254} reg_extmem_rw_csp4_cfg;
255#define REG_RD_ADDR_extmem_rw_csp4_cfg 32
256#define REG_WR_ADDR_extmem_rw_csp4_cfg 32
257
258/* Register rw_csp5_cfg, scope extmem, type rw */
259typedef struct {
260 unsigned int lw : 6;
261 unsigned int ew : 3;
262 unsigned int zw : 3;
263 unsigned int aw : 2;
264 unsigned int dw : 2;
265 unsigned int ewb : 2;
266 unsigned int bw : 1;
267 unsigned int mode : 1;
268 unsigned int erc_en : 1;
269 unsigned int dummy1 : 6;
270 unsigned int size : 3;
271 unsigned int log : 1;
272 unsigned int en : 1;
273} reg_extmem_rw_csp5_cfg;
274#define REG_RD_ADDR_extmem_rw_csp5_cfg 36
275#define REG_WR_ADDR_extmem_rw_csp5_cfg 36
276
277/* Register rw_csp6_cfg, scope extmem, type rw */
278typedef struct {
279 unsigned int lw : 6;
280 unsigned int ew : 3;
281 unsigned int zw : 3;
282 unsigned int aw : 2;
283 unsigned int dw : 2;
284 unsigned int ewb : 2;
285 unsigned int bw : 1;
286 unsigned int mode : 1;
287 unsigned int erc_en : 1;
288 unsigned int dummy1 : 6;
289 unsigned int size : 3;
290 unsigned int log : 1;
291 unsigned int en : 1;
292} reg_extmem_rw_csp6_cfg;
293#define REG_RD_ADDR_extmem_rw_csp6_cfg 40
294#define REG_WR_ADDR_extmem_rw_csp6_cfg 40
295
296/* Register rw_css_cfg, scope extmem, type rw */
297typedef struct {
298 unsigned int lw : 6;
299 unsigned int ew : 3;
300 unsigned int zw : 3;
301 unsigned int aw : 2;
302 unsigned int dw : 2;
303 unsigned int ewb : 2;
304 unsigned int bw : 1;
305 unsigned int mode : 1;
306 unsigned int erc_en : 1;
307 unsigned int dummy1 : 6;
308 unsigned int size : 3;
309 unsigned int log : 1;
310 unsigned int en : 1;
311} reg_extmem_rw_css_cfg;
312#define REG_RD_ADDR_extmem_rw_css_cfg 44
313#define REG_WR_ADDR_extmem_rw_css_cfg 44
314
315/* Register rw_status_handle, scope extmem, type rw */
316typedef struct {
317 unsigned int h : 32;
318} reg_extmem_rw_status_handle;
319#define REG_RD_ADDR_extmem_rw_status_handle 48
320#define REG_WR_ADDR_extmem_rw_status_handle 48
321
322/* Register rw_wait_pin, scope extmem, type rw */
323typedef struct {
324 unsigned int val : 16;
325 unsigned int dummy1 : 15;
326 unsigned int start : 1;
327} reg_extmem_rw_wait_pin;
328#define REG_RD_ADDR_extmem_rw_wait_pin 52
329#define REG_WR_ADDR_extmem_rw_wait_pin 52
330
331/* Register rw_gated_csp, scope extmem, type rw */
332typedef struct {
333 unsigned int dummy1 : 31;
334 unsigned int en : 1;
335} reg_extmem_rw_gated_csp;
336#define REG_RD_ADDR_extmem_rw_gated_csp 56
337#define REG_WR_ADDR_extmem_rw_gated_csp 56
338
339
340/* Constants */
341enum {
342 regk_extmem_b16 = 0x00000001,
343 regk_extmem_b32 = 0x00000000,
344 regk_extmem_bwe = 0x00000000,
345 regk_extmem_cwe = 0x00000001,
346 regk_extmem_no = 0x00000000,
347 regk_extmem_rw_cse0_cfg_default = 0x000006cf,
348 regk_extmem_rw_cse1_cfg_default = 0x000006cf,
349 regk_extmem_rw_csp0_cfg_default = 0x000006cf,
350 regk_extmem_rw_csp1_cfg_default = 0x000006cf,
351 regk_extmem_rw_csp2_cfg_default = 0x000006cf,
352 regk_extmem_rw_csp3_cfg_default = 0x000006cf,
353 regk_extmem_rw_csp4_cfg_default = 0x000006cf,
354 regk_extmem_rw_csp5_cfg_default = 0x000006cf,
355 regk_extmem_rw_csp6_cfg_default = 0x000006cf,
356 regk_extmem_rw_csr0_cfg_default = 0x000006cf,
357 regk_extmem_rw_csr1_cfg_default = 0x000006cf,
358 regk_extmem_rw_css_cfg_default = 0x000006cf,
359 regk_extmem_s128KB = 0x00000000,
360 regk_extmem_s16MB = 0x00000005,
361 regk_extmem_s1MB = 0x00000001,
362 regk_extmem_s2MB = 0x00000002,
363 regk_extmem_s32MB = 0x00000006,
364 regk_extmem_s4MB = 0x00000003,
365 regk_extmem_s64MB = 0x00000007,
366 regk_extmem_s8MB = 0x00000004,
367 regk_extmem_yes = 0x00000001
368};
369#endif /* __extmem_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/gio_defs.h b/include/asm-cris/arch-v32/hwregs/gio_defs.h
new file mode 100644
index 000000000000..3e9a0b25366f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/gio_defs.h
@@ -0,0 +1,295 @@
1#ifndef __gio_defs_h
2#define __gio_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/gio/rtl/gio_regs.r
7 * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
8 * last modfied: Mon Apr 11 16:07:47 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r
11 * id: $Id: gio_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope gio */
86
87/* Register rw_pa_dout, scope gio, type rw */
88typedef struct {
89 unsigned int data : 8;
90 unsigned int dummy1 : 24;
91} reg_gio_rw_pa_dout;
92#define REG_RD_ADDR_gio_rw_pa_dout 0
93#define REG_WR_ADDR_gio_rw_pa_dout 0
94
95/* Register r_pa_din, scope gio, type r */
96typedef struct {
97 unsigned int data : 8;
98 unsigned int dummy1 : 24;
99} reg_gio_r_pa_din;
100#define REG_RD_ADDR_gio_r_pa_din 4
101
102/* Register rw_pa_oe, scope gio, type rw */
103typedef struct {
104 unsigned int oe : 8;
105 unsigned int dummy1 : 24;
106} reg_gio_rw_pa_oe;
107#define REG_RD_ADDR_gio_rw_pa_oe 8
108#define REG_WR_ADDR_gio_rw_pa_oe 8
109
110/* Register rw_intr_cfg, scope gio, type rw */
111typedef struct {
112 unsigned int pa0 : 3;
113 unsigned int pa1 : 3;
114 unsigned int pa2 : 3;
115 unsigned int pa3 : 3;
116 unsigned int pa4 : 3;
117 unsigned int pa5 : 3;
118 unsigned int pa6 : 3;
119 unsigned int pa7 : 3;
120 unsigned int dummy1 : 8;
121} reg_gio_rw_intr_cfg;
122#define REG_RD_ADDR_gio_rw_intr_cfg 12
123#define REG_WR_ADDR_gio_rw_intr_cfg 12
124
125/* Register rw_intr_mask, scope gio, type rw */
126typedef struct {
127 unsigned int pa0 : 1;
128 unsigned int pa1 : 1;
129 unsigned int pa2 : 1;
130 unsigned int pa3 : 1;
131 unsigned int pa4 : 1;
132 unsigned int pa5 : 1;
133 unsigned int pa6 : 1;
134 unsigned int pa7 : 1;
135 unsigned int dummy1 : 24;
136} reg_gio_rw_intr_mask;
137#define REG_RD_ADDR_gio_rw_intr_mask 16
138#define REG_WR_ADDR_gio_rw_intr_mask 16
139
140/* Register rw_ack_intr, scope gio, type rw */
141typedef struct {
142 unsigned int pa0 : 1;
143 unsigned int pa1 : 1;
144 unsigned int pa2 : 1;
145 unsigned int pa3 : 1;
146 unsigned int pa4 : 1;
147 unsigned int pa5 : 1;
148 unsigned int pa6 : 1;
149 unsigned int pa7 : 1;
150 unsigned int dummy1 : 24;
151} reg_gio_rw_ack_intr;
152#define REG_RD_ADDR_gio_rw_ack_intr 20
153#define REG_WR_ADDR_gio_rw_ack_intr 20
154
155/* Register r_intr, scope gio, type r */
156typedef struct {
157 unsigned int pa0 : 1;
158 unsigned int pa1 : 1;
159 unsigned int pa2 : 1;
160 unsigned int pa3 : 1;
161 unsigned int pa4 : 1;
162 unsigned int pa5 : 1;
163 unsigned int pa6 : 1;
164 unsigned int pa7 : 1;
165 unsigned int dummy1 : 24;
166} reg_gio_r_intr;
167#define REG_RD_ADDR_gio_r_intr 24
168
169/* Register r_masked_intr, scope gio, type r */
170typedef struct {
171 unsigned int pa0 : 1;
172 unsigned int pa1 : 1;
173 unsigned int pa2 : 1;
174 unsigned int pa3 : 1;
175 unsigned int pa4 : 1;
176 unsigned int pa5 : 1;
177 unsigned int pa6 : 1;
178 unsigned int pa7 : 1;
179 unsigned int dummy1 : 24;
180} reg_gio_r_masked_intr;
181#define REG_RD_ADDR_gio_r_masked_intr 28
182
183/* Register rw_pb_dout, scope gio, type rw */
184typedef struct {
185 unsigned int data : 18;
186 unsigned int dummy1 : 14;
187} reg_gio_rw_pb_dout;
188#define REG_RD_ADDR_gio_rw_pb_dout 32
189#define REG_WR_ADDR_gio_rw_pb_dout 32
190
191/* Register r_pb_din, scope gio, type r */
192typedef struct {
193 unsigned int data : 18;
194 unsigned int dummy1 : 14;
195} reg_gio_r_pb_din;
196#define REG_RD_ADDR_gio_r_pb_din 36
197
198/* Register rw_pb_oe, scope gio, type rw */
199typedef struct {
200 unsigned int oe : 18;
201 unsigned int dummy1 : 14;
202} reg_gio_rw_pb_oe;
203#define REG_RD_ADDR_gio_rw_pb_oe 40
204#define REG_WR_ADDR_gio_rw_pb_oe 40
205
206/* Register rw_pc_dout, scope gio, type rw */
207typedef struct {
208 unsigned int data : 18;
209 unsigned int dummy1 : 14;
210} reg_gio_rw_pc_dout;
211#define REG_RD_ADDR_gio_rw_pc_dout 48
212#define REG_WR_ADDR_gio_rw_pc_dout 48
213
214/* Register r_pc_din, scope gio, type r */
215typedef struct {
216 unsigned int data : 18;
217 unsigned int dummy1 : 14;
218} reg_gio_r_pc_din;
219#define REG_RD_ADDR_gio_r_pc_din 52
220
221/* Register rw_pc_oe, scope gio, type rw */
222typedef struct {
223 unsigned int oe : 18;
224 unsigned int dummy1 : 14;
225} reg_gio_rw_pc_oe;
226#define REG_RD_ADDR_gio_rw_pc_oe 56
227#define REG_WR_ADDR_gio_rw_pc_oe 56
228
229/* Register rw_pd_dout, scope gio, type rw */
230typedef struct {
231 unsigned int data : 18;
232 unsigned int dummy1 : 14;
233} reg_gio_rw_pd_dout;
234#define REG_RD_ADDR_gio_rw_pd_dout 64
235#define REG_WR_ADDR_gio_rw_pd_dout 64
236
237/* Register r_pd_din, scope gio, type r */
238typedef struct {
239 unsigned int data : 18;
240 unsigned int dummy1 : 14;
241} reg_gio_r_pd_din;
242#define REG_RD_ADDR_gio_r_pd_din 68
243
244/* Register rw_pd_oe, scope gio, type rw */
245typedef struct {
246 unsigned int oe : 18;
247 unsigned int dummy1 : 14;
248} reg_gio_rw_pd_oe;
249#define REG_RD_ADDR_gio_rw_pd_oe 72
250#define REG_WR_ADDR_gio_rw_pd_oe 72
251
252/* Register rw_pe_dout, scope gio, type rw */
253typedef struct {
254 unsigned int data : 18;
255 unsigned int dummy1 : 14;
256} reg_gio_rw_pe_dout;
257#define REG_RD_ADDR_gio_rw_pe_dout 80
258#define REG_WR_ADDR_gio_rw_pe_dout 80
259
260/* Register r_pe_din, scope gio, type r */
261typedef struct {
262 unsigned int data : 18;
263 unsigned int dummy1 : 14;
264} reg_gio_r_pe_din;
265#define REG_RD_ADDR_gio_r_pe_din 84
266
267/* Register rw_pe_oe, scope gio, type rw */
268typedef struct {
269 unsigned int oe : 18;
270 unsigned int dummy1 : 14;
271} reg_gio_rw_pe_oe;
272#define REG_RD_ADDR_gio_rw_pe_oe 88
273#define REG_WR_ADDR_gio_rw_pe_oe 88
274
275
276/* Constants */
277enum {
278 regk_gio_anyedge = 0x00000007,
279 regk_gio_hi = 0x00000001,
280 regk_gio_lo = 0x00000002,
281 regk_gio_negedge = 0x00000006,
282 regk_gio_no = 0x00000000,
283 regk_gio_off = 0x00000000,
284 regk_gio_posedge = 0x00000005,
285 regk_gio_rw_intr_cfg_default = 0x00000000,
286 regk_gio_rw_intr_mask_default = 0x00000000,
287 regk_gio_rw_pa_oe_default = 0x00000000,
288 regk_gio_rw_pb_oe_default = 0x00000000,
289 regk_gio_rw_pc_oe_default = 0x00000000,
290 regk_gio_rw_pd_oe_default = 0x00000000,
291 regk_gio_rw_pe_oe_default = 0x00000000,
292 regk_gio_set = 0x00000003,
293 regk_gio_yes = 0x00000001
294};
295#endif /* __gio_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/intr_vect.h b/include/asm-cris/arch-v32/hwregs/intr_vect.h
new file mode 100644
index 000000000000..5c1b28fb205d
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/intr_vect.h
@@ -0,0 +1,39 @@
1/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
2 from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
3version . */
4
5#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
6#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
7#define MEMARB_INTR_VECT 0x31
8#define GEN_IO_INTR_VECT 0x32
9#define IOP0_INTR_VECT 0x33
10#define IOP1_INTR_VECT 0x34
11#define IOP2_INTR_VECT 0x35
12#define IOP3_INTR_VECT 0x36
13#define DMA0_INTR_VECT 0x37
14#define DMA1_INTR_VECT 0x38
15#define DMA2_INTR_VECT 0x39
16#define DMA3_INTR_VECT 0x3a
17#define DMA4_INTR_VECT 0x3b
18#define DMA5_INTR_VECT 0x3c
19#define DMA6_INTR_VECT 0x3d
20#define DMA7_INTR_VECT 0x3e
21#define DMA8_INTR_VECT 0x3f
22#define DMA9_INTR_VECT 0x40
23#define ATA_INTR_VECT 0x41
24#define SSER0_INTR_VECT 0x42
25#define SSER1_INTR_VECT 0x43
26#define SER0_INTR_VECT 0x44
27#define SER1_INTR_VECT 0x45
28#define SER2_INTR_VECT 0x46
29#define SER3_INTR_VECT 0x47
30#define P21_INTR_VECT 0x48
31#define ETH0_INTR_VECT 0x49
32#define ETH1_INTR_VECT 0x4a
33#define TIMER_INTR_VECT 0x4b
34#define BIF_ARB_INTR_VECT 0x4c
35#define BIF_DMA_INTR_VECT 0x4d
36#define EXT_INTR_VECT 0x4e
37#define IPI_INTR_VECT 0x4f
38
39#endif
diff --git a/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h
new file mode 100644
index 000000000000..535aaf1b4b52
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h
@@ -0,0 +1,225 @@
1#ifndef __intr_vect_defs_h
2#define __intr_vect_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r
7 * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
8 * last modfied: Mon Apr 11 16:08:03 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
11 * id: $Id: intr_vect_defs.h,v 1.8 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope intr_vect */
86
87/* Register rw_mask, scope intr_vect, type rw */
88typedef struct {
89 unsigned int memarb : 1;
90 unsigned int gen_io : 1;
91 unsigned int iop0 : 1;
92 unsigned int iop1 : 1;
93 unsigned int iop2 : 1;
94 unsigned int iop3 : 1;
95 unsigned int dma0 : 1;
96 unsigned int dma1 : 1;
97 unsigned int dma2 : 1;
98 unsigned int dma3 : 1;
99 unsigned int dma4 : 1;
100 unsigned int dma5 : 1;
101 unsigned int dma6 : 1;
102 unsigned int dma7 : 1;
103 unsigned int dma8 : 1;
104 unsigned int dma9 : 1;
105 unsigned int ata : 1;
106 unsigned int sser0 : 1;
107 unsigned int sser1 : 1;
108 unsigned int ser0 : 1;
109 unsigned int ser1 : 1;
110 unsigned int ser2 : 1;
111 unsigned int ser3 : 1;
112 unsigned int p21 : 1;
113 unsigned int eth0 : 1;
114 unsigned int eth1 : 1;
115 unsigned int timer : 1;
116 unsigned int bif_arb : 1;
117 unsigned int bif_dma : 1;
118 unsigned int ext : 1;
119 unsigned int dummy1 : 2;
120} reg_intr_vect_rw_mask;
121#define REG_RD_ADDR_intr_vect_rw_mask 0
122#define REG_WR_ADDR_intr_vect_rw_mask 0
123
124/* Register r_vect, scope intr_vect, type r */
125typedef struct {
126 unsigned int memarb : 1;
127 unsigned int gen_io : 1;
128 unsigned int iop0 : 1;
129 unsigned int iop1 : 1;
130 unsigned int iop2 : 1;
131 unsigned int iop3 : 1;
132 unsigned int dma0 : 1;
133 unsigned int dma1 : 1;
134 unsigned int dma2 : 1;
135 unsigned int dma3 : 1;
136 unsigned int dma4 : 1;
137 unsigned int dma5 : 1;
138 unsigned int dma6 : 1;
139 unsigned int dma7 : 1;
140 unsigned int dma8 : 1;
141 unsigned int dma9 : 1;
142 unsigned int ata : 1;
143 unsigned int sser0 : 1;
144 unsigned int sser1 : 1;
145 unsigned int ser0 : 1;
146 unsigned int ser1 : 1;
147 unsigned int ser2 : 1;
148 unsigned int ser3 : 1;
149 unsigned int p21 : 1;
150 unsigned int eth0 : 1;
151 unsigned int eth1 : 1;
152 unsigned int timer : 1;
153 unsigned int bif_arb : 1;
154 unsigned int bif_dma : 1;
155 unsigned int ext : 1;
156 unsigned int dummy1 : 2;
157} reg_intr_vect_r_vect;
158#define REG_RD_ADDR_intr_vect_r_vect 4
159
160/* Register r_masked_vect, scope intr_vect, type r */
161typedef struct {
162 unsigned int memarb : 1;
163 unsigned int gen_io : 1;
164 unsigned int iop0 : 1;
165 unsigned int iop1 : 1;
166 unsigned int iop2 : 1;
167 unsigned int iop3 : 1;
168 unsigned int dma0 : 1;
169 unsigned int dma1 : 1;
170 unsigned int dma2 : 1;
171 unsigned int dma3 : 1;
172 unsigned int dma4 : 1;
173 unsigned int dma5 : 1;
174 unsigned int dma6 : 1;
175 unsigned int dma7 : 1;
176 unsigned int dma8 : 1;
177 unsigned int dma9 : 1;
178 unsigned int ata : 1;
179 unsigned int sser0 : 1;
180 unsigned int sser1 : 1;
181 unsigned int ser0 : 1;
182 unsigned int ser1 : 1;
183 unsigned int ser2 : 1;
184 unsigned int ser3 : 1;
185 unsigned int p21 : 1;
186 unsigned int eth0 : 1;
187 unsigned int eth1 : 1;
188 unsigned int timer : 1;
189 unsigned int bif_arb : 1;
190 unsigned int bif_dma : 1;
191 unsigned int ext : 1;
192 unsigned int dummy1 : 2;
193} reg_intr_vect_r_masked_vect;
194#define REG_RD_ADDR_intr_vect_r_masked_vect 8
195
196/* Register r_nmi, scope intr_vect, type r */
197typedef struct {
198 unsigned int ext : 1;
199 unsigned int watchdog : 1;
200 unsigned int dummy1 : 30;
201} reg_intr_vect_r_nmi;
202#define REG_RD_ADDR_intr_vect_r_nmi 12
203
204/* Register r_guru, scope intr_vect, type r */
205typedef struct {
206 unsigned int jtag : 1;
207 unsigned int dummy1 : 31;
208} reg_intr_vect_r_guru;
209#define REG_RD_ADDR_intr_vect_r_guru 16
210
211/* Register rw_ipi, scope intr_vect, type rw */
212typedef struct
213{
214 unsigned int vector;
215} reg_intr_vect_rw_ipi;
216#define REG_RD_ADDR_intr_vect_rw_ipi 20
217#define REG_WR_ADDR_intr_vect_rw_ipi 20
218
219/* Constants */
220enum {
221 regk_intr_vect_off = 0x00000000,
222 regk_intr_vect_on = 0x00000001,
223 regk_intr_vect_rw_mask_default = 0x00000000
224};
225#endif /* __intr_vect_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/Makefile b/include/asm-cris/arch-v32/hwregs/iop/Makefile
new file mode 100644
index 000000000000..a90056a095e3
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/Makefile
@@ -0,0 +1,146 @@
1# $Id: Makefile,v 1.3 2004/01/07 20:34:55 johana Exp $
2# Makefile to generate or copy the latest register definitions
3# and related datastructures and helpermacros.
4# The offical place for these files is probably at:
5RELEASE ?= r1_alfa5
6IOPOFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/
7
8IOPROCDIR = /n/asic/design/io/io_proc/rtl
9
10IOPROCINCL_FILES =
11IOPROCINCL_FILES2=
12IOPROCINCL_FILES += iop_crc_par_defs.h
13IOPROCINCL_FILES += iop_dmc_in_defs.h
14IOPROCINCL_FILES += iop_dmc_out_defs.h
15IOPROCINCL_FILES += iop_fifo_in_defs.h
16IOPROCINCL_FILES += iop_fifo_in_xtra_defs.h
17IOPROCINCL_FILES += iop_fifo_out_defs.h
18IOPROCINCL_FILES += iop_fifo_out_xtra_defs.h
19IOPROCINCL_FILES += iop_mpu_defs.h
20IOPROCINCL_FILES2+= iop_mpu_macros.h
21IOPROCINCL_FILES2+= iop_reg_space.h
22IOPROCINCL_FILES += iop_sap_in_defs.h
23IOPROCINCL_FILES += iop_sap_out_defs.h
24IOPROCINCL_FILES += iop_scrc_in_defs.h
25IOPROCINCL_FILES += iop_scrc_out_defs.h
26IOPROCINCL_FILES += iop_spu_defs.h
27# in guiness/
28IOPROCINCL_FILES += iop_sw_cfg_defs.h
29IOPROCINCL_FILES += iop_sw_cpu_defs.h
30IOPROCINCL_FILES += iop_sw_mpu_defs.h
31IOPROCINCL_FILES += iop_sw_spu_defs.h
32#
33IOPROCINCL_FILES += iop_timer_grp_defs.h
34IOPROCINCL_FILES += iop_trigger_grp_defs.h
35# in guiness/
36IOPROCINCL_FILES += iop_version_defs.h
37
38IOPROCASMINCL_FILES = $(patsubst %_defs.h,%_defs_asm.h,$(IOPROCINCL_FILES))
39IOPROCASMINCL_FILES+= iop_reg_space_asm.h
40
41
42IOPROCREGDESC =
43IOPROCREGDESC += $(IOPROCDIR)/iop_crc_par.r
44#IOPROCREGDESC += $(IOPROCDIR)/iop_crc_ser.r
45IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_in.r
46IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_out.r
47IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in.r
48IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in_xtra.r
49IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out.r
50IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out_xtra.r
51IOPROCREGDESC += $(IOPROCDIR)/iop_mpu.r
52IOPROCREGDESC += $(IOPROCDIR)/iop_sap_in.r
53IOPROCREGDESC += $(IOPROCDIR)/iop_sap_out.r
54IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_in.r
55IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_out.r
56IOPROCREGDESC += $(IOPROCDIR)/iop_spu.r
57IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cfg.r
58IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cpu.r
59IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_mpu.r
60IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_spu.r
61IOPROCREGDESC += $(IOPROCDIR)/iop_timer_grp.r
62IOPROCREGDESC += $(IOPROCDIR)/iop_trigger_grp.r
63IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_version.r
64
65
66RDES2C = /n/asic/bin/rdes2c
67RDES2C = /n/asic/design/tools/rdesc/rdes2c
68RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr
69RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt
70
71## all - Just print help - you probably want to do 'make gen'
72all: help
73
74## help - This help
75help:
76 @grep '^## ' Makefile
77
78## gen - Generate include files
79gen: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES)
80 echo "INCL: $(IOPROCINCL_FILES)"
81 echo "INCL2: $(IOPROCINCL_FILES2)"
82 echo "ASMINCL: $(IOPROCASMINCL_FILES)"
83
84# From the official location...
85iop_reg_space.h: $(IOPOFFICIAL_INCDIR)/iop_reg_space.h
86 cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
87iop_mpu_macros.h: $(IOPOFFICIAL_INCDIR)/iop_mpu_macros.h
88 cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
89
90## copy - Copy files from official location
91copy:
92 @echo "## Copying and fixing iop files ##"
93 @for HFILE in $(IOPROCINCL_FILES); do \
94 echo " $$HFILE"; \
95 cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
96 done
97 @for HFILE in $(IOPROCINCL_FILES2); do \
98 echo " $$HFILE"; \
99 cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
100 done
101 @echo "## Copying and fixing iop asm files ##"
102 @for HFILE in $(IOPROCASMINCL_FILES); do \
103 echo " $$HFILE"; \
104 cat $(IOPOFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > asm/$$HFILE; \
105 done
106
107# I/O processor files:
108## iop - Generate I/O processor include files
109iop: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES)
110iop_sw_%_defs.h: $(IOPROCDIR)/guinness/iop_sw_%.r
111 $(RDES2C) $<
112iop_version_defs.h: $(IOPROCDIR)/guinness/iop_version.r
113 $(RDES2C) $<
114%_defs.h: $(IOPROCDIR)/%.r
115 $(RDES2C) $<
116%_defs_asm.h: $(IOPROCDIR)/%.r
117 $(RDES2C) -asm $<
118iop_version_defs_asm.h: $(IOPROCDIR)/guinness/iop_version.r
119 $(RDES2C) -asm $<
120
121## doc - Generate .axw files from register description.
122doc: $(IOPROCREGDESC)
123 for RDES in $^; do \
124 $(RDES2TXT) $$RDES; \
125 done
126
127.PHONY: axw
128## %.axw - Generate the specified .axw file (doesn't work for all files
129## due to inconsistent naming of .r files.
130%.axw: axw
131 @for RDES in $(IOPROCREGDESC); do \
132 if echo "$$RDES" | grep $* ; then \
133 $(RDES2TXT) $$RDES; \
134 fi \
135 done
136
137.PHONY: clean
138## clean - Remove .h files and .axw files.
139clean:
140 rm -rf $(IOPROCINCL_FILES) *.axw
141
142.PHONY: cleandoc
143## cleandoc - Remove .axw files.
144cleandoc:
145 rm -rf *.axw
146
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h
new file mode 100644
index 000000000000..a4b58000c164
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h
@@ -0,0 +1,171 @@
1#ifndef __iop_crc_par_defs_asm_h
2#define __iop_crc_par_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_crc_par.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:08:45 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r
11 * id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_cfg, scope iop_crc_par, type rw */
57#define reg_iop_crc_par_rw_cfg___mode___lsb 0
58#define reg_iop_crc_par_rw_cfg___mode___width 1
59#define reg_iop_crc_par_rw_cfg___mode___bit 0
60#define reg_iop_crc_par_rw_cfg___crc_out___lsb 1
61#define reg_iop_crc_par_rw_cfg___crc_out___width 1
62#define reg_iop_crc_par_rw_cfg___crc_out___bit 1
63#define reg_iop_crc_par_rw_cfg___rev_out___lsb 2
64#define reg_iop_crc_par_rw_cfg___rev_out___width 1
65#define reg_iop_crc_par_rw_cfg___rev_out___bit 2
66#define reg_iop_crc_par_rw_cfg___inv_out___lsb 3
67#define reg_iop_crc_par_rw_cfg___inv_out___width 1
68#define reg_iop_crc_par_rw_cfg___inv_out___bit 3
69#define reg_iop_crc_par_rw_cfg___trig___lsb 4
70#define reg_iop_crc_par_rw_cfg___trig___width 2
71#define reg_iop_crc_par_rw_cfg___poly___lsb 6
72#define reg_iop_crc_par_rw_cfg___poly___width 3
73#define reg_iop_crc_par_rw_cfg_offset 0
74
75/* Register rw_init_crc, scope iop_crc_par, type rw */
76#define reg_iop_crc_par_rw_init_crc_offset 4
77
78/* Register rw_correct_crc, scope iop_crc_par, type rw */
79#define reg_iop_crc_par_rw_correct_crc_offset 8
80
81/* Register rw_ctrl, scope iop_crc_par, type rw */
82#define reg_iop_crc_par_rw_ctrl___en___lsb 0
83#define reg_iop_crc_par_rw_ctrl___en___width 1
84#define reg_iop_crc_par_rw_ctrl___en___bit 0
85#define reg_iop_crc_par_rw_ctrl_offset 12
86
87/* Register rw_set_last, scope iop_crc_par, type rw */
88#define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0
89#define reg_iop_crc_par_rw_set_last___tr_dif___width 1
90#define reg_iop_crc_par_rw_set_last___tr_dif___bit 0
91#define reg_iop_crc_par_rw_set_last_offset 16
92
93/* Register rw_wr1byte, scope iop_crc_par, type rw */
94#define reg_iop_crc_par_rw_wr1byte___data___lsb 0
95#define reg_iop_crc_par_rw_wr1byte___data___width 8
96#define reg_iop_crc_par_rw_wr1byte_offset 20
97
98/* Register rw_wr2byte, scope iop_crc_par, type rw */
99#define reg_iop_crc_par_rw_wr2byte___data___lsb 0
100#define reg_iop_crc_par_rw_wr2byte___data___width 16
101#define reg_iop_crc_par_rw_wr2byte_offset 24
102
103/* Register rw_wr3byte, scope iop_crc_par, type rw */
104#define reg_iop_crc_par_rw_wr3byte___data___lsb 0
105#define reg_iop_crc_par_rw_wr3byte___data___width 24
106#define reg_iop_crc_par_rw_wr3byte_offset 28
107
108/* Register rw_wr4byte, scope iop_crc_par, type rw */
109#define reg_iop_crc_par_rw_wr4byte___data___lsb 0
110#define reg_iop_crc_par_rw_wr4byte___data___width 32
111#define reg_iop_crc_par_rw_wr4byte_offset 32
112
113/* Register rw_wr1byte_last, scope iop_crc_par, type rw */
114#define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0
115#define reg_iop_crc_par_rw_wr1byte_last___data___width 8
116#define reg_iop_crc_par_rw_wr1byte_last_offset 36
117
118/* Register rw_wr2byte_last, scope iop_crc_par, type rw */
119#define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0
120#define reg_iop_crc_par_rw_wr2byte_last___data___width 16
121#define reg_iop_crc_par_rw_wr2byte_last_offset 40
122
123/* Register rw_wr3byte_last, scope iop_crc_par, type rw */
124#define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0
125#define reg_iop_crc_par_rw_wr3byte_last___data___width 24
126#define reg_iop_crc_par_rw_wr3byte_last_offset 44
127
128/* Register rw_wr4byte_last, scope iop_crc_par, type rw */
129#define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0
130#define reg_iop_crc_par_rw_wr4byte_last___data___width 32
131#define reg_iop_crc_par_rw_wr4byte_last_offset 48
132
133/* Register r_stat, scope iop_crc_par, type r */
134#define reg_iop_crc_par_r_stat___err___lsb 0
135#define reg_iop_crc_par_r_stat___err___width 1
136#define reg_iop_crc_par_r_stat___err___bit 0
137#define reg_iop_crc_par_r_stat___busy___lsb 1
138#define reg_iop_crc_par_r_stat___busy___width 1
139#define reg_iop_crc_par_r_stat___busy___bit 1
140#define reg_iop_crc_par_r_stat_offset 52
141
142/* Register r_sh_reg, scope iop_crc_par, type r */
143#define reg_iop_crc_par_r_sh_reg_offset 56
144
145/* Register r_crc, scope iop_crc_par, type r */
146#define reg_iop_crc_par_r_crc_offset 60
147
148/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
149#define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0
150#define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2
151#define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64
152
153
154/* Constants */
155#define regk_iop_crc_par_calc 0x00000001
156#define regk_iop_crc_par_ccitt 0x00000002
157#define regk_iop_crc_par_check 0x00000000
158#define regk_iop_crc_par_crc16 0x00000001
159#define regk_iop_crc_par_crc32 0x00000000
160#define regk_iop_crc_par_crc5 0x00000003
161#define regk_iop_crc_par_crc5_11 0x00000004
162#define regk_iop_crc_par_dif_in 0x00000002
163#define regk_iop_crc_par_hi 0x00000000
164#define regk_iop_crc_par_neg 0x00000002
165#define regk_iop_crc_par_no 0x00000000
166#define regk_iop_crc_par_pos 0x00000001
167#define regk_iop_crc_par_pos_neg 0x00000003
168#define regk_iop_crc_par_rw_cfg_default 0x00000000
169#define regk_iop_crc_par_rw_ctrl_default 0x00000000
170#define regk_iop_crc_par_yes 0x00000001
171#endif /* __iop_crc_par_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h
new file mode 100644
index 000000000000..e7d539feccb1
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h
@@ -0,0 +1,321 @@
1#ifndef __iop_dmc_in_defs_asm_h
2#define __iop_dmc_in_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_dmc_in.r
7 * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp
8 * last modfied: Mon Apr 11 16:08:45 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r
11 * id: $Id: iop_dmc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_cfg, scope iop_dmc_in, type rw */
57#define reg_iop_dmc_in_rw_cfg___sth_intr___lsb 0
58#define reg_iop_dmc_in_rw_cfg___sth_intr___width 3
59#define reg_iop_dmc_in_rw_cfg___last_dis_dif___lsb 3
60#define reg_iop_dmc_in_rw_cfg___last_dis_dif___width 1
61#define reg_iop_dmc_in_rw_cfg___last_dis_dif___bit 3
62#define reg_iop_dmc_in_rw_cfg_offset 0
63
64/* Register rw_ctrl, scope iop_dmc_in, type rw */
65#define reg_iop_dmc_in_rw_ctrl___dif_en___lsb 0
66#define reg_iop_dmc_in_rw_ctrl___dif_en___width 1
67#define reg_iop_dmc_in_rw_ctrl___dif_en___bit 0
68#define reg_iop_dmc_in_rw_ctrl___dif_dis___lsb 1
69#define reg_iop_dmc_in_rw_ctrl___dif_dis___width 1
70#define reg_iop_dmc_in_rw_ctrl___dif_dis___bit 1
71#define reg_iop_dmc_in_rw_ctrl___stream_clr___lsb 2
72#define reg_iop_dmc_in_rw_ctrl___stream_clr___width 1
73#define reg_iop_dmc_in_rw_ctrl___stream_clr___bit 2
74#define reg_iop_dmc_in_rw_ctrl_offset 4
75
76/* Register r_stat, scope iop_dmc_in, type r */
77#define reg_iop_dmc_in_r_stat___dif_en___lsb 0
78#define reg_iop_dmc_in_r_stat___dif_en___width 1
79#define reg_iop_dmc_in_r_stat___dif_en___bit 0
80#define reg_iop_dmc_in_r_stat_offset 8
81
82/* Register rw_stream_cmd, scope iop_dmc_in, type rw */
83#define reg_iop_dmc_in_rw_stream_cmd___cmd___lsb 0
84#define reg_iop_dmc_in_rw_stream_cmd___cmd___width 10
85#define reg_iop_dmc_in_rw_stream_cmd___n___lsb 16
86#define reg_iop_dmc_in_rw_stream_cmd___n___width 8
87#define reg_iop_dmc_in_rw_stream_cmd_offset 12
88
89/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
90#define reg_iop_dmc_in_rw_stream_wr_data_offset 16
91
92/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
93#define reg_iop_dmc_in_rw_stream_wr_data_last_offset 20
94
95/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
96#define reg_iop_dmc_in_rw_stream_ctrl___eop___lsb 0
97#define reg_iop_dmc_in_rw_stream_ctrl___eop___width 1
98#define reg_iop_dmc_in_rw_stream_ctrl___eop___bit 0
99#define reg_iop_dmc_in_rw_stream_ctrl___wait___lsb 1
100#define reg_iop_dmc_in_rw_stream_ctrl___wait___width 1
101#define reg_iop_dmc_in_rw_stream_ctrl___wait___bit 1
102#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___lsb 2
103#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___width 1
104#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___bit 2
105#define reg_iop_dmc_in_rw_stream_ctrl___size___lsb 3
106#define reg_iop_dmc_in_rw_stream_ctrl___size___width 3
107#define reg_iop_dmc_in_rw_stream_ctrl_offset 24
108
109/* Register r_stream_stat, scope iop_dmc_in, type r */
110#define reg_iop_dmc_in_r_stream_stat___sth___lsb 0
111#define reg_iop_dmc_in_r_stream_stat___sth___width 7
112#define reg_iop_dmc_in_r_stream_stat___full___lsb 16
113#define reg_iop_dmc_in_r_stream_stat___full___width 1
114#define reg_iop_dmc_in_r_stream_stat___full___bit 16
115#define reg_iop_dmc_in_r_stream_stat___last_pkt___lsb 17
116#define reg_iop_dmc_in_r_stream_stat___last_pkt___width 1
117#define reg_iop_dmc_in_r_stream_stat___last_pkt___bit 17
118#define reg_iop_dmc_in_r_stream_stat___data_md_valid___lsb 18
119#define reg_iop_dmc_in_r_stream_stat___data_md_valid___width 1
120#define reg_iop_dmc_in_r_stream_stat___data_md_valid___bit 18
121#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___lsb 19
122#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___width 1
123#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___bit 19
124#define reg_iop_dmc_in_r_stream_stat___group_md_valid___lsb 20
125#define reg_iop_dmc_in_r_stream_stat___group_md_valid___width 1
126#define reg_iop_dmc_in_r_stream_stat___group_md_valid___bit 20
127#define reg_iop_dmc_in_r_stream_stat___stream_busy___lsb 21
128#define reg_iop_dmc_in_r_stream_stat___stream_busy___width 1
129#define reg_iop_dmc_in_r_stream_stat___stream_busy___bit 21
130#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___lsb 22
131#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___width 1
132#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___bit 22
133#define reg_iop_dmc_in_r_stream_stat_offset 28
134
135/* Register r_data_descr, scope iop_dmc_in, type r */
136#define reg_iop_dmc_in_r_data_descr___ctrl___lsb 0
137#define reg_iop_dmc_in_r_data_descr___ctrl___width 8
138#define reg_iop_dmc_in_r_data_descr___stat___lsb 8
139#define reg_iop_dmc_in_r_data_descr___stat___width 8
140#define reg_iop_dmc_in_r_data_descr___md___lsb 16
141#define reg_iop_dmc_in_r_data_descr___md___width 16
142#define reg_iop_dmc_in_r_data_descr_offset 32
143
144/* Register r_ctxt_descr, scope iop_dmc_in, type r */
145#define reg_iop_dmc_in_r_ctxt_descr___ctrl___lsb 0
146#define reg_iop_dmc_in_r_ctxt_descr___ctrl___width 8
147#define reg_iop_dmc_in_r_ctxt_descr___stat___lsb 8
148#define reg_iop_dmc_in_r_ctxt_descr___stat___width 8
149#define reg_iop_dmc_in_r_ctxt_descr___md0___lsb 16
150#define reg_iop_dmc_in_r_ctxt_descr___md0___width 16
151#define reg_iop_dmc_in_r_ctxt_descr_offset 36
152
153/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */
154#define reg_iop_dmc_in_r_ctxt_descr_md1_offset 40
155
156/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */
157#define reg_iop_dmc_in_r_ctxt_descr_md2_offset 44
158
159/* Register r_group_descr, scope iop_dmc_in, type r */
160#define reg_iop_dmc_in_r_group_descr___ctrl___lsb 0
161#define reg_iop_dmc_in_r_group_descr___ctrl___width 8
162#define reg_iop_dmc_in_r_group_descr___stat___lsb 8
163#define reg_iop_dmc_in_r_group_descr___stat___width 8
164#define reg_iop_dmc_in_r_group_descr___md___lsb 16
165#define reg_iop_dmc_in_r_group_descr___md___width 16
166#define reg_iop_dmc_in_r_group_descr_offset 56
167
168/* Register rw_data_descr, scope iop_dmc_in, type rw */
169#define reg_iop_dmc_in_rw_data_descr___md___lsb 16
170#define reg_iop_dmc_in_rw_data_descr___md___width 16
171#define reg_iop_dmc_in_rw_data_descr_offset 60
172
173/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
174#define reg_iop_dmc_in_rw_ctxt_descr___md0___lsb 16
175#define reg_iop_dmc_in_rw_ctxt_descr___md0___width 16
176#define reg_iop_dmc_in_rw_ctxt_descr_offset 64
177
178/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
179#define reg_iop_dmc_in_rw_ctxt_descr_md1_offset 68
180
181/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
182#define reg_iop_dmc_in_rw_ctxt_descr_md2_offset 72
183
184/* Register rw_group_descr, scope iop_dmc_in, type rw */
185#define reg_iop_dmc_in_rw_group_descr___md___lsb 16
186#define reg_iop_dmc_in_rw_group_descr___md___width 16
187#define reg_iop_dmc_in_rw_group_descr_offset 84
188
189/* Register rw_intr_mask, scope iop_dmc_in, type rw */
190#define reg_iop_dmc_in_rw_intr_mask___data_md___lsb 0
191#define reg_iop_dmc_in_rw_intr_mask___data_md___width 1
192#define reg_iop_dmc_in_rw_intr_mask___data_md___bit 0
193#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___lsb 1
194#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___width 1
195#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___bit 1
196#define reg_iop_dmc_in_rw_intr_mask___group_md___lsb 2
197#define reg_iop_dmc_in_rw_intr_mask___group_md___width 1
198#define reg_iop_dmc_in_rw_intr_mask___group_md___bit 2
199#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___lsb 3
200#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___width 1
201#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___bit 3
202#define reg_iop_dmc_in_rw_intr_mask___sth___lsb 4
203#define reg_iop_dmc_in_rw_intr_mask___sth___width 1
204#define reg_iop_dmc_in_rw_intr_mask___sth___bit 4
205#define reg_iop_dmc_in_rw_intr_mask___full___lsb 5
206#define reg_iop_dmc_in_rw_intr_mask___full___width 1
207#define reg_iop_dmc_in_rw_intr_mask___full___bit 5
208#define reg_iop_dmc_in_rw_intr_mask_offset 88
209
210/* Register rw_ack_intr, scope iop_dmc_in, type rw */
211#define reg_iop_dmc_in_rw_ack_intr___data_md___lsb 0
212#define reg_iop_dmc_in_rw_ack_intr___data_md___width 1
213#define reg_iop_dmc_in_rw_ack_intr___data_md___bit 0
214#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___lsb 1
215#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___width 1
216#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___bit 1
217#define reg_iop_dmc_in_rw_ack_intr___group_md___lsb 2
218#define reg_iop_dmc_in_rw_ack_intr___group_md___width 1
219#define reg_iop_dmc_in_rw_ack_intr___group_md___bit 2
220#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___lsb 3
221#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___width 1
222#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___bit 3
223#define reg_iop_dmc_in_rw_ack_intr___sth___lsb 4
224#define reg_iop_dmc_in_rw_ack_intr___sth___width 1
225#define reg_iop_dmc_in_rw_ack_intr___sth___bit 4
226#define reg_iop_dmc_in_rw_ack_intr___full___lsb 5
227#define reg_iop_dmc_in_rw_ack_intr___full___width 1
228#define reg_iop_dmc_in_rw_ack_intr___full___bit 5
229#define reg_iop_dmc_in_rw_ack_intr_offset 92
230
231/* Register r_intr, scope iop_dmc_in, type r */
232#define reg_iop_dmc_in_r_intr___data_md___lsb 0
233#define reg_iop_dmc_in_r_intr___data_md___width 1
234#define reg_iop_dmc_in_r_intr___data_md___bit 0
235#define reg_iop_dmc_in_r_intr___ctxt_md___lsb 1
236#define reg_iop_dmc_in_r_intr___ctxt_md___width 1
237#define reg_iop_dmc_in_r_intr___ctxt_md___bit 1
238#define reg_iop_dmc_in_r_intr___group_md___lsb 2
239#define reg_iop_dmc_in_r_intr___group_md___width 1
240#define reg_iop_dmc_in_r_intr___group_md___bit 2
241#define reg_iop_dmc_in_r_intr___cmd_rdy___lsb 3
242#define reg_iop_dmc_in_r_intr___cmd_rdy___width 1
243#define reg_iop_dmc_in_r_intr___cmd_rdy___bit 3
244#define reg_iop_dmc_in_r_intr___sth___lsb 4
245#define reg_iop_dmc_in_r_intr___sth___width 1
246#define reg_iop_dmc_in_r_intr___sth___bit 4
247#define reg_iop_dmc_in_r_intr___full___lsb 5
248#define reg_iop_dmc_in_r_intr___full___width 1
249#define reg_iop_dmc_in_r_intr___full___bit 5
250#define reg_iop_dmc_in_r_intr_offset 96
251
252/* Register r_masked_intr, scope iop_dmc_in, type r */
253#define reg_iop_dmc_in_r_masked_intr___data_md___lsb 0
254#define reg_iop_dmc_in_r_masked_intr___data_md___width 1
255#define reg_iop_dmc_in_r_masked_intr___data_md___bit 0
256#define reg_iop_dmc_in_r_masked_intr___ctxt_md___lsb 1
257#define reg_iop_dmc_in_r_masked_intr___ctxt_md___width 1
258#define reg_iop_dmc_in_r_masked_intr___ctxt_md___bit 1
259#define reg_iop_dmc_in_r_masked_intr___group_md___lsb 2
260#define reg_iop_dmc_in_r_masked_intr___group_md___width 1
261#define reg_iop_dmc_in_r_masked_intr___group_md___bit 2
262#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___lsb 3
263#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___width 1
264#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___bit 3
265#define reg_iop_dmc_in_r_masked_intr___sth___lsb 4
266#define reg_iop_dmc_in_r_masked_intr___sth___width 1
267#define reg_iop_dmc_in_r_masked_intr___sth___bit 4
268#define reg_iop_dmc_in_r_masked_intr___full___lsb 5
269#define reg_iop_dmc_in_r_masked_intr___full___width 1
270#define reg_iop_dmc_in_r_masked_intr___full___bit 5
271#define reg_iop_dmc_in_r_masked_intr_offset 100
272
273
274/* Constants */
275#define regk_iop_dmc_in_ack_pkt 0x00000100
276#define regk_iop_dmc_in_array 0x00000008
277#define regk_iop_dmc_in_burst 0x00000020
278#define regk_iop_dmc_in_copy_next 0x00000010
279#define regk_iop_dmc_in_copy_up 0x00000020
280#define regk_iop_dmc_in_dis_c 0x00000010
281#define regk_iop_dmc_in_dis_g 0x00000020
282#define regk_iop_dmc_in_lim1 0x00000000
283#define regk_iop_dmc_in_lim16 0x00000004
284#define regk_iop_dmc_in_lim2 0x00000001
285#define regk_iop_dmc_in_lim32 0x00000005
286#define regk_iop_dmc_in_lim4 0x00000002
287#define regk_iop_dmc_in_lim64 0x00000006
288#define regk_iop_dmc_in_lim8 0x00000003
289#define regk_iop_dmc_in_load_c 0x00000200
290#define regk_iop_dmc_in_load_c_n 0x00000280
291#define regk_iop_dmc_in_load_c_next 0x00000240
292#define regk_iop_dmc_in_load_d 0x00000140
293#define regk_iop_dmc_in_load_g 0x00000300
294#define regk_iop_dmc_in_load_g_down 0x000003c0
295#define regk_iop_dmc_in_load_g_next 0x00000340
296#define regk_iop_dmc_in_load_g_up 0x00000380
297#define regk_iop_dmc_in_next_en 0x00000010
298#define regk_iop_dmc_in_next_pkt 0x00000010
299#define regk_iop_dmc_in_no 0x00000000
300#define regk_iop_dmc_in_restore 0x00000020
301#define regk_iop_dmc_in_rw_cfg_default 0x00000000
302#define regk_iop_dmc_in_rw_ctxt_descr_default 0x00000000
303#define regk_iop_dmc_in_rw_ctxt_descr_md1_default 0x00000000
304#define regk_iop_dmc_in_rw_ctxt_descr_md2_default 0x00000000
305#define regk_iop_dmc_in_rw_data_descr_default 0x00000000
306#define regk_iop_dmc_in_rw_group_descr_default 0x00000000
307#define regk_iop_dmc_in_rw_intr_mask_default 0x00000000
308#define regk_iop_dmc_in_rw_stream_ctrl_default 0x00000000
309#define regk_iop_dmc_in_save_down 0x00000020
310#define regk_iop_dmc_in_save_up 0x00000020
311#define regk_iop_dmc_in_set_reg 0x00000050
312#define regk_iop_dmc_in_set_w_size1 0x00000190
313#define regk_iop_dmc_in_set_w_size2 0x000001a0
314#define regk_iop_dmc_in_set_w_size4 0x000001c0
315#define regk_iop_dmc_in_store_c 0x00000002
316#define regk_iop_dmc_in_store_descr 0x00000000
317#define regk_iop_dmc_in_store_g 0x00000004
318#define regk_iop_dmc_in_store_md 0x00000001
319#define regk_iop_dmc_in_update_down 0x00000020
320#define regk_iop_dmc_in_yes 0x00000001
321#endif /* __iop_dmc_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h
new file mode 100644
index 000000000000..9fe1a8054371
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h
@@ -0,0 +1,349 @@
1#ifndef __iop_dmc_out_defs_asm_h
2#define __iop_dmc_out_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_dmc_out.r
7 * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
8 * last modfied: Mon Apr 11 16:08:45 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r
11 * id: $Id: iop_dmc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_cfg, scope iop_dmc_out, type rw */
57#define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0
58#define reg_iop_dmc_out_rw_cfg___trf_lim___width 16
59#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16
60#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1
61#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16
62#define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17
63#define reg_iop_dmc_out_rw_cfg___dth_intr___width 3
64#define reg_iop_dmc_out_rw_cfg_offset 0
65
66/* Register rw_ctrl, scope iop_dmc_out, type rw */
67#define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0
68#define reg_iop_dmc_out_rw_ctrl___dif_en___width 1
69#define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0
70#define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1
71#define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1
72#define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1
73#define reg_iop_dmc_out_rw_ctrl_offset 4
74
75/* Register r_stat, scope iop_dmc_out, type r */
76#define reg_iop_dmc_out_r_stat___dif_en___lsb 0
77#define reg_iop_dmc_out_r_stat___dif_en___width 1
78#define reg_iop_dmc_out_r_stat___dif_en___bit 0
79#define reg_iop_dmc_out_r_stat_offset 8
80
81/* Register rw_stream_cmd, scope iop_dmc_out, type rw */
82#define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0
83#define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10
84#define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16
85#define reg_iop_dmc_out_rw_stream_cmd___n___width 8
86#define reg_iop_dmc_out_rw_stream_cmd_offset 12
87
88/* Register rs_stream_data, scope iop_dmc_out, type rs */
89#define reg_iop_dmc_out_rs_stream_data_offset 16
90
91/* Register r_stream_data, scope iop_dmc_out, type r */
92#define reg_iop_dmc_out_r_stream_data_offset 20
93
94/* Register r_stream_stat, scope iop_dmc_out, type r */
95#define reg_iop_dmc_out_r_stream_stat___dth___lsb 0
96#define reg_iop_dmc_out_r_stream_stat___dth___width 7
97#define reg_iop_dmc_out_r_stream_stat___dv___lsb 16
98#define reg_iop_dmc_out_r_stream_stat___dv___width 1
99#define reg_iop_dmc_out_r_stream_stat___dv___bit 16
100#define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17
101#define reg_iop_dmc_out_r_stream_stat___all_avail___width 1
102#define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17
103#define reg_iop_dmc_out_r_stream_stat___last___lsb 18
104#define reg_iop_dmc_out_r_stream_stat___last___width 1
105#define reg_iop_dmc_out_r_stream_stat___last___bit 18
106#define reg_iop_dmc_out_r_stream_stat___size___lsb 19
107#define reg_iop_dmc_out_r_stream_stat___size___width 3
108#define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22
109#define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1
110#define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22
111#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23
112#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1
113#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23
114#define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24
115#define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1
116#define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24
117#define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25
118#define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1
119#define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25
120#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26
121#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1
122#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26
123#define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27
124#define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1
125#define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27
126#define reg_iop_dmc_out_r_stream_stat_offset 24
127
128/* Register r_data_descr, scope iop_dmc_out, type r */
129#define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0
130#define reg_iop_dmc_out_r_data_descr___ctrl___width 8
131#define reg_iop_dmc_out_r_data_descr___stat___lsb 8
132#define reg_iop_dmc_out_r_data_descr___stat___width 8
133#define reg_iop_dmc_out_r_data_descr___md___lsb 16
134#define reg_iop_dmc_out_r_data_descr___md___width 16
135#define reg_iop_dmc_out_r_data_descr_offset 28
136
137/* Register r_ctxt_descr, scope iop_dmc_out, type r */
138#define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0
139#define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8
140#define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8
141#define reg_iop_dmc_out_r_ctxt_descr___stat___width 8
142#define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16
143#define reg_iop_dmc_out_r_ctxt_descr___md0___width 16
144#define reg_iop_dmc_out_r_ctxt_descr_offset 32
145
146/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
147#define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36
148
149/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
150#define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40
151
152/* Register r_group_descr, scope iop_dmc_out, type r */
153#define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0
154#define reg_iop_dmc_out_r_group_descr___ctrl___width 8
155#define reg_iop_dmc_out_r_group_descr___stat___lsb 8
156#define reg_iop_dmc_out_r_group_descr___stat___width 8
157#define reg_iop_dmc_out_r_group_descr___md___lsb 16
158#define reg_iop_dmc_out_r_group_descr___md___width 16
159#define reg_iop_dmc_out_r_group_descr_offset 52
160
161/* Register rw_data_descr, scope iop_dmc_out, type rw */
162#define reg_iop_dmc_out_rw_data_descr___md___lsb 16
163#define reg_iop_dmc_out_rw_data_descr___md___width 16
164#define reg_iop_dmc_out_rw_data_descr_offset 56
165
166/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
167#define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16
168#define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16
169#define reg_iop_dmc_out_rw_ctxt_descr_offset 60
170
171/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
172#define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64
173
174/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
175#define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68
176
177/* Register rw_group_descr, scope iop_dmc_out, type rw */
178#define reg_iop_dmc_out_rw_group_descr___md___lsb 16
179#define reg_iop_dmc_out_rw_group_descr___md___width 16
180#define reg_iop_dmc_out_rw_group_descr_offset 80
181
182/* Register rw_intr_mask, scope iop_dmc_out, type rw */
183#define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0
184#define reg_iop_dmc_out_rw_intr_mask___data_md___width 1
185#define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0
186#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1
187#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1
188#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1
189#define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2
190#define reg_iop_dmc_out_rw_intr_mask___group_md___width 1
191#define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2
192#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3
193#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1
194#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3
195#define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4
196#define reg_iop_dmc_out_rw_intr_mask___dth___width 1
197#define reg_iop_dmc_out_rw_intr_mask___dth___bit 4
198#define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5
199#define reg_iop_dmc_out_rw_intr_mask___dv___width 1
200#define reg_iop_dmc_out_rw_intr_mask___dv___bit 5
201#define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6
202#define reg_iop_dmc_out_rw_intr_mask___last_data___width 1
203#define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6
204#define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7
205#define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1
206#define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7
207#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8
208#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1
209#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8
210#define reg_iop_dmc_out_rw_intr_mask_offset 84
211
212/* Register rw_ack_intr, scope iop_dmc_out, type rw */
213#define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0
214#define reg_iop_dmc_out_rw_ack_intr___data_md___width 1
215#define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0
216#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1
217#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1
218#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1
219#define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2
220#define reg_iop_dmc_out_rw_ack_intr___group_md___width 1
221#define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2
222#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3
223#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1
224#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3
225#define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4
226#define reg_iop_dmc_out_rw_ack_intr___dth___width 1
227#define reg_iop_dmc_out_rw_ack_intr___dth___bit 4
228#define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5
229#define reg_iop_dmc_out_rw_ack_intr___dv___width 1
230#define reg_iop_dmc_out_rw_ack_intr___dv___bit 5
231#define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6
232#define reg_iop_dmc_out_rw_ack_intr___last_data___width 1
233#define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6
234#define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7
235#define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1
236#define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7
237#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8
238#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1
239#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8
240#define reg_iop_dmc_out_rw_ack_intr_offset 88
241
242/* Register r_intr, scope iop_dmc_out, type r */
243#define reg_iop_dmc_out_r_intr___data_md___lsb 0
244#define reg_iop_dmc_out_r_intr___data_md___width 1
245#define reg_iop_dmc_out_r_intr___data_md___bit 0
246#define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1
247#define reg_iop_dmc_out_r_intr___ctxt_md___width 1
248#define reg_iop_dmc_out_r_intr___ctxt_md___bit 1
249#define reg_iop_dmc_out_r_intr___group_md___lsb 2
250#define reg_iop_dmc_out_r_intr___group_md___width 1
251#define reg_iop_dmc_out_r_intr___group_md___bit 2
252#define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3
253#define reg_iop_dmc_out_r_intr___cmd_rdy___width 1
254#define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3
255#define reg_iop_dmc_out_r_intr___dth___lsb 4
256#define reg_iop_dmc_out_r_intr___dth___width 1
257#define reg_iop_dmc_out_r_intr___dth___bit 4
258#define reg_iop_dmc_out_r_intr___dv___lsb 5
259#define reg_iop_dmc_out_r_intr___dv___width 1
260#define reg_iop_dmc_out_r_intr___dv___bit 5
261#define reg_iop_dmc_out_r_intr___last_data___lsb 6
262#define reg_iop_dmc_out_r_intr___last_data___width 1
263#define reg_iop_dmc_out_r_intr___last_data___bit 6
264#define reg_iop_dmc_out_r_intr___trf_lim___lsb 7
265#define reg_iop_dmc_out_r_intr___trf_lim___width 1
266#define reg_iop_dmc_out_r_intr___trf_lim___bit 7
267#define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8
268#define reg_iop_dmc_out_r_intr___cmd_rq___width 1
269#define reg_iop_dmc_out_r_intr___cmd_rq___bit 8
270#define reg_iop_dmc_out_r_intr_offset 92
271
272/* Register r_masked_intr, scope iop_dmc_out, type r */
273#define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0
274#define reg_iop_dmc_out_r_masked_intr___data_md___width 1
275#define reg_iop_dmc_out_r_masked_intr___data_md___bit 0
276#define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1
277#define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1
278#define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1
279#define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2
280#define reg_iop_dmc_out_r_masked_intr___group_md___width 1
281#define reg_iop_dmc_out_r_masked_intr___group_md___bit 2
282#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3
283#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1
284#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3
285#define reg_iop_dmc_out_r_masked_intr___dth___lsb 4
286#define reg_iop_dmc_out_r_masked_intr___dth___width 1
287#define reg_iop_dmc_out_r_masked_intr___dth___bit 4
288#define reg_iop_dmc_out_r_masked_intr___dv___lsb 5
289#define reg_iop_dmc_out_r_masked_intr___dv___width 1
290#define reg_iop_dmc_out_r_masked_intr___dv___bit 5
291#define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6
292#define reg_iop_dmc_out_r_masked_intr___last_data___width 1
293#define reg_iop_dmc_out_r_masked_intr___last_data___bit 6
294#define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7
295#define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1
296#define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7
297#define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8
298#define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1
299#define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8
300#define reg_iop_dmc_out_r_masked_intr_offset 96
301
302
303/* Constants */
304#define regk_iop_dmc_out_ack_pkt 0x00000100
305#define regk_iop_dmc_out_array 0x00000008
306#define regk_iop_dmc_out_burst 0x00000020
307#define regk_iop_dmc_out_copy_next 0x00000010
308#define regk_iop_dmc_out_copy_up 0x00000020
309#define regk_iop_dmc_out_dis_c 0x00000010
310#define regk_iop_dmc_out_dis_g 0x00000020
311#define regk_iop_dmc_out_lim1 0x00000000
312#define regk_iop_dmc_out_lim16 0x00000004
313#define regk_iop_dmc_out_lim2 0x00000001
314#define regk_iop_dmc_out_lim32 0x00000005
315#define regk_iop_dmc_out_lim4 0x00000002
316#define regk_iop_dmc_out_lim64 0x00000006
317#define regk_iop_dmc_out_lim8 0x00000003
318#define regk_iop_dmc_out_load_c 0x00000200
319#define regk_iop_dmc_out_load_c_n 0x00000280
320#define regk_iop_dmc_out_load_c_next 0x00000240
321#define regk_iop_dmc_out_load_d 0x00000140
322#define regk_iop_dmc_out_load_g 0x00000300
323#define regk_iop_dmc_out_load_g_down 0x000003c0
324#define regk_iop_dmc_out_load_g_next 0x00000340
325#define regk_iop_dmc_out_load_g_up 0x00000380
326#define regk_iop_dmc_out_next_en 0x00000010
327#define regk_iop_dmc_out_next_pkt 0x00000010
328#define regk_iop_dmc_out_no 0x00000000
329#define regk_iop_dmc_out_restore 0x00000020
330#define regk_iop_dmc_out_rw_cfg_default 0x00000000
331#define regk_iop_dmc_out_rw_ctxt_descr_default 0x00000000
332#define regk_iop_dmc_out_rw_ctxt_descr_md1_default 0x00000000
333#define regk_iop_dmc_out_rw_ctxt_descr_md2_default 0x00000000
334#define regk_iop_dmc_out_rw_data_descr_default 0x00000000
335#define regk_iop_dmc_out_rw_group_descr_default 0x00000000
336#define regk_iop_dmc_out_rw_intr_mask_default 0x00000000
337#define regk_iop_dmc_out_save_down 0x00000020
338#define regk_iop_dmc_out_save_up 0x00000020
339#define regk_iop_dmc_out_set_reg 0x00000050
340#define regk_iop_dmc_out_set_w_size1 0x00000190
341#define regk_iop_dmc_out_set_w_size2 0x000001a0
342#define regk_iop_dmc_out_set_w_size4 0x000001c0
343#define regk_iop_dmc_out_store_c 0x00000002
344#define regk_iop_dmc_out_store_descr 0x00000000
345#define regk_iop_dmc_out_store_g 0x00000004
346#define regk_iop_dmc_out_store_md 0x00000001
347#define regk_iop_dmc_out_update_down 0x00000020
348#define regk_iop_dmc_out_yes 0x00000001
349#endif /* __iop_dmc_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h
new file mode 100644
index 000000000000..974dee082f9f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h
@@ -0,0 +1,234 @@
1#ifndef __iop_fifo_in_defs_asm_h
2#define __iop_fifo_in_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_fifo_in.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:10:07 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r
11 * id: $Id: iop_fifo_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_cfg, scope iop_fifo_in, type rw */
57#define reg_iop_fifo_in_rw_cfg___avail_lim___lsb 0
58#define reg_iop_fifo_in_rw_cfg___avail_lim___width 3
59#define reg_iop_fifo_in_rw_cfg___byte_order___lsb 3
60#define reg_iop_fifo_in_rw_cfg___byte_order___width 2
61#define reg_iop_fifo_in_rw_cfg___trig___lsb 5
62#define reg_iop_fifo_in_rw_cfg___trig___width 2
63#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___lsb 7
64#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___width 1
65#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___bit 7
66#define reg_iop_fifo_in_rw_cfg___mode___lsb 8
67#define reg_iop_fifo_in_rw_cfg___mode___width 2
68#define reg_iop_fifo_in_rw_cfg_offset 0
69
70/* Register rw_ctrl, scope iop_fifo_in, type rw */
71#define reg_iop_fifo_in_rw_ctrl___dif_in_en___lsb 0
72#define reg_iop_fifo_in_rw_ctrl___dif_in_en___width 1
73#define reg_iop_fifo_in_rw_ctrl___dif_in_en___bit 0
74#define reg_iop_fifo_in_rw_ctrl___dif_out_en___lsb 1
75#define reg_iop_fifo_in_rw_ctrl___dif_out_en___width 1
76#define reg_iop_fifo_in_rw_ctrl___dif_out_en___bit 1
77#define reg_iop_fifo_in_rw_ctrl_offset 4
78
79/* Register r_stat, scope iop_fifo_in, type r */
80#define reg_iop_fifo_in_r_stat___avail_bytes___lsb 0
81#define reg_iop_fifo_in_r_stat___avail_bytes___width 4
82#define reg_iop_fifo_in_r_stat___last___lsb 4
83#define reg_iop_fifo_in_r_stat___last___width 8
84#define reg_iop_fifo_in_r_stat___dif_in_en___lsb 12
85#define reg_iop_fifo_in_r_stat___dif_in_en___width 1
86#define reg_iop_fifo_in_r_stat___dif_in_en___bit 12
87#define reg_iop_fifo_in_r_stat___dif_out_en___lsb 13
88#define reg_iop_fifo_in_r_stat___dif_out_en___width 1
89#define reg_iop_fifo_in_r_stat___dif_out_en___bit 13
90#define reg_iop_fifo_in_r_stat_offset 8
91
92/* Register rs_rd1byte, scope iop_fifo_in, type rs */
93#define reg_iop_fifo_in_rs_rd1byte___data___lsb 0
94#define reg_iop_fifo_in_rs_rd1byte___data___width 8
95#define reg_iop_fifo_in_rs_rd1byte_offset 12
96
97/* Register r_rd1byte, scope iop_fifo_in, type r */
98#define reg_iop_fifo_in_r_rd1byte___data___lsb 0
99#define reg_iop_fifo_in_r_rd1byte___data___width 8
100#define reg_iop_fifo_in_r_rd1byte_offset 16
101
102/* Register rs_rd2byte, scope iop_fifo_in, type rs */
103#define reg_iop_fifo_in_rs_rd2byte___data___lsb 0
104#define reg_iop_fifo_in_rs_rd2byte___data___width 16
105#define reg_iop_fifo_in_rs_rd2byte_offset 20
106
107/* Register r_rd2byte, scope iop_fifo_in, type r */
108#define reg_iop_fifo_in_r_rd2byte___data___lsb 0
109#define reg_iop_fifo_in_r_rd2byte___data___width 16
110#define reg_iop_fifo_in_r_rd2byte_offset 24
111
112/* Register rs_rd3byte, scope iop_fifo_in, type rs */
113#define reg_iop_fifo_in_rs_rd3byte___data___lsb 0
114#define reg_iop_fifo_in_rs_rd3byte___data___width 24
115#define reg_iop_fifo_in_rs_rd3byte_offset 28
116
117/* Register r_rd3byte, scope iop_fifo_in, type r */
118#define reg_iop_fifo_in_r_rd3byte___data___lsb 0
119#define reg_iop_fifo_in_r_rd3byte___data___width 24
120#define reg_iop_fifo_in_r_rd3byte_offset 32
121
122/* Register rs_rd4byte, scope iop_fifo_in, type rs */
123#define reg_iop_fifo_in_rs_rd4byte___data___lsb 0
124#define reg_iop_fifo_in_rs_rd4byte___data___width 32
125#define reg_iop_fifo_in_rs_rd4byte_offset 36
126
127/* Register r_rd4byte, scope iop_fifo_in, type r */
128#define reg_iop_fifo_in_r_rd4byte___data___lsb 0
129#define reg_iop_fifo_in_r_rd4byte___data___width 32
130#define reg_iop_fifo_in_r_rd4byte_offset 40
131
132/* Register rw_set_last, scope iop_fifo_in, type rw */
133#define reg_iop_fifo_in_rw_set_last_offset 44
134
135/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
136#define reg_iop_fifo_in_rw_strb_dif_in___last___lsb 0
137#define reg_iop_fifo_in_rw_strb_dif_in___last___width 2
138#define reg_iop_fifo_in_rw_strb_dif_in_offset 48
139
140/* Register rw_intr_mask, scope iop_fifo_in, type rw */
141#define reg_iop_fifo_in_rw_intr_mask___urun___lsb 0
142#define reg_iop_fifo_in_rw_intr_mask___urun___width 1
143#define reg_iop_fifo_in_rw_intr_mask___urun___bit 0
144#define reg_iop_fifo_in_rw_intr_mask___last_data___lsb 1
145#define reg_iop_fifo_in_rw_intr_mask___last_data___width 1
146#define reg_iop_fifo_in_rw_intr_mask___last_data___bit 1
147#define reg_iop_fifo_in_rw_intr_mask___dav___lsb 2
148#define reg_iop_fifo_in_rw_intr_mask___dav___width 1
149#define reg_iop_fifo_in_rw_intr_mask___dav___bit 2
150#define reg_iop_fifo_in_rw_intr_mask___avail___lsb 3
151#define reg_iop_fifo_in_rw_intr_mask___avail___width 1
152#define reg_iop_fifo_in_rw_intr_mask___avail___bit 3
153#define reg_iop_fifo_in_rw_intr_mask___orun___lsb 4
154#define reg_iop_fifo_in_rw_intr_mask___orun___width 1
155#define reg_iop_fifo_in_rw_intr_mask___orun___bit 4
156#define reg_iop_fifo_in_rw_intr_mask_offset 52
157
158/* Register rw_ack_intr, scope iop_fifo_in, type rw */
159#define reg_iop_fifo_in_rw_ack_intr___urun___lsb 0
160#define reg_iop_fifo_in_rw_ack_intr___urun___width 1
161#define reg_iop_fifo_in_rw_ack_intr___urun___bit 0
162#define reg_iop_fifo_in_rw_ack_intr___last_data___lsb 1
163#define reg_iop_fifo_in_rw_ack_intr___last_data___width 1
164#define reg_iop_fifo_in_rw_ack_intr___last_data___bit 1
165#define reg_iop_fifo_in_rw_ack_intr___dav___lsb 2
166#define reg_iop_fifo_in_rw_ack_intr___dav___width 1
167#define reg_iop_fifo_in_rw_ack_intr___dav___bit 2
168#define reg_iop_fifo_in_rw_ack_intr___avail___lsb 3
169#define reg_iop_fifo_in_rw_ack_intr___avail___width 1
170#define reg_iop_fifo_in_rw_ack_intr___avail___bit 3
171#define reg_iop_fifo_in_rw_ack_intr___orun___lsb 4
172#define reg_iop_fifo_in_rw_ack_intr___orun___width 1
173#define reg_iop_fifo_in_rw_ack_intr___orun___bit 4
174#define reg_iop_fifo_in_rw_ack_intr_offset 56
175
176/* Register r_intr, scope iop_fifo_in, type r */
177#define reg_iop_fifo_in_r_intr___urun___lsb 0
178#define reg_iop_fifo_in_r_intr___urun___width 1
179#define reg_iop_fifo_in_r_intr___urun___bit 0
180#define reg_iop_fifo_in_r_intr___last_data___lsb 1
181#define reg_iop_fifo_in_r_intr___last_data___width 1
182#define reg_iop_fifo_in_r_intr___last_data___bit 1
183#define reg_iop_fifo_in_r_intr___dav___lsb 2
184#define reg_iop_fifo_in_r_intr___dav___width 1
185#define reg_iop_fifo_in_r_intr___dav___bit 2
186#define reg_iop_fifo_in_r_intr___avail___lsb 3
187#define reg_iop_fifo_in_r_intr___avail___width 1
188#define reg_iop_fifo_in_r_intr___avail___bit 3
189#define reg_iop_fifo_in_r_intr___orun___lsb 4
190#define reg_iop_fifo_in_r_intr___orun___width 1
191#define reg_iop_fifo_in_r_intr___orun___bit 4
192#define reg_iop_fifo_in_r_intr_offset 60
193
194/* Register r_masked_intr, scope iop_fifo_in, type r */
195#define reg_iop_fifo_in_r_masked_intr___urun___lsb 0
196#define reg_iop_fifo_in_r_masked_intr___urun___width 1
197#define reg_iop_fifo_in_r_masked_intr___urun___bit 0
198#define reg_iop_fifo_in_r_masked_intr___last_data___lsb 1
199#define reg_iop_fifo_in_r_masked_intr___last_data___width 1
200#define reg_iop_fifo_in_r_masked_intr___last_data___bit 1
201#define reg_iop_fifo_in_r_masked_intr___dav___lsb 2
202#define reg_iop_fifo_in_r_masked_intr___dav___width 1
203#define reg_iop_fifo_in_r_masked_intr___dav___bit 2
204#define reg_iop_fifo_in_r_masked_intr___avail___lsb 3
205#define reg_iop_fifo_in_r_masked_intr___avail___width 1
206#define reg_iop_fifo_in_r_masked_intr___avail___bit 3
207#define reg_iop_fifo_in_r_masked_intr___orun___lsb 4
208#define reg_iop_fifo_in_r_masked_intr___orun___width 1
209#define reg_iop_fifo_in_r_masked_intr___orun___bit 4
210#define reg_iop_fifo_in_r_masked_intr_offset 64
211
212
213/* Constants */
214#define regk_iop_fifo_in_dif_in 0x00000002
215#define regk_iop_fifo_in_hi 0x00000000
216#define regk_iop_fifo_in_neg 0x00000002
217#define regk_iop_fifo_in_no 0x00000000
218#define regk_iop_fifo_in_order16 0x00000001
219#define regk_iop_fifo_in_order24 0x00000002
220#define regk_iop_fifo_in_order32 0x00000003
221#define regk_iop_fifo_in_order8 0x00000000
222#define regk_iop_fifo_in_pos 0x00000001
223#define regk_iop_fifo_in_pos_neg 0x00000003
224#define regk_iop_fifo_in_rw_cfg_default 0x00000024
225#define regk_iop_fifo_in_rw_ctrl_default 0x00000000
226#define regk_iop_fifo_in_rw_intr_mask_default 0x00000000
227#define regk_iop_fifo_in_rw_set_last_default 0x00000000
228#define regk_iop_fifo_in_rw_strb_dif_in_default 0x00000000
229#define regk_iop_fifo_in_size16 0x00000002
230#define regk_iop_fifo_in_size24 0x00000001
231#define regk_iop_fifo_in_size32 0x00000000
232#define regk_iop_fifo_in_size8 0x00000003
233#define regk_iop_fifo_in_yes 0x00000001
234#endif /* __iop_fifo_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h
new file mode 100644
index 000000000000..e00fab0c9335
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h
@@ -0,0 +1,155 @@
1#ifndef __iop_fifo_in_extra_defs_asm_h
2#define __iop_fifo_in_extra_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:10:08 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
11 * id: $Id: iop_fifo_in_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
57#define reg_iop_fifo_in_extra_rw_wr_data_offset 0
58
59/* Register r_stat, scope iop_fifo_in_extra, type r */
60#define reg_iop_fifo_in_extra_r_stat___avail_bytes___lsb 0
61#define reg_iop_fifo_in_extra_r_stat___avail_bytes___width 4
62#define reg_iop_fifo_in_extra_r_stat___last___lsb 4
63#define reg_iop_fifo_in_extra_r_stat___last___width 8
64#define reg_iop_fifo_in_extra_r_stat___dif_in_en___lsb 12
65#define reg_iop_fifo_in_extra_r_stat___dif_in_en___width 1
66#define reg_iop_fifo_in_extra_r_stat___dif_in_en___bit 12
67#define reg_iop_fifo_in_extra_r_stat___dif_out_en___lsb 13
68#define reg_iop_fifo_in_extra_r_stat___dif_out_en___width 1
69#define reg_iop_fifo_in_extra_r_stat___dif_out_en___bit 13
70#define reg_iop_fifo_in_extra_r_stat_offset 4
71
72/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
73#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___lsb 0
74#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___width 2
75#define reg_iop_fifo_in_extra_rw_strb_dif_in_offset 8
76
77/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
78#define reg_iop_fifo_in_extra_rw_intr_mask___urun___lsb 0
79#define reg_iop_fifo_in_extra_rw_intr_mask___urun___width 1
80#define reg_iop_fifo_in_extra_rw_intr_mask___urun___bit 0
81#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___lsb 1
82#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___width 1
83#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___bit 1
84#define reg_iop_fifo_in_extra_rw_intr_mask___dav___lsb 2
85#define reg_iop_fifo_in_extra_rw_intr_mask___dav___width 1
86#define reg_iop_fifo_in_extra_rw_intr_mask___dav___bit 2
87#define reg_iop_fifo_in_extra_rw_intr_mask___avail___lsb 3
88#define reg_iop_fifo_in_extra_rw_intr_mask___avail___width 1
89#define reg_iop_fifo_in_extra_rw_intr_mask___avail___bit 3
90#define reg_iop_fifo_in_extra_rw_intr_mask___orun___lsb 4
91#define reg_iop_fifo_in_extra_rw_intr_mask___orun___width 1
92#define reg_iop_fifo_in_extra_rw_intr_mask___orun___bit 4
93#define reg_iop_fifo_in_extra_rw_intr_mask_offset 12
94
95/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
96#define reg_iop_fifo_in_extra_rw_ack_intr___urun___lsb 0
97#define reg_iop_fifo_in_extra_rw_ack_intr___urun___width 1
98#define reg_iop_fifo_in_extra_rw_ack_intr___urun___bit 0
99#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___lsb 1
100#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___width 1
101#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___bit 1
102#define reg_iop_fifo_in_extra_rw_ack_intr___dav___lsb 2
103#define reg_iop_fifo_in_extra_rw_ack_intr___dav___width 1
104#define reg_iop_fifo_in_extra_rw_ack_intr___dav___bit 2
105#define reg_iop_fifo_in_extra_rw_ack_intr___avail___lsb 3
106#define reg_iop_fifo_in_extra_rw_ack_intr___avail___width 1
107#define reg_iop_fifo_in_extra_rw_ack_intr___avail___bit 3
108#define reg_iop_fifo_in_extra_rw_ack_intr___orun___lsb 4
109#define reg_iop_fifo_in_extra_rw_ack_intr___orun___width 1
110#define reg_iop_fifo_in_extra_rw_ack_intr___orun___bit 4
111#define reg_iop_fifo_in_extra_rw_ack_intr_offset 16
112
113/* Register r_intr, scope iop_fifo_in_extra, type r */
114#define reg_iop_fifo_in_extra_r_intr___urun___lsb 0
115#define reg_iop_fifo_in_extra_r_intr___urun___width 1
116#define reg_iop_fifo_in_extra_r_intr___urun___bit 0
117#define reg_iop_fifo_in_extra_r_intr___last_data___lsb 1
118#define reg_iop_fifo_in_extra_r_intr___last_data___width 1
119#define reg_iop_fifo_in_extra_r_intr___last_data___bit 1
120#define reg_iop_fifo_in_extra_r_intr___dav___lsb 2
121#define reg_iop_fifo_in_extra_r_intr___dav___width 1
122#define reg_iop_fifo_in_extra_r_intr___dav___bit 2
123#define reg_iop_fifo_in_extra_r_intr___avail___lsb 3
124#define reg_iop_fifo_in_extra_r_intr___avail___width 1
125#define reg_iop_fifo_in_extra_r_intr___avail___bit 3
126#define reg_iop_fifo_in_extra_r_intr___orun___lsb 4
127#define reg_iop_fifo_in_extra_r_intr___orun___width 1
128#define reg_iop_fifo_in_extra_r_intr___orun___bit 4
129#define reg_iop_fifo_in_extra_r_intr_offset 20
130
131/* Register r_masked_intr, scope iop_fifo_in_extra, type r */
132#define reg_iop_fifo_in_extra_r_masked_intr___urun___lsb 0
133#define reg_iop_fifo_in_extra_r_masked_intr___urun___width 1
134#define reg_iop_fifo_in_extra_r_masked_intr___urun___bit 0
135#define reg_iop_fifo_in_extra_r_masked_intr___last_data___lsb 1
136#define reg_iop_fifo_in_extra_r_masked_intr___last_data___width 1
137#define reg_iop_fifo_in_extra_r_masked_intr___last_data___bit 1
138#define reg_iop_fifo_in_extra_r_masked_intr___dav___lsb 2
139#define reg_iop_fifo_in_extra_r_masked_intr___dav___width 1
140#define reg_iop_fifo_in_extra_r_masked_intr___dav___bit 2
141#define reg_iop_fifo_in_extra_r_masked_intr___avail___lsb 3
142#define reg_iop_fifo_in_extra_r_masked_intr___avail___width 1
143#define reg_iop_fifo_in_extra_r_masked_intr___avail___bit 3
144#define reg_iop_fifo_in_extra_r_masked_intr___orun___lsb 4
145#define reg_iop_fifo_in_extra_r_masked_intr___orun___width 1
146#define reg_iop_fifo_in_extra_r_masked_intr___orun___bit 4
147#define reg_iop_fifo_in_extra_r_masked_intr_offset 24
148
149
150/* Constants */
151#define regk_iop_fifo_in_extra_fifo_in 0x00000002
152#define regk_iop_fifo_in_extra_no 0x00000000
153#define regk_iop_fifo_in_extra_rw_intr_mask_default 0x00000000
154#define regk_iop_fifo_in_extra_yes 0x00000001
155#endif /* __iop_fifo_in_extra_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h
new file mode 100644
index 000000000000..9ec5f4a826df
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h
@@ -0,0 +1,254 @@
1#ifndef __iop_fifo_out_defs_asm_h
2#define __iop_fifo_out_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_fifo_out.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:10:09 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r
11 * id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_cfg, scope iop_fifo_out, type rw */
57#define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0
58#define reg_iop_fifo_out_rw_cfg___free_lim___width 3
59#define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3
60#define reg_iop_fifo_out_rw_cfg___byte_order___width 2
61#define reg_iop_fifo_out_rw_cfg___trig___lsb 5
62#define reg_iop_fifo_out_rw_cfg___trig___width 2
63#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7
64#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1
65#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7
66#define reg_iop_fifo_out_rw_cfg___mode___lsb 8
67#define reg_iop_fifo_out_rw_cfg___mode___width 2
68#define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10
69#define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1
70#define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10
71#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11
72#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1
73#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11
74#define reg_iop_fifo_out_rw_cfg_offset 0
75
76/* Register rw_ctrl, scope iop_fifo_out, type rw */
77#define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0
78#define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1
79#define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0
80#define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1
81#define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1
82#define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1
83#define reg_iop_fifo_out_rw_ctrl_offset 4
84
85/* Register r_stat, scope iop_fifo_out, type r */
86#define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0
87#define reg_iop_fifo_out_r_stat___avail_bytes___width 4
88#define reg_iop_fifo_out_r_stat___last___lsb 4
89#define reg_iop_fifo_out_r_stat___last___width 8
90#define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12
91#define reg_iop_fifo_out_r_stat___dif_in_en___width 1
92#define reg_iop_fifo_out_r_stat___dif_in_en___bit 12
93#define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13
94#define reg_iop_fifo_out_r_stat___dif_out_en___width 1
95#define reg_iop_fifo_out_r_stat___dif_out_en___bit 13
96#define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14
97#define reg_iop_fifo_out_r_stat___zero_data_last___width 1
98#define reg_iop_fifo_out_r_stat___zero_data_last___bit 14
99#define reg_iop_fifo_out_r_stat_offset 8
100
101/* Register rw_wr1byte, scope iop_fifo_out, type rw */
102#define reg_iop_fifo_out_rw_wr1byte___data___lsb 0
103#define reg_iop_fifo_out_rw_wr1byte___data___width 8
104#define reg_iop_fifo_out_rw_wr1byte_offset 12
105
106/* Register rw_wr2byte, scope iop_fifo_out, type rw */
107#define reg_iop_fifo_out_rw_wr2byte___data___lsb 0
108#define reg_iop_fifo_out_rw_wr2byte___data___width 16
109#define reg_iop_fifo_out_rw_wr2byte_offset 16
110
111/* Register rw_wr3byte, scope iop_fifo_out, type rw */
112#define reg_iop_fifo_out_rw_wr3byte___data___lsb 0
113#define reg_iop_fifo_out_rw_wr3byte___data___width 24
114#define reg_iop_fifo_out_rw_wr3byte_offset 20
115
116/* Register rw_wr4byte, scope iop_fifo_out, type rw */
117#define reg_iop_fifo_out_rw_wr4byte___data___lsb 0
118#define reg_iop_fifo_out_rw_wr4byte___data___width 32
119#define reg_iop_fifo_out_rw_wr4byte_offset 24
120
121/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
122#define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0
123#define reg_iop_fifo_out_rw_wr1byte_last___data___width 8
124#define reg_iop_fifo_out_rw_wr1byte_last_offset 28
125
126/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
127#define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0
128#define reg_iop_fifo_out_rw_wr2byte_last___data___width 16
129#define reg_iop_fifo_out_rw_wr2byte_last_offset 32
130
131/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
132#define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0
133#define reg_iop_fifo_out_rw_wr3byte_last___data___width 24
134#define reg_iop_fifo_out_rw_wr3byte_last_offset 36
135
136/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
137#define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0
138#define reg_iop_fifo_out_rw_wr4byte_last___data___width 32
139#define reg_iop_fifo_out_rw_wr4byte_last_offset 40
140
141/* Register rw_set_last, scope iop_fifo_out, type rw */
142#define reg_iop_fifo_out_rw_set_last_offset 44
143
144/* Register rs_rd_data, scope iop_fifo_out, type rs */
145#define reg_iop_fifo_out_rs_rd_data_offset 48
146
147/* Register r_rd_data, scope iop_fifo_out, type r */
148#define reg_iop_fifo_out_r_rd_data_offset 52
149
150/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
151#define reg_iop_fifo_out_rw_strb_dif_out_offset 56
152
153/* Register rw_intr_mask, scope iop_fifo_out, type rw */
154#define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0
155#define reg_iop_fifo_out_rw_intr_mask___urun___width 1
156#define reg_iop_fifo_out_rw_intr_mask___urun___bit 0
157#define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1
158#define reg_iop_fifo_out_rw_intr_mask___last_data___width 1
159#define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1
160#define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2
161#define reg_iop_fifo_out_rw_intr_mask___dav___width 1
162#define reg_iop_fifo_out_rw_intr_mask___dav___bit 2
163#define reg_iop_fifo_out_rw_intr_mask___free___lsb 3
164#define reg_iop_fifo_out_rw_intr_mask___free___width 1
165#define reg_iop_fifo_out_rw_intr_mask___free___bit 3
166#define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4
167#define reg_iop_fifo_out_rw_intr_mask___orun___width 1
168#define reg_iop_fifo_out_rw_intr_mask___orun___bit 4
169#define reg_iop_fifo_out_rw_intr_mask_offset 60
170
171/* Register rw_ack_intr, scope iop_fifo_out, type rw */
172#define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0
173#define reg_iop_fifo_out_rw_ack_intr___urun___width 1
174#define reg_iop_fifo_out_rw_ack_intr___urun___bit 0
175#define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1
176#define reg_iop_fifo_out_rw_ack_intr___last_data___width 1
177#define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1
178#define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2
179#define reg_iop_fifo_out_rw_ack_intr___dav___width 1
180#define reg_iop_fifo_out_rw_ack_intr___dav___bit 2
181#define reg_iop_fifo_out_rw_ack_intr___free___lsb 3
182#define reg_iop_fifo_out_rw_ack_intr___free___width 1
183#define reg_iop_fifo_out_rw_ack_intr___free___bit 3
184#define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4
185#define reg_iop_fifo_out_rw_ack_intr___orun___width 1
186#define reg_iop_fifo_out_rw_ack_intr___orun___bit 4
187#define reg_iop_fifo_out_rw_ack_intr_offset 64
188
189/* Register r_intr, scope iop_fifo_out, type r */
190#define reg_iop_fifo_out_r_intr___urun___lsb 0
191#define reg_iop_fifo_out_r_intr___urun___width 1
192#define reg_iop_fifo_out_r_intr___urun___bit 0
193#define reg_iop_fifo_out_r_intr___last_data___lsb 1
194#define reg_iop_fifo_out_r_intr___last_data___width 1
195#define reg_iop_fifo_out_r_intr___last_data___bit 1
196#define reg_iop_fifo_out_r_intr___dav___lsb 2
197#define reg_iop_fifo_out_r_intr___dav___width 1
198#define reg_iop_fifo_out_r_intr___dav___bit 2
199#define reg_iop_fifo_out_r_intr___free___lsb 3
200#define reg_iop_fifo_out_r_intr___free___width 1
201#define reg_iop_fifo_out_r_intr___free___bit 3
202#define reg_iop_fifo_out_r_intr___orun___lsb 4
203#define reg_iop_fifo_out_r_intr___orun___width 1
204#define reg_iop_fifo_out_r_intr___orun___bit 4
205#define reg_iop_fifo_out_r_intr_offset 68
206
207/* Register r_masked_intr, scope iop_fifo_out, type r */
208#define reg_iop_fifo_out_r_masked_intr___urun___lsb 0
209#define reg_iop_fifo_out_r_masked_intr___urun___width 1
210#define reg_iop_fifo_out_r_masked_intr___urun___bit 0
211#define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1
212#define reg_iop_fifo_out_r_masked_intr___last_data___width 1
213#define reg_iop_fifo_out_r_masked_intr___last_data___bit 1
214#define reg_iop_fifo_out_r_masked_intr___dav___lsb 2
215#define reg_iop_fifo_out_r_masked_intr___dav___width 1
216#define reg_iop_fifo_out_r_masked_intr___dav___bit 2
217#define reg_iop_fifo_out_r_masked_intr___free___lsb 3
218#define reg_iop_fifo_out_r_masked_intr___free___width 1
219#define reg_iop_fifo_out_r_masked_intr___free___bit 3
220#define reg_iop_fifo_out_r_masked_intr___orun___lsb 4
221#define reg_iop_fifo_out_r_masked_intr___orun___width 1
222#define reg_iop_fifo_out_r_masked_intr___orun___bit 4
223#define reg_iop_fifo_out_r_masked_intr_offset 72
224
225
226/* Constants */
227#define regk_iop_fifo_out_hi 0x00000000
228#define regk_iop_fifo_out_neg 0x00000002
229#define regk_iop_fifo_out_no 0x00000000
230#define regk_iop_fifo_out_order16 0x00000001
231#define regk_iop_fifo_out_order24 0x00000002
232#define regk_iop_fifo_out_order32 0x00000003
233#define regk_iop_fifo_out_order8 0x00000000
234#define regk_iop_fifo_out_pos 0x00000001
235#define regk_iop_fifo_out_pos_neg 0x00000003
236#define regk_iop_fifo_out_rw_cfg_default 0x00000024
237#define regk_iop_fifo_out_rw_ctrl_default 0x00000000
238#define regk_iop_fifo_out_rw_intr_mask_default 0x00000000
239#define regk_iop_fifo_out_rw_set_last_default 0x00000000
240#define regk_iop_fifo_out_rw_strb_dif_out_default 0x00000000
241#define regk_iop_fifo_out_rw_wr1byte_default 0x00000000
242#define regk_iop_fifo_out_rw_wr1byte_last_default 0x00000000
243#define regk_iop_fifo_out_rw_wr2byte_default 0x00000000
244#define regk_iop_fifo_out_rw_wr2byte_last_default 0x00000000
245#define regk_iop_fifo_out_rw_wr3byte_default 0x00000000
246#define regk_iop_fifo_out_rw_wr3byte_last_default 0x00000000
247#define regk_iop_fifo_out_rw_wr4byte_default 0x00000000
248#define regk_iop_fifo_out_rw_wr4byte_last_default 0x00000000
249#define regk_iop_fifo_out_size16 0x00000002
250#define regk_iop_fifo_out_size24 0x00000001
251#define regk_iop_fifo_out_size32 0x00000000
252#define regk_iop_fifo_out_size8 0x00000003
253#define regk_iop_fifo_out_yes 0x00000001
254#endif /* __iop_fifo_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h
new file mode 100644
index 000000000000..0f84a50cf77c
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h
@@ -0,0 +1,158 @@
1#ifndef __iop_fifo_out_extra_defs_asm_h
2#define __iop_fifo_out_extra_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:10:10 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
11 * id: $Id: iop_fifo_out_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
57#define reg_iop_fifo_out_extra_rs_rd_data_offset 0
58
59/* Register r_rd_data, scope iop_fifo_out_extra, type r */
60#define reg_iop_fifo_out_extra_r_rd_data_offset 4
61
62/* Register r_stat, scope iop_fifo_out_extra, type r */
63#define reg_iop_fifo_out_extra_r_stat___avail_bytes___lsb 0
64#define reg_iop_fifo_out_extra_r_stat___avail_bytes___width 4
65#define reg_iop_fifo_out_extra_r_stat___last___lsb 4
66#define reg_iop_fifo_out_extra_r_stat___last___width 8
67#define reg_iop_fifo_out_extra_r_stat___dif_in_en___lsb 12
68#define reg_iop_fifo_out_extra_r_stat___dif_in_en___width 1
69#define reg_iop_fifo_out_extra_r_stat___dif_in_en___bit 12
70#define reg_iop_fifo_out_extra_r_stat___dif_out_en___lsb 13
71#define reg_iop_fifo_out_extra_r_stat___dif_out_en___width 1
72#define reg_iop_fifo_out_extra_r_stat___dif_out_en___bit 13
73#define reg_iop_fifo_out_extra_r_stat___zero_data_last___lsb 14
74#define reg_iop_fifo_out_extra_r_stat___zero_data_last___width 1
75#define reg_iop_fifo_out_extra_r_stat___zero_data_last___bit 14
76#define reg_iop_fifo_out_extra_r_stat_offset 8
77
78/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
79#define reg_iop_fifo_out_extra_rw_strb_dif_out_offset 12
80
81/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
82#define reg_iop_fifo_out_extra_rw_intr_mask___urun___lsb 0
83#define reg_iop_fifo_out_extra_rw_intr_mask___urun___width 1
84#define reg_iop_fifo_out_extra_rw_intr_mask___urun___bit 0
85#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___lsb 1
86#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___width 1
87#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___bit 1
88#define reg_iop_fifo_out_extra_rw_intr_mask___dav___lsb 2
89#define reg_iop_fifo_out_extra_rw_intr_mask___dav___width 1
90#define reg_iop_fifo_out_extra_rw_intr_mask___dav___bit 2
91#define reg_iop_fifo_out_extra_rw_intr_mask___free___lsb 3
92#define reg_iop_fifo_out_extra_rw_intr_mask___free___width 1
93#define reg_iop_fifo_out_extra_rw_intr_mask___free___bit 3
94#define reg_iop_fifo_out_extra_rw_intr_mask___orun___lsb 4
95#define reg_iop_fifo_out_extra_rw_intr_mask___orun___width 1
96#define reg_iop_fifo_out_extra_rw_intr_mask___orun___bit 4
97#define reg_iop_fifo_out_extra_rw_intr_mask_offset 16
98
99/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
100#define reg_iop_fifo_out_extra_rw_ack_intr___urun___lsb 0
101#define reg_iop_fifo_out_extra_rw_ack_intr___urun___width 1
102#define reg_iop_fifo_out_extra_rw_ack_intr___urun___bit 0
103#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___lsb 1
104#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___width 1
105#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___bit 1
106#define reg_iop_fifo_out_extra_rw_ack_intr___dav___lsb 2
107#define reg_iop_fifo_out_extra_rw_ack_intr___dav___width 1
108#define reg_iop_fifo_out_extra_rw_ack_intr___dav___bit 2
109#define reg_iop_fifo_out_extra_rw_ack_intr___free___lsb 3
110#define reg_iop_fifo_out_extra_rw_ack_intr___free___width 1
111#define reg_iop_fifo_out_extra_rw_ack_intr___free___bit 3
112#define reg_iop_fifo_out_extra_rw_ack_intr___orun___lsb 4
113#define reg_iop_fifo_out_extra_rw_ack_intr___orun___width 1
114#define reg_iop_fifo_out_extra_rw_ack_intr___orun___bit 4
115#define reg_iop_fifo_out_extra_rw_ack_intr_offset 20
116
117/* Register r_intr, scope iop_fifo_out_extra, type r */
118#define reg_iop_fifo_out_extra_r_intr___urun___lsb 0
119#define reg_iop_fifo_out_extra_r_intr___urun___width 1
120#define reg_iop_fifo_out_extra_r_intr___urun___bit 0
121#define reg_iop_fifo_out_extra_r_intr___last_data___lsb 1
122#define reg_iop_fifo_out_extra_r_intr___last_data___width 1
123#define reg_iop_fifo_out_extra_r_intr___last_data___bit 1
124#define reg_iop_fifo_out_extra_r_intr___dav___lsb 2
125#define reg_iop_fifo_out_extra_r_intr___dav___width 1
126#define reg_iop_fifo_out_extra_r_intr___dav___bit 2
127#define reg_iop_fifo_out_extra_r_intr___free___lsb 3
128#define reg_iop_fifo_out_extra_r_intr___free___width 1
129#define reg_iop_fifo_out_extra_r_intr___free___bit 3
130#define reg_iop_fifo_out_extra_r_intr___orun___lsb 4
131#define reg_iop_fifo_out_extra_r_intr___orun___width 1
132#define reg_iop_fifo_out_extra_r_intr___orun___bit 4
133#define reg_iop_fifo_out_extra_r_intr_offset 24
134
135/* Register r_masked_intr, scope iop_fifo_out_extra, type r */
136#define reg_iop_fifo_out_extra_r_masked_intr___urun___lsb 0
137#define reg_iop_fifo_out_extra_r_masked_intr___urun___width 1
138#define reg_iop_fifo_out_extra_r_masked_intr___urun___bit 0
139#define reg_iop_fifo_out_extra_r_masked_intr___last_data___lsb 1
140#define reg_iop_fifo_out_extra_r_masked_intr___last_data___width 1
141#define reg_iop_fifo_out_extra_r_masked_intr___last_data___bit 1
142#define reg_iop_fifo_out_extra_r_masked_intr___dav___lsb 2
143#define reg_iop_fifo_out_extra_r_masked_intr___dav___width 1
144#define reg_iop_fifo_out_extra_r_masked_intr___dav___bit 2
145#define reg_iop_fifo_out_extra_r_masked_intr___free___lsb 3
146#define reg_iop_fifo_out_extra_r_masked_intr___free___width 1
147#define reg_iop_fifo_out_extra_r_masked_intr___free___bit 3
148#define reg_iop_fifo_out_extra_r_masked_intr___orun___lsb 4
149#define reg_iop_fifo_out_extra_r_masked_intr___orun___width 1
150#define reg_iop_fifo_out_extra_r_masked_intr___orun___bit 4
151#define reg_iop_fifo_out_extra_r_masked_intr_offset 28
152
153
154/* Constants */
155#define regk_iop_fifo_out_extra_no 0x00000000
156#define regk_iop_fifo_out_extra_rw_intr_mask_default 0x00000000
157#define regk_iop_fifo_out_extra_yes 0x00000001
158#endif /* __iop_fifo_out_extra_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h
new file mode 100644
index 000000000000..80490c82cc29
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h
@@ -0,0 +1,177 @@
1#ifndef __iop_mpu_defs_asm_h
2#define __iop_mpu_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_mpu.r
7 * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp
8 * last modfied: Mon Apr 11 16:08:45 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r
11 * id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56#define STRIDE_iop_mpu_rw_r 4
57/* Register rw_r, scope iop_mpu, type rw */
58#define reg_iop_mpu_rw_r_offset 0
59
60/* Register rw_ctrl, scope iop_mpu, type rw */
61#define reg_iop_mpu_rw_ctrl___en___lsb 0
62#define reg_iop_mpu_rw_ctrl___en___width 1
63#define reg_iop_mpu_rw_ctrl___en___bit 0
64#define reg_iop_mpu_rw_ctrl_offset 128
65
66/* Register r_pc, scope iop_mpu, type r */
67#define reg_iop_mpu_r_pc___addr___lsb 0
68#define reg_iop_mpu_r_pc___addr___width 12
69#define reg_iop_mpu_r_pc_offset 132
70
71/* Register r_stat, scope iop_mpu, type r */
72#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0
73#define reg_iop_mpu_r_stat___instr_reg_busy___width 1
74#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0
75#define reg_iop_mpu_r_stat___intr_busy___lsb 1
76#define reg_iop_mpu_r_stat___intr_busy___width 1
77#define reg_iop_mpu_r_stat___intr_busy___bit 1
78#define reg_iop_mpu_r_stat___intr_vect___lsb 2
79#define reg_iop_mpu_r_stat___intr_vect___width 16
80#define reg_iop_mpu_r_stat_offset 136
81
82/* Register rw_instr, scope iop_mpu, type rw */
83#define reg_iop_mpu_rw_instr_offset 140
84
85/* Register rw_immediate, scope iop_mpu, type rw */
86#define reg_iop_mpu_rw_immediate_offset 144
87
88/* Register r_trace, scope iop_mpu, type r */
89#define reg_iop_mpu_r_trace___intr_vect___lsb 0
90#define reg_iop_mpu_r_trace___intr_vect___width 16
91#define reg_iop_mpu_r_trace___pc___lsb 16
92#define reg_iop_mpu_r_trace___pc___width 12
93#define reg_iop_mpu_r_trace___en___lsb 28
94#define reg_iop_mpu_r_trace___en___width 1
95#define reg_iop_mpu_r_trace___en___bit 28
96#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29
97#define reg_iop_mpu_r_trace___instr_reg_busy___width 1
98#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29
99#define reg_iop_mpu_r_trace___intr_busy___lsb 30
100#define reg_iop_mpu_r_trace___intr_busy___width 1
101#define reg_iop_mpu_r_trace___intr_busy___bit 30
102#define reg_iop_mpu_r_trace_offset 148
103
104/* Register r_wr_stat, scope iop_mpu, type r */
105#define reg_iop_mpu_r_wr_stat___r0___lsb 0
106#define reg_iop_mpu_r_wr_stat___r0___width 1
107#define reg_iop_mpu_r_wr_stat___r0___bit 0
108#define reg_iop_mpu_r_wr_stat___r1___lsb 1
109#define reg_iop_mpu_r_wr_stat___r1___width 1
110#define reg_iop_mpu_r_wr_stat___r1___bit 1
111#define reg_iop_mpu_r_wr_stat___r2___lsb 2
112#define reg_iop_mpu_r_wr_stat___r2___width 1
113#define reg_iop_mpu_r_wr_stat___r2___bit 2
114#define reg_iop_mpu_r_wr_stat___r3___lsb 3
115#define reg_iop_mpu_r_wr_stat___r3___width 1
116#define reg_iop_mpu_r_wr_stat___r3___bit 3
117#define reg_iop_mpu_r_wr_stat___r4___lsb 4
118#define reg_iop_mpu_r_wr_stat___r4___width 1
119#define reg_iop_mpu_r_wr_stat___r4___bit 4
120#define reg_iop_mpu_r_wr_stat___r5___lsb 5
121#define reg_iop_mpu_r_wr_stat___r5___width 1
122#define reg_iop_mpu_r_wr_stat___r5___bit 5
123#define reg_iop_mpu_r_wr_stat___r6___lsb 6
124#define reg_iop_mpu_r_wr_stat___r6___width 1
125#define reg_iop_mpu_r_wr_stat___r6___bit 6
126#define reg_iop_mpu_r_wr_stat___r7___lsb 7
127#define reg_iop_mpu_r_wr_stat___r7___width 1
128#define reg_iop_mpu_r_wr_stat___r7___bit 7
129#define reg_iop_mpu_r_wr_stat___r8___lsb 8
130#define reg_iop_mpu_r_wr_stat___r8___width 1
131#define reg_iop_mpu_r_wr_stat___r8___bit 8
132#define reg_iop_mpu_r_wr_stat___r9___lsb 9
133#define reg_iop_mpu_r_wr_stat___r9___width 1
134#define reg_iop_mpu_r_wr_stat___r9___bit 9
135#define reg_iop_mpu_r_wr_stat___r10___lsb 10
136#define reg_iop_mpu_r_wr_stat___r10___width 1
137#define reg_iop_mpu_r_wr_stat___r10___bit 10
138#define reg_iop_mpu_r_wr_stat___r11___lsb 11
139#define reg_iop_mpu_r_wr_stat___r11___width 1
140#define reg_iop_mpu_r_wr_stat___r11___bit 11
141#define reg_iop_mpu_r_wr_stat___r12___lsb 12
142#define reg_iop_mpu_r_wr_stat___r12___width 1
143#define reg_iop_mpu_r_wr_stat___r12___bit 12
144#define reg_iop_mpu_r_wr_stat___r13___lsb 13
145#define reg_iop_mpu_r_wr_stat___r13___width 1
146#define reg_iop_mpu_r_wr_stat___r13___bit 13
147#define reg_iop_mpu_r_wr_stat___r14___lsb 14
148#define reg_iop_mpu_r_wr_stat___r14___width 1
149#define reg_iop_mpu_r_wr_stat___r14___bit 14
150#define reg_iop_mpu_r_wr_stat___r15___lsb 15
151#define reg_iop_mpu_r_wr_stat___r15___width 1
152#define reg_iop_mpu_r_wr_stat___r15___bit 15
153#define reg_iop_mpu_r_wr_stat_offset 152
154
155#define STRIDE_iop_mpu_rw_thread 4
156/* Register rw_thread, scope iop_mpu, type rw */
157#define reg_iop_mpu_rw_thread___addr___lsb 0
158#define reg_iop_mpu_rw_thread___addr___width 12
159#define reg_iop_mpu_rw_thread_offset 156
160
161#define STRIDE_iop_mpu_rw_intr 4
162/* Register rw_intr, scope iop_mpu, type rw */
163#define reg_iop_mpu_rw_intr___addr___lsb 0
164#define reg_iop_mpu_rw_intr___addr___width 12
165#define reg_iop_mpu_rw_intr_offset 196
166
167
168/* Constants */
169#define regk_iop_mpu_no 0x00000000
170#define regk_iop_mpu_r_pc_default 0x00000000
171#define regk_iop_mpu_rw_ctrl_default 0x00000000
172#define regk_iop_mpu_rw_intr_size 0x00000010
173#define regk_iop_mpu_rw_r_size 0x00000010
174#define regk_iop_mpu_rw_thread_default 0x00000000
175#define regk_iop_mpu_rw_thread_size 0x00000004
176#define regk_iop_mpu_yes 0x00000001
177#endif /* __iop_mpu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h
new file mode 100644
index 000000000000..a20b8857b4d0
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h
@@ -0,0 +1,44 @@
1/* Autogenerated Changes here will be lost!
2 * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg
3 */
4#define iop_version 0
5#define iop_fifo_in0_extra 64
6#define iop_fifo_in1_extra 128
7#define iop_fifo_out0_extra 192
8#define iop_fifo_out1_extra 256
9#define iop_trigger_grp0 320
10#define iop_trigger_grp1 384
11#define iop_trigger_grp2 448
12#define iop_trigger_grp3 512
13#define iop_trigger_grp4 576
14#define iop_trigger_grp5 640
15#define iop_trigger_grp6 704
16#define iop_trigger_grp7 768
17#define iop_crc_par0 896
18#define iop_crc_par1 1024
19#define iop_dmc_in0 1152
20#define iop_dmc_in1 1280
21#define iop_dmc_out0 1408
22#define iop_dmc_out1 1536
23#define iop_fifo_in0 1664
24#define iop_fifo_in1 1792
25#define iop_fifo_out0 1920
26#define iop_fifo_out1 2048
27#define iop_scrc_in0 2176
28#define iop_scrc_in1 2304
29#define iop_scrc_out0 2432
30#define iop_scrc_out1 2560
31#define iop_timer_grp0 2688
32#define iop_timer_grp1 2816
33#define iop_timer_grp2 2944
34#define iop_timer_grp3 3072
35#define iop_sap_in 3328
36#define iop_sap_out 3584
37#define iop_spu0 3840
38#define iop_spu1 4096
39#define iop_sw_cfg 4352
40#define iop_sw_cpu 4608
41#define iop_sw_mpu 4864
42#define iop_sw_spu0 5120
43#define iop_sw_spu1 5376
44#define iop_mpu 5632
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h
new file mode 100644
index 000000000000..a4a10ff300b3
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h
@@ -0,0 +1,182 @@
1#ifndef __iop_sap_in_defs_asm_h
2#define __iop_sap_in_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_sap_in.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:08:45 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r
11 * id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_bus0_sync, scope iop_sap_in, type rw */
57#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0
58#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2
59#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2
60#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3
61#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5
62#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2
63#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7
64#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1
65#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7
66#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8
67#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2
68#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10
69#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3
70#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13
71#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2
72#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15
73#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1
74#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15
75#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16
76#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2
77#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18
78#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3
79#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21
80#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2
81#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23
82#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1
83#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23
84#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24
85#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2
86#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26
87#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3
88#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29
89#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2
90#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31
91#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1
92#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31
93#define reg_iop_sap_in_rw_bus0_sync_offset 0
94
95/* Register rw_bus1_sync, scope iop_sap_in, type rw */
96#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0
97#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2
98#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2
99#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3
100#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5
101#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2
102#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7
103#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1
104#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7
105#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8
106#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2
107#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10
108#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3
109#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13
110#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2
111#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15
112#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1
113#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15
114#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16
115#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2
116#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18
117#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3
118#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21
119#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2
120#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23
121#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1
122#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23
123#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24
124#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2
125#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26
126#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3
127#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29
128#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2
129#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31
130#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1
131#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31
132#define reg_iop_sap_in_rw_bus1_sync_offset 4
133
134#define STRIDE_iop_sap_in_rw_gio 4
135/* Register rw_gio, scope iop_sap_in, type rw */
136#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
137#define reg_iop_sap_in_rw_gio___sync_sel___width 2
138#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
139#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
140#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
141#define reg_iop_sap_in_rw_gio___sync_edge___width 2
142#define reg_iop_sap_in_rw_gio___delay___lsb 7
143#define reg_iop_sap_in_rw_gio___delay___width 1
144#define reg_iop_sap_in_rw_gio___delay___bit 7
145#define reg_iop_sap_in_rw_gio___logic___lsb 8
146#define reg_iop_sap_in_rw_gio___logic___width 2
147#define reg_iop_sap_in_rw_gio_offset 8
148
149
150/* Constants */
151#define regk_iop_sap_in_and 0x00000002
152#define regk_iop_sap_in_ext_clk200 0x00000003
153#define regk_iop_sap_in_gio1 0x00000000
154#define regk_iop_sap_in_gio13 0x00000005
155#define regk_iop_sap_in_gio18 0x00000003
156#define regk_iop_sap_in_gio19 0x00000004
157#define regk_iop_sap_in_gio21 0x00000006
158#define regk_iop_sap_in_gio23 0x00000005
159#define regk_iop_sap_in_gio29 0x00000007
160#define regk_iop_sap_in_gio5 0x00000004
161#define regk_iop_sap_in_gio6 0x00000001
162#define regk_iop_sap_in_gio7 0x00000002
163#define regk_iop_sap_in_inv 0x00000001
164#define regk_iop_sap_in_neg 0x00000002
165#define regk_iop_sap_in_no 0x00000000
166#define regk_iop_sap_in_no_del_ext_clk200 0x00000001
167#define regk_iop_sap_in_none 0x00000000
168#define regk_iop_sap_in_or 0x00000003
169#define regk_iop_sap_in_pos 0x00000001
170#define regk_iop_sap_in_pos_neg 0x00000003
171#define regk_iop_sap_in_rw_bus0_sync_default 0x02020202
172#define regk_iop_sap_in_rw_bus1_sync_default 0x02020202
173#define regk_iop_sap_in_rw_gio_default 0x00000002
174#define regk_iop_sap_in_rw_gio_size 0x00000020
175#define regk_iop_sap_in_timer_grp0_tmr3 0x00000006
176#define regk_iop_sap_in_timer_grp1_tmr3 0x00000004
177#define regk_iop_sap_in_timer_grp2_tmr3 0x00000005
178#define regk_iop_sap_in_timer_grp3_tmr3 0x00000007
179#define regk_iop_sap_in_tmr_clk200 0x00000000
180#define regk_iop_sap_in_two_clk200 0x00000002
181#define regk_iop_sap_in_yes 0x00000001
182#endif /* __iop_sap_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h
new file mode 100644
index 000000000000..0ec727f92a25
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h
@@ -0,0 +1,346 @@
1#ifndef __iop_sap_out_defs_asm_h
2#define __iop_sap_out_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_sap_out.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:08:46 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r
11 * id: $Id: iop_sap_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_gen_gated, scope iop_sap_out, type rw */
57#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0
58#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2
59#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2
60#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2
61#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4
62#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3
63#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7
64#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2
65#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9
66#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2
67#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11
68#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3
69#define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14
70#define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2
71#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16
72#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2
73#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18
74#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3
75#define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21
76#define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2
77#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23
78#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2
79#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25
80#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3
81#define reg_iop_sap_out_rw_gen_gated_offset 0
82
83/* Register rw_bus0, scope iop_sap_out, type rw */
84#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0
85#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3
86#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3
87#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2
88#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5
89#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1
90#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5
91#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6
92#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3
93#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9
94#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2
95#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11
96#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1
97#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11
98#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12
99#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3
100#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15
101#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2
102#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17
103#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1
104#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17
105#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18
106#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3
107#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21
108#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2
109#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23
110#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1
111#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23
112#define reg_iop_sap_out_rw_bus0_offset 4
113
114/* Register rw_bus1, scope iop_sap_out, type rw */
115#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0
116#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3
117#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3
118#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2
119#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5
120#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1
121#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5
122#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6
123#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3
124#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9
125#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2
126#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11
127#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1
128#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11
129#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12
130#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3
131#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15
132#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2
133#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17
134#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1
135#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17
136#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18
137#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3
138#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21
139#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2
140#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23
141#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1
142#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23
143#define reg_iop_sap_out_rw_bus1_offset 8
144
145/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */
146#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0
147#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3
148#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3
149#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3
150#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6
151#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2
152#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8
153#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1
154#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8
155#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9
156#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2
157#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11
158#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3
159#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14
160#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3
161#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17
162#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2
163#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19
164#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1
165#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19
166#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20
167#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2
168#define reg_iop_sap_out_rw_bus0_lo_oe_offset 12
169
170/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */
171#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0
172#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3
173#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3
174#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3
175#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6
176#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2
177#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8
178#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1
179#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8
180#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9
181#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2
182#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11
183#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3
184#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14
185#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3
186#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17
187#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2
188#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19
189#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1
190#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19
191#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20
192#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2
193#define reg_iop_sap_out_rw_bus0_hi_oe_offset 16
194
195/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */
196#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0
197#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3
198#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3
199#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3
200#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6
201#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2
202#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8
203#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1
204#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8
205#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9
206#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2
207#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11
208#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3
209#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14
210#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3
211#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17
212#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2
213#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19
214#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1
215#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19
216#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20
217#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2
218#define reg_iop_sap_out_rw_bus1_lo_oe_offset 20
219
220/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */
221#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0
222#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3
223#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3
224#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3
225#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6
226#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2
227#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8
228#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1
229#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8
230#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9
231#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2
232#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11
233#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3
234#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14
235#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3
236#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17
237#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2
238#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19
239#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1
240#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19
241#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20
242#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2
243#define reg_iop_sap_out_rw_bus1_hi_oe_offset 24
244
245#define STRIDE_iop_sap_out_rw_gio 4
246/* Register rw_gio, scope iop_sap_out, type rw */
247#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0
248#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3
249#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3
250#define reg_iop_sap_out_rw_gio___out_clk_ext___width 4
251#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7
252#define reg_iop_sap_out_rw_gio___out_gated_clk___width 2
253#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9
254#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1
255#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9
256#define reg_iop_sap_out_rw_gio___out_logic___lsb 10
257#define reg_iop_sap_out_rw_gio___out_logic___width 1
258#define reg_iop_sap_out_rw_gio___out_logic___bit 10
259#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11
260#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3
261#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14
262#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3
263#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17
264#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2
265#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19
266#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1
267#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19
268#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20
269#define reg_iop_sap_out_rw_gio___oe_logic___width 2
270#define reg_iop_sap_out_rw_gio_offset 28
271
272
273/* Constants */
274#define regk_iop_sap_out_and 0x00000002
275#define regk_iop_sap_out_clk0 0x00000000
276#define regk_iop_sap_out_clk1 0x00000001
277#define regk_iop_sap_out_clk12 0x00000002
278#define regk_iop_sap_out_clk2 0x00000002
279#define regk_iop_sap_out_clk200 0x00000001
280#define regk_iop_sap_out_clk3 0x00000003
281#define regk_iop_sap_out_ext 0x00000003
282#define regk_iop_sap_out_gated 0x00000004
283#define regk_iop_sap_out_gio1 0x00000000
284#define regk_iop_sap_out_gio13 0x00000002
285#define regk_iop_sap_out_gio13_clk 0x0000000c
286#define regk_iop_sap_out_gio15 0x00000001
287#define regk_iop_sap_out_gio18 0x00000003
288#define regk_iop_sap_out_gio18_clk 0x0000000d
289#define regk_iop_sap_out_gio1_clk 0x00000008
290#define regk_iop_sap_out_gio21_clk 0x0000000e
291#define regk_iop_sap_out_gio23 0x00000002
292#define regk_iop_sap_out_gio29_clk 0x0000000f
293#define regk_iop_sap_out_gio31 0x00000003
294#define regk_iop_sap_out_gio5 0x00000001
295#define regk_iop_sap_out_gio5_clk 0x00000009
296#define regk_iop_sap_out_gio6_clk 0x0000000a
297#define regk_iop_sap_out_gio7 0x00000000
298#define regk_iop_sap_out_gio7_clk 0x0000000b
299#define regk_iop_sap_out_gio_in13 0x00000001
300#define regk_iop_sap_out_gio_in21 0x00000002
301#define regk_iop_sap_out_gio_in29 0x00000003
302#define regk_iop_sap_out_gio_in5 0x00000000
303#define regk_iop_sap_out_inv 0x00000001
304#define regk_iop_sap_out_nand 0x00000003
305#define regk_iop_sap_out_no 0x00000000
306#define regk_iop_sap_out_none 0x00000000
307#define regk_iop_sap_out_rw_bus0_default 0x00000000
308#define regk_iop_sap_out_rw_bus0_hi_oe_default 0x00000000
309#define regk_iop_sap_out_rw_bus0_lo_oe_default 0x00000000
310#define regk_iop_sap_out_rw_bus1_default 0x00000000
311#define regk_iop_sap_out_rw_bus1_hi_oe_default 0x00000000
312#define regk_iop_sap_out_rw_bus1_lo_oe_default 0x00000000
313#define regk_iop_sap_out_rw_gen_gated_default 0x00000000
314#define regk_iop_sap_out_rw_gio_default 0x00000000
315#define regk_iop_sap_out_rw_gio_size 0x00000020
316#define regk_iop_sap_out_spu0_gio0 0x00000002
317#define regk_iop_sap_out_spu0_gio1 0x00000003
318#define regk_iop_sap_out_spu0_gio12 0x00000004
319#define regk_iop_sap_out_spu0_gio13 0x00000004
320#define regk_iop_sap_out_spu0_gio14 0x00000004
321#define regk_iop_sap_out_spu0_gio15 0x00000004
322#define regk_iop_sap_out_spu0_gio2 0x00000002
323#define regk_iop_sap_out_spu0_gio3 0x00000003
324#define regk_iop_sap_out_spu0_gio4 0x00000002
325#define regk_iop_sap_out_spu0_gio5 0x00000003
326#define regk_iop_sap_out_spu0_gio6 0x00000002
327#define regk_iop_sap_out_spu0_gio7 0x00000003
328#define regk_iop_sap_out_spu1_gio0 0x00000005
329#define regk_iop_sap_out_spu1_gio1 0x00000006
330#define regk_iop_sap_out_spu1_gio12 0x00000007
331#define regk_iop_sap_out_spu1_gio13 0x00000007
332#define regk_iop_sap_out_spu1_gio14 0x00000007
333#define regk_iop_sap_out_spu1_gio15 0x00000007
334#define regk_iop_sap_out_spu1_gio2 0x00000005
335#define regk_iop_sap_out_spu1_gio3 0x00000006
336#define regk_iop_sap_out_spu1_gio4 0x00000005
337#define regk_iop_sap_out_spu1_gio5 0x00000006
338#define regk_iop_sap_out_spu1_gio6 0x00000005
339#define regk_iop_sap_out_spu1_gio7 0x00000006
340#define regk_iop_sap_out_timer_grp0_tmr2 0x00000004
341#define regk_iop_sap_out_timer_grp1_tmr2 0x00000005
342#define regk_iop_sap_out_timer_grp2_tmr2 0x00000006
343#define regk_iop_sap_out_timer_grp3_tmr2 0x00000007
344#define regk_iop_sap_out_tmr 0x00000005
345#define regk_iop_sap_out_yes 0x00000001
346#endif /* __iop_sap_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h
new file mode 100644
index 000000000000..2cf5721597fc
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h
@@ -0,0 +1,111 @@
1#ifndef __iop_scrc_in_defs_asm_h
2#define __iop_scrc_in_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_scrc_in.r
7 * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp
8 * last modfied: Mon Apr 11 16:08:46 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r
11 * id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_cfg, scope iop_scrc_in, type rw */
57#define reg_iop_scrc_in_rw_cfg___trig___lsb 0
58#define reg_iop_scrc_in_rw_cfg___trig___width 2
59#define reg_iop_scrc_in_rw_cfg_offset 0
60
61/* Register rw_ctrl, scope iop_scrc_in, type rw */
62#define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0
63#define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1
64#define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0
65#define reg_iop_scrc_in_rw_ctrl_offset 4
66
67/* Register r_stat, scope iop_scrc_in, type r */
68#define reg_iop_scrc_in_r_stat___err___lsb 0
69#define reg_iop_scrc_in_r_stat___err___width 1
70#define reg_iop_scrc_in_r_stat___err___bit 0
71#define reg_iop_scrc_in_r_stat_offset 8
72
73/* Register rw_init_crc, scope iop_scrc_in, type rw */
74#define reg_iop_scrc_in_rw_init_crc_offset 12
75
76/* Register rs_computed_crc, scope iop_scrc_in, type rs */
77#define reg_iop_scrc_in_rs_computed_crc_offset 16
78
79/* Register r_computed_crc, scope iop_scrc_in, type r */
80#define reg_iop_scrc_in_r_computed_crc_offset 20
81
82/* Register rw_crc, scope iop_scrc_in, type rw */
83#define reg_iop_scrc_in_rw_crc_offset 24
84
85/* Register rw_correct_crc, scope iop_scrc_in, type rw */
86#define reg_iop_scrc_in_rw_correct_crc_offset 28
87
88/* Register rw_wr1bit, scope iop_scrc_in, type rw */
89#define reg_iop_scrc_in_rw_wr1bit___data___lsb 0
90#define reg_iop_scrc_in_rw_wr1bit___data___width 2
91#define reg_iop_scrc_in_rw_wr1bit___last___lsb 2
92#define reg_iop_scrc_in_rw_wr1bit___last___width 2
93#define reg_iop_scrc_in_rw_wr1bit_offset 32
94
95
96/* Constants */
97#define regk_iop_scrc_in_dif_in 0x00000002
98#define regk_iop_scrc_in_hi 0x00000000
99#define regk_iop_scrc_in_neg 0x00000002
100#define regk_iop_scrc_in_no 0x00000000
101#define regk_iop_scrc_in_pos 0x00000001
102#define regk_iop_scrc_in_pos_neg 0x00000003
103#define regk_iop_scrc_in_r_computed_crc_default 0x00000000
104#define regk_iop_scrc_in_rs_computed_crc_default 0x00000000
105#define regk_iop_scrc_in_rw_cfg_default 0x00000000
106#define regk_iop_scrc_in_rw_ctrl_default 0x00000000
107#define regk_iop_scrc_in_rw_init_crc_default 0x00000000
108#define regk_iop_scrc_in_set0 0x00000000
109#define regk_iop_scrc_in_set1 0x00000001
110#define regk_iop_scrc_in_yes 0x00000001
111#endif /* __iop_scrc_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h
new file mode 100644
index 000000000000..640a25725f20
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h
@@ -0,0 +1,105 @@
1#ifndef __iop_scrc_out_defs_asm_h
2#define __iop_scrc_out_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_scrc_out.r
7 * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp
8 * last modfied: Mon Apr 11 16:08:46 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r
11 * id: $Id: iop_scrc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_cfg, scope iop_scrc_out, type rw */
57#define reg_iop_scrc_out_rw_cfg___trig___lsb 0
58#define reg_iop_scrc_out_rw_cfg___trig___width 2
59#define reg_iop_scrc_out_rw_cfg___inv_crc___lsb 2
60#define reg_iop_scrc_out_rw_cfg___inv_crc___width 1
61#define reg_iop_scrc_out_rw_cfg___inv_crc___bit 2
62#define reg_iop_scrc_out_rw_cfg_offset 0
63
64/* Register rw_ctrl, scope iop_scrc_out, type rw */
65#define reg_iop_scrc_out_rw_ctrl___strb_src___lsb 0
66#define reg_iop_scrc_out_rw_ctrl___strb_src___width 1
67#define reg_iop_scrc_out_rw_ctrl___strb_src___bit 0
68#define reg_iop_scrc_out_rw_ctrl___out_src___lsb 1
69#define reg_iop_scrc_out_rw_ctrl___out_src___width 1
70#define reg_iop_scrc_out_rw_ctrl___out_src___bit 1
71#define reg_iop_scrc_out_rw_ctrl_offset 4
72
73/* Register rw_init_crc, scope iop_scrc_out, type rw */
74#define reg_iop_scrc_out_rw_init_crc_offset 8
75
76/* Register rw_crc, scope iop_scrc_out, type rw */
77#define reg_iop_scrc_out_rw_crc_offset 12
78
79/* Register rw_data, scope iop_scrc_out, type rw */
80#define reg_iop_scrc_out_rw_data___val___lsb 0
81#define reg_iop_scrc_out_rw_data___val___width 1
82#define reg_iop_scrc_out_rw_data___val___bit 0
83#define reg_iop_scrc_out_rw_data_offset 16
84
85/* Register r_computed_crc, scope iop_scrc_out, type r */
86#define reg_iop_scrc_out_r_computed_crc_offset 20
87
88
89/* Constants */
90#define regk_iop_scrc_out_crc 0x00000001
91#define regk_iop_scrc_out_data 0x00000000
92#define regk_iop_scrc_out_dif 0x00000001
93#define regk_iop_scrc_out_hi 0x00000000
94#define regk_iop_scrc_out_neg 0x00000002
95#define regk_iop_scrc_out_no 0x00000000
96#define regk_iop_scrc_out_pos 0x00000001
97#define regk_iop_scrc_out_pos_neg 0x00000003
98#define regk_iop_scrc_out_reg 0x00000000
99#define regk_iop_scrc_out_rw_cfg_default 0x00000000
100#define regk_iop_scrc_out_rw_crc_default 0x00000000
101#define regk_iop_scrc_out_rw_ctrl_default 0x00000000
102#define regk_iop_scrc_out_rw_data_default 0x00000000
103#define regk_iop_scrc_out_rw_init_crc_default 0x00000000
104#define regk_iop_scrc_out_yes 0x00000001
105#endif /* __iop_scrc_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h
new file mode 100644
index 000000000000..bb402c1aa761
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h
@@ -0,0 +1,573 @@
1#ifndef __iop_spu_defs_asm_h
2#define __iop_spu_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_spu.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:08:46 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r
11 * id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56#define STRIDE_iop_spu_rw_r 4
57/* Register rw_r, scope iop_spu, type rw */
58#define reg_iop_spu_rw_r_offset 0
59
60/* Register rw_seq_pc, scope iop_spu, type rw */
61#define reg_iop_spu_rw_seq_pc___addr___lsb 0
62#define reg_iop_spu_rw_seq_pc___addr___width 12
63#define reg_iop_spu_rw_seq_pc_offset 64
64
65/* Register rw_fsm_pc, scope iop_spu, type rw */
66#define reg_iop_spu_rw_fsm_pc___addr___lsb 0
67#define reg_iop_spu_rw_fsm_pc___addr___width 12
68#define reg_iop_spu_rw_fsm_pc_offset 68
69
70/* Register rw_ctrl, scope iop_spu, type rw */
71#define reg_iop_spu_rw_ctrl___fsm___lsb 0
72#define reg_iop_spu_rw_ctrl___fsm___width 1
73#define reg_iop_spu_rw_ctrl___fsm___bit 0
74#define reg_iop_spu_rw_ctrl___en___lsb 1
75#define reg_iop_spu_rw_ctrl___en___width 1
76#define reg_iop_spu_rw_ctrl___en___bit 1
77#define reg_iop_spu_rw_ctrl_offset 72
78
79/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
80#define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0
81#define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5
82#define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5
83#define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3
84#define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8
85#define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5
86#define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13
87#define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3
88#define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16
89#define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5
90#define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21
91#define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3
92#define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24
93#define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5
94#define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29
95#define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3
96#define reg_iop_spu_rw_fsm_inputs3_0_offset 76
97
98/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
99#define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0
100#define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5
101#define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5
102#define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3
103#define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8
104#define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5
105#define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13
106#define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3
107#define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16
108#define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5
109#define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21
110#define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3
111#define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24
112#define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5
113#define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29
114#define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3
115#define reg_iop_spu_rw_fsm_inputs7_4_offset 80
116
117/* Register rw_gio_out, scope iop_spu, type rw */
118#define reg_iop_spu_rw_gio_out_offset 84
119
120/* Register rw_bus0_out, scope iop_spu, type rw */
121#define reg_iop_spu_rw_bus0_out_offset 88
122
123/* Register rw_bus1_out, scope iop_spu, type rw */
124#define reg_iop_spu_rw_bus1_out_offset 92
125
126/* Register r_gio_in, scope iop_spu, type r */
127#define reg_iop_spu_r_gio_in_offset 96
128
129/* Register r_bus0_in, scope iop_spu, type r */
130#define reg_iop_spu_r_bus0_in_offset 100
131
132/* Register r_bus1_in, scope iop_spu, type r */
133#define reg_iop_spu_r_bus1_in_offset 104
134
135/* Register rw_gio_out_set, scope iop_spu, type rw */
136#define reg_iop_spu_rw_gio_out_set_offset 108
137
138/* Register rw_gio_out_clr, scope iop_spu, type rw */
139#define reg_iop_spu_rw_gio_out_clr_offset 112
140
141/* Register rs_wr_stat, scope iop_spu, type rs */
142#define reg_iop_spu_rs_wr_stat___r0___lsb 0
143#define reg_iop_spu_rs_wr_stat___r0___width 1
144#define reg_iop_spu_rs_wr_stat___r0___bit 0
145#define reg_iop_spu_rs_wr_stat___r1___lsb 1
146#define reg_iop_spu_rs_wr_stat___r1___width 1
147#define reg_iop_spu_rs_wr_stat___r1___bit 1
148#define reg_iop_spu_rs_wr_stat___r2___lsb 2
149#define reg_iop_spu_rs_wr_stat___r2___width 1
150#define reg_iop_spu_rs_wr_stat___r2___bit 2
151#define reg_iop_spu_rs_wr_stat___r3___lsb 3
152#define reg_iop_spu_rs_wr_stat___r3___width 1
153#define reg_iop_spu_rs_wr_stat___r3___bit 3
154#define reg_iop_spu_rs_wr_stat___r4___lsb 4
155#define reg_iop_spu_rs_wr_stat___r4___width 1
156#define reg_iop_spu_rs_wr_stat___r4___bit 4
157#define reg_iop_spu_rs_wr_stat___r5___lsb 5
158#define reg_iop_spu_rs_wr_stat___r5___width 1
159#define reg_iop_spu_rs_wr_stat___r5___bit 5
160#define reg_iop_spu_rs_wr_stat___r6___lsb 6
161#define reg_iop_spu_rs_wr_stat___r6___width 1
162#define reg_iop_spu_rs_wr_stat___r6___bit 6
163#define reg_iop_spu_rs_wr_stat___r7___lsb 7
164#define reg_iop_spu_rs_wr_stat___r7___width 1
165#define reg_iop_spu_rs_wr_stat___r7___bit 7
166#define reg_iop_spu_rs_wr_stat___r8___lsb 8
167#define reg_iop_spu_rs_wr_stat___r8___width 1
168#define reg_iop_spu_rs_wr_stat___r8___bit 8
169#define reg_iop_spu_rs_wr_stat___r9___lsb 9
170#define reg_iop_spu_rs_wr_stat___r9___width 1
171#define reg_iop_spu_rs_wr_stat___r9___bit 9
172#define reg_iop_spu_rs_wr_stat___r10___lsb 10
173#define reg_iop_spu_rs_wr_stat___r10___width 1
174#define reg_iop_spu_rs_wr_stat___r10___bit 10
175#define reg_iop_spu_rs_wr_stat___r11___lsb 11
176#define reg_iop_spu_rs_wr_stat___r11___width 1
177#define reg_iop_spu_rs_wr_stat___r11___bit 11
178#define reg_iop_spu_rs_wr_stat___r12___lsb 12
179#define reg_iop_spu_rs_wr_stat___r12___width 1
180#define reg_iop_spu_rs_wr_stat___r12___bit 12
181#define reg_iop_spu_rs_wr_stat___r13___lsb 13
182#define reg_iop_spu_rs_wr_stat___r13___width 1
183#define reg_iop_spu_rs_wr_stat___r13___bit 13
184#define reg_iop_spu_rs_wr_stat___r14___lsb 14
185#define reg_iop_spu_rs_wr_stat___r14___width 1
186#define reg_iop_spu_rs_wr_stat___r14___bit 14
187#define reg_iop_spu_rs_wr_stat___r15___lsb 15
188#define reg_iop_spu_rs_wr_stat___r15___width 1
189#define reg_iop_spu_rs_wr_stat___r15___bit 15
190#define reg_iop_spu_rs_wr_stat_offset 116
191
192/* Register r_wr_stat, scope iop_spu, type r */
193#define reg_iop_spu_r_wr_stat___r0___lsb 0
194#define reg_iop_spu_r_wr_stat___r0___width 1
195#define reg_iop_spu_r_wr_stat___r0___bit 0
196#define reg_iop_spu_r_wr_stat___r1___lsb 1
197#define reg_iop_spu_r_wr_stat___r1___width 1
198#define reg_iop_spu_r_wr_stat___r1___bit 1
199#define reg_iop_spu_r_wr_stat___r2___lsb 2
200#define reg_iop_spu_r_wr_stat___r2___width 1
201#define reg_iop_spu_r_wr_stat___r2___bit 2
202#define reg_iop_spu_r_wr_stat___r3___lsb 3
203#define reg_iop_spu_r_wr_stat___r3___width 1
204#define reg_iop_spu_r_wr_stat___r3___bit 3
205#define reg_iop_spu_r_wr_stat___r4___lsb 4
206#define reg_iop_spu_r_wr_stat___r4___width 1
207#define reg_iop_spu_r_wr_stat___r4___bit 4
208#define reg_iop_spu_r_wr_stat___r5___lsb 5
209#define reg_iop_spu_r_wr_stat___r5___width 1
210#define reg_iop_spu_r_wr_stat___r5___bit 5
211#define reg_iop_spu_r_wr_stat___r6___lsb 6
212#define reg_iop_spu_r_wr_stat___r6___width 1
213#define reg_iop_spu_r_wr_stat___r6___bit 6
214#define reg_iop_spu_r_wr_stat___r7___lsb 7
215#define reg_iop_spu_r_wr_stat___r7___width 1
216#define reg_iop_spu_r_wr_stat___r7___bit 7
217#define reg_iop_spu_r_wr_stat___r8___lsb 8
218#define reg_iop_spu_r_wr_stat___r8___width 1
219#define reg_iop_spu_r_wr_stat___r8___bit 8
220#define reg_iop_spu_r_wr_stat___r9___lsb 9
221#define reg_iop_spu_r_wr_stat___r9___width 1
222#define reg_iop_spu_r_wr_stat___r9___bit 9
223#define reg_iop_spu_r_wr_stat___r10___lsb 10
224#define reg_iop_spu_r_wr_stat___r10___width 1
225#define reg_iop_spu_r_wr_stat___r10___bit 10
226#define reg_iop_spu_r_wr_stat___r11___lsb 11
227#define reg_iop_spu_r_wr_stat___r11___width 1
228#define reg_iop_spu_r_wr_stat___r11___bit 11
229#define reg_iop_spu_r_wr_stat___r12___lsb 12
230#define reg_iop_spu_r_wr_stat___r12___width 1
231#define reg_iop_spu_r_wr_stat___r12___bit 12
232#define reg_iop_spu_r_wr_stat___r13___lsb 13
233#define reg_iop_spu_r_wr_stat___r13___width 1
234#define reg_iop_spu_r_wr_stat___r13___bit 13
235#define reg_iop_spu_r_wr_stat___r14___lsb 14
236#define reg_iop_spu_r_wr_stat___r14___width 1
237#define reg_iop_spu_r_wr_stat___r14___bit 14
238#define reg_iop_spu_r_wr_stat___r15___lsb 15
239#define reg_iop_spu_r_wr_stat___r15___width 1
240#define reg_iop_spu_r_wr_stat___r15___bit 15
241#define reg_iop_spu_r_wr_stat_offset 120
242
243/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */
244#define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124
245
246/* Register r_stat_in, scope iop_spu, type r */
247#define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0
248#define reg_iop_spu_r_stat_in___timer_grp_lo___width 4
249#define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4
250#define reg_iop_spu_r_stat_in___fifo_out_last___width 1
251#define reg_iop_spu_r_stat_in___fifo_out_last___bit 4
252#define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5
253#define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1
254#define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5
255#define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6
256#define reg_iop_spu_r_stat_in___fifo_out_all___width 1
257#define reg_iop_spu_r_stat_in___fifo_out_all___bit 6
258#define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7
259#define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1
260#define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7
261#define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8
262#define reg_iop_spu_r_stat_in___dmc_out_all___width 1
263#define reg_iop_spu_r_stat_in___dmc_out_all___bit 8
264#define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9
265#define reg_iop_spu_r_stat_in___dmc_out_dth___width 1
266#define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9
267#define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10
268#define reg_iop_spu_r_stat_in___dmc_out_eop___width 1
269#define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10
270#define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11
271#define reg_iop_spu_r_stat_in___dmc_out_dv___width 1
272#define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11
273#define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12
274#define reg_iop_spu_r_stat_in___dmc_out_last___width 1
275#define reg_iop_spu_r_stat_in___dmc_out_last___bit 12
276#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13
277#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1
278#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13
279#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14
280#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1
281#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14
282#define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15
283#define reg_iop_spu_r_stat_in___pcrc_correct___width 1
284#define reg_iop_spu_r_stat_in___pcrc_correct___bit 15
285#define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16
286#define reg_iop_spu_r_stat_in___timer_grp_hi___width 4
287#define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20
288#define reg_iop_spu_r_stat_in___dmc_in_sth___width 1
289#define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20
290#define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21
291#define reg_iop_spu_r_stat_in___dmc_in_full___width 1
292#define reg_iop_spu_r_stat_in___dmc_in_full___bit 21
293#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22
294#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1
295#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22
296#define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23
297#define reg_iop_spu_r_stat_in___spu_gio_out___width 4
298#define reg_iop_spu_r_stat_in___sync_clk12___lsb 27
299#define reg_iop_spu_r_stat_in___sync_clk12___width 1
300#define reg_iop_spu_r_stat_in___sync_clk12___bit 27
301#define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28
302#define reg_iop_spu_r_stat_in___scrc_out_data___width 1
303#define reg_iop_spu_r_stat_in___scrc_out_data___bit 28
304#define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29
305#define reg_iop_spu_r_stat_in___scrc_in_err___width 1
306#define reg_iop_spu_r_stat_in___scrc_in_err___bit 29
307#define reg_iop_spu_r_stat_in___mc_busy___lsb 30
308#define reg_iop_spu_r_stat_in___mc_busy___width 1
309#define reg_iop_spu_r_stat_in___mc_busy___bit 30
310#define reg_iop_spu_r_stat_in___mc_owned___lsb 31
311#define reg_iop_spu_r_stat_in___mc_owned___width 1
312#define reg_iop_spu_r_stat_in___mc_owned___bit 31
313#define reg_iop_spu_r_stat_in_offset 128
314
315/* Register r_trigger_in, scope iop_spu, type r */
316#define reg_iop_spu_r_trigger_in_offset 132
317
318/* Register r_special_stat, scope iop_spu, type r */
319#define reg_iop_spu_r_special_stat___c_flag___lsb 0
320#define reg_iop_spu_r_special_stat___c_flag___width 1
321#define reg_iop_spu_r_special_stat___c_flag___bit 0
322#define reg_iop_spu_r_special_stat___v_flag___lsb 1
323#define reg_iop_spu_r_special_stat___v_flag___width 1
324#define reg_iop_spu_r_special_stat___v_flag___bit 1
325#define reg_iop_spu_r_special_stat___z_flag___lsb 2
326#define reg_iop_spu_r_special_stat___z_flag___width 1
327#define reg_iop_spu_r_special_stat___z_flag___bit 2
328#define reg_iop_spu_r_special_stat___n_flag___lsb 3
329#define reg_iop_spu_r_special_stat___n_flag___width 1
330#define reg_iop_spu_r_special_stat___n_flag___bit 3
331#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4
332#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1
333#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4
334#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5
335#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1
336#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5
337#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6
338#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1
339#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6
340#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7
341#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1
342#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7
343#define reg_iop_spu_r_special_stat___fsm_in0___lsb 8
344#define reg_iop_spu_r_special_stat___fsm_in0___width 1
345#define reg_iop_spu_r_special_stat___fsm_in0___bit 8
346#define reg_iop_spu_r_special_stat___fsm_in1___lsb 9
347#define reg_iop_spu_r_special_stat___fsm_in1___width 1
348#define reg_iop_spu_r_special_stat___fsm_in1___bit 9
349#define reg_iop_spu_r_special_stat___fsm_in2___lsb 10
350#define reg_iop_spu_r_special_stat___fsm_in2___width 1
351#define reg_iop_spu_r_special_stat___fsm_in2___bit 10
352#define reg_iop_spu_r_special_stat___fsm_in3___lsb 11
353#define reg_iop_spu_r_special_stat___fsm_in3___width 1
354#define reg_iop_spu_r_special_stat___fsm_in3___bit 11
355#define reg_iop_spu_r_special_stat___fsm_in4___lsb 12
356#define reg_iop_spu_r_special_stat___fsm_in4___width 1
357#define reg_iop_spu_r_special_stat___fsm_in4___bit 12
358#define reg_iop_spu_r_special_stat___fsm_in5___lsb 13
359#define reg_iop_spu_r_special_stat___fsm_in5___width 1
360#define reg_iop_spu_r_special_stat___fsm_in5___bit 13
361#define reg_iop_spu_r_special_stat___fsm_in6___lsb 14
362#define reg_iop_spu_r_special_stat___fsm_in6___width 1
363#define reg_iop_spu_r_special_stat___fsm_in6___bit 14
364#define reg_iop_spu_r_special_stat___fsm_in7___lsb 15
365#define reg_iop_spu_r_special_stat___fsm_in7___width 1
366#define reg_iop_spu_r_special_stat___fsm_in7___bit 15
367#define reg_iop_spu_r_special_stat___event0___lsb 16
368#define reg_iop_spu_r_special_stat___event0___width 1
369#define reg_iop_spu_r_special_stat___event0___bit 16
370#define reg_iop_spu_r_special_stat___event1___lsb 17
371#define reg_iop_spu_r_special_stat___event1___width 1
372#define reg_iop_spu_r_special_stat___event1___bit 17
373#define reg_iop_spu_r_special_stat___event2___lsb 18
374#define reg_iop_spu_r_special_stat___event2___width 1
375#define reg_iop_spu_r_special_stat___event2___bit 18
376#define reg_iop_spu_r_special_stat___event3___lsb 19
377#define reg_iop_spu_r_special_stat___event3___width 1
378#define reg_iop_spu_r_special_stat___event3___bit 19
379#define reg_iop_spu_r_special_stat_offset 136
380
381/* Register rw_reg_access, scope iop_spu, type rw */
382#define reg_iop_spu_rw_reg_access___addr___lsb 0
383#define reg_iop_spu_rw_reg_access___addr___width 13
384#define reg_iop_spu_rw_reg_access___imm_hi___lsb 16
385#define reg_iop_spu_rw_reg_access___imm_hi___width 16
386#define reg_iop_spu_rw_reg_access_offset 140
387
388#define STRIDE_iop_spu_rw_event_cfg 4
389/* Register rw_event_cfg, scope iop_spu, type rw */
390#define reg_iop_spu_rw_event_cfg___addr___lsb 0
391#define reg_iop_spu_rw_event_cfg___addr___width 12
392#define reg_iop_spu_rw_event_cfg___src___lsb 12
393#define reg_iop_spu_rw_event_cfg___src___width 2
394#define reg_iop_spu_rw_event_cfg___eq_en___lsb 14
395#define reg_iop_spu_rw_event_cfg___eq_en___width 1
396#define reg_iop_spu_rw_event_cfg___eq_en___bit 14
397#define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15
398#define reg_iop_spu_rw_event_cfg___eq_inv___width 1
399#define reg_iop_spu_rw_event_cfg___eq_inv___bit 15
400#define reg_iop_spu_rw_event_cfg___gt_en___lsb 16
401#define reg_iop_spu_rw_event_cfg___gt_en___width 1
402#define reg_iop_spu_rw_event_cfg___gt_en___bit 16
403#define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17
404#define reg_iop_spu_rw_event_cfg___gt_inv___width 1
405#define reg_iop_spu_rw_event_cfg___gt_inv___bit 17
406#define reg_iop_spu_rw_event_cfg_offset 144
407
408#define STRIDE_iop_spu_rw_event_mask 4
409/* Register rw_event_mask, scope iop_spu, type rw */
410#define reg_iop_spu_rw_event_mask_offset 160
411
412#define STRIDE_iop_spu_rw_event_val 4
413/* Register rw_event_val, scope iop_spu, type rw */
414#define reg_iop_spu_rw_event_val_offset 176
415
416/* Register rw_event_ret, scope iop_spu, type rw */
417#define reg_iop_spu_rw_event_ret___addr___lsb 0
418#define reg_iop_spu_rw_event_ret___addr___width 12
419#define reg_iop_spu_rw_event_ret_offset 192
420
421/* Register r_trace, scope iop_spu, type r */
422#define reg_iop_spu_r_trace___fsm___lsb 0
423#define reg_iop_spu_r_trace___fsm___width 1
424#define reg_iop_spu_r_trace___fsm___bit 0
425#define reg_iop_spu_r_trace___en___lsb 1
426#define reg_iop_spu_r_trace___en___width 1
427#define reg_iop_spu_r_trace___en___bit 1
428#define reg_iop_spu_r_trace___c_flag___lsb 2
429#define reg_iop_spu_r_trace___c_flag___width 1
430#define reg_iop_spu_r_trace___c_flag___bit 2
431#define reg_iop_spu_r_trace___v_flag___lsb 3
432#define reg_iop_spu_r_trace___v_flag___width 1
433#define reg_iop_spu_r_trace___v_flag___bit 3
434#define reg_iop_spu_r_trace___z_flag___lsb 4
435#define reg_iop_spu_r_trace___z_flag___width 1
436#define reg_iop_spu_r_trace___z_flag___bit 4
437#define reg_iop_spu_r_trace___n_flag___lsb 5
438#define reg_iop_spu_r_trace___n_flag___width 1
439#define reg_iop_spu_r_trace___n_flag___bit 5
440#define reg_iop_spu_r_trace___seq_addr___lsb 6
441#define reg_iop_spu_r_trace___seq_addr___width 12
442#define reg_iop_spu_r_trace___fsm_addr___lsb 20
443#define reg_iop_spu_r_trace___fsm_addr___width 12
444#define reg_iop_spu_r_trace_offset 196
445
446/* Register r_fsm_trace, scope iop_spu, type r */
447#define reg_iop_spu_r_fsm_trace___fsm___lsb 0
448#define reg_iop_spu_r_fsm_trace___fsm___width 1
449#define reg_iop_spu_r_fsm_trace___fsm___bit 0
450#define reg_iop_spu_r_fsm_trace___en___lsb 1
451#define reg_iop_spu_r_fsm_trace___en___width 1
452#define reg_iop_spu_r_fsm_trace___en___bit 1
453#define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2
454#define reg_iop_spu_r_fsm_trace___tmr_done___width 1
455#define reg_iop_spu_r_fsm_trace___tmr_done___bit 2
456#define reg_iop_spu_r_fsm_trace___inp0___lsb 3
457#define reg_iop_spu_r_fsm_trace___inp0___width 1
458#define reg_iop_spu_r_fsm_trace___inp0___bit 3
459#define reg_iop_spu_r_fsm_trace___inp1___lsb 4
460#define reg_iop_spu_r_fsm_trace___inp1___width 1
461#define reg_iop_spu_r_fsm_trace___inp1___bit 4
462#define reg_iop_spu_r_fsm_trace___inp2___lsb 5
463#define reg_iop_spu_r_fsm_trace___inp2___width 1
464#define reg_iop_spu_r_fsm_trace___inp2___bit 5
465#define reg_iop_spu_r_fsm_trace___inp3___lsb 6
466#define reg_iop_spu_r_fsm_trace___inp3___width 1
467#define reg_iop_spu_r_fsm_trace___inp3___bit 6
468#define reg_iop_spu_r_fsm_trace___event0___lsb 7
469#define reg_iop_spu_r_fsm_trace___event0___width 1
470#define reg_iop_spu_r_fsm_trace___event0___bit 7
471#define reg_iop_spu_r_fsm_trace___event1___lsb 8
472#define reg_iop_spu_r_fsm_trace___event1___width 1
473#define reg_iop_spu_r_fsm_trace___event1___bit 8
474#define reg_iop_spu_r_fsm_trace___event2___lsb 9
475#define reg_iop_spu_r_fsm_trace___event2___width 1
476#define reg_iop_spu_r_fsm_trace___event2___bit 9
477#define reg_iop_spu_r_fsm_trace___event3___lsb 10
478#define reg_iop_spu_r_fsm_trace___event3___width 1
479#define reg_iop_spu_r_fsm_trace___event3___bit 10
480#define reg_iop_spu_r_fsm_trace___gio_out___lsb 11
481#define reg_iop_spu_r_fsm_trace___gio_out___width 8
482#define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20
483#define reg_iop_spu_r_fsm_trace___fsm_addr___width 12
484#define reg_iop_spu_r_fsm_trace_offset 200
485
486#define STRIDE_iop_spu_rw_brp 4
487/* Register rw_brp, scope iop_spu, type rw */
488#define reg_iop_spu_rw_brp___addr___lsb 0
489#define reg_iop_spu_rw_brp___addr___width 12
490#define reg_iop_spu_rw_brp___fsm___lsb 12
491#define reg_iop_spu_rw_brp___fsm___width 1
492#define reg_iop_spu_rw_brp___fsm___bit 12
493#define reg_iop_spu_rw_brp___en___lsb 13
494#define reg_iop_spu_rw_brp___en___width 1
495#define reg_iop_spu_rw_brp___en___bit 13
496#define reg_iop_spu_rw_brp_offset 204
497
498
499/* Constants */
500#define regk_iop_spu_attn_hi 0x00000005
501#define regk_iop_spu_attn_lo 0x00000005
502#define regk_iop_spu_attn_r0 0x00000000
503#define regk_iop_spu_attn_r1 0x00000001
504#define regk_iop_spu_attn_r10 0x00000002
505#define regk_iop_spu_attn_r11 0x00000003
506#define regk_iop_spu_attn_r12 0x00000004
507#define regk_iop_spu_attn_r13 0x00000005
508#define regk_iop_spu_attn_r14 0x00000006
509#define regk_iop_spu_attn_r15 0x00000007
510#define regk_iop_spu_attn_r2 0x00000002
511#define regk_iop_spu_attn_r3 0x00000003
512#define regk_iop_spu_attn_r4 0x00000004
513#define regk_iop_spu_attn_r5 0x00000005
514#define regk_iop_spu_attn_r6 0x00000006
515#define regk_iop_spu_attn_r7 0x00000007
516#define regk_iop_spu_attn_r8 0x00000000
517#define regk_iop_spu_attn_r9 0x00000001
518#define regk_iop_spu_c 0x00000000
519#define regk_iop_spu_flag 0x00000002
520#define regk_iop_spu_gio_in 0x00000000
521#define regk_iop_spu_gio_out 0x00000005
522#define regk_iop_spu_gio_out0 0x00000008
523#define regk_iop_spu_gio_out1 0x00000009
524#define regk_iop_spu_gio_out2 0x0000000a
525#define regk_iop_spu_gio_out3 0x0000000b
526#define regk_iop_spu_gio_out4 0x0000000c
527#define regk_iop_spu_gio_out5 0x0000000d
528#define regk_iop_spu_gio_out6 0x0000000e
529#define regk_iop_spu_gio_out7 0x0000000f
530#define regk_iop_spu_n 0x00000003
531#define regk_iop_spu_no 0x00000000
532#define regk_iop_spu_r0 0x00000008
533#define regk_iop_spu_r1 0x00000009
534#define regk_iop_spu_r10 0x0000000a
535#define regk_iop_spu_r11 0x0000000b
536#define regk_iop_spu_r12 0x0000000c
537#define regk_iop_spu_r13 0x0000000d
538#define regk_iop_spu_r14 0x0000000e
539#define regk_iop_spu_r15 0x0000000f
540#define regk_iop_spu_r2 0x0000000a
541#define regk_iop_spu_r3 0x0000000b
542#define regk_iop_spu_r4 0x0000000c
543#define regk_iop_spu_r5 0x0000000d
544#define regk_iop_spu_r6 0x0000000e
545#define regk_iop_spu_r7 0x0000000f
546#define regk_iop_spu_r8 0x00000008
547#define regk_iop_spu_r9 0x00000009
548#define regk_iop_spu_reg_hi 0x00000002
549#define regk_iop_spu_reg_lo 0x00000002
550#define regk_iop_spu_rw_brp_default 0x00000000
551#define regk_iop_spu_rw_brp_size 0x00000004
552#define regk_iop_spu_rw_ctrl_default 0x00000000
553#define regk_iop_spu_rw_event_cfg_size 0x00000004
554#define regk_iop_spu_rw_event_mask_size 0x00000004
555#define regk_iop_spu_rw_event_val_size 0x00000004
556#define regk_iop_spu_rw_gio_out_default 0x00000000
557#define regk_iop_spu_rw_r_size 0x00000010
558#define regk_iop_spu_rw_reg_access_default 0x00000000
559#define regk_iop_spu_stat_in 0x00000002
560#define regk_iop_spu_statin_hi 0x00000004
561#define regk_iop_spu_statin_lo 0x00000004
562#define regk_iop_spu_trig 0x00000003
563#define regk_iop_spu_trigger 0x00000006
564#define regk_iop_spu_v 0x00000001
565#define regk_iop_spu_wsts_gioout_spec 0x00000001
566#define regk_iop_spu_xor 0x00000003
567#define regk_iop_spu_xor_bus0_r2_0 0x00000000
568#define regk_iop_spu_xor_bus0m_r2_0 0x00000002
569#define regk_iop_spu_xor_bus1_r3_0 0x00000001
570#define regk_iop_spu_xor_bus1m_r3_0 0x00000003
571#define regk_iop_spu_yes 0x00000001
572#define regk_iop_spu_z 0x00000002
573#endif /* __iop_spu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
new file mode 100644
index 000000000000..3be60f9b024c
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
@@ -0,0 +1,1052 @@
1#ifndef __iop_sw_cfg_defs_asm_h
2#define __iop_sw_cfg_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:10:19 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
11 * id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
57#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0
58#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2
59#define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0
60
61/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
62#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0
63#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2
64#define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4
65
66/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
67#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0
68#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2
69#define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8
70
71/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
72#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0
73#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2
74#define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12
75
76/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
77#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0
78#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2
79#define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16
80
81/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
82#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0
83#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2
84#define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20
85
86/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
87#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0
88#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2
89#define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24
90
91/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
92#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0
93#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2
94#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28
95
96/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
97#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0
98#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2
99#define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32
100
101/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
102#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0
103#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2
104#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36
105
106/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
107#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0
108#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2
109#define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40
110
111/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
112#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0
113#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2
114#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44
115
116/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
117#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0
118#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2
119#define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48
120
121/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
122#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0
123#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2
124#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52
125
126/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
127#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0
128#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2
129#define reg_iop_sw_cfg_rw_sap_in_owner_offset 56
130
131/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
132#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0
133#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2
134#define reg_iop_sw_cfg_rw_sap_out_owner_offset 60
135
136/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
137#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0
138#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2
139#define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64
140
141/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
142#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0
143#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2
144#define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68
145
146/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
147#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0
148#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2
149#define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72
150
151/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
152#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0
153#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2
154#define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76
155
156/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
157#define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0
158#define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2
159#define reg_iop_sw_cfg_rw_spu0_owner_offset 80
160
161/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
162#define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0
163#define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2
164#define reg_iop_sw_cfg_rw_spu1_owner_offset 84
165
166/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
167#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0
168#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2
169#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88
170
171/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
172#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0
173#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2
174#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92
175
176/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
177#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0
178#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2
179#define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96
180
181/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
182#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0
183#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2
184#define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100
185
186/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
187#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0
188#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2
189#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104
190
191/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
192#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0
193#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2
194#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108
195
196/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
197#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0
198#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2
199#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112
200
201/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
202#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0
203#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2
204#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116
205
206/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
207#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0
208#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2
209#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120
210
211/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
212#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0
213#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2
214#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124
215
216/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
217#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0
218#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2
219#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128
220
221/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
222#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0
223#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2
224#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132
225
226/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
227#define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0
228#define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8
229#define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8
230#define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8
231#define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16
232#define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8
233#define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24
234#define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8
235#define reg_iop_sw_cfg_rw_bus0_mask_offset 136
236
237/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
238#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0
239#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1
240#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0
241#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1
242#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1
243#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1
244#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2
245#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1
246#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2
247#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3
248#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1
249#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3
250#define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140
251
252/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
253#define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0
254#define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8
255#define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8
256#define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8
257#define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16
258#define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8
259#define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24
260#define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8
261#define reg_iop_sw_cfg_rw_bus1_mask_offset 144
262
263/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
264#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0
265#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1
266#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0
267#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1
268#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1
269#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1
270#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2
271#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1
272#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2
273#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3
274#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1
275#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3
276#define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148
277
278/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
279#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0
280#define reg_iop_sw_cfg_rw_gio_mask___val___width 32
281#define reg_iop_sw_cfg_rw_gio_mask_offset 152
282
283/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
284#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0
285#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32
286#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156
287
288/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
289#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0
290#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2
291#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2
292#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2
293#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4
294#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2
295#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6
296#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2
297#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8
298#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2
299#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10
300#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2
301#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12
302#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2
303#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14
304#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2
305#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16
306#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2
307#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18
308#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2
309#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20
310#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2
311#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22
312#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2
313#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24
314#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2
315#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26
316#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2
317#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28
318#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2
319#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30
320#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2
321#define reg_iop_sw_cfg_rw_pinmapping_offset 160
322
323/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
324#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0
325#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3
326#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3
327#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3
328#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6
329#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3
330#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9
331#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3
332#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12
333#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3
334#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15
335#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3
336#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18
337#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3
338#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21
339#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3
340#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164
341
342/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
343#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0
344#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4
345#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4
346#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2
347#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6
348#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4
349#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10
350#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2
351#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12
352#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4
353#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16
354#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2
355#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18
356#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4
357#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22
358#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2
359#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168
360
361/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
362#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0
363#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4
364#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4
365#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2
366#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6
367#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4
368#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10
369#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2
370#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12
371#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4
372#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16
373#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2
374#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18
375#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4
376#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22
377#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2
378#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172
379
380/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
381#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0
382#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4
383#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4
384#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2
385#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6
386#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4
387#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10
388#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2
389#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12
390#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4
391#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16
392#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2
393#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18
394#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4
395#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22
396#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2
397#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176
398
399/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
400#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0
401#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4
402#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4
403#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2
404#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6
405#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4
406#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10
407#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2
408#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12
409#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4
410#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16
411#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2
412#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18
413#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4
414#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22
415#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2
416#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180
417
418/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
419#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0
420#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4
421#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4
422#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2
423#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6
424#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4
425#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10
426#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2
427#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12
428#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4
429#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16
430#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2
431#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18
432#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4
433#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22
434#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2
435#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184
436
437/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
438#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0
439#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4
440#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4
441#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2
442#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6
443#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4
444#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10
445#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2
446#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12
447#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4
448#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16
449#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2
450#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18
451#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4
452#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22
453#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2
454#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188
455
456/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
457#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0
458#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4
459#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4
460#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2
461#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6
462#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4
463#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10
464#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2
465#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12
466#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4
467#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16
468#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2
469#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18
470#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4
471#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22
472#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2
473#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192
474
475/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
476#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0
477#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4
478#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4
479#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2
480#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6
481#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4
482#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10
483#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2
484#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12
485#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4
486#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16
487#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2
488#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18
489#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4
490#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22
491#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2
492#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196
493
494/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
495#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0
496#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2
497#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2
498#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2
499#define reg_iop_sw_cfg_rw_spu0_cfg_offset 200
500
501/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
502#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0
503#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2
504#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2
505#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2
506#define reg_iop_sw_cfg_rw_spu1_cfg_offset 204
507
508/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
509#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0
510#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3
511#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3
512#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1
513#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3
514#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4
515#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1
516#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4
517#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5
518#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1
519#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5
520#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6
521#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1
522#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6
523#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7
524#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1
525#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7
526#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8
527#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1
528#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8
529#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9
530#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1
531#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9
532#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10
533#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1
534#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10
535#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208
536
537/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
538#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0
539#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3
540#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3
541#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1
542#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3
543#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4
544#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1
545#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4
546#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5
547#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1
548#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5
549#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6
550#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1
551#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6
552#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7
553#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1
554#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7
555#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8
556#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1
557#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8
558#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9
559#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1
560#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9
561#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10
562#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1
563#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10
564#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212
565
566/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
567#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0
568#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3
569#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3
570#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1
571#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3
572#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4
573#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1
574#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4
575#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5
576#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1
577#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5
578#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6
579#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1
580#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6
581#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7
582#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1
583#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7
584#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8
585#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1
586#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8
587#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9
588#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1
589#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9
590#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10
591#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1
592#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10
593#define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216
594
595/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
596#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0
597#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3
598#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3
599#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1
600#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3
601#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4
602#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1
603#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4
604#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5
605#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1
606#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5
607#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6
608#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1
609#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6
610#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7
611#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1
612#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7
613#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8
614#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1
615#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8
616#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9
617#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1
618#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9
619#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10
620#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1
621#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10
622#define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220
623
624/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
625#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0
626#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1
627#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0
628#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1
629#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1
630#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1
631#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2
632#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1
633#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2
634#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3
635#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1
636#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3
637#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4
638#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1
639#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4
640#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5
641#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1
642#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5
643#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6
644#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1
645#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6
646#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7
647#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1
648#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7
649#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8
650#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1
651#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8
652#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9
653#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1
654#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9
655#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10
656#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1
657#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10
658#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11
659#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1
660#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11
661#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12
662#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1
663#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12
664#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13
665#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1
666#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13
667#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14
668#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1
669#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14
670#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15
671#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1
672#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15
673#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224
674
675/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
676#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0
677#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1
678#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0
679#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1
680#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5
681#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6
682#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3
683#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9
684#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3
685#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12
686#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2
687#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14
688#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4
689#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18
690#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1
691#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18
692#define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228
693
694/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
695#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0
696#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1
697#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0
698#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1
699#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5
700#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6
701#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3
702#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9
703#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3
704#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12
705#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2
706#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14
707#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4
708#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18
709#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1
710#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18
711#define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232
712
713/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
714#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0
715#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3
716#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3
717#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3
718#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6
719#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3
720#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9
721#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2
722#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11
723#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3
724#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14
725#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3
726#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17
727#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2
728#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19
729#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3
730#define reg_iop_sw_cfg_rw_sdp_cfg_offset 236
731
732
733/* Constants */
734#define regk_iop_sw_cfg_a 0x00000001
735#define regk_iop_sw_cfg_b 0x00000002
736#define regk_iop_sw_cfg_bus0 0x00000000
737#define regk_iop_sw_cfg_bus0_rot16 0x00000004
738#define regk_iop_sw_cfg_bus0_rot24 0x00000006
739#define regk_iop_sw_cfg_bus0_rot8 0x00000002
740#define regk_iop_sw_cfg_bus1 0x00000001
741#define regk_iop_sw_cfg_bus1_rot16 0x00000005
742#define regk_iop_sw_cfg_bus1_rot24 0x00000007
743#define regk_iop_sw_cfg_bus1_rot8 0x00000003
744#define regk_iop_sw_cfg_clk12 0x00000000
745#define regk_iop_sw_cfg_cpu 0x00000000
746#define regk_iop_sw_cfg_dmc0 0x00000000
747#define regk_iop_sw_cfg_dmc1 0x00000001
748#define regk_iop_sw_cfg_gated_clk0 0x00000010
749#define regk_iop_sw_cfg_gated_clk1 0x00000011
750#define regk_iop_sw_cfg_gated_clk2 0x00000012
751#define regk_iop_sw_cfg_gated_clk3 0x00000013
752#define regk_iop_sw_cfg_gio0 0x00000004
753#define regk_iop_sw_cfg_gio1 0x00000001
754#define regk_iop_sw_cfg_gio2 0x00000005
755#define regk_iop_sw_cfg_gio3 0x00000002
756#define regk_iop_sw_cfg_gio4 0x00000006
757#define regk_iop_sw_cfg_gio5 0x00000003
758#define regk_iop_sw_cfg_gio6 0x00000007
759#define regk_iop_sw_cfg_gio7 0x00000004
760#define regk_iop_sw_cfg_gio_in0 0x00000000
761#define regk_iop_sw_cfg_gio_in1 0x00000001
762#define regk_iop_sw_cfg_gio_in10 0x00000002
763#define regk_iop_sw_cfg_gio_in11 0x00000003
764#define regk_iop_sw_cfg_gio_in14 0x00000004
765#define regk_iop_sw_cfg_gio_in15 0x00000005
766#define regk_iop_sw_cfg_gio_in18 0x00000002
767#define regk_iop_sw_cfg_gio_in19 0x00000003
768#define regk_iop_sw_cfg_gio_in20 0x00000004
769#define regk_iop_sw_cfg_gio_in21 0x00000005
770#define regk_iop_sw_cfg_gio_in26 0x00000006
771#define regk_iop_sw_cfg_gio_in27 0x00000007
772#define regk_iop_sw_cfg_gio_in28 0x00000006
773#define regk_iop_sw_cfg_gio_in29 0x00000007
774#define regk_iop_sw_cfg_gio_in4 0x00000000
775#define regk_iop_sw_cfg_gio_in5 0x00000001
776#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001
777#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000001
778#define regk_iop_sw_cfg_last_timer_grp2_tmr2 0x00000002
779#define regk_iop_sw_cfg_last_timer_grp2_tmr3 0x00000003
780#define regk_iop_sw_cfg_last_timer_grp3_tmr2 0x00000002
781#define regk_iop_sw_cfg_last_timer_grp3_tmr3 0x00000003
782#define regk_iop_sw_cfg_mpu 0x00000001
783#define regk_iop_sw_cfg_none 0x00000000
784#define regk_iop_sw_cfg_par0 0x00000000
785#define regk_iop_sw_cfg_par1 0x00000001
786#define regk_iop_sw_cfg_pdp_out0 0x00000002
787#define regk_iop_sw_cfg_pdp_out0_hi 0x00000001
788#define regk_iop_sw_cfg_pdp_out0_hi_rot8 0x00000005
789#define regk_iop_sw_cfg_pdp_out0_lo 0x00000000
790#define regk_iop_sw_cfg_pdp_out0_lo_rot8 0x00000004
791#define regk_iop_sw_cfg_pdp_out1 0x00000003
792#define regk_iop_sw_cfg_pdp_out1_hi 0x00000003
793#define regk_iop_sw_cfg_pdp_out1_hi_rot8 0x00000005
794#define regk_iop_sw_cfg_pdp_out1_lo 0x00000002
795#define regk_iop_sw_cfg_pdp_out1_lo_rot8 0x00000004
796#define regk_iop_sw_cfg_rw_bus0_mask_default 0x00000000
797#define regk_iop_sw_cfg_rw_bus0_oe_mask_default 0x00000000
798#define regk_iop_sw_cfg_rw_bus1_mask_default 0x00000000
799#define regk_iop_sw_cfg_rw_bus1_oe_mask_default 0x00000000
800#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000
801#define regk_iop_sw_cfg_rw_crc_par0_owner_default 0x00000000
802#define regk_iop_sw_cfg_rw_crc_par1_owner_default 0x00000000
803#define regk_iop_sw_cfg_rw_dmc_in0_owner_default 0x00000000
804#define regk_iop_sw_cfg_rw_dmc_in1_owner_default 0x00000000
805#define regk_iop_sw_cfg_rw_dmc_out0_owner_default 0x00000000
806#define regk_iop_sw_cfg_rw_dmc_out1_owner_default 0x00000000
807#define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default 0x00000000
808#define regk_iop_sw_cfg_rw_fifo_in0_owner_default 0x00000000
809#define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default 0x00000000
810#define regk_iop_sw_cfg_rw_fifo_in1_owner_default 0x00000000
811#define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default 0x00000000
812#define regk_iop_sw_cfg_rw_fifo_out0_owner_default 0x00000000
813#define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default 0x00000000
814#define regk_iop_sw_cfg_rw_fifo_out1_owner_default 0x00000000
815#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000
816#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000
817#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000
818#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000
819#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000
820#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000
821#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000
822#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000
823#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000
824#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000
825#define regk_iop_sw_cfg_rw_pdp0_cfg_default 0x00000000
826#define regk_iop_sw_cfg_rw_pdp1_cfg_default 0x00000000
827#define regk_iop_sw_cfg_rw_pinmapping_default 0x55555555
828#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000
829#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000
830#define regk_iop_sw_cfg_rw_scrc_in0_owner_default 0x00000000
831#define regk_iop_sw_cfg_rw_scrc_in1_owner_default 0x00000000
832#define regk_iop_sw_cfg_rw_scrc_out0_owner_default 0x00000000
833#define regk_iop_sw_cfg_rw_scrc_out1_owner_default 0x00000000
834#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000
835#define regk_iop_sw_cfg_rw_spu0_cfg_default 0x00000000
836#define regk_iop_sw_cfg_rw_spu0_owner_default 0x00000000
837#define regk_iop_sw_cfg_rw_spu1_cfg_default 0x00000000
838#define regk_iop_sw_cfg_rw_spu1_owner_default 0x00000000
839#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000
840#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000
841#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000
842#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000
843#define regk_iop_sw_cfg_rw_timer_grp2_cfg_default 0x00000000
844#define regk_iop_sw_cfg_rw_timer_grp2_owner_default 0x00000000
845#define regk_iop_sw_cfg_rw_timer_grp3_cfg_default 0x00000000
846#define regk_iop_sw_cfg_rw_timer_grp3_owner_default 0x00000000
847#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000
848#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000
849#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000
850#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000
851#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000
852#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000
853#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000
854#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000
855#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000
856#define regk_iop_sw_cfg_sdp_out0 0x00000008
857#define regk_iop_sw_cfg_sdp_out1 0x00000009
858#define regk_iop_sw_cfg_size16 0x00000002
859#define regk_iop_sw_cfg_size24 0x00000003
860#define regk_iop_sw_cfg_size32 0x00000004
861#define regk_iop_sw_cfg_size8 0x00000001
862#define regk_iop_sw_cfg_spu0 0x00000002
863#define regk_iop_sw_cfg_spu0_bus_out0_hi 0x00000006
864#define regk_iop_sw_cfg_spu0_bus_out0_lo 0x00000006
865#define regk_iop_sw_cfg_spu0_bus_out1_hi 0x00000007
866#define regk_iop_sw_cfg_spu0_bus_out1_lo 0x00000007
867#define regk_iop_sw_cfg_spu0_g0 0x0000000e
868#define regk_iop_sw_cfg_spu0_g1 0x0000000e
869#define regk_iop_sw_cfg_spu0_g2 0x0000000e
870#define regk_iop_sw_cfg_spu0_g3 0x0000000e
871#define regk_iop_sw_cfg_spu0_g4 0x0000000e
872#define regk_iop_sw_cfg_spu0_g5 0x0000000e
873#define regk_iop_sw_cfg_spu0_g6 0x0000000e
874#define regk_iop_sw_cfg_spu0_g7 0x0000000e
875#define regk_iop_sw_cfg_spu0_gio0 0x00000000
876#define regk_iop_sw_cfg_spu0_gio1 0x00000001
877#define regk_iop_sw_cfg_spu0_gio2 0x00000000
878#define regk_iop_sw_cfg_spu0_gio5 0x00000005
879#define regk_iop_sw_cfg_spu0_gio6 0x00000006
880#define regk_iop_sw_cfg_spu0_gio7 0x00000007
881#define regk_iop_sw_cfg_spu0_gio_out0 0x00000008
882#define regk_iop_sw_cfg_spu0_gio_out1 0x00000009
883#define regk_iop_sw_cfg_spu0_gio_out2 0x0000000a
884#define regk_iop_sw_cfg_spu0_gio_out3 0x0000000b
885#define regk_iop_sw_cfg_spu0_gio_out4 0x0000000c
886#define regk_iop_sw_cfg_spu0_gio_out5 0x0000000d
887#define regk_iop_sw_cfg_spu0_gio_out6 0x0000000e
888#define regk_iop_sw_cfg_spu0_gio_out7 0x0000000f
889#define regk_iop_sw_cfg_spu0_gioout0 0x00000000
890#define regk_iop_sw_cfg_spu0_gioout1 0x00000000
891#define regk_iop_sw_cfg_spu0_gioout10 0x0000000e
892#define regk_iop_sw_cfg_spu0_gioout11 0x0000000e
893#define regk_iop_sw_cfg_spu0_gioout12 0x0000000e
894#define regk_iop_sw_cfg_spu0_gioout13 0x0000000e
895#define regk_iop_sw_cfg_spu0_gioout14 0x0000000e
896#define regk_iop_sw_cfg_spu0_gioout15 0x0000000e
897#define regk_iop_sw_cfg_spu0_gioout16 0x0000000e
898#define regk_iop_sw_cfg_spu0_gioout17 0x0000000e
899#define regk_iop_sw_cfg_spu0_gioout18 0x0000000e
900#define regk_iop_sw_cfg_spu0_gioout19 0x0000000e
901#define regk_iop_sw_cfg_spu0_gioout2 0x00000002
902#define regk_iop_sw_cfg_spu0_gioout20 0x0000000e
903#define regk_iop_sw_cfg_spu0_gioout21 0x0000000e
904#define regk_iop_sw_cfg_spu0_gioout22 0x0000000e
905#define regk_iop_sw_cfg_spu0_gioout23 0x0000000e
906#define regk_iop_sw_cfg_spu0_gioout24 0x0000000e
907#define regk_iop_sw_cfg_spu0_gioout25 0x0000000e
908#define regk_iop_sw_cfg_spu0_gioout26 0x0000000e
909#define regk_iop_sw_cfg_spu0_gioout27 0x0000000e
910#define regk_iop_sw_cfg_spu0_gioout28 0x0000000e
911#define regk_iop_sw_cfg_spu0_gioout29 0x0000000e
912#define regk_iop_sw_cfg_spu0_gioout3 0x00000002
913#define regk_iop_sw_cfg_spu0_gioout30 0x0000000e
914#define regk_iop_sw_cfg_spu0_gioout31 0x0000000e
915#define regk_iop_sw_cfg_spu0_gioout4 0x00000004
916#define regk_iop_sw_cfg_spu0_gioout5 0x00000004
917#define regk_iop_sw_cfg_spu0_gioout6 0x00000006
918#define regk_iop_sw_cfg_spu0_gioout7 0x00000006
919#define regk_iop_sw_cfg_spu0_gioout8 0x0000000e
920#define regk_iop_sw_cfg_spu0_gioout9 0x0000000e
921#define regk_iop_sw_cfg_spu1 0x00000003
922#define regk_iop_sw_cfg_spu1_bus_out0_hi 0x00000006
923#define regk_iop_sw_cfg_spu1_bus_out0_lo 0x00000006
924#define regk_iop_sw_cfg_spu1_bus_out1_hi 0x00000007
925#define regk_iop_sw_cfg_spu1_bus_out1_lo 0x00000007
926#define regk_iop_sw_cfg_spu1_g0 0x0000000f
927#define regk_iop_sw_cfg_spu1_g1 0x0000000f
928#define regk_iop_sw_cfg_spu1_g2 0x0000000f
929#define regk_iop_sw_cfg_spu1_g3 0x0000000f
930#define regk_iop_sw_cfg_spu1_g4 0x0000000f
931#define regk_iop_sw_cfg_spu1_g5 0x0000000f
932#define regk_iop_sw_cfg_spu1_g6 0x0000000f
933#define regk_iop_sw_cfg_spu1_g7 0x0000000f
934#define regk_iop_sw_cfg_spu1_gio0 0x00000002
935#define regk_iop_sw_cfg_spu1_gio1 0x00000003
936#define regk_iop_sw_cfg_spu1_gio2 0x00000002
937#define regk_iop_sw_cfg_spu1_gio5 0x00000005
938#define regk_iop_sw_cfg_spu1_gio6 0x00000006
939#define regk_iop_sw_cfg_spu1_gio7 0x00000007
940#define regk_iop_sw_cfg_spu1_gio_out0 0x00000008
941#define regk_iop_sw_cfg_spu1_gio_out1 0x00000009
942#define regk_iop_sw_cfg_spu1_gio_out2 0x0000000a
943#define regk_iop_sw_cfg_spu1_gio_out3 0x0000000b
944#define regk_iop_sw_cfg_spu1_gio_out4 0x0000000c
945#define regk_iop_sw_cfg_spu1_gio_out5 0x0000000d
946#define regk_iop_sw_cfg_spu1_gio_out6 0x0000000e
947#define regk_iop_sw_cfg_spu1_gio_out7 0x0000000f
948#define regk_iop_sw_cfg_spu1_gioout0 0x00000001
949#define regk_iop_sw_cfg_spu1_gioout1 0x00000001
950#define regk_iop_sw_cfg_spu1_gioout10 0x0000000f
951#define regk_iop_sw_cfg_spu1_gioout11 0x0000000f
952#define regk_iop_sw_cfg_spu1_gioout12 0x0000000f
953#define regk_iop_sw_cfg_spu1_gioout13 0x0000000f
954#define regk_iop_sw_cfg_spu1_gioout14 0x0000000f
955#define regk_iop_sw_cfg_spu1_gioout15 0x0000000f
956#define regk_iop_sw_cfg_spu1_gioout16 0x0000000f
957#define regk_iop_sw_cfg_spu1_gioout17 0x0000000f
958#define regk_iop_sw_cfg_spu1_gioout18 0x0000000f
959#define regk_iop_sw_cfg_spu1_gioout19 0x0000000f
960#define regk_iop_sw_cfg_spu1_gioout2 0x00000003
961#define regk_iop_sw_cfg_spu1_gioout20 0x0000000f
962#define regk_iop_sw_cfg_spu1_gioout21 0x0000000f
963#define regk_iop_sw_cfg_spu1_gioout22 0x0000000f
964#define regk_iop_sw_cfg_spu1_gioout23 0x0000000f
965#define regk_iop_sw_cfg_spu1_gioout24 0x0000000f
966#define regk_iop_sw_cfg_spu1_gioout25 0x0000000f
967#define regk_iop_sw_cfg_spu1_gioout26 0x0000000f
968#define regk_iop_sw_cfg_spu1_gioout27 0x0000000f
969#define regk_iop_sw_cfg_spu1_gioout28 0x0000000f
970#define regk_iop_sw_cfg_spu1_gioout29 0x0000000f
971#define regk_iop_sw_cfg_spu1_gioout3 0x00000003
972#define regk_iop_sw_cfg_spu1_gioout30 0x0000000f
973#define regk_iop_sw_cfg_spu1_gioout31 0x0000000f
974#define regk_iop_sw_cfg_spu1_gioout4 0x00000005
975#define regk_iop_sw_cfg_spu1_gioout5 0x00000005
976#define regk_iop_sw_cfg_spu1_gioout6 0x00000007
977#define regk_iop_sw_cfg_spu1_gioout7 0x00000007
978#define regk_iop_sw_cfg_spu1_gioout8 0x0000000f
979#define regk_iop_sw_cfg_spu1_gioout9 0x0000000f
980#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001
981#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002
982#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000001
983#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002
984#define regk_iop_sw_cfg_strb_timer_grp2_tmr0 0x00000003
985#define regk_iop_sw_cfg_strb_timer_grp2_tmr1 0x00000002
986#define regk_iop_sw_cfg_strb_timer_grp3_tmr0 0x00000003
987#define regk_iop_sw_cfg_strb_timer_grp3_tmr1 0x00000002
988#define regk_iop_sw_cfg_timer_grp0 0x00000000
989#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001
990#define regk_iop_sw_cfg_timer_grp0_strb0 0x0000000a
991#define regk_iop_sw_cfg_timer_grp0_strb1 0x0000000a
992#define regk_iop_sw_cfg_timer_grp0_strb2 0x0000000a
993#define regk_iop_sw_cfg_timer_grp0_strb3 0x0000000a
994#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000004
995#define regk_iop_sw_cfg_timer_grp0_tmr1 0x00000004
996#define regk_iop_sw_cfg_timer_grp1 0x00000000
997#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001
998#define regk_iop_sw_cfg_timer_grp1_strb0 0x0000000b
999#define regk_iop_sw_cfg_timer_grp1_strb1 0x0000000b
1000#define regk_iop_sw_cfg_timer_grp1_strb2 0x0000000b
1001#define regk_iop_sw_cfg_timer_grp1_strb3 0x0000000b
1002#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000005
1003#define regk_iop_sw_cfg_timer_grp1_tmr1 0x00000005
1004#define regk_iop_sw_cfg_timer_grp2 0x00000000
1005#define regk_iop_sw_cfg_timer_grp2_rot 0x00000001
1006#define regk_iop_sw_cfg_timer_grp2_strb0 0x0000000c
1007#define regk_iop_sw_cfg_timer_grp2_strb1 0x0000000c
1008#define regk_iop_sw_cfg_timer_grp2_strb2 0x0000000c
1009#define regk_iop_sw_cfg_timer_grp2_strb3 0x0000000c
1010#define regk_iop_sw_cfg_timer_grp2_tmr0 0x00000006
1011#define regk_iop_sw_cfg_timer_grp2_tmr1 0x00000006
1012#define regk_iop_sw_cfg_timer_grp3 0x00000000
1013#define regk_iop_sw_cfg_timer_grp3_rot 0x00000001
1014#define regk_iop_sw_cfg_timer_grp3_strb0 0x0000000d
1015#define regk_iop_sw_cfg_timer_grp3_strb1 0x0000000d
1016#define regk_iop_sw_cfg_timer_grp3_strb2 0x0000000d
1017#define regk_iop_sw_cfg_timer_grp3_strb3 0x0000000d
1018#define regk_iop_sw_cfg_timer_grp3_tmr0 0x00000007
1019#define regk_iop_sw_cfg_timer_grp3_tmr1 0x00000007
1020#define regk_iop_sw_cfg_trig0_0 0x00000000
1021#define regk_iop_sw_cfg_trig0_1 0x00000000
1022#define regk_iop_sw_cfg_trig0_2 0x00000000
1023#define regk_iop_sw_cfg_trig0_3 0x00000000
1024#define regk_iop_sw_cfg_trig1_0 0x00000000
1025#define regk_iop_sw_cfg_trig1_1 0x00000000
1026#define regk_iop_sw_cfg_trig1_2 0x00000000
1027#define regk_iop_sw_cfg_trig1_3 0x00000000
1028#define regk_iop_sw_cfg_trig2_0 0x00000000
1029#define regk_iop_sw_cfg_trig2_1 0x00000000
1030#define regk_iop_sw_cfg_trig2_2 0x00000000
1031#define regk_iop_sw_cfg_trig2_3 0x00000000
1032#define regk_iop_sw_cfg_trig3_0 0x00000000
1033#define regk_iop_sw_cfg_trig3_1 0x00000000
1034#define regk_iop_sw_cfg_trig3_2 0x00000000
1035#define regk_iop_sw_cfg_trig3_3 0x00000000
1036#define regk_iop_sw_cfg_trig4_0 0x00000001
1037#define regk_iop_sw_cfg_trig4_1 0x00000001
1038#define regk_iop_sw_cfg_trig4_2 0x00000001
1039#define regk_iop_sw_cfg_trig4_3 0x00000001
1040#define regk_iop_sw_cfg_trig5_0 0x00000001
1041#define regk_iop_sw_cfg_trig5_1 0x00000001
1042#define regk_iop_sw_cfg_trig5_2 0x00000001
1043#define regk_iop_sw_cfg_trig5_3 0x00000001
1044#define regk_iop_sw_cfg_trig6_0 0x00000001
1045#define regk_iop_sw_cfg_trig6_1 0x00000001
1046#define regk_iop_sw_cfg_trig6_2 0x00000001
1047#define regk_iop_sw_cfg_trig6_3 0x00000001
1048#define regk_iop_sw_cfg_trig7_0 0x00000001
1049#define regk_iop_sw_cfg_trig7_1 0x00000001
1050#define regk_iop_sw_cfg_trig7_2 0x00000001
1051#define regk_iop_sw_cfg_trig7_3 0x00000001
1052#endif /* __iop_sw_cfg_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
new file mode 100644
index 000000000000..db347bcba025
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
@@ -0,0 +1,1758 @@
1#ifndef __iop_sw_cpu_defs_asm_h
2#define __iop_sw_cpu_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:10:19 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
11 * id: $Id: iop_sw_cpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
57#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0
58#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1
59#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0
60#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1
61#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2
62#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3
63#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3
64#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___lsb 6
65#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___width 1
66#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___bit 6
67#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___lsb 7
68#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___width 1
69#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___bit 7
70#define reg_iop_sw_cpu_rw_mc_ctrl_offset 0
71
72/* Register rw_mc_data, scope iop_sw_cpu, type rw */
73#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0
74#define reg_iop_sw_cpu_rw_mc_data___val___width 32
75#define reg_iop_sw_cpu_rw_mc_data_offset 4
76
77/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
78#define reg_iop_sw_cpu_rw_mc_addr_offset 8
79
80/* Register rs_mc_data, scope iop_sw_cpu, type rs */
81#define reg_iop_sw_cpu_rs_mc_data_offset 12
82
83/* Register r_mc_data, scope iop_sw_cpu, type r */
84#define reg_iop_sw_cpu_r_mc_data_offset 16
85
86/* Register r_mc_stat, scope iop_sw_cpu, type r */
87#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0
88#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1
89#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0
90#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1
91#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1
92#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1
93#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___lsb 2
94#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___width 1
95#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___bit 2
96#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___lsb 3
97#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___width 1
98#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___bit 3
99#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 4
100#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1
101#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 4
102#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 5
103#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1
104#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 5
105#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___lsb 6
106#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___width 1
107#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___bit 6
108#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___lsb 7
109#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___width 1
110#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___bit 7
111#define reg_iop_sw_cpu_r_mc_stat_offset 20
112
113/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */
114#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___lsb 0
115#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___width 8
116#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___lsb 8
117#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___width 8
118#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___lsb 16
119#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___width 8
120#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___lsb 24
121#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___width 8
122#define reg_iop_sw_cpu_rw_bus0_clr_mask_offset 24
123
124/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */
125#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___lsb 0
126#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___width 8
127#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___lsb 8
128#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___width 8
129#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___lsb 16
130#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___width 8
131#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___lsb 24
132#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___width 8
133#define reg_iop_sw_cpu_rw_bus0_set_mask_offset 28
134
135/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */
136#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___lsb 0
137#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___width 1
138#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___bit 0
139#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___lsb 1
140#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___width 1
141#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___bit 1
142#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___lsb 2
143#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___width 1
144#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___bit 2
145#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___lsb 3
146#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___width 1
147#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___bit 3
148#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask_offset 32
149
150/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */
151#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___lsb 0
152#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___width 1
153#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___bit 0
154#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___lsb 1
155#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___width 1
156#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___bit 1
157#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___lsb 2
158#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___width 1
159#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___bit 2
160#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___lsb 3
161#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___width 1
162#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___bit 3
163#define reg_iop_sw_cpu_rw_bus0_oe_set_mask_offset 36
164
165/* Register r_bus0_in, scope iop_sw_cpu, type r */
166#define reg_iop_sw_cpu_r_bus0_in_offset 40
167
168/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */
169#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___lsb 0
170#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___width 8
171#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___lsb 8
172#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___width 8
173#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___lsb 16
174#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___width 8
175#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___lsb 24
176#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___width 8
177#define reg_iop_sw_cpu_rw_bus1_clr_mask_offset 44
178
179/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */
180#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___lsb 0
181#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___width 8
182#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___lsb 8
183#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___width 8
184#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___lsb 16
185#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___width 8
186#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___lsb 24
187#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___width 8
188#define reg_iop_sw_cpu_rw_bus1_set_mask_offset 48
189
190/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */
191#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___lsb 0
192#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___width 1
193#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___bit 0
194#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___lsb 1
195#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___width 1
196#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___bit 1
197#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___lsb 2
198#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___width 1
199#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___bit 2
200#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___lsb 3
201#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___width 1
202#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___bit 3
203#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask_offset 52
204
205/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */
206#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___lsb 0
207#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___width 1
208#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___bit 0
209#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___lsb 1
210#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___width 1
211#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___bit 1
212#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___lsb 2
213#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___width 1
214#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___bit 2
215#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___lsb 3
216#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___width 1
217#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___bit 3
218#define reg_iop_sw_cpu_rw_bus1_oe_set_mask_offset 56
219
220/* Register r_bus1_in, scope iop_sw_cpu, type r */
221#define reg_iop_sw_cpu_r_bus1_in_offset 60
222
223/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
224#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0
225#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32
226#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 64
227
228/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
229#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0
230#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32
231#define reg_iop_sw_cpu_rw_gio_set_mask_offset 68
232
233/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
234#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0
235#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32
236#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 72
237
238/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
239#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0
240#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32
241#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 76
242
243/* Register r_gio_in, scope iop_sw_cpu, type r */
244#define reg_iop_sw_cpu_r_gio_in_offset 80
245
246/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
247#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0
248#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1
249#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0
250#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1
251#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1
252#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1
253#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2
254#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1
255#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2
256#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3
257#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1
258#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3
259#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4
260#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1
261#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4
262#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5
263#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1
264#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5
265#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6
266#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1
267#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6
268#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7
269#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1
270#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7
271#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8
272#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1
273#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8
274#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9
275#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1
276#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9
277#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10
278#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1
279#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10
280#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11
281#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1
282#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11
283#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12
284#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1
285#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12
286#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13
287#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1
288#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13
289#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14
290#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1
291#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14
292#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15
293#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1
294#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15
295#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16
296#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1
297#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16
298#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17
299#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1
300#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17
301#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18
302#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1
303#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18
304#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19
305#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1
306#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19
307#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20
308#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1
309#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20
310#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21
311#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1
312#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21
313#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22
314#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1
315#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22
316#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23
317#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1
318#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23
319#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24
320#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1
321#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24
322#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25
323#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1
324#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25
325#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26
326#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1
327#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26
328#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27
329#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1
330#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27
331#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28
332#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1
333#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28
334#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29
335#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1
336#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29
337#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30
338#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1
339#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30
340#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31
341#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1
342#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31
343#define reg_iop_sw_cpu_rw_intr0_mask_offset 84
344
345/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
346#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0
347#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1
348#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0
349#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1
350#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1
351#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1
352#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2
353#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1
354#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2
355#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3
356#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1
357#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3
358#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4
359#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1
360#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4
361#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5
362#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1
363#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5
364#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6
365#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1
366#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6
367#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7
368#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1
369#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7
370#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8
371#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1
372#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8
373#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9
374#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1
375#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9
376#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10
377#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1
378#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10
379#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11
380#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1
381#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11
382#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12
383#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1
384#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12
385#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13
386#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1
387#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13
388#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14
389#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1
390#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14
391#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15
392#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1
393#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15
394#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16
395#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1
396#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16
397#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17
398#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1
399#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17
400#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18
401#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1
402#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18
403#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19
404#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1
405#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19
406#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20
407#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1
408#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20
409#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21
410#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1
411#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21
412#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22
413#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1
414#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22
415#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23
416#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1
417#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23
418#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24
419#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1
420#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24
421#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25
422#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1
423#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25
424#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26
425#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1
426#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26
427#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27
428#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1
429#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27
430#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28
431#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1
432#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28
433#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29
434#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1
435#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29
436#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30
437#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1
438#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30
439#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31
440#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1
441#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31
442#define reg_iop_sw_cpu_rw_ack_intr0_offset 88
443
444/* Register r_intr0, scope iop_sw_cpu, type r */
445#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0
446#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1
447#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0
448#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1
449#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1
450#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1
451#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2
452#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1
453#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2
454#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3
455#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1
456#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3
457#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4
458#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1
459#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4
460#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5
461#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1
462#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5
463#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6
464#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1
465#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6
466#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7
467#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1
468#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7
469#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8
470#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1
471#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8
472#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9
473#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1
474#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9
475#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10
476#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1
477#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10
478#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11
479#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1
480#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11
481#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12
482#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1
483#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12
484#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13
485#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1
486#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13
487#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14
488#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1
489#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14
490#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15
491#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1
492#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15
493#define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16
494#define reg_iop_sw_cpu_r_intr0___spu0_0___width 1
495#define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16
496#define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17
497#define reg_iop_sw_cpu_r_intr0___spu0_1___width 1
498#define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17
499#define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18
500#define reg_iop_sw_cpu_r_intr0___spu0_2___width 1
501#define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18
502#define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19
503#define reg_iop_sw_cpu_r_intr0___spu0_3___width 1
504#define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19
505#define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20
506#define reg_iop_sw_cpu_r_intr0___spu0_4___width 1
507#define reg_iop_sw_cpu_r_intr0___spu0_4___bit 20
508#define reg_iop_sw_cpu_r_intr0___spu0_5___lsb 21
509#define reg_iop_sw_cpu_r_intr0___spu0_5___width 1
510#define reg_iop_sw_cpu_r_intr0___spu0_5___bit 21
511#define reg_iop_sw_cpu_r_intr0___spu0_6___lsb 22
512#define reg_iop_sw_cpu_r_intr0___spu0_6___width 1
513#define reg_iop_sw_cpu_r_intr0___spu0_6___bit 22
514#define reg_iop_sw_cpu_r_intr0___spu0_7___lsb 23
515#define reg_iop_sw_cpu_r_intr0___spu0_7___width 1
516#define reg_iop_sw_cpu_r_intr0___spu0_7___bit 23
517#define reg_iop_sw_cpu_r_intr0___spu1_8___lsb 24
518#define reg_iop_sw_cpu_r_intr0___spu1_8___width 1
519#define reg_iop_sw_cpu_r_intr0___spu1_8___bit 24
520#define reg_iop_sw_cpu_r_intr0___spu1_9___lsb 25
521#define reg_iop_sw_cpu_r_intr0___spu1_9___width 1
522#define reg_iop_sw_cpu_r_intr0___spu1_9___bit 25
523#define reg_iop_sw_cpu_r_intr0___spu1_10___lsb 26
524#define reg_iop_sw_cpu_r_intr0___spu1_10___width 1
525#define reg_iop_sw_cpu_r_intr0___spu1_10___bit 26
526#define reg_iop_sw_cpu_r_intr0___spu1_11___lsb 27
527#define reg_iop_sw_cpu_r_intr0___spu1_11___width 1
528#define reg_iop_sw_cpu_r_intr0___spu1_11___bit 27
529#define reg_iop_sw_cpu_r_intr0___spu1_12___lsb 28
530#define reg_iop_sw_cpu_r_intr0___spu1_12___width 1
531#define reg_iop_sw_cpu_r_intr0___spu1_12___bit 28
532#define reg_iop_sw_cpu_r_intr0___spu1_13___lsb 29
533#define reg_iop_sw_cpu_r_intr0___spu1_13___width 1
534#define reg_iop_sw_cpu_r_intr0___spu1_13___bit 29
535#define reg_iop_sw_cpu_r_intr0___spu1_14___lsb 30
536#define reg_iop_sw_cpu_r_intr0___spu1_14___width 1
537#define reg_iop_sw_cpu_r_intr0___spu1_14___bit 30
538#define reg_iop_sw_cpu_r_intr0___spu1_15___lsb 31
539#define reg_iop_sw_cpu_r_intr0___spu1_15___width 1
540#define reg_iop_sw_cpu_r_intr0___spu1_15___bit 31
541#define reg_iop_sw_cpu_r_intr0_offset 92
542
543/* Register r_masked_intr0, scope iop_sw_cpu, type r */
544#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0
545#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1
546#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0
547#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1
548#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1
549#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1
550#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2
551#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1
552#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2
553#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3
554#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1
555#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3
556#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4
557#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1
558#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4
559#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5
560#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1
561#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5
562#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6
563#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1
564#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6
565#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7
566#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1
567#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7
568#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8
569#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1
570#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8
571#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9
572#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1
573#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9
574#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10
575#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1
576#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10
577#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11
578#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1
579#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11
580#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12
581#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1
582#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12
583#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13
584#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1
585#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13
586#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14
587#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1
588#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14
589#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15
590#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1
591#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15
592#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___lsb 16
593#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___width 1
594#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___bit 16
595#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___lsb 17
596#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___width 1
597#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___bit 17
598#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___lsb 18
599#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___width 1
600#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___bit 18
601#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___lsb 19
602#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___width 1
603#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___bit 19
604#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___lsb 20
605#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___width 1
606#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___bit 20
607#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___lsb 21
608#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___width 1
609#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___bit 21
610#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___lsb 22
611#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___width 1
612#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___bit 22
613#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___lsb 23
614#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___width 1
615#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___bit 23
616#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___lsb 24
617#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___width 1
618#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___bit 24
619#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___lsb 25
620#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___width 1
621#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___bit 25
622#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___lsb 26
623#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___width 1
624#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___bit 26
625#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___lsb 27
626#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___width 1
627#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___bit 27
628#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___lsb 28
629#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___width 1
630#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___bit 28
631#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___lsb 29
632#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___width 1
633#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___bit 29
634#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___lsb 30
635#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___width 1
636#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___bit 30
637#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___lsb 31
638#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___width 1
639#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___bit 31
640#define reg_iop_sw_cpu_r_masked_intr0_offset 96
641
642/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
643#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0
644#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1
645#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0
646#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1
647#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1
648#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1
649#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2
650#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1
651#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2
652#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3
653#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1
654#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3
655#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4
656#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1
657#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4
658#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5
659#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1
660#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5
661#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6
662#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1
663#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6
664#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7
665#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1
666#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7
667#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8
668#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1
669#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8
670#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9
671#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1
672#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9
673#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10
674#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1
675#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10
676#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11
677#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1
678#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11
679#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12
680#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1
681#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12
682#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13
683#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1
684#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13
685#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14
686#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1
687#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14
688#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15
689#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1
690#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15
691#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___lsb 16
692#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___width 1
693#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___bit 16
694#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___lsb 17
695#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___width 1
696#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___bit 17
697#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___lsb 18
698#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___width 1
699#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___bit 18
700#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___lsb 19
701#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___width 1
702#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___bit 19
703#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___lsb 20
704#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___width 1
705#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___bit 20
706#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___lsb 21
707#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___width 1
708#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___bit 21
709#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___lsb 22
710#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___width 1
711#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___bit 22
712#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___lsb 23
713#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___width 1
714#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___bit 23
715#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___lsb 24
716#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___width 1
717#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___bit 24
718#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___lsb 25
719#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___width 1
720#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___bit 25
721#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___lsb 26
722#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___width 1
723#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___bit 26
724#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___lsb 27
725#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___width 1
726#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___bit 27
727#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___lsb 28
728#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___width 1
729#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___bit 28
730#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___lsb 29
731#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___width 1
732#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___bit 29
733#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___lsb 30
734#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___width 1
735#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___bit 30
736#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___lsb 31
737#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___width 1
738#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___bit 31
739#define reg_iop_sw_cpu_rw_intr1_mask_offset 100
740
741/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
742#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0
743#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1
744#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0
745#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1
746#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1
747#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1
748#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2
749#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1
750#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2
751#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3
752#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1
753#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3
754#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4
755#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1
756#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4
757#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5
758#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1
759#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5
760#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6
761#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1
762#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6
763#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7
764#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1
765#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7
766#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8
767#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1
768#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8
769#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9
770#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1
771#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9
772#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10
773#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1
774#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10
775#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11
776#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1
777#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11
778#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12
779#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1
780#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12
781#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13
782#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1
783#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13
784#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14
785#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1
786#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14
787#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15
788#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1
789#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15
790#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16
791#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1
792#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16
793#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17
794#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1
795#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17
796#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18
797#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1
798#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18
799#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19
800#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1
801#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19
802#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20
803#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1
804#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20
805#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21
806#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1
807#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21
808#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22
809#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1
810#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22
811#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23
812#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1
813#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23
814#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24
815#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1
816#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24
817#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25
818#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1
819#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25
820#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26
821#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1
822#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26
823#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27
824#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1
825#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27
826#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28
827#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1
828#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28
829#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29
830#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1
831#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29
832#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30
833#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1
834#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30
835#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31
836#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1
837#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31
838#define reg_iop_sw_cpu_rw_ack_intr1_offset 104
839
840/* Register r_intr1, scope iop_sw_cpu, type r */
841#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0
842#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1
843#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0
844#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1
845#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1
846#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1
847#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2
848#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1
849#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2
850#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3
851#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1
852#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3
853#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4
854#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1
855#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4
856#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5
857#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1
858#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5
859#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6
860#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1
861#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6
862#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7
863#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1
864#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7
865#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8
866#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1
867#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8
868#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9
869#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1
870#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9
871#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10
872#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1
873#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10
874#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11
875#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1
876#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11
877#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12
878#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1
879#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12
880#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13
881#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1
882#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13
883#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14
884#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1
885#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14
886#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15
887#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1
888#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15
889#define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16
890#define reg_iop_sw_cpu_r_intr1___spu0_8___width 1
891#define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16
892#define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17
893#define reg_iop_sw_cpu_r_intr1___spu0_9___width 1
894#define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17
895#define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18
896#define reg_iop_sw_cpu_r_intr1___spu0_10___width 1
897#define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18
898#define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19
899#define reg_iop_sw_cpu_r_intr1___spu0_11___width 1
900#define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19
901#define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20
902#define reg_iop_sw_cpu_r_intr1___spu0_12___width 1
903#define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20
904#define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21
905#define reg_iop_sw_cpu_r_intr1___spu0_13___width 1
906#define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21
907#define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22
908#define reg_iop_sw_cpu_r_intr1___spu0_14___width 1
909#define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22
910#define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23
911#define reg_iop_sw_cpu_r_intr1___spu0_15___width 1
912#define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23
913#define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24
914#define reg_iop_sw_cpu_r_intr1___spu1_0___width 1
915#define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24
916#define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25
917#define reg_iop_sw_cpu_r_intr1___spu1_1___width 1
918#define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25
919#define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26
920#define reg_iop_sw_cpu_r_intr1___spu1_2___width 1
921#define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26
922#define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27
923#define reg_iop_sw_cpu_r_intr1___spu1_3___width 1
924#define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27
925#define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28
926#define reg_iop_sw_cpu_r_intr1___spu1_4___width 1
927#define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28
928#define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29
929#define reg_iop_sw_cpu_r_intr1___spu1_5___width 1
930#define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29
931#define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30
932#define reg_iop_sw_cpu_r_intr1___spu1_6___width 1
933#define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30
934#define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31
935#define reg_iop_sw_cpu_r_intr1___spu1_7___width 1
936#define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31
937#define reg_iop_sw_cpu_r_intr1_offset 108
938
939/* Register r_masked_intr1, scope iop_sw_cpu, type r */
940#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0
941#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1
942#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0
943#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1
944#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1
945#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1
946#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2
947#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1
948#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2
949#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3
950#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1
951#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3
952#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4
953#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1
954#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4
955#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5
956#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1
957#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5
958#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6
959#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1
960#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6
961#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7
962#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1
963#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7
964#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8
965#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1
966#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8
967#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9
968#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1
969#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9
970#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10
971#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1
972#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10
973#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11
974#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1
975#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11
976#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12
977#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1
978#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12
979#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13
980#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1
981#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13
982#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14
983#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1
984#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14
985#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15
986#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1
987#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15
988#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16
989#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1
990#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16
991#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17
992#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1
993#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17
994#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18
995#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1
996#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18
997#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19
998#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1
999#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19
1000#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20
1001#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1
1002#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20
1003#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21
1004#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1
1005#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21
1006#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22
1007#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1
1008#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22
1009#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23
1010#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1
1011#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23
1012#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24
1013#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1
1014#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24
1015#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25
1016#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1
1017#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25
1018#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26
1019#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1
1020#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26
1021#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27
1022#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1
1023#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27
1024#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28
1025#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1
1026#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28
1027#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29
1028#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1
1029#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29
1030#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30
1031#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1
1032#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30
1033#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31
1034#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1
1035#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31
1036#define reg_iop_sw_cpu_r_masked_intr1_offset 112
1037
1038/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
1039#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0
1040#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1
1041#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0
1042#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1
1043#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1
1044#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1
1045#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2
1046#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1
1047#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2
1048#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3
1049#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1
1050#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3
1051#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4
1052#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1
1053#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4
1054#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5
1055#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1
1056#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5
1057#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6
1058#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1
1059#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6
1060#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7
1061#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1
1062#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7
1063#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8
1064#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1
1065#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8
1066#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9
1067#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1
1068#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9
1069#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10
1070#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1
1071#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10
1072#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11
1073#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1
1074#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11
1075#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12
1076#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1
1077#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12
1078#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13
1079#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1
1080#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13
1081#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14
1082#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1
1083#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14
1084#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15
1085#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1
1086#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15
1087#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16
1088#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1
1089#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16
1090#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17
1091#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1
1092#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17
1093#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18
1094#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1
1095#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18
1096#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19
1097#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1
1098#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19
1099#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20
1100#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1
1101#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20
1102#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21
1103#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1
1104#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21
1105#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22
1106#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1
1107#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22
1108#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23
1109#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1
1110#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23
1111#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24
1112#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1
1113#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24
1114#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25
1115#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1
1116#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25
1117#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26
1118#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1
1119#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26
1120#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27
1121#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1
1122#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27
1123#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28
1124#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1
1125#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28
1126#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29
1127#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1
1128#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29
1129#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30
1130#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1
1131#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30
1132#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31
1133#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1
1134#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31
1135#define reg_iop_sw_cpu_rw_intr2_mask_offset 116
1136
1137/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
1138#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0
1139#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1
1140#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0
1141#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1
1142#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1
1143#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1
1144#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2
1145#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1
1146#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2
1147#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3
1148#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1
1149#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3
1150#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4
1151#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1
1152#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4
1153#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5
1154#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1
1155#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5
1156#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6
1157#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1
1158#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6
1159#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7
1160#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1
1161#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7
1162#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8
1163#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1
1164#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8
1165#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9
1166#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1
1167#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9
1168#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10
1169#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1
1170#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10
1171#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11
1172#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1
1173#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11
1174#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12
1175#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1
1176#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12
1177#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13
1178#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1
1179#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13
1180#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14
1181#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1
1182#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14
1183#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15
1184#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1
1185#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15
1186#define reg_iop_sw_cpu_rw_ack_intr2_offset 120
1187
1188/* Register r_intr2, scope iop_sw_cpu, type r */
1189#define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0
1190#define reg_iop_sw_cpu_r_intr2___mpu_0___width 1
1191#define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0
1192#define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1
1193#define reg_iop_sw_cpu_r_intr2___mpu_1___width 1
1194#define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1
1195#define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2
1196#define reg_iop_sw_cpu_r_intr2___mpu_2___width 1
1197#define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2
1198#define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3
1199#define reg_iop_sw_cpu_r_intr2___mpu_3___width 1
1200#define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3
1201#define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4
1202#define reg_iop_sw_cpu_r_intr2___mpu_4___width 1
1203#define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4
1204#define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5
1205#define reg_iop_sw_cpu_r_intr2___mpu_5___width 1
1206#define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5
1207#define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6
1208#define reg_iop_sw_cpu_r_intr2___mpu_6___width 1
1209#define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6
1210#define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7
1211#define reg_iop_sw_cpu_r_intr2___mpu_7___width 1
1212#define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7
1213#define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8
1214#define reg_iop_sw_cpu_r_intr2___spu0_0___width 1
1215#define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8
1216#define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9
1217#define reg_iop_sw_cpu_r_intr2___spu0_1___width 1
1218#define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9
1219#define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10
1220#define reg_iop_sw_cpu_r_intr2___spu0_2___width 1
1221#define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10
1222#define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11
1223#define reg_iop_sw_cpu_r_intr2___spu0_3___width 1
1224#define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11
1225#define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12
1226#define reg_iop_sw_cpu_r_intr2___spu0_4___width 1
1227#define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12
1228#define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13
1229#define reg_iop_sw_cpu_r_intr2___spu0_5___width 1
1230#define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13
1231#define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14
1232#define reg_iop_sw_cpu_r_intr2___spu0_6___width 1
1233#define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14
1234#define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15
1235#define reg_iop_sw_cpu_r_intr2___spu0_7___width 1
1236#define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15
1237#define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16
1238#define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1
1239#define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16
1240#define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17
1241#define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1
1242#define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17
1243#define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18
1244#define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1
1245#define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18
1246#define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19
1247#define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1
1248#define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19
1249#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20
1250#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1
1251#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20
1252#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21
1253#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1
1254#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21
1255#define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22
1256#define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1
1257#define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22
1258#define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23
1259#define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1
1260#define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23
1261#define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24
1262#define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1
1263#define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24
1264#define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25
1265#define reg_iop_sw_cpu_r_intr2___trigger_grp3___width 1
1266#define reg_iop_sw_cpu_r_intr2___trigger_grp3___bit 25
1267#define reg_iop_sw_cpu_r_intr2___trigger_grp4___lsb 26
1268#define reg_iop_sw_cpu_r_intr2___trigger_grp4___width 1
1269#define reg_iop_sw_cpu_r_intr2___trigger_grp4___bit 26
1270#define reg_iop_sw_cpu_r_intr2___trigger_grp5___lsb 27
1271#define reg_iop_sw_cpu_r_intr2___trigger_grp5___width 1
1272#define reg_iop_sw_cpu_r_intr2___trigger_grp5___bit 27
1273#define reg_iop_sw_cpu_r_intr2___trigger_grp6___lsb 28
1274#define reg_iop_sw_cpu_r_intr2___trigger_grp6___width 1
1275#define reg_iop_sw_cpu_r_intr2___trigger_grp6___bit 28
1276#define reg_iop_sw_cpu_r_intr2___trigger_grp7___lsb 29
1277#define reg_iop_sw_cpu_r_intr2___trigger_grp7___width 1
1278#define reg_iop_sw_cpu_r_intr2___trigger_grp7___bit 29
1279#define reg_iop_sw_cpu_r_intr2___timer_grp0___lsb 30
1280#define reg_iop_sw_cpu_r_intr2___timer_grp0___width 1
1281#define reg_iop_sw_cpu_r_intr2___timer_grp0___bit 30
1282#define reg_iop_sw_cpu_r_intr2___timer_grp1___lsb 31
1283#define reg_iop_sw_cpu_r_intr2___timer_grp1___width 1
1284#define reg_iop_sw_cpu_r_intr2___timer_grp1___bit 31
1285#define reg_iop_sw_cpu_r_intr2_offset 124
1286
1287/* Register r_masked_intr2, scope iop_sw_cpu, type r */
1288#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___lsb 0
1289#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___width 1
1290#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___bit 0
1291#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___lsb 1
1292#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___width 1
1293#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___bit 1
1294#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___lsb 2
1295#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___width 1
1296#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___bit 2
1297#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___lsb 3
1298#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___width 1
1299#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___bit 3
1300#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___lsb 4
1301#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___width 1
1302#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___bit 4
1303#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___lsb 5
1304#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___width 1
1305#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___bit 5
1306#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___lsb 6
1307#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___width 1
1308#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___bit 6
1309#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___lsb 7
1310#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___width 1
1311#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___bit 7
1312#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___lsb 8
1313#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___width 1
1314#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___bit 8
1315#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___lsb 9
1316#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___width 1
1317#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___bit 9
1318#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___lsb 10
1319#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___width 1
1320#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___bit 10
1321#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___lsb 11
1322#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___width 1
1323#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___bit 11
1324#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___lsb 12
1325#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___width 1
1326#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___bit 12
1327#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___lsb 13
1328#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___width 1
1329#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___bit 13
1330#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___lsb 14
1331#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___width 1
1332#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___bit 14
1333#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___lsb 15
1334#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___width 1
1335#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___bit 15
1336#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___lsb 16
1337#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___width 1
1338#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___bit 16
1339#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___lsb 17
1340#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___width 1
1341#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___bit 17
1342#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___lsb 18
1343#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___width 1
1344#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___bit 18
1345#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___lsb 19
1346#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___width 1
1347#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___bit 19
1348#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___lsb 20
1349#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___width 1
1350#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___bit 20
1351#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___lsb 21
1352#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___width 1
1353#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___bit 21
1354#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___lsb 22
1355#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___width 1
1356#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___bit 22
1357#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___lsb 23
1358#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___width 1
1359#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___bit 23
1360#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___lsb 24
1361#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___width 1
1362#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___bit 24
1363#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___lsb 25
1364#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___width 1
1365#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___bit 25
1366#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___lsb 26
1367#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___width 1
1368#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___bit 26
1369#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___lsb 27
1370#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___width 1
1371#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___bit 27
1372#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___lsb 28
1373#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___width 1
1374#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___bit 28
1375#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___lsb 29
1376#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___width 1
1377#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___bit 29
1378#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___lsb 30
1379#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___width 1
1380#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___bit 30
1381#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___lsb 31
1382#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___width 1
1383#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___bit 31
1384#define reg_iop_sw_cpu_r_masked_intr2_offset 128
1385
1386/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */
1387#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___lsb 0
1388#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___width 1
1389#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___bit 0
1390#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___lsb 1
1391#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___width 1
1392#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___bit 1
1393#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___lsb 2
1394#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___width 1
1395#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___bit 2
1396#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___lsb 3
1397#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___width 1
1398#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___bit 3
1399#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___lsb 4
1400#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___width 1
1401#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___bit 4
1402#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___lsb 5
1403#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___width 1
1404#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___bit 5
1405#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___lsb 6
1406#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___width 1
1407#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___bit 6
1408#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___lsb 7
1409#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___width 1
1410#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___bit 7
1411#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___lsb 8
1412#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___width 1
1413#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___bit 8
1414#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___lsb 9
1415#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___width 1
1416#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___bit 9
1417#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___lsb 10
1418#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___width 1
1419#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___bit 10
1420#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___lsb 11
1421#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___width 1
1422#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___bit 11
1423#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___lsb 12
1424#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___width 1
1425#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___bit 12
1426#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___lsb 13
1427#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___width 1
1428#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___bit 13
1429#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___lsb 14
1430#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___width 1
1431#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___bit 14
1432#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___lsb 15
1433#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___width 1
1434#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___bit 15
1435#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___lsb 16
1436#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___width 1
1437#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___bit 16
1438#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___lsb 17
1439#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___width 1
1440#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___bit 17
1441#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___lsb 18
1442#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___width 1
1443#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___bit 18
1444#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___lsb 19
1445#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___width 1
1446#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___bit 19
1447#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___lsb 20
1448#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___width 1
1449#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___bit 20
1450#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___lsb 21
1451#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___width 1
1452#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___bit 21
1453#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___lsb 22
1454#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___width 1
1455#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___bit 22
1456#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___lsb 23
1457#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___width 1
1458#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___bit 23
1459#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___lsb 24
1460#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___width 1
1461#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___bit 24
1462#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___lsb 25
1463#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___width 1
1464#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___bit 25
1465#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___lsb 26
1466#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___width 1
1467#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___bit 26
1468#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___lsb 27
1469#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___width 1
1470#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___bit 27
1471#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___lsb 28
1472#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___width 1
1473#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___bit 28
1474#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___lsb 29
1475#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___width 1
1476#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___bit 29
1477#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___lsb 30
1478#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___width 1
1479#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___bit 30
1480#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___lsb 31
1481#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___width 1
1482#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___bit 31
1483#define reg_iop_sw_cpu_rw_intr3_mask_offset 132
1484
1485/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */
1486#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___lsb 0
1487#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___width 1
1488#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___bit 0
1489#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___lsb 1
1490#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___width 1
1491#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___bit 1
1492#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___lsb 2
1493#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___width 1
1494#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___bit 2
1495#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___lsb 3
1496#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___width 1
1497#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___bit 3
1498#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___lsb 4
1499#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___width 1
1500#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___bit 4
1501#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___lsb 5
1502#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___width 1
1503#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___bit 5
1504#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___lsb 6
1505#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___width 1
1506#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___bit 6
1507#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___lsb 7
1508#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___width 1
1509#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___bit 7
1510#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___lsb 8
1511#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___width 1
1512#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___bit 8
1513#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___lsb 9
1514#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___width 1
1515#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___bit 9
1516#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___lsb 10
1517#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___width 1
1518#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___bit 10
1519#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___lsb 11
1520#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___width 1
1521#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___bit 11
1522#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___lsb 12
1523#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___width 1
1524#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___bit 12
1525#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___lsb 13
1526#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___width 1
1527#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___bit 13
1528#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___lsb 14
1529#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___width 1
1530#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___bit 14
1531#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___lsb 15
1532#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___width 1
1533#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___bit 15
1534#define reg_iop_sw_cpu_rw_ack_intr3_offset 136
1535
1536/* Register r_intr3, scope iop_sw_cpu, type r */
1537#define reg_iop_sw_cpu_r_intr3___mpu_16___lsb 0
1538#define reg_iop_sw_cpu_r_intr3___mpu_16___width 1
1539#define reg_iop_sw_cpu_r_intr3___mpu_16___bit 0
1540#define reg_iop_sw_cpu_r_intr3___mpu_17___lsb 1
1541#define reg_iop_sw_cpu_r_intr3___mpu_17___width 1
1542#define reg_iop_sw_cpu_r_intr3___mpu_17___bit 1
1543#define reg_iop_sw_cpu_r_intr3___mpu_18___lsb 2
1544#define reg_iop_sw_cpu_r_intr3___mpu_18___width 1
1545#define reg_iop_sw_cpu_r_intr3___mpu_18___bit 2
1546#define reg_iop_sw_cpu_r_intr3___mpu_19___lsb 3
1547#define reg_iop_sw_cpu_r_intr3___mpu_19___width 1
1548#define reg_iop_sw_cpu_r_intr3___mpu_19___bit 3
1549#define reg_iop_sw_cpu_r_intr3___mpu_20___lsb 4
1550#define reg_iop_sw_cpu_r_intr3___mpu_20___width 1
1551#define reg_iop_sw_cpu_r_intr3___mpu_20___bit 4
1552#define reg_iop_sw_cpu_r_intr3___mpu_21___lsb 5
1553#define reg_iop_sw_cpu_r_intr3___mpu_21___width 1
1554#define reg_iop_sw_cpu_r_intr3___mpu_21___bit 5
1555#define reg_iop_sw_cpu_r_intr3___mpu_22___lsb 6
1556#define reg_iop_sw_cpu_r_intr3___mpu_22___width 1
1557#define reg_iop_sw_cpu_r_intr3___mpu_22___bit 6
1558#define reg_iop_sw_cpu_r_intr3___mpu_23___lsb 7
1559#define reg_iop_sw_cpu_r_intr3___mpu_23___width 1
1560#define reg_iop_sw_cpu_r_intr3___mpu_23___bit 7
1561#define reg_iop_sw_cpu_r_intr3___spu1_0___lsb 8
1562#define reg_iop_sw_cpu_r_intr3___spu1_0___width 1
1563#define reg_iop_sw_cpu_r_intr3___spu1_0___bit 8
1564#define reg_iop_sw_cpu_r_intr3___spu1_1___lsb 9
1565#define reg_iop_sw_cpu_r_intr3___spu1_1___width 1
1566#define reg_iop_sw_cpu_r_intr3___spu1_1___bit 9
1567#define reg_iop_sw_cpu_r_intr3___spu1_2___lsb 10
1568#define reg_iop_sw_cpu_r_intr3___spu1_2___width 1
1569#define reg_iop_sw_cpu_r_intr3___spu1_2___bit 10
1570#define reg_iop_sw_cpu_r_intr3___spu1_3___lsb 11
1571#define reg_iop_sw_cpu_r_intr3___spu1_3___width 1
1572#define reg_iop_sw_cpu_r_intr3___spu1_3___bit 11
1573#define reg_iop_sw_cpu_r_intr3___spu1_4___lsb 12
1574#define reg_iop_sw_cpu_r_intr3___spu1_4___width 1
1575#define reg_iop_sw_cpu_r_intr3___spu1_4___bit 12
1576#define reg_iop_sw_cpu_r_intr3___spu1_5___lsb 13
1577#define reg_iop_sw_cpu_r_intr3___spu1_5___width 1
1578#define reg_iop_sw_cpu_r_intr3___spu1_5___bit 13
1579#define reg_iop_sw_cpu_r_intr3___spu1_6___lsb 14
1580#define reg_iop_sw_cpu_r_intr3___spu1_6___width 1
1581#define reg_iop_sw_cpu_r_intr3___spu1_6___bit 14
1582#define reg_iop_sw_cpu_r_intr3___spu1_7___lsb 15
1583#define reg_iop_sw_cpu_r_intr3___spu1_7___width 1
1584#define reg_iop_sw_cpu_r_intr3___spu1_7___bit 15
1585#define reg_iop_sw_cpu_r_intr3___dmc_in1___lsb 16
1586#define reg_iop_sw_cpu_r_intr3___dmc_in1___width 1
1587#define reg_iop_sw_cpu_r_intr3___dmc_in1___bit 16
1588#define reg_iop_sw_cpu_r_intr3___dmc_out1___lsb 17
1589#define reg_iop_sw_cpu_r_intr3___dmc_out1___width 1
1590#define reg_iop_sw_cpu_r_intr3___dmc_out1___bit 17
1591#define reg_iop_sw_cpu_r_intr3___fifo_in1___lsb 18
1592#define reg_iop_sw_cpu_r_intr3___fifo_in1___width 1
1593#define reg_iop_sw_cpu_r_intr3___fifo_in1___bit 18
1594#define reg_iop_sw_cpu_r_intr3___fifo_out1___lsb 19
1595#define reg_iop_sw_cpu_r_intr3___fifo_out1___width 1
1596#define reg_iop_sw_cpu_r_intr3___fifo_out1___bit 19
1597#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___lsb 20
1598#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___width 1
1599#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___bit 20
1600#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___lsb 21
1601#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___width 1
1602#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___bit 21
1603#define reg_iop_sw_cpu_r_intr3___trigger_grp0___lsb 22
1604#define reg_iop_sw_cpu_r_intr3___trigger_grp0___width 1
1605#define reg_iop_sw_cpu_r_intr3___trigger_grp0___bit 22
1606#define reg_iop_sw_cpu_r_intr3___trigger_grp1___lsb 23
1607#define reg_iop_sw_cpu_r_intr3___trigger_grp1___width 1
1608#define reg_iop_sw_cpu_r_intr3___trigger_grp1___bit 23
1609#define reg_iop_sw_cpu_r_intr3___trigger_grp2___lsb 24
1610#define reg_iop_sw_cpu_r_intr3___trigger_grp2___width 1
1611#define reg_iop_sw_cpu_r_intr3___trigger_grp2___bit 24
1612#define reg_iop_sw_cpu_r_intr3___trigger_grp3___lsb 25
1613#define reg_iop_sw_cpu_r_intr3___trigger_grp3___width 1
1614#define reg_iop_sw_cpu_r_intr3___trigger_grp3___bit 25
1615#define reg_iop_sw_cpu_r_intr3___trigger_grp4___lsb 26
1616#define reg_iop_sw_cpu_r_intr3___trigger_grp4___width 1
1617#define reg_iop_sw_cpu_r_intr3___trigger_grp4___bit 26
1618#define reg_iop_sw_cpu_r_intr3___trigger_grp5___lsb 27
1619#define reg_iop_sw_cpu_r_intr3___trigger_grp5___width 1
1620#define reg_iop_sw_cpu_r_intr3___trigger_grp5___bit 27
1621#define reg_iop_sw_cpu_r_intr3___trigger_grp6___lsb 28
1622#define reg_iop_sw_cpu_r_intr3___trigger_grp6___width 1
1623#define reg_iop_sw_cpu_r_intr3___trigger_grp6___bit 28
1624#define reg_iop_sw_cpu_r_intr3___trigger_grp7___lsb 29
1625#define reg_iop_sw_cpu_r_intr3___trigger_grp7___width 1
1626#define reg_iop_sw_cpu_r_intr3___trigger_grp7___bit 29
1627#define reg_iop_sw_cpu_r_intr3___timer_grp2___lsb 30
1628#define reg_iop_sw_cpu_r_intr3___timer_grp2___width 1
1629#define reg_iop_sw_cpu_r_intr3___timer_grp2___bit 30
1630#define reg_iop_sw_cpu_r_intr3___timer_grp3___lsb 31
1631#define reg_iop_sw_cpu_r_intr3___timer_grp3___width 1
1632#define reg_iop_sw_cpu_r_intr3___timer_grp3___bit 31
1633#define reg_iop_sw_cpu_r_intr3_offset 140
1634
1635/* Register r_masked_intr3, scope iop_sw_cpu, type r */
1636#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___lsb 0
1637#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___width 1
1638#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___bit 0
1639#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___lsb 1
1640#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___width 1
1641#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___bit 1
1642#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___lsb 2
1643#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___width 1
1644#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___bit 2
1645#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___lsb 3
1646#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___width 1
1647#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___bit 3
1648#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___lsb 4
1649#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___width 1
1650#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___bit 4
1651#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___lsb 5
1652#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___width 1
1653#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___bit 5
1654#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___lsb 6
1655#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___width 1
1656#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___bit 6
1657#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___lsb 7
1658#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___width 1
1659#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___bit 7
1660#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___lsb 8
1661#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___width 1
1662#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___bit 8
1663#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___lsb 9
1664#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___width 1
1665#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___bit 9
1666#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___lsb 10
1667#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___width 1
1668#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___bit 10
1669#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___lsb 11
1670#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___width 1
1671#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___bit 11
1672#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___lsb 12
1673#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___width 1
1674#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___bit 12
1675#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___lsb 13
1676#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___width 1
1677#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___bit 13
1678#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___lsb 14
1679#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___width 1
1680#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___bit 14
1681#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___lsb 15
1682#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___width 1
1683#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___bit 15
1684#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___lsb 16
1685#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___width 1
1686#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___bit 16
1687#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___lsb 17
1688#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___width 1
1689#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___bit 17
1690#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___lsb 18
1691#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___width 1
1692#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___bit 18
1693#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___lsb 19
1694#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___width 1
1695#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___bit 19
1696#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___lsb 20
1697#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___width 1
1698#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___bit 20
1699#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___lsb 21
1700#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___width 1
1701#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___bit 21
1702#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___lsb 22
1703#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___width 1
1704#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___bit 22
1705#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___lsb 23
1706#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___width 1
1707#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___bit 23
1708#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___lsb 24
1709#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___width 1
1710#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___bit 24
1711#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___lsb 25
1712#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___width 1
1713#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___bit 25
1714#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___lsb 26
1715#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___width 1
1716#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___bit 26
1717#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___lsb 27
1718#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___width 1
1719#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___bit 27
1720#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___lsb 28
1721#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___width 1
1722#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___bit 28
1723#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___lsb 29
1724#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___width 1
1725#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___bit 29
1726#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___lsb 30
1727#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___width 1
1728#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___bit 30
1729#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___lsb 31
1730#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___width 1
1731#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___bit 31
1732#define reg_iop_sw_cpu_r_masked_intr3_offset 144
1733
1734
1735/* Constants */
1736#define regk_iop_sw_cpu_copy 0x00000000
1737#define regk_iop_sw_cpu_no 0x00000000
1738#define regk_iop_sw_cpu_rd 0x00000002
1739#define regk_iop_sw_cpu_reg_copy 0x00000001
1740#define regk_iop_sw_cpu_rw_bus0_clr_mask_default 0x00000000
1741#define regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default 0x00000000
1742#define regk_iop_sw_cpu_rw_bus0_oe_set_mask_default 0x00000000
1743#define regk_iop_sw_cpu_rw_bus0_set_mask_default 0x00000000
1744#define regk_iop_sw_cpu_rw_bus1_clr_mask_default 0x00000000
1745#define regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default 0x00000000
1746#define regk_iop_sw_cpu_rw_bus1_oe_set_mask_default 0x00000000
1747#define regk_iop_sw_cpu_rw_bus1_set_mask_default 0x00000000
1748#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000
1749#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000
1750#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000
1751#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000
1752#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000
1753#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000
1754#define regk_iop_sw_cpu_rw_intr2_mask_default 0x00000000
1755#define regk_iop_sw_cpu_rw_intr3_mask_default 0x00000000
1756#define regk_iop_sw_cpu_wr 0x00000003
1757#define regk_iop_sw_cpu_yes 0x00000001
1758#endif /* __iop_sw_cpu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
new file mode 100644
index 000000000000..ee7dc0435b59
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
@@ -0,0 +1,1776 @@
1#ifndef __iop_sw_mpu_defs_asm_h
2#define __iop_sw_mpu_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:10:19 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_mpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
11 * id: $Id: iop_sw_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
57#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0
58#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2
59#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0
60
61/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
62#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0
63#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1
64#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0
65#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1
66#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2
67#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3
68#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3
69#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___lsb 6
70#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___width 1
71#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___bit 6
72#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7
73#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___width 1
74#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7
75#define reg_iop_sw_mpu_rw_mc_ctrl_offset 4
76
77/* Register rw_mc_data, scope iop_sw_mpu, type rw */
78#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0
79#define reg_iop_sw_mpu_rw_mc_data___val___width 32
80#define reg_iop_sw_mpu_rw_mc_data_offset 8
81
82/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
83#define reg_iop_sw_mpu_rw_mc_addr_offset 12
84
85/* Register rs_mc_data, scope iop_sw_mpu, type rs */
86#define reg_iop_sw_mpu_rs_mc_data_offset 16
87
88/* Register r_mc_data, scope iop_sw_mpu, type r */
89#define reg_iop_sw_mpu_r_mc_data_offset 20
90
91/* Register r_mc_stat, scope iop_sw_mpu, type r */
92#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0
93#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1
94#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0
95#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1
96#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1
97#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1
98#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___lsb 2
99#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___width 1
100#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___bit 2
101#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___lsb 3
102#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___width 1
103#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___bit 3
104#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 4
105#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1
106#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 4
107#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 5
108#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1
109#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 5
110#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___lsb 6
111#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___width 1
112#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___bit 6
113#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7
114#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___width 1
115#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7
116#define reg_iop_sw_mpu_r_mc_stat_offset 24
117
118/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
119#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___lsb 0
120#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___width 8
121#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___lsb 8
122#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___width 8
123#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___lsb 16
124#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___width 8
125#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___lsb 24
126#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___width 8
127#define reg_iop_sw_mpu_rw_bus0_clr_mask_offset 28
128
129/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
130#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___lsb 0
131#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___width 8
132#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___lsb 8
133#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___width 8
134#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___lsb 16
135#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___width 8
136#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___lsb 24
137#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___width 8
138#define reg_iop_sw_mpu_rw_bus0_set_mask_offset 32
139
140/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
141#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___lsb 0
142#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___width 1
143#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___bit 0
144#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___lsb 1
145#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___width 1
146#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___bit 1
147#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___lsb 2
148#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___width 1
149#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___bit 2
150#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___lsb 3
151#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___width 1
152#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___bit 3
153#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask_offset 36
154
155/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
156#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___lsb 0
157#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___width 1
158#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___bit 0
159#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___lsb 1
160#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___width 1
161#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___bit 1
162#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___lsb 2
163#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___width 1
164#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___bit 2
165#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___lsb 3
166#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___width 1
167#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___bit 3
168#define reg_iop_sw_mpu_rw_bus0_oe_set_mask_offset 40
169
170/* Register r_bus0_in, scope iop_sw_mpu, type r */
171#define reg_iop_sw_mpu_r_bus0_in_offset 44
172
173/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
174#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___lsb 0
175#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___width 8
176#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___lsb 8
177#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___width 8
178#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___lsb 16
179#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___width 8
180#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___lsb 24
181#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___width 8
182#define reg_iop_sw_mpu_rw_bus1_clr_mask_offset 48
183
184/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
185#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___lsb 0
186#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___width 8
187#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___lsb 8
188#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___width 8
189#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___lsb 16
190#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___width 8
191#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___lsb 24
192#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___width 8
193#define reg_iop_sw_mpu_rw_bus1_set_mask_offset 52
194
195/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
196#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___lsb 0
197#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___width 1
198#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___bit 0
199#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___lsb 1
200#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___width 1
201#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___bit 1
202#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___lsb 2
203#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___width 1
204#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___bit 2
205#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___lsb 3
206#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___width 1
207#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___bit 3
208#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask_offset 56
209
210/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
211#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___lsb 0
212#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___width 1
213#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___bit 0
214#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___lsb 1
215#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___width 1
216#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___bit 1
217#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___lsb 2
218#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___width 1
219#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___bit 2
220#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___lsb 3
221#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___width 1
222#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___bit 3
223#define reg_iop_sw_mpu_rw_bus1_oe_set_mask_offset 60
224
225/* Register r_bus1_in, scope iop_sw_mpu, type r */
226#define reg_iop_sw_mpu_r_bus1_in_offset 64
227
228/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
229#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0
230#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32
231#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 68
232
233/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
234#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0
235#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32
236#define reg_iop_sw_mpu_rw_gio_set_mask_offset 72
237
238/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
239#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0
240#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32
241#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 76
242
243/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
244#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0
245#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32
246#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 80
247
248/* Register r_gio_in, scope iop_sw_mpu, type r */
249#define reg_iop_sw_mpu_r_gio_in_offset 84
250
251/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
252#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0
253#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1
254#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0
255#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1
256#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1
257#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1
258#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2
259#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1
260#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2
261#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3
262#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1
263#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3
264#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4
265#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1
266#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4
267#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5
268#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1
269#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5
270#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6
271#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1
272#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6
273#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7
274#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1
275#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7
276#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8
277#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1
278#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8
279#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9
280#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1
281#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9
282#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10
283#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1
284#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10
285#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11
286#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1
287#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11
288#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12
289#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1
290#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12
291#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13
292#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1
293#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13
294#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14
295#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1
296#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14
297#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15
298#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1
299#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15
300#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16
301#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1
302#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16
303#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17
304#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1
305#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17
306#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18
307#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1
308#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18
309#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19
310#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1
311#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19
312#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20
313#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1
314#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20
315#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21
316#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1
317#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21
318#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22
319#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1
320#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22
321#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23
322#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1
323#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23
324#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24
325#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1
326#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24
327#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25
328#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1
329#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25
330#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26
331#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1
332#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26
333#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27
334#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1
335#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27
336#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28
337#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1
338#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28
339#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29
340#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1
341#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29
342#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30
343#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1
344#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30
345#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31
346#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1
347#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31
348#define reg_iop_sw_mpu_rw_cpu_intr_offset 88
349
350/* Register r_cpu_intr, scope iop_sw_mpu, type r */
351#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0
352#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1
353#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0
354#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1
355#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1
356#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1
357#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2
358#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1
359#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2
360#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3
361#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1
362#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3
363#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4
364#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1
365#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4
366#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5
367#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1
368#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5
369#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6
370#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1
371#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6
372#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7
373#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1
374#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7
375#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8
376#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1
377#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8
378#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9
379#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1
380#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9
381#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10
382#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1
383#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10
384#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11
385#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1
386#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11
387#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12
388#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1
389#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12
390#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13
391#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1
392#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13
393#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14
394#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1
395#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14
396#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15
397#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1
398#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15
399#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16
400#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1
401#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16
402#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17
403#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1
404#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17
405#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18
406#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1
407#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18
408#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19
409#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1
410#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19
411#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20
412#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1
413#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20
414#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21
415#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1
416#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21
417#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22
418#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1
419#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22
420#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23
421#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1
422#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23
423#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24
424#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1
425#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24
426#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25
427#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1
428#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25
429#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26
430#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1
431#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26
432#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27
433#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1
434#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27
435#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28
436#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1
437#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28
438#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29
439#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1
440#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29
441#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30
442#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1
443#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30
444#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31
445#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1
446#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31
447#define reg_iop_sw_mpu_r_cpu_intr_offset 92
448
449/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
450#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___lsb 0
451#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___width 1
452#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___bit 0
453#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___lsb 1
454#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___width 1
455#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___bit 1
456#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 2
457#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1
458#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 2
459#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___lsb 3
460#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___width 1
461#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___bit 3
462#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 4
463#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1
464#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 4
465#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___lsb 5
466#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___width 1
467#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___bit 5
468#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___lsb 6
469#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___width 1
470#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___bit 6
471#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7
472#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___width 1
473#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7
474#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___lsb 8
475#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___width 1
476#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___bit 8
477#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___lsb 9
478#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___width 1
479#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___bit 9
480#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 10
481#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1
482#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 10
483#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___lsb 11
484#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___width 1
485#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___bit 11
486#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 12
487#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1
488#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 12
489#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___lsb 13
490#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___width 1
491#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___bit 13
492#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___lsb 14
493#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___width 1
494#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___bit 14
495#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___lsb 15
496#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___width 1
497#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___bit 15
498#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___lsb 16
499#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___width 1
500#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___bit 16
501#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___lsb 17
502#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___width 1
503#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___bit 17
504#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 18
505#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1
506#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 18
507#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___lsb 19
508#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___width 1
509#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___bit 19
510#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___lsb 20
511#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___width 1
512#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___bit 20
513#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___lsb 21
514#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___width 1
515#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___bit 21
516#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___lsb 22
517#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___width 1
518#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___bit 22
519#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___lsb 23
520#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___width 1
521#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___bit 23
522#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___lsb 24
523#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___width 1
524#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___bit 24
525#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___lsb 25
526#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___width 1
527#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___bit 25
528#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 26
529#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1
530#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 26
531#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___lsb 27
532#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___width 1
533#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___bit 27
534#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___lsb 28
535#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___width 1
536#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___bit 28
537#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___lsb 29
538#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___width 1
539#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___bit 29
540#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___lsb 30
541#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___width 1
542#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___bit 30
543#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___lsb 31
544#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___width 1
545#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___bit 31
546#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 96
547
548/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
549#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___lsb 0
550#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___width 1
551#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___bit 0
552#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___lsb 1
553#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___width 1
554#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___bit 1
555#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___lsb 8
556#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___width 1
557#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___bit 8
558#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___lsb 9
559#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___width 1
560#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___bit 9
561#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___lsb 16
562#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___width 1
563#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___bit 16
564#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___lsb 17
565#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___width 1
566#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___bit 17
567#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___lsb 24
568#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___width 1
569#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___bit 24
570#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___lsb 25
571#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___width 1
572#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___bit 25
573#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 100
574
575/* Register r_intr_grp0, scope iop_sw_mpu, type r */
576#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___lsb 0
577#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___width 1
578#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___bit 0
579#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___lsb 1
580#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___width 1
581#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___bit 1
582#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 2
583#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1
584#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 2
585#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___lsb 3
586#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___width 1
587#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___bit 3
588#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 4
589#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1
590#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 4
591#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___lsb 5
592#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___width 1
593#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___bit 5
594#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___lsb 6
595#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___width 1
596#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___bit 6
597#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___lsb 7
598#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___width 1
599#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___bit 7
600#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___lsb 8
601#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___width 1
602#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___bit 8
603#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___lsb 9
604#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___width 1
605#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___bit 9
606#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 10
607#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1
608#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 10
609#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___lsb 11
610#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___width 1
611#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___bit 11
612#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 12
613#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1
614#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 12
615#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___lsb 13
616#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___width 1
617#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___bit 13
618#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___lsb 14
619#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___width 1
620#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___bit 14
621#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___lsb 15
622#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___width 1
623#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___bit 15
624#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___lsb 16
625#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___width 1
626#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___bit 16
627#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___lsb 17
628#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___width 1
629#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___bit 17
630#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 18
631#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1
632#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 18
633#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___lsb 19
634#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___width 1
635#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___bit 19
636#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___lsb 20
637#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___width 1
638#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___bit 20
639#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___lsb 21
640#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___width 1
641#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___bit 21
642#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___lsb 22
643#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___width 1
644#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___bit 22
645#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___lsb 23
646#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___width 1
647#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___bit 23
648#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___lsb 24
649#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___width 1
650#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___bit 24
651#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___lsb 25
652#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___width 1
653#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___bit 25
654#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 26
655#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1
656#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 26
657#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___lsb 27
658#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___width 1
659#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___bit 27
660#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___lsb 28
661#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___width 1
662#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___bit 28
663#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___lsb 29
664#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___width 1
665#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___bit 29
666#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___lsb 30
667#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___width 1
668#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___bit 30
669#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___lsb 31
670#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___width 1
671#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___bit 31
672#define reg_iop_sw_mpu_r_intr_grp0_offset 104
673
674/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
675#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___lsb 0
676#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___width 1
677#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___bit 0
678#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___lsb 1
679#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___width 1
680#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___bit 1
681#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 2
682#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1
683#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 2
684#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___lsb 3
685#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___width 1
686#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___bit 3
687#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 4
688#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1
689#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 4
690#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___lsb 5
691#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___width 1
692#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___bit 5
693#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___lsb 6
694#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___width 1
695#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___bit 6
696#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___lsb 7
697#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___width 1
698#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___bit 7
699#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___lsb 8
700#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1
701#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8
702#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9
703#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1
704#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9
705#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10
706#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1
707#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10
708#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11
709#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1
710#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11
711#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12
712#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1
713#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12
714#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13
715#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1
716#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13
717#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14
718#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1
719#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14
720#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15
721#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1
722#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15
723#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16
724#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1
725#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16
726#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17
727#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1
728#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17
729#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18
730#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1
731#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18
732#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19
733#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1
734#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19
735#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20
736#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1
737#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20
738#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21
739#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1
740#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21
741#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22
742#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1
743#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22
744#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23
745#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1
746#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23
747#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24
748#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1
749#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24
750#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25
751#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1
752#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25
753#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26
754#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1
755#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26
756#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27
757#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1
758#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27
759#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28
760#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1
761#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28
762#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29
763#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1
764#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29
765#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30
766#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1
767#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30
768#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31
769#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1
770#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31
771#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108
772
773/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
774#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0
775#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1
776#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0
777#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1
778#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1
779#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1
780#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2
781#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1
782#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2
783#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3
784#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1
785#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3
786#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4
787#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1
788#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4
789#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5
790#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1
791#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5
792#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6
793#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1
794#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6
795#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7
796#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1
797#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7
798#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8
799#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1
800#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8
801#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9
802#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1
803#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9
804#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10
805#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1
806#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10
807#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11
808#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1
809#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11
810#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12
811#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1
812#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12
813#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13
814#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1
815#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13
816#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14
817#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1
818#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14
819#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15
820#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1
821#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15
822#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16
823#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1
824#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16
825#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17
826#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1
827#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17
828#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18
829#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1
830#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18
831#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19
832#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1
833#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19
834#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20
835#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1
836#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20
837#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21
838#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1
839#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21
840#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22
841#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1
842#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22
843#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23
844#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1
845#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23
846#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24
847#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1
848#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24
849#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25
850#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1
851#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25
852#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26
853#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1
854#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26
855#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27
856#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1
857#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27
858#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28
859#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1
860#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28
861#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29
862#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1
863#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29
864#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30
865#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1
866#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30
867#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31
868#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1
869#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31
870#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112
871
872/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
873#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0
874#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1
875#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0
876#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1
877#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1
878#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1
879#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8
880#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1
881#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8
882#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9
883#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1
884#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9
885#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16
886#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1
887#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16
888#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17
889#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1
890#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17
891#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24
892#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1
893#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24
894#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25
895#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1
896#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25
897#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116
898
899/* Register r_intr_grp1, scope iop_sw_mpu, type r */
900#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0
901#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1
902#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0
903#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1
904#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1
905#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1
906#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2
907#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1
908#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2
909#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3
910#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1
911#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3
912#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4
913#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1
914#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4
915#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5
916#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1
917#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5
918#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6
919#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1
920#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6
921#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7
922#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1
923#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7
924#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8
925#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1
926#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8
927#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9
928#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1
929#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9
930#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10
931#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1
932#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10
933#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 11
934#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1
935#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 11
936#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 12
937#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1
938#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 12
939#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___lsb 13
940#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___width 1
941#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___bit 13
942#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___lsb 14
943#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___width 1
944#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___bit 14
945#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___lsb 15
946#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___width 1
947#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___bit 15
948#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___lsb 16
949#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___width 1
950#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___bit 16
951#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___lsb 17
952#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___width 1
953#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___bit 17
954#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___lsb 18
955#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___width 1
956#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___bit 18
957#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 19
958#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1
959#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 19
960#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___lsb 20
961#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___width 1
962#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___bit 20
963#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___lsb 21
964#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___width 1
965#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___bit 21
966#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___lsb 22
967#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___width 1
968#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___bit 22
969#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___lsb 23
970#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___width 1
971#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___bit 23
972#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___lsb 24
973#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___width 1
974#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___bit 24
975#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___lsb 25
976#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___width 1
977#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___bit 25
978#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___lsb 26
979#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___width 1
980#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___bit 26
981#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 27
982#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1
983#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 27
984#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___lsb 28
985#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___width 1
986#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___bit 28
987#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___lsb 29
988#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___width 1
989#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___bit 29
990#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___lsb 30
991#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___width 1
992#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___bit 30
993#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___lsb 31
994#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___width 1
995#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___bit 31
996#define reg_iop_sw_mpu_r_intr_grp1_offset 120
997
998/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
999#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___lsb 0
1000#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___width 1
1001#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___bit 0
1002#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___lsb 1
1003#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___width 1
1004#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___bit 1
1005#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___lsb 2
1006#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___width 1
1007#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___bit 2
1008#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 3
1009#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1
1010#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 3
1011#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 4
1012#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1
1013#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 4
1014#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___lsb 5
1015#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___width 1
1016#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___bit 5
1017#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___lsb 6
1018#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___width 1
1019#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___bit 6
1020#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___lsb 7
1021#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___width 1
1022#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___bit 7
1023#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___lsb 8
1024#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___width 1
1025#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___bit 8
1026#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___lsb 9
1027#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___width 1
1028#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___bit 9
1029#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___lsb 10
1030#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___width 1
1031#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___bit 10
1032#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 11
1033#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1
1034#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 11
1035#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 12
1036#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1
1037#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 12
1038#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___lsb 13
1039#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___width 1
1040#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___bit 13
1041#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___lsb 14
1042#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___width 1
1043#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___bit 14
1044#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___lsb 15
1045#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___width 1
1046#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___bit 15
1047#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___lsb 16
1048#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___width 1
1049#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___bit 16
1050#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___lsb 17
1051#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___width 1
1052#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___bit 17
1053#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___lsb 18
1054#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___width 1
1055#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___bit 18
1056#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 19
1057#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1
1058#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 19
1059#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___lsb 20
1060#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___width 1
1061#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___bit 20
1062#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___lsb 21
1063#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___width 1
1064#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___bit 21
1065#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___lsb 22
1066#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___width 1
1067#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___bit 22
1068#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___lsb 23
1069#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___width 1
1070#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___bit 23
1071#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___lsb 24
1072#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___width 1
1073#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___bit 24
1074#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___lsb 25
1075#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___width 1
1076#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___bit 25
1077#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___lsb 26
1078#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___width 1
1079#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___bit 26
1080#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 27
1081#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1
1082#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 27
1083#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___lsb 28
1084#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___width 1
1085#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___bit 28
1086#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___lsb 29
1087#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___width 1
1088#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___bit 29
1089#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___lsb 30
1090#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___width 1
1091#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___bit 30
1092#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___lsb 31
1093#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___width 1
1094#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___bit 31
1095#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 124
1096
1097/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
1098#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___lsb 0
1099#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___width 1
1100#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___bit 0
1101#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___lsb 1
1102#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___width 1
1103#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___bit 1
1104#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 2
1105#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1
1106#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 2
1107#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___lsb 3
1108#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___width 1
1109#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___bit 3
1110#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 4
1111#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1
1112#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 4
1113#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___lsb 5
1114#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___width 1
1115#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___bit 5
1116#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___lsb 6
1117#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___width 1
1118#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___bit 6
1119#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___lsb 7
1120#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___width 1
1121#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___bit 7
1122#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___lsb 8
1123#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___width 1
1124#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___bit 8
1125#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___lsb 9
1126#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___width 1
1127#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___bit 9
1128#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 10
1129#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1
1130#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 10
1131#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___lsb 11
1132#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___width 1
1133#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___bit 11
1134#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 12
1135#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1
1136#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 12
1137#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___lsb 13
1138#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___width 1
1139#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___bit 13
1140#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___lsb 14
1141#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___width 1
1142#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___bit 14
1143#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___lsb 15
1144#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___width 1
1145#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___bit 15
1146#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___lsb 16
1147#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___width 1
1148#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___bit 16
1149#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___lsb 17
1150#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___width 1
1151#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___bit 17
1152#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 18
1153#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1
1154#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 18
1155#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___lsb 19
1156#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___width 1
1157#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___bit 19
1158#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___lsb 20
1159#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___width 1
1160#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___bit 20
1161#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___lsb 21
1162#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___width 1
1163#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___bit 21
1164#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___lsb 22
1165#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___width 1
1166#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___bit 22
1167#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___lsb 23
1168#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___width 1
1169#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___bit 23
1170#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___lsb 24
1171#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___width 1
1172#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___bit 24
1173#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___lsb 25
1174#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___width 1
1175#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___bit 25
1176#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 26
1177#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1
1178#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 26
1179#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___lsb 27
1180#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___width 1
1181#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___bit 27
1182#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___lsb 28
1183#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___width 1
1184#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___bit 28
1185#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___lsb 29
1186#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___width 1
1187#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___bit 29
1188#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___lsb 30
1189#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___width 1
1190#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___bit 30
1191#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___lsb 31
1192#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___width 1
1193#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___bit 31
1194#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 128
1195
1196/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
1197#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___lsb 0
1198#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___width 1
1199#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___bit 0
1200#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___lsb 1
1201#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___width 1
1202#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___bit 1
1203#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___lsb 8
1204#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___width 1
1205#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___bit 8
1206#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___lsb 9
1207#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___width 1
1208#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___bit 9
1209#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___lsb 16
1210#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___width 1
1211#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___bit 16
1212#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___lsb 17
1213#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___width 1
1214#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___bit 17
1215#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___lsb 24
1216#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___width 1
1217#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___bit 24
1218#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___lsb 25
1219#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___width 1
1220#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___bit 25
1221#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 132
1222
1223/* Register r_intr_grp2, scope iop_sw_mpu, type r */
1224#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___lsb 0
1225#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___width 1
1226#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___bit 0
1227#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___lsb 1
1228#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___width 1
1229#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___bit 1
1230#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 2
1231#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1
1232#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 2
1233#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___lsb 3
1234#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___width 1
1235#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___bit 3
1236#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 4
1237#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1
1238#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 4
1239#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___lsb 5
1240#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___width 1
1241#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___bit 5
1242#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___lsb 6
1243#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___width 1
1244#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___bit 6
1245#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___lsb 7
1246#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___width 1
1247#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___bit 7
1248#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___lsb 8
1249#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___width 1
1250#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___bit 8
1251#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___lsb 9
1252#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___width 1
1253#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___bit 9
1254#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 10
1255#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1
1256#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 10
1257#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___lsb 11
1258#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___width 1
1259#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___bit 11
1260#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 12
1261#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1
1262#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 12
1263#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___lsb 13
1264#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___width 1
1265#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___bit 13
1266#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___lsb 14
1267#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___width 1
1268#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___bit 14
1269#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___lsb 15
1270#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___width 1
1271#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___bit 15
1272#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___lsb 16
1273#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___width 1
1274#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___bit 16
1275#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___lsb 17
1276#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___width 1
1277#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___bit 17
1278#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 18
1279#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1
1280#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 18
1281#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___lsb 19
1282#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___width 1
1283#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___bit 19
1284#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___lsb 20
1285#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___width 1
1286#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___bit 20
1287#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___lsb 21
1288#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___width 1
1289#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___bit 21
1290#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___lsb 22
1291#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___width 1
1292#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___bit 22
1293#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___lsb 23
1294#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___width 1
1295#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___bit 23
1296#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___lsb 24
1297#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___width 1
1298#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___bit 24
1299#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___lsb 25
1300#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___width 1
1301#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___bit 25
1302#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 26
1303#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1
1304#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 26
1305#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___lsb 27
1306#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___width 1
1307#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___bit 27
1308#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___lsb 28
1309#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___width 1
1310#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___bit 28
1311#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___lsb 29
1312#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___width 1
1313#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___bit 29
1314#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___lsb 30
1315#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___width 1
1316#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___bit 30
1317#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___lsb 31
1318#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___width 1
1319#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___bit 31
1320#define reg_iop_sw_mpu_r_intr_grp2_offset 136
1321
1322/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
1323#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___lsb 0
1324#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___width 1
1325#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___bit 0
1326#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___lsb 1
1327#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___width 1
1328#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___bit 1
1329#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 2
1330#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1
1331#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 2
1332#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___lsb 3
1333#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___width 1
1334#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___bit 3
1335#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 4
1336#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1
1337#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 4
1338#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___lsb 5
1339#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___width 1
1340#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___bit 5
1341#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___lsb 6
1342#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___width 1
1343#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___bit 6
1344#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___lsb 7
1345#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___width 1
1346#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___bit 7
1347#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___lsb 8
1348#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___width 1
1349#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___bit 8
1350#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___lsb 9
1351#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___width 1
1352#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___bit 9
1353#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 10
1354#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1
1355#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 10
1356#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___lsb 11
1357#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___width 1
1358#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___bit 11
1359#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 12
1360#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1
1361#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 12
1362#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___lsb 13
1363#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___width 1
1364#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___bit 13
1365#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___lsb 14
1366#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___width 1
1367#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___bit 14
1368#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___lsb 15
1369#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___width 1
1370#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___bit 15
1371#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___lsb 16
1372#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___width 1
1373#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___bit 16
1374#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___lsb 17
1375#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___width 1
1376#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___bit 17
1377#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 18
1378#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1
1379#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 18
1380#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___lsb 19
1381#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___width 1
1382#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___bit 19
1383#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___lsb 20
1384#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___width 1
1385#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___bit 20
1386#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___lsb 21
1387#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___width 1
1388#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___bit 21
1389#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___lsb 22
1390#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___width 1
1391#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___bit 22
1392#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___lsb 23
1393#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___width 1
1394#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___bit 23
1395#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___lsb 24
1396#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___width 1
1397#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___bit 24
1398#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___lsb 25
1399#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___width 1
1400#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___bit 25
1401#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 26
1402#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1
1403#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 26
1404#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___lsb 27
1405#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___width 1
1406#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___bit 27
1407#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___lsb 28
1408#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___width 1
1409#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___bit 28
1410#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___lsb 29
1411#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___width 1
1412#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___bit 29
1413#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___lsb 30
1414#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___width 1
1415#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___bit 30
1416#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___lsb 31
1417#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___width 1
1418#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___bit 31
1419#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 140
1420
1421/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
1422#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___lsb 0
1423#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___width 1
1424#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___bit 0
1425#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___lsb 1
1426#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___width 1
1427#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___bit 1
1428#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___lsb 2
1429#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___width 1
1430#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___bit 2
1431#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 3
1432#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1
1433#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 3
1434#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 4
1435#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1
1436#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 4
1437#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___lsb 5
1438#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___width 1
1439#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___bit 5
1440#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___lsb 6
1441#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___width 1
1442#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___bit 6
1443#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___lsb 7
1444#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___width 1
1445#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___bit 7
1446#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___lsb 8
1447#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___width 1
1448#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___bit 8
1449#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___lsb 9
1450#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___width 1
1451#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___bit 9
1452#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___lsb 10
1453#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___width 1
1454#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___bit 10
1455#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 11
1456#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1
1457#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 11
1458#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 12
1459#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1
1460#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 12
1461#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___lsb 13
1462#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___width 1
1463#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___bit 13
1464#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___lsb 14
1465#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___width 1
1466#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___bit 14
1467#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___lsb 15
1468#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___width 1
1469#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___bit 15
1470#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___lsb 16
1471#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___width 1
1472#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___bit 16
1473#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___lsb 17
1474#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___width 1
1475#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___bit 17
1476#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___lsb 18
1477#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___width 1
1478#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___bit 18
1479#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 19
1480#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1
1481#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 19
1482#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___lsb 20
1483#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___width 1
1484#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___bit 20
1485#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___lsb 21
1486#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___width 1
1487#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___bit 21
1488#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___lsb 22
1489#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___width 1
1490#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___bit 22
1491#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___lsb 23
1492#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___width 1
1493#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___bit 23
1494#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___lsb 24
1495#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___width 1
1496#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___bit 24
1497#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___lsb 25
1498#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___width 1
1499#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___bit 25
1500#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___lsb 26
1501#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___width 1
1502#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___bit 26
1503#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 27
1504#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1
1505#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 27
1506#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___lsb 28
1507#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___width 1
1508#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___bit 28
1509#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___lsb 29
1510#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___width 1
1511#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___bit 29
1512#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___lsb 30
1513#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___width 1
1514#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___bit 30
1515#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___lsb 31
1516#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___width 1
1517#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___bit 31
1518#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 144
1519
1520/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
1521#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___lsb 0
1522#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___width 1
1523#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___bit 0
1524#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___lsb 1
1525#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___width 1
1526#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___bit 1
1527#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___lsb 8
1528#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___width 1
1529#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___bit 8
1530#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___lsb 9
1531#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___width 1
1532#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___bit 9
1533#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___lsb 16
1534#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___width 1
1535#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___bit 16
1536#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___lsb 17
1537#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___width 1
1538#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___bit 17
1539#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___lsb 24
1540#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___width 1
1541#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___bit 24
1542#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___lsb 25
1543#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___width 1
1544#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___bit 25
1545#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 148
1546
1547/* Register r_intr_grp3, scope iop_sw_mpu, type r */
1548#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___lsb 0
1549#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___width 1
1550#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___bit 0
1551#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___lsb 1
1552#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___width 1
1553#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___bit 1
1554#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___lsb 2
1555#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___width 1
1556#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___bit 2
1557#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 3
1558#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1
1559#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 3
1560#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 4
1561#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1
1562#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 4
1563#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___lsb 5
1564#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___width 1
1565#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___bit 5
1566#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___lsb 6
1567#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___width 1
1568#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___bit 6
1569#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___lsb 7
1570#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___width 1
1571#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___bit 7
1572#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___lsb 8
1573#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___width 1
1574#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___bit 8
1575#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___lsb 9
1576#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___width 1
1577#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___bit 9
1578#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___lsb 10
1579#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___width 1
1580#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___bit 10
1581#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 11
1582#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1
1583#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 11
1584#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 12
1585#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1
1586#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 12
1587#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___lsb 13
1588#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___width 1
1589#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___bit 13
1590#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___lsb 14
1591#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___width 1
1592#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___bit 14
1593#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___lsb 15
1594#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___width 1
1595#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___bit 15
1596#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___lsb 16
1597#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___width 1
1598#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___bit 16
1599#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___lsb 17
1600#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___width 1
1601#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___bit 17
1602#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___lsb 18
1603#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___width 1
1604#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___bit 18
1605#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 19
1606#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1
1607#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 19
1608#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___lsb 20
1609#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___width 1
1610#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___bit 20
1611#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___lsb 21
1612#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___width 1
1613#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___bit 21
1614#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___lsb 22
1615#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___width 1
1616#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___bit 22
1617#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___lsb 23
1618#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___width 1
1619#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___bit 23
1620#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___lsb 24
1621#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___width 1
1622#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___bit 24
1623#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___lsb 25
1624#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___width 1
1625#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___bit 25
1626#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___lsb 26
1627#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___width 1
1628#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___bit 26
1629#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 27
1630#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1
1631#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 27
1632#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___lsb 28
1633#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___width 1
1634#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___bit 28
1635#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___lsb 29
1636#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___width 1
1637#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___bit 29
1638#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___lsb 30
1639#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___width 1
1640#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___bit 30
1641#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___lsb 31
1642#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___width 1
1643#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___bit 31
1644#define reg_iop_sw_mpu_r_intr_grp3_offset 152
1645
1646/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
1647#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___lsb 0
1648#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___width 1
1649#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___bit 0
1650#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___lsb 1
1651#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___width 1
1652#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___bit 1
1653#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___lsb 2
1654#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___width 1
1655#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___bit 2
1656#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 3
1657#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1
1658#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 3
1659#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 4
1660#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1
1661#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 4
1662#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___lsb 5
1663#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___width 1
1664#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___bit 5
1665#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___lsb 6
1666#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___width 1
1667#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___bit 6
1668#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___lsb 7
1669#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___width 1
1670#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___bit 7
1671#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___lsb 8
1672#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___width 1
1673#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___bit 8
1674#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___lsb 9
1675#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___width 1
1676#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___bit 9
1677#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___lsb 10
1678#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___width 1
1679#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___bit 10
1680#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 11
1681#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1
1682#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 11
1683#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 12
1684#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1
1685#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 12
1686#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___lsb 13
1687#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___width 1
1688#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___bit 13
1689#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___lsb 14
1690#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___width 1
1691#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___bit 14
1692#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___lsb 15
1693#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___width 1
1694#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___bit 15
1695#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___lsb 16
1696#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___width 1
1697#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___bit 16
1698#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___lsb 17
1699#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___width 1
1700#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___bit 17
1701#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___lsb 18
1702#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___width 1
1703#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___bit 18
1704#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 19
1705#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1
1706#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19
1707#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___lsb 20
1708#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___width 1
1709#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___bit 20
1710#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___lsb 21
1711#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___width 1
1712#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___bit 21
1713#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___lsb 22
1714#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___width 1
1715#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___bit 22
1716#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___lsb 23
1717#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___width 1
1718#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___bit 23
1719#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___lsb 24
1720#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___width 1
1721#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___bit 24
1722#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___lsb 25
1723#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___width 1
1724#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___bit 25
1725#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___lsb 26
1726#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___width 1
1727#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___bit 26
1728#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 27
1729#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1
1730#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 27
1731#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___lsb 28
1732#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___width 1
1733#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___bit 28
1734#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___lsb 29
1735#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___width 1
1736#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___bit 29
1737#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___lsb 30
1738#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___width 1
1739#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___bit 30
1740#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___lsb 31
1741#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___width 1
1742#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___bit 31
1743#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 156
1744
1745
1746/* Constants */
1747#define regk_iop_sw_mpu_copy 0x00000000
1748#define regk_iop_sw_mpu_cpu 0x00000000
1749#define regk_iop_sw_mpu_mpu 0x00000001
1750#define regk_iop_sw_mpu_no 0x00000000
1751#define regk_iop_sw_mpu_nop 0x00000000
1752#define regk_iop_sw_mpu_rd 0x00000002
1753#define regk_iop_sw_mpu_reg_copy 0x00000001
1754#define regk_iop_sw_mpu_rw_bus0_clr_mask_default 0x00000000
1755#define regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default 0x00000000
1756#define regk_iop_sw_mpu_rw_bus0_oe_set_mask_default 0x00000000
1757#define regk_iop_sw_mpu_rw_bus0_set_mask_default 0x00000000
1758#define regk_iop_sw_mpu_rw_bus1_clr_mask_default 0x00000000
1759#define regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default 0x00000000
1760#define regk_iop_sw_mpu_rw_bus1_oe_set_mask_default 0x00000000
1761#define regk_iop_sw_mpu_rw_bus1_set_mask_default 0x00000000
1762#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000
1763#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000
1764#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000
1765#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000
1766#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000
1767#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000
1768#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000
1769#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000
1770#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000
1771#define regk_iop_sw_mpu_set 0x00000001
1772#define regk_iop_sw_mpu_spu0 0x00000002
1773#define regk_iop_sw_mpu_spu1 0x00000003
1774#define regk_iop_sw_mpu_wr 0x00000003
1775#define regk_iop_sw_mpu_yes 0x00000001
1776#endif /* __iop_sw_mpu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h
new file mode 100644
index 000000000000..0929f144cfa1
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h
@@ -0,0 +1,691 @@
1#ifndef __iop_sw_spu_defs_asm_h
2#define __iop_sw_spu_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:10:19 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
11 * id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
57#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0
58#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1
59#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0
60#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1
61#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2
62#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3
63#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3
64#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6
65#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1
66#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6
67#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7
68#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1
69#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7
70#define reg_iop_sw_spu_rw_mc_ctrl_offset 0
71
72/* Register rw_mc_data, scope iop_sw_spu, type rw */
73#define reg_iop_sw_spu_rw_mc_data___val___lsb 0
74#define reg_iop_sw_spu_rw_mc_data___val___width 32
75#define reg_iop_sw_spu_rw_mc_data_offset 4
76
77/* Register rw_mc_addr, scope iop_sw_spu, type rw */
78#define reg_iop_sw_spu_rw_mc_addr_offset 8
79
80/* Register rs_mc_data, scope iop_sw_spu, type rs */
81#define reg_iop_sw_spu_rs_mc_data_offset 12
82
83/* Register r_mc_data, scope iop_sw_spu, type r */
84#define reg_iop_sw_spu_r_mc_data_offset 16
85
86/* Register r_mc_stat, scope iop_sw_spu, type r */
87#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0
88#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1
89#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0
90#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1
91#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1
92#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1
93#define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2
94#define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1
95#define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2
96#define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3
97#define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1
98#define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3
99#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4
100#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1
101#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4
102#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5
103#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1
104#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5
105#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6
106#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1
107#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6
108#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7
109#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1
110#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7
111#define reg_iop_sw_spu_r_mc_stat_offset 20
112
113/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
114#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0
115#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8
116#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8
117#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8
118#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16
119#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8
120#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24
121#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8
122#define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24
123
124/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
125#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0
126#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8
127#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8
128#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8
129#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16
130#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8
131#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24
132#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8
133#define reg_iop_sw_spu_rw_bus0_set_mask_offset 28
134
135/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
136#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0
137#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1
138#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0
139#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1
140#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1
141#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1
142#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2
143#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1
144#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2
145#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3
146#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1
147#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3
148#define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32
149
150/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
151#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0
152#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1
153#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0
154#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1
155#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1
156#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1
157#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2
158#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1
159#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2
160#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3
161#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1
162#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3
163#define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36
164
165/* Register r_bus0_in, scope iop_sw_spu, type r */
166#define reg_iop_sw_spu_r_bus0_in_offset 40
167
168/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
169#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0
170#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8
171#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8
172#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8
173#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16
174#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8
175#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24
176#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8
177#define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44
178
179/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
180#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0
181#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8
182#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8
183#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8
184#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16
185#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8
186#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24
187#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8
188#define reg_iop_sw_spu_rw_bus1_set_mask_offset 48
189
190/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
191#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0
192#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1
193#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0
194#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1
195#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1
196#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1
197#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2
198#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1
199#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2
200#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3
201#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1
202#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3
203#define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52
204
205/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
206#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0
207#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1
208#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0
209#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1
210#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1
211#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1
212#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2
213#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1
214#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2
215#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3
216#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1
217#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3
218#define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56
219
220/* Register r_bus1_in, scope iop_sw_spu, type r */
221#define reg_iop_sw_spu_r_bus1_in_offset 60
222
223/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
224#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0
225#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32
226#define reg_iop_sw_spu_rw_gio_clr_mask_offset 64
227
228/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
229#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0
230#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32
231#define reg_iop_sw_spu_rw_gio_set_mask_offset 68
232
233/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
234#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0
235#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32
236#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72
237
238/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
239#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0
240#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32
241#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76
242
243/* Register r_gio_in, scope iop_sw_spu, type r */
244#define reg_iop_sw_spu_r_gio_in_offset 80
245
246/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
247#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0
248#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8
249#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8
250#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8
251#define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84
252
253/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
254#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0
255#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8
256#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8
257#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8
258#define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88
259
260/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
261#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0
262#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8
263#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8
264#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8
265#define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92
266
267/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
268#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0
269#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8
270#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8
271#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8
272#define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96
273
274/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
275#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0
276#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8
277#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8
278#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8
279#define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100
280
281/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
282#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0
283#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8
284#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8
285#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8
286#define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104
287
288/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
289#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0
290#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8
291#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8
292#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8
293#define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108
294
295/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
296#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0
297#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8
298#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8
299#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8
300#define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112
301
302/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
303#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0
304#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16
305#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116
306
307/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
308#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0
309#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16
310#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120
311
312/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
313#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0
314#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16
315#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124
316
317/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
318#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0
319#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16
320#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128
321
322/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
323#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0
324#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16
325#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132
326
327/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
328#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0
329#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16
330#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136
331
332/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
333#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0
334#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16
335#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140
336
337/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
338#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0
339#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16
340#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144
341
342/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
343#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0
344#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1
345#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0
346#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1
347#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1
348#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1
349#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2
350#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1
351#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2
352#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3
353#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1
354#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3
355#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4
356#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1
357#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4
358#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5
359#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1
360#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5
361#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6
362#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1
363#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6
364#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7
365#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1
366#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7
367#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8
368#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1
369#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8
370#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9
371#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1
372#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9
373#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10
374#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1
375#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10
376#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11
377#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1
378#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11
379#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12
380#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1
381#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12
382#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13
383#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1
384#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13
385#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14
386#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1
387#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14
388#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15
389#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1
390#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15
391#define reg_iop_sw_spu_rw_cpu_intr_offset 148
392
393/* Register r_cpu_intr, scope iop_sw_spu, type r */
394#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0
395#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1
396#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0
397#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1
398#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1
399#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1
400#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2
401#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1
402#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2
403#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3
404#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1
405#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3
406#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4
407#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1
408#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4
409#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5
410#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1
411#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5
412#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6
413#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1
414#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6
415#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7
416#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1
417#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7
418#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8
419#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1
420#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8
421#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9
422#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1
423#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9
424#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10
425#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1
426#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10
427#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11
428#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1
429#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11
430#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12
431#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1
432#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12
433#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13
434#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1
435#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13
436#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14
437#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1
438#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14
439#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15
440#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1
441#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15
442#define reg_iop_sw_spu_r_cpu_intr_offset 152
443
444/* Register r_hw_intr, scope iop_sw_spu, type r */
445#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0
446#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1
447#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0
448#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1
449#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1
450#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1
451#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2
452#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1
453#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2
454#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3
455#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1
456#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3
457#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4
458#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1
459#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4
460#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5
461#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1
462#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5
463#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6
464#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1
465#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6
466#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7
467#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1
468#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7
469#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8
470#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1
471#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8
472#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9
473#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1
474#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9
475#define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10
476#define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1
477#define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10
478#define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11
479#define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1
480#define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11
481#define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12
482#define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1
483#define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12
484#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13
485#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1
486#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13
487#define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14
488#define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1
489#define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14
490#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15
491#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1
492#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15
493#define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16
494#define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1
495#define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16
496#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17
497#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1
498#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17
499#define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18
500#define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1
501#define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18
502#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19
503#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1
504#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19
505#define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20
506#define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1
507#define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20
508#define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21
509#define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1
510#define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21
511#define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22
512#define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1
513#define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22
514#define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23
515#define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1
516#define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23
517#define reg_iop_sw_spu_r_hw_intr_offset 156
518
519/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
520#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0
521#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1
522#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0
523#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1
524#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1
525#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1
526#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2
527#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1
528#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2
529#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3
530#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1
531#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3
532#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4
533#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1
534#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4
535#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5
536#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1
537#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5
538#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6
539#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1
540#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6
541#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7
542#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1
543#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7
544#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8
545#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1
546#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8
547#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9
548#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1
549#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9
550#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10
551#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1
552#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10
553#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11
554#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1
555#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11
556#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12
557#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1
558#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12
559#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13
560#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1
561#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13
562#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14
563#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1
564#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14
565#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15
566#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1
567#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15
568#define reg_iop_sw_spu_rw_mpu_intr_offset 160
569
570/* Register r_mpu_intr, scope iop_sw_spu, type r */
571#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0
572#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1
573#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0
574#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1
575#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1
576#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1
577#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2
578#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1
579#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2
580#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3
581#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1
582#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3
583#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4
584#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1
585#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4
586#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5
587#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1
588#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5
589#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6
590#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1
591#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6
592#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7
593#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1
594#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7
595#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8
596#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1
597#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8
598#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9
599#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1
600#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9
601#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10
602#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1
603#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10
604#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11
605#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1
606#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11
607#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12
608#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1
609#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12
610#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13
611#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1
612#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13
613#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14
614#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1
615#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14
616#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15
617#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1
618#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15
619#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16
620#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1
621#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16
622#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17
623#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1
624#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17
625#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18
626#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1
627#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18
628#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19
629#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1
630#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19
631#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20
632#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1
633#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20
634#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21
635#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1
636#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21
637#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22
638#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1
639#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22
640#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23
641#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1
642#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23
643#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24
644#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1
645#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24
646#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25
647#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1
648#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25
649#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26
650#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1
651#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26
652#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27
653#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1
654#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27
655#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28
656#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1
657#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28
658#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29
659#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1
660#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29
661#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30
662#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1
663#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30
664#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31
665#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1
666#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31
667#define reg_iop_sw_spu_r_mpu_intr_offset 164
668
669
670/* Constants */
671#define regk_iop_sw_spu_copy 0x00000000
672#define regk_iop_sw_spu_no 0x00000000
673#define regk_iop_sw_spu_nop 0x00000000
674#define regk_iop_sw_spu_rd 0x00000002
675#define regk_iop_sw_spu_reg_copy 0x00000001
676#define regk_iop_sw_spu_rw_bus0_clr_mask_default 0x00000000
677#define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default 0x00000000
678#define regk_iop_sw_spu_rw_bus0_oe_set_mask_default 0x00000000
679#define regk_iop_sw_spu_rw_bus0_set_mask_default 0x00000000
680#define regk_iop_sw_spu_rw_bus1_clr_mask_default 0x00000000
681#define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default 0x00000000
682#define regk_iop_sw_spu_rw_bus1_oe_set_mask_default 0x00000000
683#define regk_iop_sw_spu_rw_bus1_set_mask_default 0x00000000
684#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000
685#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000
686#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000
687#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000
688#define regk_iop_sw_spu_set 0x00000001
689#define regk_iop_sw_spu_wr 0x00000003
690#define regk_iop_sw_spu_yes 0x00000001
691#endif /* __iop_sw_spu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h
new file mode 100644
index 000000000000..7129a9a4bedc
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h
@@ -0,0 +1,237 @@
1#ifndef __iop_timer_grp_defs_asm_h
2#define __iop_timer_grp_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_timer_grp.r
7 * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
8 * last modfied: Mon Apr 11 16:08:46 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r
11 * id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_cfg, scope iop_timer_grp, type rw */
57#define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0
58#define reg_iop_timer_grp_rw_cfg___clk_src___width 1
59#define reg_iop_timer_grp_rw_cfg___clk_src___bit 0
60#define reg_iop_timer_grp_rw_cfg___trig___lsb 1
61#define reg_iop_timer_grp_rw_cfg___trig___width 2
62#define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3
63#define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8
64#define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11
65#define reg_iop_timer_grp_rw_cfg___clk_div___width 8
66#define reg_iop_timer_grp_rw_cfg_offset 0
67
68/* Register rw_half_period, scope iop_timer_grp, type rw */
69#define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0
70#define reg_iop_timer_grp_rw_half_period___quota_lo___width 15
71#define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15
72#define reg_iop_timer_grp_rw_half_period___quota_hi___width 15
73#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30
74#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1
75#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30
76#define reg_iop_timer_grp_rw_half_period_offset 4
77
78/* Register rw_half_period_len, scope iop_timer_grp, type rw */
79#define reg_iop_timer_grp_rw_half_period_len_offset 8
80
81#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
82/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
83#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0
84#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3
85#define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3
86#define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2
87#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5
88#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2
89#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7
90#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1
91#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7
92#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8
93#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2
94#define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10
95#define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1
96#define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10
97#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11
98#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2
99#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13
100#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2
101#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15
102#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1
103#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15
104#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16
105#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1
106#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16
107#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17
108#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1
109#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17
110#define reg_iop_timer_grp_rw_tmr_cfg_offset 12
111
112#define STRIDE_iop_timer_grp_rw_tmr_len 4
113/* Register rw_tmr_len, scope iop_timer_grp, type rw */
114#define reg_iop_timer_grp_rw_tmr_len___val___lsb 0
115#define reg_iop_timer_grp_rw_tmr_len___val___width 16
116#define reg_iop_timer_grp_rw_tmr_len_offset 44
117
118/* Register rw_cmd, scope iop_timer_grp, type rw */
119#define reg_iop_timer_grp_rw_cmd___rst___lsb 0
120#define reg_iop_timer_grp_rw_cmd___rst___width 4
121#define reg_iop_timer_grp_rw_cmd___en___lsb 4
122#define reg_iop_timer_grp_rw_cmd___en___width 4
123#define reg_iop_timer_grp_rw_cmd___dis___lsb 8
124#define reg_iop_timer_grp_rw_cmd___dis___width 4
125#define reg_iop_timer_grp_rw_cmd___strb___lsb 12
126#define reg_iop_timer_grp_rw_cmd___strb___width 4
127#define reg_iop_timer_grp_rw_cmd_offset 60
128
129/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
130#define reg_iop_timer_grp_r_clk_gen_cnt_offset 64
131
132#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
133/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
134#define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0
135#define reg_iop_timer_grp_rs_tmr_cnt___val___width 16
136#define reg_iop_timer_grp_rs_tmr_cnt_offset 68
137
138#define STRIDE_iop_timer_grp_r_tmr_cnt 8
139/* Register r_tmr_cnt, scope iop_timer_grp, type r */
140#define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0
141#define reg_iop_timer_grp_r_tmr_cnt___val___width 16
142#define reg_iop_timer_grp_r_tmr_cnt_offset 72
143
144/* Register rw_intr_mask, scope iop_timer_grp, type rw */
145#define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0
146#define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1
147#define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0
148#define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1
149#define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1
150#define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1
151#define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2
152#define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1
153#define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2
154#define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3
155#define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1
156#define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3
157#define reg_iop_timer_grp_rw_intr_mask_offset 100
158
159/* Register rw_ack_intr, scope iop_timer_grp, type rw */
160#define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0
161#define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1
162#define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0
163#define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1
164#define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1
165#define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1
166#define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2
167#define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1
168#define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2
169#define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3
170#define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1
171#define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3
172#define reg_iop_timer_grp_rw_ack_intr_offset 104
173
174/* Register r_intr, scope iop_timer_grp, type r */
175#define reg_iop_timer_grp_r_intr___tmr0___lsb 0
176#define reg_iop_timer_grp_r_intr___tmr0___width 1
177#define reg_iop_timer_grp_r_intr___tmr0___bit 0
178#define reg_iop_timer_grp_r_intr___tmr1___lsb 1
179#define reg_iop_timer_grp_r_intr___tmr1___width 1
180#define reg_iop_timer_grp_r_intr___tmr1___bit 1
181#define reg_iop_timer_grp_r_intr___tmr2___lsb 2
182#define reg_iop_timer_grp_r_intr___tmr2___width 1
183#define reg_iop_timer_grp_r_intr___tmr2___bit 2
184#define reg_iop_timer_grp_r_intr___tmr3___lsb 3
185#define reg_iop_timer_grp_r_intr___tmr3___width 1
186#define reg_iop_timer_grp_r_intr___tmr3___bit 3
187#define reg_iop_timer_grp_r_intr_offset 108
188
189/* Register r_masked_intr, scope iop_timer_grp, type r */
190#define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0
191#define reg_iop_timer_grp_r_masked_intr___tmr0___width 1
192#define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0
193#define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1
194#define reg_iop_timer_grp_r_masked_intr___tmr1___width 1
195#define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1
196#define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2
197#define reg_iop_timer_grp_r_masked_intr___tmr2___width 1
198#define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2
199#define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3
200#define reg_iop_timer_grp_r_masked_intr___tmr3___width 1
201#define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3
202#define reg_iop_timer_grp_r_masked_intr_offset 112
203
204
205/* Constants */
206#define regk_iop_timer_grp_clk200 0x00000000
207#define regk_iop_timer_grp_clk_gen 0x00000002
208#define regk_iop_timer_grp_complete 0x00000002
209#define regk_iop_timer_grp_div_clk200 0x00000001
210#define regk_iop_timer_grp_div_clk_gen 0x00000003
211#define regk_iop_timer_grp_ext 0x00000001
212#define regk_iop_timer_grp_hi 0x00000000
213#define regk_iop_timer_grp_long_period 0x00000001
214#define regk_iop_timer_grp_neg 0x00000002
215#define regk_iop_timer_grp_no 0x00000000
216#define regk_iop_timer_grp_once 0x00000003
217#define regk_iop_timer_grp_pause 0x00000001
218#define regk_iop_timer_grp_pos 0x00000001
219#define regk_iop_timer_grp_pos_neg 0x00000003
220#define regk_iop_timer_grp_pulse 0x00000000
221#define regk_iop_timer_grp_r_tmr_cnt_size 0x00000004
222#define regk_iop_timer_grp_rs_tmr_cnt_size 0x00000004
223#define regk_iop_timer_grp_rw_cfg_default 0x00000002
224#define regk_iop_timer_grp_rw_intr_mask_default 0x00000000
225#define regk_iop_timer_grp_rw_tmr_cfg_default0 0x00018000
226#define regk_iop_timer_grp_rw_tmr_cfg_default1 0x0001a900
227#define regk_iop_timer_grp_rw_tmr_cfg_default2 0x0001d200
228#define regk_iop_timer_grp_rw_tmr_cfg_default3 0x0001fb00
229#define regk_iop_timer_grp_rw_tmr_cfg_size 0x00000004
230#define regk_iop_timer_grp_rw_tmr_len_default 0x00000000
231#define regk_iop_timer_grp_rw_tmr_len_size 0x00000004
232#define regk_iop_timer_grp_short_period 0x00000000
233#define regk_iop_timer_grp_stop 0x00000000
234#define regk_iop_timer_grp_tmr 0x00000004
235#define regk_iop_timer_grp_toggle 0x00000001
236#define regk_iop_timer_grp_yes 0x00000001
237#endif /* __iop_timer_grp_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h
new file mode 100644
index 000000000000..1005d9db80dc
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h
@@ -0,0 +1,157 @@
1#ifndef __iop_trigger_grp_defs_asm_h
2#define __iop_trigger_grp_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_trigger_grp.r
7 * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp
8 * last modfied: Mon Apr 11 16:08:46 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r
11 * id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56#define STRIDE_iop_trigger_grp_rw_cfg 4
57/* Register rw_cfg, scope iop_trigger_grp, type rw */
58#define reg_iop_trigger_grp_rw_cfg___action___lsb 0
59#define reg_iop_trigger_grp_rw_cfg___action___width 2
60#define reg_iop_trigger_grp_rw_cfg___once___lsb 2
61#define reg_iop_trigger_grp_rw_cfg___once___width 1
62#define reg_iop_trigger_grp_rw_cfg___once___bit 2
63#define reg_iop_trigger_grp_rw_cfg___trig___lsb 3
64#define reg_iop_trigger_grp_rw_cfg___trig___width 3
65#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6
66#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1
67#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6
68#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7
69#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1
70#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7
71#define reg_iop_trigger_grp_rw_cfg_offset 0
72
73/* Register rw_cmd, scope iop_trigger_grp, type rw */
74#define reg_iop_trigger_grp_rw_cmd___dis___lsb 0
75#define reg_iop_trigger_grp_rw_cmd___dis___width 4
76#define reg_iop_trigger_grp_rw_cmd___en___lsb 4
77#define reg_iop_trigger_grp_rw_cmd___en___width 4
78#define reg_iop_trigger_grp_rw_cmd_offset 16
79
80/* Register rw_intr_mask, scope iop_trigger_grp, type rw */
81#define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0
82#define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1
83#define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0
84#define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1
85#define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1
86#define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1
87#define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2
88#define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1
89#define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2
90#define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3
91#define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1
92#define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3
93#define reg_iop_trigger_grp_rw_intr_mask_offset 20
94
95/* Register rw_ack_intr, scope iop_trigger_grp, type rw */
96#define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0
97#define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1
98#define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0
99#define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1
100#define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1
101#define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1
102#define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2
103#define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1
104#define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2
105#define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3
106#define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1
107#define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3
108#define reg_iop_trigger_grp_rw_ack_intr_offset 24
109
110/* Register r_intr, scope iop_trigger_grp, type r */
111#define reg_iop_trigger_grp_r_intr___trig0___lsb 0
112#define reg_iop_trigger_grp_r_intr___trig0___width 1
113#define reg_iop_trigger_grp_r_intr___trig0___bit 0
114#define reg_iop_trigger_grp_r_intr___trig1___lsb 1
115#define reg_iop_trigger_grp_r_intr___trig1___width 1
116#define reg_iop_trigger_grp_r_intr___trig1___bit 1
117#define reg_iop_trigger_grp_r_intr___trig2___lsb 2
118#define reg_iop_trigger_grp_r_intr___trig2___width 1
119#define reg_iop_trigger_grp_r_intr___trig2___bit 2
120#define reg_iop_trigger_grp_r_intr___trig3___lsb 3
121#define reg_iop_trigger_grp_r_intr___trig3___width 1
122#define reg_iop_trigger_grp_r_intr___trig3___bit 3
123#define reg_iop_trigger_grp_r_intr_offset 28
124
125/* Register r_masked_intr, scope iop_trigger_grp, type r */
126#define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0
127#define reg_iop_trigger_grp_r_masked_intr___trig0___width 1
128#define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0
129#define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1
130#define reg_iop_trigger_grp_r_masked_intr___trig1___width 1
131#define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1
132#define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2
133#define reg_iop_trigger_grp_r_masked_intr___trig2___width 1
134#define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2
135#define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3
136#define reg_iop_trigger_grp_r_masked_intr___trig3___width 1
137#define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3
138#define reg_iop_trigger_grp_r_masked_intr_offset 32
139
140
141/* Constants */
142#define regk_iop_trigger_grp_fall 0x00000002
143#define regk_iop_trigger_grp_fall_lo 0x00000006
144#define regk_iop_trigger_grp_no 0x00000000
145#define regk_iop_trigger_grp_off 0x00000000
146#define regk_iop_trigger_grp_pulse 0x00000000
147#define regk_iop_trigger_grp_rise 0x00000001
148#define regk_iop_trigger_grp_rise_fall 0x00000003
149#define regk_iop_trigger_grp_rise_fall_hi 0x00000007
150#define regk_iop_trigger_grp_rise_fall_lo 0x00000004
151#define regk_iop_trigger_grp_rise_hi 0x00000005
152#define regk_iop_trigger_grp_rw_cfg_default 0x000000c0
153#define regk_iop_trigger_grp_rw_cfg_size 0x00000004
154#define regk_iop_trigger_grp_rw_intr_mask_default 0x00000000
155#define regk_iop_trigger_grp_toggle 0x00000003
156#define regk_iop_trigger_grp_yes 0x00000001
157#endif /* __iop_trigger_grp_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h
new file mode 100644
index 000000000000..e13feb20a7e3
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h
@@ -0,0 +1,64 @@
1#ifndef __iop_version_defs_asm_h
2#define __iop_version_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/guinness/iop_version.r
7 * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp
8 * last modfied: Mon Apr 11 16:08:44 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r
11 * id: $Id: iop_version_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register r_version, scope iop_version, type r */
57#define reg_iop_version_r_version___nr___lsb 0
58#define reg_iop_version_r_version___nr___width 8
59#define reg_iop_version_r_version_offset 0
60
61
62/* Constants */
63#define regk_iop_version_v1_0 0x00000001
64#endif /* __iop_version_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h
new file mode 100644
index 000000000000..90e4785b6474
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h
@@ -0,0 +1,232 @@
1#ifndef __iop_crc_par_defs_h
2#define __iop_crc_par_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_crc_par.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:08:45 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r
11 * id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_crc_par */
86
87/* Register rw_cfg, scope iop_crc_par, type rw */
88typedef struct {
89 unsigned int mode : 1;
90 unsigned int crc_out : 1;
91 unsigned int rev_out : 1;
92 unsigned int inv_out : 1;
93 unsigned int trig : 2;
94 unsigned int poly : 3;
95 unsigned int dummy1 : 23;
96} reg_iop_crc_par_rw_cfg;
97#define REG_RD_ADDR_iop_crc_par_rw_cfg 0
98#define REG_WR_ADDR_iop_crc_par_rw_cfg 0
99
100/* Register rw_init_crc, scope iop_crc_par, type rw */
101typedef unsigned int reg_iop_crc_par_rw_init_crc;
102#define REG_RD_ADDR_iop_crc_par_rw_init_crc 4
103#define REG_WR_ADDR_iop_crc_par_rw_init_crc 4
104
105/* Register rw_correct_crc, scope iop_crc_par, type rw */
106typedef unsigned int reg_iop_crc_par_rw_correct_crc;
107#define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8
108#define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8
109
110/* Register rw_ctrl, scope iop_crc_par, type rw */
111typedef struct {
112 unsigned int en : 1;
113 unsigned int dummy1 : 31;
114} reg_iop_crc_par_rw_ctrl;
115#define REG_RD_ADDR_iop_crc_par_rw_ctrl 12
116#define REG_WR_ADDR_iop_crc_par_rw_ctrl 12
117
118/* Register rw_set_last, scope iop_crc_par, type rw */
119typedef struct {
120 unsigned int tr_dif : 1;
121 unsigned int dummy1 : 31;
122} reg_iop_crc_par_rw_set_last;
123#define REG_RD_ADDR_iop_crc_par_rw_set_last 16
124#define REG_WR_ADDR_iop_crc_par_rw_set_last 16
125
126/* Register rw_wr1byte, scope iop_crc_par, type rw */
127typedef struct {
128 unsigned int data : 8;
129 unsigned int dummy1 : 24;
130} reg_iop_crc_par_rw_wr1byte;
131#define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20
132#define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20
133
134/* Register rw_wr2byte, scope iop_crc_par, type rw */
135typedef struct {
136 unsigned int data : 16;
137 unsigned int dummy1 : 16;
138} reg_iop_crc_par_rw_wr2byte;
139#define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24
140#define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24
141
142/* Register rw_wr3byte, scope iop_crc_par, type rw */
143typedef struct {
144 unsigned int data : 24;
145 unsigned int dummy1 : 8;
146} reg_iop_crc_par_rw_wr3byte;
147#define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28
148#define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28
149
150/* Register rw_wr4byte, scope iop_crc_par, type rw */
151typedef struct {
152 unsigned int data : 32;
153} reg_iop_crc_par_rw_wr4byte;
154#define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32
155#define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32
156
157/* Register rw_wr1byte_last, scope iop_crc_par, type rw */
158typedef struct {
159 unsigned int data : 8;
160 unsigned int dummy1 : 24;
161} reg_iop_crc_par_rw_wr1byte_last;
162#define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36
163#define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36
164
165/* Register rw_wr2byte_last, scope iop_crc_par, type rw */
166typedef struct {
167 unsigned int data : 16;
168 unsigned int dummy1 : 16;
169} reg_iop_crc_par_rw_wr2byte_last;
170#define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40
171#define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40
172
173/* Register rw_wr3byte_last, scope iop_crc_par, type rw */
174typedef struct {
175 unsigned int data : 24;
176 unsigned int dummy1 : 8;
177} reg_iop_crc_par_rw_wr3byte_last;
178#define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44
179#define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44
180
181/* Register rw_wr4byte_last, scope iop_crc_par, type rw */
182typedef struct {
183 unsigned int data : 32;
184} reg_iop_crc_par_rw_wr4byte_last;
185#define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48
186#define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48
187
188/* Register r_stat, scope iop_crc_par, type r */
189typedef struct {
190 unsigned int err : 1;
191 unsigned int busy : 1;
192 unsigned int dummy1 : 30;
193} reg_iop_crc_par_r_stat;
194#define REG_RD_ADDR_iop_crc_par_r_stat 52
195
196/* Register r_sh_reg, scope iop_crc_par, type r */
197typedef unsigned int reg_iop_crc_par_r_sh_reg;
198#define REG_RD_ADDR_iop_crc_par_r_sh_reg 56
199
200/* Register r_crc, scope iop_crc_par, type r */
201typedef unsigned int reg_iop_crc_par_r_crc;
202#define REG_RD_ADDR_iop_crc_par_r_crc 60
203
204/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
205typedef struct {
206 unsigned int last : 2;
207 unsigned int dummy1 : 30;
208} reg_iop_crc_par_rw_strb_rec_dif_in;
209#define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
210#define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
211
212
213/* Constants */
214enum {
215 regk_iop_crc_par_calc = 0x00000001,
216 regk_iop_crc_par_ccitt = 0x00000002,
217 regk_iop_crc_par_check = 0x00000000,
218 regk_iop_crc_par_crc16 = 0x00000001,
219 regk_iop_crc_par_crc32 = 0x00000000,
220 regk_iop_crc_par_crc5 = 0x00000003,
221 regk_iop_crc_par_crc5_11 = 0x00000004,
222 regk_iop_crc_par_dif_in = 0x00000002,
223 regk_iop_crc_par_hi = 0x00000000,
224 regk_iop_crc_par_neg = 0x00000002,
225 regk_iop_crc_par_no = 0x00000000,
226 regk_iop_crc_par_pos = 0x00000001,
227 regk_iop_crc_par_pos_neg = 0x00000003,
228 regk_iop_crc_par_rw_cfg_default = 0x00000000,
229 regk_iop_crc_par_rw_ctrl_default = 0x00000000,
230 regk_iop_crc_par_yes = 0x00000001
231};
232#endif /* __iop_crc_par_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h
new file mode 100644
index 000000000000..76aec6e37f3e
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h
@@ -0,0 +1,325 @@
1#ifndef __iop_dmc_in_defs_h
2#define __iop_dmc_in_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_dmc_in.r
7 * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp
8 * last modfied: Mon Apr 11 16:08:45 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r
11 * id: $Id: iop_dmc_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_dmc_in */
86
87/* Register rw_cfg, scope iop_dmc_in, type rw */
88typedef struct {
89 unsigned int sth_intr : 3;
90 unsigned int last_dis_dif : 1;
91 unsigned int dummy1 : 28;
92} reg_iop_dmc_in_rw_cfg;
93#define REG_RD_ADDR_iop_dmc_in_rw_cfg 0
94#define REG_WR_ADDR_iop_dmc_in_rw_cfg 0
95
96/* Register rw_ctrl, scope iop_dmc_in, type rw */
97typedef struct {
98 unsigned int dif_en : 1;
99 unsigned int dif_dis : 1;
100 unsigned int stream_clr : 1;
101 unsigned int dummy1 : 29;
102} reg_iop_dmc_in_rw_ctrl;
103#define REG_RD_ADDR_iop_dmc_in_rw_ctrl 4
104#define REG_WR_ADDR_iop_dmc_in_rw_ctrl 4
105
106/* Register r_stat, scope iop_dmc_in, type r */
107typedef struct {
108 unsigned int dif_en : 1;
109 unsigned int dummy1 : 31;
110} reg_iop_dmc_in_r_stat;
111#define REG_RD_ADDR_iop_dmc_in_r_stat 8
112
113/* Register rw_stream_cmd, scope iop_dmc_in, type rw */
114typedef struct {
115 unsigned int cmd : 10;
116 unsigned int dummy1 : 6;
117 unsigned int n : 8;
118 unsigned int dummy2 : 8;
119} reg_iop_dmc_in_rw_stream_cmd;
120#define REG_RD_ADDR_iop_dmc_in_rw_stream_cmd 12
121#define REG_WR_ADDR_iop_dmc_in_rw_stream_cmd 12
122
123/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
124typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data;
125#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data 16
126#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data 16
127
128/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
129typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data_last;
130#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data_last 20
131#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data_last 20
132
133/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
134typedef struct {
135 unsigned int eop : 1;
136 unsigned int wait : 1;
137 unsigned int keep_md : 1;
138 unsigned int size : 3;
139 unsigned int dummy1 : 26;
140} reg_iop_dmc_in_rw_stream_ctrl;
141#define REG_RD_ADDR_iop_dmc_in_rw_stream_ctrl 24
142#define REG_WR_ADDR_iop_dmc_in_rw_stream_ctrl 24
143
144/* Register r_stream_stat, scope iop_dmc_in, type r */
145typedef struct {
146 unsigned int sth : 7;
147 unsigned int dummy1 : 9;
148 unsigned int full : 1;
149 unsigned int last_pkt : 1;
150 unsigned int data_md_valid : 1;
151 unsigned int ctxt_md_valid : 1;
152 unsigned int group_md_valid : 1;
153 unsigned int stream_busy : 1;
154 unsigned int cmd_rdy : 1;
155 unsigned int dummy2 : 9;
156} reg_iop_dmc_in_r_stream_stat;
157#define REG_RD_ADDR_iop_dmc_in_r_stream_stat 28
158
159/* Register r_data_descr, scope iop_dmc_in, type r */
160typedef struct {
161 unsigned int ctrl : 8;
162 unsigned int stat : 8;
163 unsigned int md : 16;
164} reg_iop_dmc_in_r_data_descr;
165#define REG_RD_ADDR_iop_dmc_in_r_data_descr 32
166
167/* Register r_ctxt_descr, scope iop_dmc_in, type r */
168typedef struct {
169 unsigned int ctrl : 8;
170 unsigned int stat : 8;
171 unsigned int md0 : 16;
172} reg_iop_dmc_in_r_ctxt_descr;
173#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr 36
174
175/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */
176typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md1;
177#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md1 40
178
179/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */
180typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md2;
181#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md2 44
182
183/* Register r_group_descr, scope iop_dmc_in, type r */
184typedef struct {
185 unsigned int ctrl : 8;
186 unsigned int stat : 8;
187 unsigned int md : 16;
188} reg_iop_dmc_in_r_group_descr;
189#define REG_RD_ADDR_iop_dmc_in_r_group_descr 56
190
191/* Register rw_data_descr, scope iop_dmc_in, type rw */
192typedef struct {
193 unsigned int dummy1 : 16;
194 unsigned int md : 16;
195} reg_iop_dmc_in_rw_data_descr;
196#define REG_RD_ADDR_iop_dmc_in_rw_data_descr 60
197#define REG_WR_ADDR_iop_dmc_in_rw_data_descr 60
198
199/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
200typedef struct {
201 unsigned int dummy1 : 16;
202 unsigned int md0 : 16;
203} reg_iop_dmc_in_rw_ctxt_descr;
204#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr 64
205#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr 64
206
207/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
208typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md1;
209#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68
210#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68
211
212/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
213typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md2;
214#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72
215#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72
216
217/* Register rw_group_descr, scope iop_dmc_in, type rw */
218typedef struct {
219 unsigned int dummy1 : 16;
220 unsigned int md : 16;
221} reg_iop_dmc_in_rw_group_descr;
222#define REG_RD_ADDR_iop_dmc_in_rw_group_descr 84
223#define REG_WR_ADDR_iop_dmc_in_rw_group_descr 84
224
225/* Register rw_intr_mask, scope iop_dmc_in, type rw */
226typedef struct {
227 unsigned int data_md : 1;
228 unsigned int ctxt_md : 1;
229 unsigned int group_md : 1;
230 unsigned int cmd_rdy : 1;
231 unsigned int sth : 1;
232 unsigned int full : 1;
233 unsigned int dummy1 : 26;
234} reg_iop_dmc_in_rw_intr_mask;
235#define REG_RD_ADDR_iop_dmc_in_rw_intr_mask 88
236#define REG_WR_ADDR_iop_dmc_in_rw_intr_mask 88
237
238/* Register rw_ack_intr, scope iop_dmc_in, type rw */
239typedef struct {
240 unsigned int data_md : 1;
241 unsigned int ctxt_md : 1;
242 unsigned int group_md : 1;
243 unsigned int cmd_rdy : 1;
244 unsigned int sth : 1;
245 unsigned int full : 1;
246 unsigned int dummy1 : 26;
247} reg_iop_dmc_in_rw_ack_intr;
248#define REG_RD_ADDR_iop_dmc_in_rw_ack_intr 92
249#define REG_WR_ADDR_iop_dmc_in_rw_ack_intr 92
250
251/* Register r_intr, scope iop_dmc_in, type r */
252typedef struct {
253 unsigned int data_md : 1;
254 unsigned int ctxt_md : 1;
255 unsigned int group_md : 1;
256 unsigned int cmd_rdy : 1;
257 unsigned int sth : 1;
258 unsigned int full : 1;
259 unsigned int dummy1 : 26;
260} reg_iop_dmc_in_r_intr;
261#define REG_RD_ADDR_iop_dmc_in_r_intr 96
262
263/* Register r_masked_intr, scope iop_dmc_in, type r */
264typedef struct {
265 unsigned int data_md : 1;
266 unsigned int ctxt_md : 1;
267 unsigned int group_md : 1;
268 unsigned int cmd_rdy : 1;
269 unsigned int sth : 1;
270 unsigned int full : 1;
271 unsigned int dummy1 : 26;
272} reg_iop_dmc_in_r_masked_intr;
273#define REG_RD_ADDR_iop_dmc_in_r_masked_intr 100
274
275
276/* Constants */
277enum {
278 regk_iop_dmc_in_ack_pkt = 0x00000100,
279 regk_iop_dmc_in_array = 0x00000008,
280 regk_iop_dmc_in_burst = 0x00000020,
281 regk_iop_dmc_in_copy_next = 0x00000010,
282 regk_iop_dmc_in_copy_up = 0x00000020,
283 regk_iop_dmc_in_dis_c = 0x00000010,
284 regk_iop_dmc_in_dis_g = 0x00000020,
285 regk_iop_dmc_in_lim1 = 0x00000000,
286 regk_iop_dmc_in_lim16 = 0x00000004,
287 regk_iop_dmc_in_lim2 = 0x00000001,
288 regk_iop_dmc_in_lim32 = 0x00000005,
289 regk_iop_dmc_in_lim4 = 0x00000002,
290 regk_iop_dmc_in_lim64 = 0x00000006,
291 regk_iop_dmc_in_lim8 = 0x00000003,
292 regk_iop_dmc_in_load_c = 0x00000200,
293 regk_iop_dmc_in_load_c_n = 0x00000280,
294 regk_iop_dmc_in_load_c_next = 0x00000240,
295 regk_iop_dmc_in_load_d = 0x00000140,
296 regk_iop_dmc_in_load_g = 0x00000300,
297 regk_iop_dmc_in_load_g_down = 0x000003c0,
298 regk_iop_dmc_in_load_g_next = 0x00000340,
299 regk_iop_dmc_in_load_g_up = 0x00000380,
300 regk_iop_dmc_in_next_en = 0x00000010,
301 regk_iop_dmc_in_next_pkt = 0x00000010,
302 regk_iop_dmc_in_no = 0x00000000,
303 regk_iop_dmc_in_restore = 0x00000020,
304 regk_iop_dmc_in_rw_cfg_default = 0x00000000,
305 regk_iop_dmc_in_rw_ctxt_descr_default = 0x00000000,
306 regk_iop_dmc_in_rw_ctxt_descr_md1_default = 0x00000000,
307 regk_iop_dmc_in_rw_ctxt_descr_md2_default = 0x00000000,
308 regk_iop_dmc_in_rw_data_descr_default = 0x00000000,
309 regk_iop_dmc_in_rw_group_descr_default = 0x00000000,
310 regk_iop_dmc_in_rw_intr_mask_default = 0x00000000,
311 regk_iop_dmc_in_rw_stream_ctrl_default = 0x00000000,
312 regk_iop_dmc_in_save_down = 0x00000020,
313 regk_iop_dmc_in_save_up = 0x00000020,
314 regk_iop_dmc_in_set_reg = 0x00000050,
315 regk_iop_dmc_in_set_w_size1 = 0x00000190,
316 regk_iop_dmc_in_set_w_size2 = 0x000001a0,
317 regk_iop_dmc_in_set_w_size4 = 0x000001c0,
318 regk_iop_dmc_in_store_c = 0x00000002,
319 regk_iop_dmc_in_store_descr = 0x00000000,
320 regk_iop_dmc_in_store_g = 0x00000004,
321 regk_iop_dmc_in_store_md = 0x00000001,
322 regk_iop_dmc_in_update_down = 0x00000020,
323 regk_iop_dmc_in_yes = 0x00000001
324};
325#endif /* __iop_dmc_in_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h
new file mode 100644
index 000000000000..938a0d4c4604
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h
@@ -0,0 +1,326 @@
1#ifndef __iop_dmc_out_defs_h
2#define __iop_dmc_out_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_dmc_out.r
7 * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
8 * last modfied: Mon Apr 11 16:08:45 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r
11 * id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_dmc_out */
86
87/* Register rw_cfg, scope iop_dmc_out, type rw */
88typedef struct {
89 unsigned int trf_lim : 16;
90 unsigned int last_at_trf_lim : 1;
91 unsigned int dth_intr : 3;
92 unsigned int dummy1 : 12;
93} reg_iop_dmc_out_rw_cfg;
94#define REG_RD_ADDR_iop_dmc_out_rw_cfg 0
95#define REG_WR_ADDR_iop_dmc_out_rw_cfg 0
96
97/* Register rw_ctrl, scope iop_dmc_out, type rw */
98typedef struct {
99 unsigned int dif_en : 1;
100 unsigned int dif_dis : 1;
101 unsigned int dummy1 : 30;
102} reg_iop_dmc_out_rw_ctrl;
103#define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4
104#define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4
105
106/* Register r_stat, scope iop_dmc_out, type r */
107typedef struct {
108 unsigned int dif_en : 1;
109 unsigned int dummy1 : 31;
110} reg_iop_dmc_out_r_stat;
111#define REG_RD_ADDR_iop_dmc_out_r_stat 8
112
113/* Register rw_stream_cmd, scope iop_dmc_out, type rw */
114typedef struct {
115 unsigned int cmd : 10;
116 unsigned int dummy1 : 6;
117 unsigned int n : 8;
118 unsigned int dummy2 : 8;
119} reg_iop_dmc_out_rw_stream_cmd;
120#define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12
121#define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12
122
123/* Register rs_stream_data, scope iop_dmc_out, type rs */
124typedef unsigned int reg_iop_dmc_out_rs_stream_data;
125#define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16
126
127/* Register r_stream_data, scope iop_dmc_out, type r */
128typedef unsigned int reg_iop_dmc_out_r_stream_data;
129#define REG_RD_ADDR_iop_dmc_out_r_stream_data 20
130
131/* Register r_stream_stat, scope iop_dmc_out, type r */
132typedef struct {
133 unsigned int dth : 7;
134 unsigned int dummy1 : 9;
135 unsigned int dv : 1;
136 unsigned int all_avail : 1;
137 unsigned int last : 1;
138 unsigned int size : 3;
139 unsigned int data_md_valid : 1;
140 unsigned int ctxt_md_valid : 1;
141 unsigned int group_md_valid : 1;
142 unsigned int stream_busy : 1;
143 unsigned int cmd_rdy : 1;
144 unsigned int cmd_rq : 1;
145 unsigned int dummy2 : 4;
146} reg_iop_dmc_out_r_stream_stat;
147#define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24
148
149/* Register r_data_descr, scope iop_dmc_out, type r */
150typedef struct {
151 unsigned int ctrl : 8;
152 unsigned int stat : 8;
153 unsigned int md : 16;
154} reg_iop_dmc_out_r_data_descr;
155#define REG_RD_ADDR_iop_dmc_out_r_data_descr 28
156
157/* Register r_ctxt_descr, scope iop_dmc_out, type r */
158typedef struct {
159 unsigned int ctrl : 8;
160 unsigned int stat : 8;
161 unsigned int md0 : 16;
162} reg_iop_dmc_out_r_ctxt_descr;
163#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32
164
165/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
166typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1;
167#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36
168
169/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
170typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2;
171#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40
172
173/* Register r_group_descr, scope iop_dmc_out, type r */
174typedef struct {
175 unsigned int ctrl : 8;
176 unsigned int stat : 8;
177 unsigned int md : 16;
178} reg_iop_dmc_out_r_group_descr;
179#define REG_RD_ADDR_iop_dmc_out_r_group_descr 52
180
181/* Register rw_data_descr, scope iop_dmc_out, type rw */
182typedef struct {
183 unsigned int dummy1 : 16;
184 unsigned int md : 16;
185} reg_iop_dmc_out_rw_data_descr;
186#define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56
187#define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56
188
189/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
190typedef struct {
191 unsigned int dummy1 : 16;
192 unsigned int md0 : 16;
193} reg_iop_dmc_out_rw_ctxt_descr;
194#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60
195#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60
196
197/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
198typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1;
199#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
200#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
201
202/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
203typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2;
204#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
205#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
206
207/* Register rw_group_descr, scope iop_dmc_out, type rw */
208typedef struct {
209 unsigned int dummy1 : 16;
210 unsigned int md : 16;
211} reg_iop_dmc_out_rw_group_descr;
212#define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80
213#define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80
214
215/* Register rw_intr_mask, scope iop_dmc_out, type rw */
216typedef struct {
217 unsigned int data_md : 1;
218 unsigned int ctxt_md : 1;
219 unsigned int group_md : 1;
220 unsigned int cmd_rdy : 1;
221 unsigned int dth : 1;
222 unsigned int dv : 1;
223 unsigned int last_data : 1;
224 unsigned int trf_lim : 1;
225 unsigned int cmd_rq : 1;
226 unsigned int dummy1 : 23;
227} reg_iop_dmc_out_rw_intr_mask;
228#define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84
229#define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84
230
231/* Register rw_ack_intr, scope iop_dmc_out, type rw */
232typedef struct {
233 unsigned int data_md : 1;
234 unsigned int ctxt_md : 1;
235 unsigned int group_md : 1;
236 unsigned int cmd_rdy : 1;
237 unsigned int dth : 1;
238 unsigned int dv : 1;
239 unsigned int last_data : 1;
240 unsigned int trf_lim : 1;
241 unsigned int cmd_rq : 1;
242 unsigned int dummy1 : 23;
243} reg_iop_dmc_out_rw_ack_intr;
244#define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88
245#define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88
246
247/* Register r_intr, scope iop_dmc_out, type r */
248typedef struct {
249 unsigned int data_md : 1;
250 unsigned int ctxt_md : 1;
251 unsigned int group_md : 1;
252 unsigned int cmd_rdy : 1;
253 unsigned int dth : 1;
254 unsigned int dv : 1;
255 unsigned int last_data : 1;
256 unsigned int trf_lim : 1;
257 unsigned int cmd_rq : 1;
258 unsigned int dummy1 : 23;
259} reg_iop_dmc_out_r_intr;
260#define REG_RD_ADDR_iop_dmc_out_r_intr 92
261
262/* Register r_masked_intr, scope iop_dmc_out, type r */
263typedef struct {
264 unsigned int data_md : 1;
265 unsigned int ctxt_md : 1;
266 unsigned int group_md : 1;
267 unsigned int cmd_rdy : 1;
268 unsigned int dth : 1;
269 unsigned int dv : 1;
270 unsigned int last_data : 1;
271 unsigned int trf_lim : 1;
272 unsigned int cmd_rq : 1;
273 unsigned int dummy1 : 23;
274} reg_iop_dmc_out_r_masked_intr;
275#define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96
276
277
278/* Constants */
279enum {
280 regk_iop_dmc_out_ack_pkt = 0x00000100,
281 regk_iop_dmc_out_array = 0x00000008,
282 regk_iop_dmc_out_burst = 0x00000020,
283 regk_iop_dmc_out_copy_next = 0x00000010,
284 regk_iop_dmc_out_copy_up = 0x00000020,
285 regk_iop_dmc_out_dis_c = 0x00000010,
286 regk_iop_dmc_out_dis_g = 0x00000020,
287 regk_iop_dmc_out_lim1 = 0x00000000,
288 regk_iop_dmc_out_lim16 = 0x00000004,
289 regk_iop_dmc_out_lim2 = 0x00000001,
290 regk_iop_dmc_out_lim32 = 0x00000005,
291 regk_iop_dmc_out_lim4 = 0x00000002,
292 regk_iop_dmc_out_lim64 = 0x00000006,
293 regk_iop_dmc_out_lim8 = 0x00000003,
294 regk_iop_dmc_out_load_c = 0x00000200,
295 regk_iop_dmc_out_load_c_n = 0x00000280,
296 regk_iop_dmc_out_load_c_next = 0x00000240,
297 regk_iop_dmc_out_load_d = 0x00000140,
298 regk_iop_dmc_out_load_g = 0x00000300,
299 regk_iop_dmc_out_load_g_down = 0x000003c0,
300 regk_iop_dmc_out_load_g_next = 0x00000340,
301 regk_iop_dmc_out_load_g_up = 0x00000380,
302 regk_iop_dmc_out_next_en = 0x00000010,
303 regk_iop_dmc_out_next_pkt = 0x00000010,
304 regk_iop_dmc_out_no = 0x00000000,
305 regk_iop_dmc_out_restore = 0x00000020,
306 regk_iop_dmc_out_rw_cfg_default = 0x00000000,
307 regk_iop_dmc_out_rw_ctxt_descr_default = 0x00000000,
308 regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000,
309 regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000,
310 regk_iop_dmc_out_rw_data_descr_default = 0x00000000,
311 regk_iop_dmc_out_rw_group_descr_default = 0x00000000,
312 regk_iop_dmc_out_rw_intr_mask_default = 0x00000000,
313 regk_iop_dmc_out_save_down = 0x00000020,
314 regk_iop_dmc_out_save_up = 0x00000020,
315 regk_iop_dmc_out_set_reg = 0x00000050,
316 regk_iop_dmc_out_set_w_size1 = 0x00000190,
317 regk_iop_dmc_out_set_w_size2 = 0x000001a0,
318 regk_iop_dmc_out_set_w_size4 = 0x000001c0,
319 regk_iop_dmc_out_store_c = 0x00000002,
320 regk_iop_dmc_out_store_descr = 0x00000000,
321 regk_iop_dmc_out_store_g = 0x00000004,
322 regk_iop_dmc_out_store_md = 0x00000001,
323 regk_iop_dmc_out_update_down = 0x00000020,
324 regk_iop_dmc_out_yes = 0x00000001
325};
326#endif /* __iop_dmc_out_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h
new file mode 100644
index 000000000000..e0c982b263fa
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h
@@ -0,0 +1,255 @@
1#ifndef __iop_fifo_in_defs_h
2#define __iop_fifo_in_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_fifo_in.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:10:07 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r
11 * id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_fifo_in */
86
87/* Register rw_cfg, scope iop_fifo_in, type rw */
88typedef struct {
89 unsigned int avail_lim : 3;
90 unsigned int byte_order : 2;
91 unsigned int trig : 2;
92 unsigned int last_dis_dif_in : 1;
93 unsigned int mode : 2;
94 unsigned int dummy1 : 22;
95} reg_iop_fifo_in_rw_cfg;
96#define REG_RD_ADDR_iop_fifo_in_rw_cfg 0
97#define REG_WR_ADDR_iop_fifo_in_rw_cfg 0
98
99/* Register rw_ctrl, scope iop_fifo_in, type rw */
100typedef struct {
101 unsigned int dif_in_en : 1;
102 unsigned int dif_out_en : 1;
103 unsigned int dummy1 : 30;
104} reg_iop_fifo_in_rw_ctrl;
105#define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4
106#define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4
107
108/* Register r_stat, scope iop_fifo_in, type r */
109typedef struct {
110 unsigned int avail_bytes : 4;
111 unsigned int last : 8;
112 unsigned int dif_in_en : 1;
113 unsigned int dif_out_en : 1;
114 unsigned int dummy1 : 18;
115} reg_iop_fifo_in_r_stat;
116#define REG_RD_ADDR_iop_fifo_in_r_stat 8
117
118/* Register rs_rd1byte, scope iop_fifo_in, type rs */
119typedef struct {
120 unsigned int data : 8;
121 unsigned int dummy1 : 24;
122} reg_iop_fifo_in_rs_rd1byte;
123#define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12
124
125/* Register r_rd1byte, scope iop_fifo_in, type r */
126typedef struct {
127 unsigned int data : 8;
128 unsigned int dummy1 : 24;
129} reg_iop_fifo_in_r_rd1byte;
130#define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16
131
132/* Register rs_rd2byte, scope iop_fifo_in, type rs */
133typedef struct {
134 unsigned int data : 16;
135 unsigned int dummy1 : 16;
136} reg_iop_fifo_in_rs_rd2byte;
137#define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20
138
139/* Register r_rd2byte, scope iop_fifo_in, type r */
140typedef struct {
141 unsigned int data : 16;
142 unsigned int dummy1 : 16;
143} reg_iop_fifo_in_r_rd2byte;
144#define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24
145
146/* Register rs_rd3byte, scope iop_fifo_in, type rs */
147typedef struct {
148 unsigned int data : 24;
149 unsigned int dummy1 : 8;
150} reg_iop_fifo_in_rs_rd3byte;
151#define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28
152
153/* Register r_rd3byte, scope iop_fifo_in, type r */
154typedef struct {
155 unsigned int data : 24;
156 unsigned int dummy1 : 8;
157} reg_iop_fifo_in_r_rd3byte;
158#define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32
159
160/* Register rs_rd4byte, scope iop_fifo_in, type rs */
161typedef struct {
162 unsigned int data : 32;
163} reg_iop_fifo_in_rs_rd4byte;
164#define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36
165
166/* Register r_rd4byte, scope iop_fifo_in, type r */
167typedef struct {
168 unsigned int data : 32;
169} reg_iop_fifo_in_r_rd4byte;
170#define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40
171
172/* Register rw_set_last, scope iop_fifo_in, type rw */
173typedef unsigned int reg_iop_fifo_in_rw_set_last;
174#define REG_RD_ADDR_iop_fifo_in_rw_set_last 44
175#define REG_WR_ADDR_iop_fifo_in_rw_set_last 44
176
177/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
178typedef struct {
179 unsigned int last : 2;
180 unsigned int dummy1 : 30;
181} reg_iop_fifo_in_rw_strb_dif_in;
182#define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48
183#define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48
184
185/* Register rw_intr_mask, scope iop_fifo_in, type rw */
186typedef struct {
187 unsigned int urun : 1;
188 unsigned int last_data : 1;
189 unsigned int dav : 1;
190 unsigned int avail : 1;
191 unsigned int orun : 1;
192 unsigned int dummy1 : 27;
193} reg_iop_fifo_in_rw_intr_mask;
194#define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52
195#define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52
196
197/* Register rw_ack_intr, scope iop_fifo_in, type rw */
198typedef struct {
199 unsigned int urun : 1;
200 unsigned int last_data : 1;
201 unsigned int dav : 1;
202 unsigned int avail : 1;
203 unsigned int orun : 1;
204 unsigned int dummy1 : 27;
205} reg_iop_fifo_in_rw_ack_intr;
206#define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56
207#define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56
208
209/* Register r_intr, scope iop_fifo_in, type r */
210typedef struct {
211 unsigned int urun : 1;
212 unsigned int last_data : 1;
213 unsigned int dav : 1;
214 unsigned int avail : 1;
215 unsigned int orun : 1;
216 unsigned int dummy1 : 27;
217} reg_iop_fifo_in_r_intr;
218#define REG_RD_ADDR_iop_fifo_in_r_intr 60
219
220/* Register r_masked_intr, scope iop_fifo_in, type r */
221typedef struct {
222 unsigned int urun : 1;
223 unsigned int last_data : 1;
224 unsigned int dav : 1;
225 unsigned int avail : 1;
226 unsigned int orun : 1;
227 unsigned int dummy1 : 27;
228} reg_iop_fifo_in_r_masked_intr;
229#define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64
230
231
232/* Constants */
233enum {
234 regk_iop_fifo_in_dif_in = 0x00000002,
235 regk_iop_fifo_in_hi = 0x00000000,
236 regk_iop_fifo_in_neg = 0x00000002,
237 regk_iop_fifo_in_no = 0x00000000,
238 regk_iop_fifo_in_order16 = 0x00000001,
239 regk_iop_fifo_in_order24 = 0x00000002,
240 regk_iop_fifo_in_order32 = 0x00000003,
241 regk_iop_fifo_in_order8 = 0x00000000,
242 regk_iop_fifo_in_pos = 0x00000001,
243 regk_iop_fifo_in_pos_neg = 0x00000003,
244 regk_iop_fifo_in_rw_cfg_default = 0x00000024,
245 regk_iop_fifo_in_rw_ctrl_default = 0x00000000,
246 regk_iop_fifo_in_rw_intr_mask_default = 0x00000000,
247 regk_iop_fifo_in_rw_set_last_default = 0x00000000,
248 regk_iop_fifo_in_rw_strb_dif_in_default = 0x00000000,
249 regk_iop_fifo_in_size16 = 0x00000002,
250 regk_iop_fifo_in_size24 = 0x00000001,
251 regk_iop_fifo_in_size32 = 0x00000000,
252 regk_iop_fifo_in_size8 = 0x00000003,
253 regk_iop_fifo_in_yes = 0x00000001
254};
255#endif /* __iop_fifo_in_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h
new file mode 100644
index 000000000000..798ac95870e9
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h
@@ -0,0 +1,164 @@
1#ifndef __iop_fifo_in_extra_defs_h
2#define __iop_fifo_in_extra_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:10:08 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
11 * id: $Id: iop_fifo_in_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_fifo_in_extra */
86
87/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
88typedef unsigned int reg_iop_fifo_in_extra_rw_wr_data;
89#define REG_RD_ADDR_iop_fifo_in_extra_rw_wr_data 0
90#define REG_WR_ADDR_iop_fifo_in_extra_rw_wr_data 0
91
92/* Register r_stat, scope iop_fifo_in_extra, type r */
93typedef struct {
94 unsigned int avail_bytes : 4;
95 unsigned int last : 8;
96 unsigned int dif_in_en : 1;
97 unsigned int dif_out_en : 1;
98 unsigned int dummy1 : 18;
99} reg_iop_fifo_in_extra_r_stat;
100#define REG_RD_ADDR_iop_fifo_in_extra_r_stat 4
101
102/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
103typedef struct {
104 unsigned int last : 2;
105 unsigned int dummy1 : 30;
106} reg_iop_fifo_in_extra_rw_strb_dif_in;
107#define REG_RD_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8
108#define REG_WR_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8
109
110/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
111typedef struct {
112 unsigned int urun : 1;
113 unsigned int last_data : 1;
114 unsigned int dav : 1;
115 unsigned int avail : 1;
116 unsigned int orun : 1;
117 unsigned int dummy1 : 27;
118} reg_iop_fifo_in_extra_rw_intr_mask;
119#define REG_RD_ADDR_iop_fifo_in_extra_rw_intr_mask 12
120#define REG_WR_ADDR_iop_fifo_in_extra_rw_intr_mask 12
121
122/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
123typedef struct {
124 unsigned int urun : 1;
125 unsigned int last_data : 1;
126 unsigned int dav : 1;
127 unsigned int avail : 1;
128 unsigned int orun : 1;
129 unsigned int dummy1 : 27;
130} reg_iop_fifo_in_extra_rw_ack_intr;
131#define REG_RD_ADDR_iop_fifo_in_extra_rw_ack_intr 16
132#define REG_WR_ADDR_iop_fifo_in_extra_rw_ack_intr 16
133
134/* Register r_intr, scope iop_fifo_in_extra, type r */
135typedef struct {
136 unsigned int urun : 1;
137 unsigned int last_data : 1;
138 unsigned int dav : 1;
139 unsigned int avail : 1;
140 unsigned int orun : 1;
141 unsigned int dummy1 : 27;
142} reg_iop_fifo_in_extra_r_intr;
143#define REG_RD_ADDR_iop_fifo_in_extra_r_intr 20
144
145/* Register r_masked_intr, scope iop_fifo_in_extra, type r */
146typedef struct {
147 unsigned int urun : 1;
148 unsigned int last_data : 1;
149 unsigned int dav : 1;
150 unsigned int avail : 1;
151 unsigned int orun : 1;
152 unsigned int dummy1 : 27;
153} reg_iop_fifo_in_extra_r_masked_intr;
154#define REG_RD_ADDR_iop_fifo_in_extra_r_masked_intr 24
155
156
157/* Constants */
158enum {
159 regk_iop_fifo_in_extra_fifo_in = 0x00000002,
160 regk_iop_fifo_in_extra_no = 0x00000000,
161 regk_iop_fifo_in_extra_rw_intr_mask_default = 0x00000000,
162 regk_iop_fifo_in_extra_yes = 0x00000001
163};
164#endif /* __iop_fifo_in_extra_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h
new file mode 100644
index 000000000000..833e10f02526
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h
@@ -0,0 +1,278 @@
1#ifndef __iop_fifo_out_defs_h
2#define __iop_fifo_out_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_fifo_out.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:10:09 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r
11 * id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_fifo_out */
86
87/* Register rw_cfg, scope iop_fifo_out, type rw */
88typedef struct {
89 unsigned int free_lim : 3;
90 unsigned int byte_order : 2;
91 unsigned int trig : 2;
92 unsigned int last_dis_dif_in : 1;
93 unsigned int mode : 2;
94 unsigned int delay_out_last : 1;
95 unsigned int last_dis_dif_out : 1;
96 unsigned int dummy1 : 20;
97} reg_iop_fifo_out_rw_cfg;
98#define REG_RD_ADDR_iop_fifo_out_rw_cfg 0
99#define REG_WR_ADDR_iop_fifo_out_rw_cfg 0
100
101/* Register rw_ctrl, scope iop_fifo_out, type rw */
102typedef struct {
103 unsigned int dif_in_en : 1;
104 unsigned int dif_out_en : 1;
105 unsigned int dummy1 : 30;
106} reg_iop_fifo_out_rw_ctrl;
107#define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4
108#define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4
109
110/* Register r_stat, scope iop_fifo_out, type r */
111typedef struct {
112 unsigned int avail_bytes : 4;
113 unsigned int last : 8;
114 unsigned int dif_in_en : 1;
115 unsigned int dif_out_en : 1;
116 unsigned int zero_data_last : 1;
117 unsigned int dummy1 : 17;
118} reg_iop_fifo_out_r_stat;
119#define REG_RD_ADDR_iop_fifo_out_r_stat 8
120
121/* Register rw_wr1byte, scope iop_fifo_out, type rw */
122typedef struct {
123 unsigned int data : 8;
124 unsigned int dummy1 : 24;
125} reg_iop_fifo_out_rw_wr1byte;
126#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12
127#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12
128
129/* Register rw_wr2byte, scope iop_fifo_out, type rw */
130typedef struct {
131 unsigned int data : 16;
132 unsigned int dummy1 : 16;
133} reg_iop_fifo_out_rw_wr2byte;
134#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16
135#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16
136
137/* Register rw_wr3byte, scope iop_fifo_out, type rw */
138typedef struct {
139 unsigned int data : 24;
140 unsigned int dummy1 : 8;
141} reg_iop_fifo_out_rw_wr3byte;
142#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20
143#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20
144
145/* Register rw_wr4byte, scope iop_fifo_out, type rw */
146typedef struct {
147 unsigned int data : 32;
148} reg_iop_fifo_out_rw_wr4byte;
149#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24
150#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24
151
152/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
153typedef struct {
154 unsigned int data : 8;
155 unsigned int dummy1 : 24;
156} reg_iop_fifo_out_rw_wr1byte_last;
157#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28
158#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28
159
160/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
161typedef struct {
162 unsigned int data : 16;
163 unsigned int dummy1 : 16;
164} reg_iop_fifo_out_rw_wr2byte_last;
165#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32
166#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32
167
168/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
169typedef struct {
170 unsigned int data : 24;
171 unsigned int dummy1 : 8;
172} reg_iop_fifo_out_rw_wr3byte_last;
173#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36
174#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36
175
176/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
177typedef struct {
178 unsigned int data : 32;
179} reg_iop_fifo_out_rw_wr4byte_last;
180#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40
181#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40
182
183/* Register rw_set_last, scope iop_fifo_out, type rw */
184typedef unsigned int reg_iop_fifo_out_rw_set_last;
185#define REG_RD_ADDR_iop_fifo_out_rw_set_last 44
186#define REG_WR_ADDR_iop_fifo_out_rw_set_last 44
187
188/* Register rs_rd_data, scope iop_fifo_out, type rs */
189typedef unsigned int reg_iop_fifo_out_rs_rd_data;
190#define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48
191
192/* Register r_rd_data, scope iop_fifo_out, type r */
193typedef unsigned int reg_iop_fifo_out_r_rd_data;
194#define REG_RD_ADDR_iop_fifo_out_r_rd_data 52
195
196/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
197typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out;
198#define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56
199#define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56
200
201/* Register rw_intr_mask, scope iop_fifo_out, type rw */
202typedef struct {
203 unsigned int urun : 1;
204 unsigned int last_data : 1;
205 unsigned int dav : 1;
206 unsigned int free : 1;
207 unsigned int orun : 1;
208 unsigned int dummy1 : 27;
209} reg_iop_fifo_out_rw_intr_mask;
210#define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60
211#define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60
212
213/* Register rw_ack_intr, scope iop_fifo_out, type rw */
214typedef struct {
215 unsigned int urun : 1;
216 unsigned int last_data : 1;
217 unsigned int dav : 1;
218 unsigned int free : 1;
219 unsigned int orun : 1;
220 unsigned int dummy1 : 27;
221} reg_iop_fifo_out_rw_ack_intr;
222#define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64
223#define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64
224
225/* Register r_intr, scope iop_fifo_out, type r */
226typedef struct {
227 unsigned int urun : 1;
228 unsigned int last_data : 1;
229 unsigned int dav : 1;
230 unsigned int free : 1;
231 unsigned int orun : 1;
232 unsigned int dummy1 : 27;
233} reg_iop_fifo_out_r_intr;
234#define REG_RD_ADDR_iop_fifo_out_r_intr 68
235
236/* Register r_masked_intr, scope iop_fifo_out, type r */
237typedef struct {
238 unsigned int urun : 1;
239 unsigned int last_data : 1;
240 unsigned int dav : 1;
241 unsigned int free : 1;
242 unsigned int orun : 1;
243 unsigned int dummy1 : 27;
244} reg_iop_fifo_out_r_masked_intr;
245#define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72
246
247
248/* Constants */
249enum {
250 regk_iop_fifo_out_hi = 0x00000000,
251 regk_iop_fifo_out_neg = 0x00000002,
252 regk_iop_fifo_out_no = 0x00000000,
253 regk_iop_fifo_out_order16 = 0x00000001,
254 regk_iop_fifo_out_order24 = 0x00000002,
255 regk_iop_fifo_out_order32 = 0x00000003,
256 regk_iop_fifo_out_order8 = 0x00000000,
257 regk_iop_fifo_out_pos = 0x00000001,
258 regk_iop_fifo_out_pos_neg = 0x00000003,
259 regk_iop_fifo_out_rw_cfg_default = 0x00000024,
260 regk_iop_fifo_out_rw_ctrl_default = 0x00000000,
261 regk_iop_fifo_out_rw_intr_mask_default = 0x00000000,
262 regk_iop_fifo_out_rw_set_last_default = 0x00000000,
263 regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000,
264 regk_iop_fifo_out_rw_wr1byte_default = 0x00000000,
265 regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000,
266 regk_iop_fifo_out_rw_wr2byte_default = 0x00000000,
267 regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000,
268 regk_iop_fifo_out_rw_wr3byte_default = 0x00000000,
269 regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000,
270 regk_iop_fifo_out_rw_wr4byte_default = 0x00000000,
271 regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000,
272 regk_iop_fifo_out_size16 = 0x00000002,
273 regk_iop_fifo_out_size24 = 0x00000001,
274 regk_iop_fifo_out_size32 = 0x00000000,
275 regk_iop_fifo_out_size8 = 0x00000003,
276 regk_iop_fifo_out_yes = 0x00000001
277};
278#endif /* __iop_fifo_out_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h
new file mode 100644
index 000000000000..4a840aae84ee
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h
@@ -0,0 +1,164 @@
1#ifndef __iop_fifo_out_extra_defs_h
2#define __iop_fifo_out_extra_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:10:10 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
11 * id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_fifo_out_extra */
86
87/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
88typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data;
89#define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0
90
91/* Register r_rd_data, scope iop_fifo_out_extra, type r */
92typedef unsigned int reg_iop_fifo_out_extra_r_rd_data;
93#define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4
94
95/* Register r_stat, scope iop_fifo_out_extra, type r */
96typedef struct {
97 unsigned int avail_bytes : 4;
98 unsigned int last : 8;
99 unsigned int dif_in_en : 1;
100 unsigned int dif_out_en : 1;
101 unsigned int zero_data_last : 1;
102 unsigned int dummy1 : 17;
103} reg_iop_fifo_out_extra_r_stat;
104#define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8
105
106/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
107typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out;
108#define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
109#define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
110
111/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
112typedef struct {
113 unsigned int urun : 1;
114 unsigned int last_data : 1;
115 unsigned int dav : 1;
116 unsigned int free : 1;
117 unsigned int orun : 1;
118 unsigned int dummy1 : 27;
119} reg_iop_fifo_out_extra_rw_intr_mask;
120#define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16
121#define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16
122
123/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
124typedef struct {
125 unsigned int urun : 1;
126 unsigned int last_data : 1;
127 unsigned int dav : 1;
128 unsigned int free : 1;
129 unsigned int orun : 1;
130 unsigned int dummy1 : 27;
131} reg_iop_fifo_out_extra_rw_ack_intr;
132#define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20
133#define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20
134
135/* Register r_intr, scope iop_fifo_out_extra, type r */
136typedef struct {
137 unsigned int urun : 1;
138 unsigned int last_data : 1;
139 unsigned int dav : 1;
140 unsigned int free : 1;
141 unsigned int orun : 1;
142 unsigned int dummy1 : 27;
143} reg_iop_fifo_out_extra_r_intr;
144#define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24
145
146/* Register r_masked_intr, scope iop_fifo_out_extra, type r */
147typedef struct {
148 unsigned int urun : 1;
149 unsigned int last_data : 1;
150 unsigned int dav : 1;
151 unsigned int free : 1;
152 unsigned int orun : 1;
153 unsigned int dummy1 : 27;
154} reg_iop_fifo_out_extra_r_masked_intr;
155#define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28
156
157
158/* Constants */
159enum {
160 regk_iop_fifo_out_extra_no = 0x00000000,
161 regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000,
162 regk_iop_fifo_out_extra_yes = 0x00000001
163};
164#endif /* __iop_fifo_out_extra_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h
new file mode 100644
index 000000000000..c2b0ba1be60f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h
@@ -0,0 +1,190 @@
1#ifndef __iop_mpu_defs_h
2#define __iop_mpu_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_mpu.r
7 * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp
8 * last modfied: Mon Apr 11 16:08:45 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_mpu_defs.h ../../inst/io_proc/rtl/iop_mpu.r
11 * id: $Id: iop_mpu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_mpu */
86
87#define STRIDE_iop_mpu_rw_r 4
88/* Register rw_r, scope iop_mpu, type rw */
89typedef unsigned int reg_iop_mpu_rw_r;
90#define REG_RD_ADDR_iop_mpu_rw_r 0
91#define REG_WR_ADDR_iop_mpu_rw_r 0
92
93/* Register rw_ctrl, scope iop_mpu, type rw */
94typedef struct {
95 unsigned int en : 1;
96 unsigned int dummy1 : 31;
97} reg_iop_mpu_rw_ctrl;
98#define REG_RD_ADDR_iop_mpu_rw_ctrl 128
99#define REG_WR_ADDR_iop_mpu_rw_ctrl 128
100
101/* Register r_pc, scope iop_mpu, type r */
102typedef struct {
103 unsigned int addr : 12;
104 unsigned int dummy1 : 20;
105} reg_iop_mpu_r_pc;
106#define REG_RD_ADDR_iop_mpu_r_pc 132
107
108/* Register r_stat, scope iop_mpu, type r */
109typedef struct {
110 unsigned int instr_reg_busy : 1;
111 unsigned int intr_busy : 1;
112 unsigned int intr_vect : 16;
113 unsigned int dummy1 : 14;
114} reg_iop_mpu_r_stat;
115#define REG_RD_ADDR_iop_mpu_r_stat 136
116
117/* Register rw_instr, scope iop_mpu, type rw */
118typedef unsigned int reg_iop_mpu_rw_instr;
119#define REG_RD_ADDR_iop_mpu_rw_instr 140
120#define REG_WR_ADDR_iop_mpu_rw_instr 140
121
122/* Register rw_immediate, scope iop_mpu, type rw */
123typedef unsigned int reg_iop_mpu_rw_immediate;
124#define REG_RD_ADDR_iop_mpu_rw_immediate 144
125#define REG_WR_ADDR_iop_mpu_rw_immediate 144
126
127/* Register r_trace, scope iop_mpu, type r */
128typedef struct {
129 unsigned int intr_vect : 16;
130 unsigned int pc : 12;
131 unsigned int en : 1;
132 unsigned int instr_reg_busy : 1;
133 unsigned int intr_busy : 1;
134 unsigned int dummy1 : 1;
135} reg_iop_mpu_r_trace;
136#define REG_RD_ADDR_iop_mpu_r_trace 148
137
138/* Register r_wr_stat, scope iop_mpu, type r */
139typedef struct {
140 unsigned int r0 : 1;
141 unsigned int r1 : 1;
142 unsigned int r2 : 1;
143 unsigned int r3 : 1;
144 unsigned int r4 : 1;
145 unsigned int r5 : 1;
146 unsigned int r6 : 1;
147 unsigned int r7 : 1;
148 unsigned int r8 : 1;
149 unsigned int r9 : 1;
150 unsigned int r10 : 1;
151 unsigned int r11 : 1;
152 unsigned int r12 : 1;
153 unsigned int r13 : 1;
154 unsigned int r14 : 1;
155 unsigned int r15 : 1;
156 unsigned int dummy1 : 16;
157} reg_iop_mpu_r_wr_stat;
158#define REG_RD_ADDR_iop_mpu_r_wr_stat 152
159
160#define STRIDE_iop_mpu_rw_thread 4
161/* Register rw_thread, scope iop_mpu, type rw */
162typedef struct {
163 unsigned int addr : 12;
164 unsigned int dummy1 : 20;
165} reg_iop_mpu_rw_thread;
166#define REG_RD_ADDR_iop_mpu_rw_thread 156
167#define REG_WR_ADDR_iop_mpu_rw_thread 156
168
169#define STRIDE_iop_mpu_rw_intr 4
170/* Register rw_intr, scope iop_mpu, type rw */
171typedef struct {
172 unsigned int addr : 12;
173 unsigned int dummy1 : 20;
174} reg_iop_mpu_rw_intr;
175#define REG_RD_ADDR_iop_mpu_rw_intr 196
176#define REG_WR_ADDR_iop_mpu_rw_intr 196
177
178
179/* Constants */
180enum {
181 regk_iop_mpu_no = 0x00000000,
182 regk_iop_mpu_r_pc_default = 0x00000000,
183 regk_iop_mpu_rw_ctrl_default = 0x00000000,
184 regk_iop_mpu_rw_intr_size = 0x00000010,
185 regk_iop_mpu_rw_r_size = 0x00000010,
186 regk_iop_mpu_rw_thread_default = 0x00000000,
187 regk_iop_mpu_rw_thread_size = 0x00000004,
188 regk_iop_mpu_yes = 0x00000001
189};
190#endif /* __iop_mpu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h
new file mode 100644
index 000000000000..2ec897ced166
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h
@@ -0,0 +1,764 @@
1/* ************************************************************************* */
2/* This file is autogenerated by IOPASM Version 1.2 */
3/* DO NOT EDIT THIS FILE - All changes will be lost! */
4/* ************************************************************************* */
5
6
7
8#ifndef __IOP_MPU_MACROS_H__
9#define __IOP_MPU_MACROS_H__
10
11
12/* ************************************************************************* */
13/* REGISTER DEFINITIONS */
14/* ************************************************************************* */
15#define MPU_R0 (0x0)
16#define MPU_R1 (0x1)
17#define MPU_R2 (0x2)
18#define MPU_R3 (0x3)
19#define MPU_R4 (0x4)
20#define MPU_R5 (0x5)
21#define MPU_R6 (0x6)
22#define MPU_R7 (0x7)
23#define MPU_R8 (0x8)
24#define MPU_R9 (0x9)
25#define MPU_R10 (0xa)
26#define MPU_R11 (0xb)
27#define MPU_R12 (0xc)
28#define MPU_R13 (0xd)
29#define MPU_R14 (0xe)
30#define MPU_R15 (0xf)
31#define MPU_PC (0x2)
32#define MPU_WSTS (0x3)
33#define MPU_JADDR (0x4)
34#define MPU_IRP (0x5)
35#define MPU_SRP (0x6)
36#define MPU_T0 (0x8)
37#define MPU_T1 (0x9)
38#define MPU_T2 (0xa)
39#define MPU_T3 (0xb)
40#define MPU_I0 (0x10)
41#define MPU_I1 (0x11)
42#define MPU_I2 (0x12)
43#define MPU_I3 (0x13)
44#define MPU_I4 (0x14)
45#define MPU_I5 (0x15)
46#define MPU_I6 (0x16)
47#define MPU_I7 (0x17)
48#define MPU_I8 (0x18)
49#define MPU_I9 (0x19)
50#define MPU_I10 (0x1a)
51#define MPU_I11 (0x1b)
52#define MPU_I12 (0x1c)
53#define MPU_I13 (0x1d)
54#define MPU_I14 (0x1e)
55#define MPU_I15 (0x1f)
56#define MPU_P2 (0x2)
57#define MPU_P3 (0x3)
58#define MPU_P5 (0x5)
59#define MPU_P6 (0x6)
60#define MPU_P8 (0x8)
61#define MPU_P9 (0x9)
62#define MPU_P10 (0xa)
63#define MPU_P11 (0xb)
64#define MPU_P16 (0x10)
65#define MPU_P17 (0x12)
66#define MPU_P18 (0x12)
67#define MPU_P19 (0x13)
68#define MPU_P20 (0x14)
69#define MPU_P21 (0x15)
70#define MPU_P22 (0x16)
71#define MPU_P23 (0x17)
72#define MPU_P24 (0x18)
73#define MPU_P25 (0x19)
74#define MPU_P26 (0x1a)
75#define MPU_P27 (0x1b)
76#define MPU_P28 (0x1c)
77#define MPU_P29 (0x1d)
78#define MPU_P30 (0x1e)
79#define MPU_P31 (0x1f)
80#define MPU_P1 (0x1)
81#define MPU_REGA (0x1)
82
83
84
85/* ************************************************************************* */
86/* ADDRESS MACROS */
87/* ************************************************************************* */
88#define MK_DWORD_ADDR(ADDR) (ADDR >> 2)
89#define MK_BYTE_ADDR(ADDR) (ADDR)
90
91
92
93/* ************************************************************************* */
94/* INSTRUCTION MACROS */
95/* ************************************************************************* */
96#define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\
97 | ((N & ((1 << 5) - 1)) << 11)\
98 | ((D & ((1 << 5) - 1)) << 21))
99
100#define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\
101 | ((N & ((1 << 5) - 1)) << 11)\
102 | ((D & ((1 << 5) - 1)) << 21))
103
104#define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\
105 | ((N & ((1 << 5) - 1)) << 11)\
106 | ((D & ((1 << 5) - 1)) << 21))
107
108#define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\
109 | ((N & ((1 << 5) - 1)) << 11)\
110 | ((D & ((1 << 5) - 1)) << 21))
111
112#define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\
113 | ((N & ((1 << 5) - 1)) << 11)\
114 | ((D & ((1 << 5) - 1)) << 21))
115
116#define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\
117 | ((N & ((1 << 5) - 1)) << 11)\
118 | ((D & ((1 << 5) - 1)) << 21))
119
120#define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\
121 | ((N & ((1 << 5) - 1)) << 11)\
122 | ((D & ((1 << 5) - 1)) << 21))
123
124#define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\
125 | ((N & ((1 << 5) - 1)) << 11)\
126 | ((D & ((1 << 5) - 1)) << 21))
127
128#define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\
129 | ((N & ((1 << 16) - 1)) << 0)\
130 | ((D & ((1 << 5) - 1)) << 21))
131
132#define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\
133 | ((N & ((1 << 5) - 1)) << 16)\
134 | ((D & ((1 << 5) - 1)) << 21))
135
136#define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\
137 | ((D & ((1 << 5) - 1)) << 21))
138
139#define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
140
141#define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\
142 | ((D & ((1 << 5) - 1)) << 21))
143
144#define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
145
146#define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\
147 | ((D & ((1 << 5) - 1)) << 21))
148
149#define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
150
151#define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\
152 | ((D & ((1 << 5) - 1)) << 21))
153
154#define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
155
156#define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\
157 | ((D & ((1 << 5) - 1)) << 21))
158
159#define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
160
161#define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\
162 | ((D & ((1 << 5) - 1)) << 21))
163
164#define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
165
166#define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\
167 | ((D & ((1 << 5) - 1)) << 21))
168
169#define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
170
171#define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\
172 | ((D & ((1 << 5) - 1)) << 21))
173
174#define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
175
176#define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\
177 | ((N & ((1 << 5) - 1)) << 11)\
178 | ((D & ((1 << 5) - 1)) << 21))
179
180#define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\
181 | ((N & ((1 << 5) - 1)) << 11)\
182 | ((D & ((1 << 5) - 1)) << 21))
183
184#define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\
185 | ((N & ((1 << 5) - 1)) << 11)\
186 | ((D & ((1 << 5) - 1)) << 21))
187
188#define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\
189 | ((N & ((1 << 5) - 1)) << 11)\
190 | ((D & ((1 << 5) - 1)) << 21))
191
192#define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\
193 | ((N & ((1 << 5) - 1)) << 11)\
194 | ((D & ((1 << 5) - 1)) << 21))
195
196#define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\
197 | ((N & ((1 << 5) - 1)) << 11)\
198 | ((D & ((1 << 5) - 1)) << 21))
199
200#define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\
201 | ((N & ((1 << 5) - 1)) << 11)\
202 | ((D & ((1 << 5) - 1)) << 21))
203
204#define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\
205 | ((N & ((1 << 5) - 1)) << 11)\
206 | ((D & ((1 << 5) - 1)) << 21))
207
208#define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\
209 | ((N & ((1 << 16) - 1)) << 0)\
210 | ((D & ((1 << 5) - 1)) << 21))
211
212#define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\
213 | ((N & ((1 << 5) - 1)) << 16)\
214 | ((D & ((1 << 5) - 1)) << 21))
215
216#define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\
217 | ((D & ((1 << 5) - 1)) << 21))
218
219#define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
220
221#define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\
222 | ((D & ((1 << 5) - 1)) << 21))
223
224#define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
225
226#define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\
227 | ((D & ((1 << 5) - 1)) << 21))
228
229#define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
230
231#define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\
232 | ((D & ((1 << 5) - 1)) << 21))
233
234#define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
235
236#define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\
237 | ((D & ((1 << 5) - 1)) << 21))
238
239#define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
240
241#define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\
242 | ((D & ((1 << 5) - 1)) << 21))
243
244#define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
245
246#define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\
247 | ((D & ((1 << 5) - 1)) << 21))
248
249#define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
250
251#define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\
252 | ((D & ((1 << 5) - 1)) << 21))
253
254#define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
255
256#define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0))
257
258#define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11))
259
260#define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11))
261
262#define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\
263 | ((N & ((1 << 5) - 1)) << 21)\
264 | ((D & ((1 << 16) - 1)) << 0))
265
266#define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\
267 | ((N & ((1 << 5) - 1)) << 21)\
268 | ((D & ((1 << 16) - 1)) << 0))
269
270#define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\
271 | ((D & ((1 << 16) - 1)) << 0))
272
273#define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\
274 | ((D & ((1 << 16) - 1)) << 0))
275
276#define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\
277 | ((D & ((1 << 16) - 1)) << 0))
278
279#define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\
280 | ((D & ((1 << 16) - 1)) << 0))
281
282#define MPU_DI() (0x40000001)
283
284#define MPU_EI() (0x40000003)
285
286#define MPU_HALT() (0x40000002)
287
288#define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0))
289
290#define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11))
291
292#define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11))
293
294#define MPU_JNT() (0x61000000)
295
296#define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0))
297
298#define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11))
299
300#define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11))
301
302#define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\
303 | ((N & ((1 << 5) - 1)) << 11)\
304 | ((D & ((1 << 5) - 1)) << 21))
305
306#define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\
307 | ((N & ((1 << 5) - 1)) << 11)\
308 | ((D & ((1 << 5) - 1)) << 21))
309
310#define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\
311 | ((N & ((1 << 5) - 1)) << 11)\
312 | ((D & ((1 << 5) - 1)) << 21))
313
314#define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\
315 | ((N & ((1 << 5) - 1)) << 11)\
316 | ((D & ((1 << 5) - 1)) << 21))
317
318#define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\
319 | ((N & ((1 << 5) - 1)) << 11)\
320 | ((D & ((1 << 5) - 1)) << 21))
321
322#define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\
323 | ((N & ((1 << 5) - 1)) << 11)\
324 | ((D & ((1 << 5) - 1)) << 21))
325
326#define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\
327 | ((N & ((1 << 5) - 1)) << 11)\
328 | ((D & ((1 << 5) - 1)) << 21))
329
330#define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\
331 | ((N & ((1 << 5) - 1)) << 11)\
332 | ((D & ((1 << 5) - 1)) << 21))
333
334#define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\
335 | ((N & ((1 << 16) - 1)) << 0)\
336 | ((D & ((1 << 5) - 1)) << 21))
337
338#define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\
339 | ((N & ((1 << 5) - 1)) << 11)\
340 | ((D & ((1 << 5) - 1)) << 21))
341
342#define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\
343 | ((N & ((1 << 5) - 1)) << 11)\
344 | ((D & ((1 << 5) - 1)) << 21))
345
346#define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\
347 | ((N & ((1 << 5) - 1)) << 11)\
348 | ((D & ((1 << 5) - 1)) << 21))
349
350#define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\
351 | ((N & ((1 << 5) - 1)) << 11)\
352 | ((D & ((1 << 5) - 1)) << 21))
353
354#define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\
355 | ((N & ((1 << 5) - 1)) << 11)\
356 | ((D & ((1 << 5) - 1)) << 21))
357
358#define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\
359 | ((N & ((1 << 5) - 1)) << 11)\
360 | ((D & ((1 << 5) - 1)) << 21))
361
362#define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\
363 | ((N & ((1 << 5) - 1)) << 11)\
364 | ((D & ((1 << 5) - 1)) << 21))
365
366#define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\
367 | ((N & ((1 << 5) - 1)) << 11)\
368 | ((D & ((1 << 5) - 1)) << 21))
369
370#define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\
371 | ((N & ((1 << 16) - 1)) << 0)\
372 | ((D & ((1 << 5) - 1)) << 21))
373
374#define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\
375 | ((D & ((1 << 5) - 1)) << 16))
376
377#define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\
378 | ((D & ((1 << 5) - 1)) << 16))
379
380#define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
381 | ((D & ((1 << 5) - 1)) << 16))
382
383#define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
384 | ((D & ((1 << 5) - 1)) << 16))
385
386#define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
387 | ((D & ((1 << 5) - 1)) << 16))
388
389#define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
390 | ((D & ((1 << 5) - 1)) << 16))
391
392#define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
393 | ((N & ((1 << 8) - 1)) << 0)\
394 | ((D & ((1 << 5) - 1)) << 16))
395
396#define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
397 | ((N & ((1 << 8) - 1)) << 0)\
398 | ((D & ((1 << 5) - 1)) << 16))
399
400#define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
401 | ((N & ((1 << 8) - 1)) << 0)\
402 | ((D & ((1 << 5) - 1)) << 16))
403
404#define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
405 | ((N & ((1 << 8) - 1)) << 0)\
406 | ((D & ((1 << 5) - 1)) << 16))
407
408#define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\
409 | ((D & ((1 << 5) - 1)) << 21))
410
411#define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\
412 | ((D & ((1 << 5) - 1)) << 21))
413
414#define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\
415 | ((D & ((1 << 5) - 1)) << 21))
416
417#define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\
418 | ((D & ((1 << 5) - 1)) << 21))
419
420#define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\
421 | ((D & ((1 << 5) - 1)) << 21))
422
423#define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\
424 | ((D & ((1 << 5) - 1)) << 21))
425
426#define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21))
427
428#define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF)
429
430#define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21))
431
432#define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF)
433
434#define MPU_NOP() (0x40000000)
435
436#define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\
437 | ((D & ((1 << 5) - 1)) << 21))
438
439#define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\
440 | ((D & ((1 << 5) - 1)) << 21))
441
442#define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\
443 | ((D & ((1 << 5) - 1)) << 21))
444
445#define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\
446 | ((D & ((1 << 5) - 1)) << 21))
447
448#define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\
449 | ((N & ((1 << 5) - 1)) << 11)\
450 | ((D & ((1 << 5) - 1)) << 21))
451
452#define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\
453 | ((N & ((1 << 5) - 1)) << 11)\
454 | ((D & ((1 << 5) - 1)) << 21))
455
456#define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\
457 | ((N & ((1 << 5) - 1)) << 11)\
458 | ((D & ((1 << 5) - 1)) << 21))
459
460#define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\
461 | ((N & ((1 << 5) - 1)) << 11)\
462 | ((D & ((1 << 5) - 1)) << 21))
463
464#define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\
465 | ((N & ((1 << 5) - 1)) << 11)\
466 | ((D & ((1 << 5) - 1)) << 21))
467
468#define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\
469 | ((N & ((1 << 5) - 1)) << 11)\
470 | ((D & ((1 << 5) - 1)) << 21))
471
472#define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\
473 | ((N & ((1 << 5) - 1)) << 11)\
474 | ((D & ((1 << 5) - 1)) << 21))
475
476#define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\
477 | ((N & ((1 << 5) - 1)) << 11)\
478 | ((D & ((1 << 5) - 1)) << 21))
479
480#define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\
481 | ((N & ((1 << 16) - 1)) << 0)\
482 | ((D & ((1 << 5) - 1)) << 21))
483
484#define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\
485 | ((N & ((1 << 5) - 1)) << 16)\
486 | ((D & ((1 << 5) - 1)) << 21))
487
488#define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\
489 | ((D & ((1 << 5) - 1)) << 21))
490
491#define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
492
493#define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\
494 | ((D & ((1 << 5) - 1)) << 21))
495
496#define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
497
498#define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\
499 | ((D & ((1 << 5) - 1)) << 21))
500
501#define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
502
503#define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\
504 | ((D & ((1 << 5) - 1)) << 21))
505
506#define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
507
508#define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\
509 | ((D & ((1 << 5) - 1)) << 21))
510
511#define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
512
513#define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\
514 | ((D & ((1 << 5) - 1)) << 21))
515
516#define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
517
518#define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\
519 | ((D & ((1 << 5) - 1)) << 21))
520
521#define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
522
523#define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\
524 | ((D & ((1 << 5) - 1)) << 21))
525
526#define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
527
528#define MPU_RET() (0x63003000)
529
530#define MPU_RETI() (0x63602800)
531
532#define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\
533 | ((D & ((1 << 5) - 1)) << 21))
534
535#define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\
536 | ((D & ((1 << 5) - 1)) << 21))
537
538#define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\
539 | ((D & ((1 << 11) - 1)) << 0))
540
541#define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\
542 | ((D & ((1 << 5) - 1)) << 16))
543
544#define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\
545 | ((D & ((1 << 11) - 1)) << 0))
546
547#define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\
548 | ((D & ((1 << 5) - 1)) << 16))
549
550#define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0))
551
552#define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF)
553
554#define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16))
555
556#define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF)
557
558#define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\
559 | ((N & ((1 << 5) - 1)) << 11)\
560 | ((D & ((1 << 5) - 1)) << 21))
561
562#define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\
563 | ((N & ((1 << 5) - 1)) << 11)\
564 | ((D & ((1 << 5) - 1)) << 21))
565
566#define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\
567 | ((N & ((1 << 5) - 1)) << 11)\
568 | ((D & ((1 << 5) - 1)) << 21))
569
570#define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\
571 | ((N & ((1 << 5) - 1)) << 11)\
572 | ((D & ((1 << 5) - 1)) << 21))
573
574#define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\
575 | ((N & ((1 << 5) - 1)) << 11)\
576 | ((D & ((1 << 5) - 1)) << 21))
577
578#define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\
579 | ((N & ((1 << 5) - 1)) << 11)\
580 | ((D & ((1 << 5) - 1)) << 21))
581
582#define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\
583 | ((N & ((1 << 5) - 1)) << 11)\
584 | ((D & ((1 << 5) - 1)) << 21))
585
586#define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\
587 | ((N & ((1 << 5) - 1)) << 11)\
588 | ((D & ((1 << 5) - 1)) << 21))
589
590#define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\
591 | ((N & ((1 << 16) - 1)) << 0)\
592 | ((D & ((1 << 5) - 1)) << 21))
593
594#define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\
595 | ((D & ((1 << 5) - 1)) << 21))
596
597#define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
598
599#define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\
600 | ((D & ((1 << 5) - 1)) << 21))
601
602#define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
603
604#define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\
605 | ((D & ((1 << 5) - 1)) << 21))
606
607#define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
608
609#define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\
610 | ((D & ((1 << 5) - 1)) << 21))
611
612#define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
613
614#define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\
615 | ((D & ((1 << 16) - 1)) << 0))
616
617#define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\
618 | ((D & ((1 << 16) - 1)) << 0))
619
620#define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
621 | ((D & ((1 << 5) - 1)) << 11))
622
623#define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
624 | ((D & ((1 << 5) - 1)) << 11))
625
626#define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
627 | ((D & ((1 << 5) - 1)) << 11))
628
629#define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
630 | ((D & ((1 << 5) - 1)) << 11))
631
632#define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
633 | ((N & ((1 << 8) - 1)) << 0)\
634 | ((D & ((1 << 5) - 1)) << 11))
635
636#define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
637 | ((N & ((1 << 8) - 1)) << 0)\
638 | ((D & ((1 << 5) - 1)) << 11))
639
640#define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
641 | ((N & ((1 << 8) - 1)) << 0)\
642 | ((D & ((1 << 5) - 1)) << 11))
643
644#define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
645 | ((N & ((1 << 8) - 1)) << 0)\
646 | ((D & ((1 << 5) - 1)) << 11))
647
648#define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0))
649
650#define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF)
651
652#define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11))
653
654#define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF)
655
656#define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11))
657
658#define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF)
659
660#define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\
661 | ((D & ((1 << 5) - 1)) << 11))
662
663#define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF)
664
665#define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\
666 | ((D & ((1 << 5) - 1)) << 11))
667
668#define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF)
669
670#define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\
671 | ((N & ((1 << 5) - 1)) << 11)\
672 | ((D & ((1 << 5) - 1)) << 21))
673
674#define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\
675 | ((N & ((1 << 5) - 1)) << 11)\
676 | ((D & ((1 << 5) - 1)) << 21))
677
678#define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\
679 | ((N & ((1 << 5) - 1)) << 11)\
680 | ((D & ((1 << 5) - 1)) << 21))
681
682#define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\
683 | ((N & ((1 << 5) - 1)) << 11)\
684 | ((D & ((1 << 5) - 1)) << 21))
685
686#define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\
687 | ((N & ((1 << 5) - 1)) << 11)\
688 | ((D & ((1 << 5) - 1)) << 21))
689
690#define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\
691 | ((N & ((1 << 5) - 1)) << 11)\
692 | ((D & ((1 << 5) - 1)) << 21))
693
694#define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\
695 | ((N & ((1 << 5) - 1)) << 11)\
696 | ((D & ((1 << 5) - 1)) << 21))
697
698#define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\
699 | ((N & ((1 << 5) - 1)) << 11)\
700 | ((D & ((1 << 5) - 1)) << 21))
701
702#define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\
703 | ((D & ((1 << 5) - 1)) << 21))
704
705#define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\
706 | ((D & ((1 << 5) - 1)) << 21))
707
708#define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\
709 | ((D & ((1 << 5) - 1)) << 21))
710
711#define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\
712 | ((D & ((1 << 5) - 1)) << 21))
713
714#define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\
715 | ((N & ((1 << 16) - 1)) << 0)\
716 | ((D & ((1 << 5) - 1)) << 21))
717
718#define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\
719 | ((N & ((1 << 5) - 1)) << 16)\
720 | ((D & ((1 << 5) - 1)) << 21))
721
722#define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\
723 | ((D & ((1 << 5) - 1)) << 21))
724
725#define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
726
727#define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\
728 | ((D & ((1 << 5) - 1)) << 21))
729
730#define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
731
732#define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\
733 | ((D & ((1 << 5) - 1)) << 21))
734
735#define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
736
737#define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\
738 | ((D & ((1 << 5) - 1)) << 21))
739
740#define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
741
742#define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\
743 | ((D & ((1 << 5) - 1)) << 21))
744
745#define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
746
747#define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\
748 | ((D & ((1 << 5) - 1)) << 21))
749
750#define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
751
752#define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\
753 | ((D & ((1 << 5) - 1)) << 21))
754
755#define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
756
757#define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\
758 | ((D & ((1 << 5) - 1)) << 21))
759
760#define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
761
762
763#endif /* end of __IOP_MPU_MACROS_H__ */
764/* End of iop_mpu_macros.h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h b/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h
new file mode 100644
index 000000000000..756550f5d6cb
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h
@@ -0,0 +1,44 @@
1/* Autogenerated Changes here will be lost!
2 * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg
3 */
4#define regi_iop_version (regi_iop + 0)
5#define regi_iop_fifo_in0_extra (regi_iop + 64)
6#define regi_iop_fifo_in1_extra (regi_iop + 128)
7#define regi_iop_fifo_out0_extra (regi_iop + 192)
8#define regi_iop_fifo_out1_extra (regi_iop + 256)
9#define regi_iop_trigger_grp0 (regi_iop + 320)
10#define regi_iop_trigger_grp1 (regi_iop + 384)
11#define regi_iop_trigger_grp2 (regi_iop + 448)
12#define regi_iop_trigger_grp3 (regi_iop + 512)
13#define regi_iop_trigger_grp4 (regi_iop + 576)
14#define regi_iop_trigger_grp5 (regi_iop + 640)
15#define regi_iop_trigger_grp6 (regi_iop + 704)
16#define regi_iop_trigger_grp7 (regi_iop + 768)
17#define regi_iop_crc_par0 (regi_iop + 896)
18#define regi_iop_crc_par1 (regi_iop + 1024)
19#define regi_iop_dmc_in0 (regi_iop + 1152)
20#define regi_iop_dmc_in1 (regi_iop + 1280)
21#define regi_iop_dmc_out0 (regi_iop + 1408)
22#define regi_iop_dmc_out1 (regi_iop + 1536)
23#define regi_iop_fifo_in0 (regi_iop + 1664)
24#define regi_iop_fifo_in1 (regi_iop + 1792)
25#define regi_iop_fifo_out0 (regi_iop + 1920)
26#define regi_iop_fifo_out1 (regi_iop + 2048)
27#define regi_iop_scrc_in0 (regi_iop + 2176)
28#define regi_iop_scrc_in1 (regi_iop + 2304)
29#define regi_iop_scrc_out0 (regi_iop + 2432)
30#define regi_iop_scrc_out1 (regi_iop + 2560)
31#define regi_iop_timer_grp0 (regi_iop + 2688)
32#define regi_iop_timer_grp1 (regi_iop + 2816)
33#define regi_iop_timer_grp2 (regi_iop + 2944)
34#define regi_iop_timer_grp3 (regi_iop + 3072)
35#define regi_iop_sap_in (regi_iop + 3328)
36#define regi_iop_sap_out (regi_iop + 3584)
37#define regi_iop_spu0 (regi_iop + 3840)
38#define regi_iop_spu1 (regi_iop + 4096)
39#define regi_iop_sw_cfg (regi_iop + 4352)
40#define regi_iop_sw_cpu (regi_iop + 4608)
41#define regi_iop_sw_mpu (regi_iop + 4864)
42#define regi_iop_sw_spu0 (regi_iop + 5120)
43#define regi_iop_sw_spu1 (regi_iop + 5376)
44#define regi_iop_mpu (regi_iop + 5632)
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h
new file mode 100644
index 000000000000..5548ac10074f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h
@@ -0,0 +1,179 @@
1#ifndef __iop_sap_in_defs_h
2#define __iop_sap_in_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_sap_in.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:08:45 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r
11 * id: $Id: iop_sap_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_sap_in */
86
87/* Register rw_bus0_sync, scope iop_sap_in, type rw */
88typedef struct {
89 unsigned int byte0_sel : 2;
90 unsigned int byte0_ext_src : 3;
91 unsigned int byte0_edge : 2;
92 unsigned int byte0_delay : 1;
93 unsigned int byte1_sel : 2;
94 unsigned int byte1_ext_src : 3;
95 unsigned int byte1_edge : 2;
96 unsigned int byte1_delay : 1;
97 unsigned int byte2_sel : 2;
98 unsigned int byte2_ext_src : 3;
99 unsigned int byte2_edge : 2;
100 unsigned int byte2_delay : 1;
101 unsigned int byte3_sel : 2;
102 unsigned int byte3_ext_src : 3;
103 unsigned int byte3_edge : 2;
104 unsigned int byte3_delay : 1;
105} reg_iop_sap_in_rw_bus0_sync;
106#define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0
107#define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0
108
109/* Register rw_bus1_sync, scope iop_sap_in, type rw */
110typedef struct {
111 unsigned int byte0_sel : 2;
112 unsigned int byte0_ext_src : 3;
113 unsigned int byte0_edge : 2;
114 unsigned int byte0_delay : 1;
115 unsigned int byte1_sel : 2;
116 unsigned int byte1_ext_src : 3;
117 unsigned int byte1_edge : 2;
118 unsigned int byte1_delay : 1;
119 unsigned int byte2_sel : 2;
120 unsigned int byte2_ext_src : 3;
121 unsigned int byte2_edge : 2;
122 unsigned int byte2_delay : 1;
123 unsigned int byte3_sel : 2;
124 unsigned int byte3_ext_src : 3;
125 unsigned int byte3_edge : 2;
126 unsigned int byte3_delay : 1;
127} reg_iop_sap_in_rw_bus1_sync;
128#define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4
129#define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4
130
131#define STRIDE_iop_sap_in_rw_gio 4
132/* Register rw_gio, scope iop_sap_in, type rw */
133typedef struct {
134 unsigned int sync_sel : 2;
135 unsigned int sync_ext_src : 3;
136 unsigned int sync_edge : 2;
137 unsigned int delay : 1;
138 unsigned int logic : 2;
139 unsigned int dummy1 : 22;
140} reg_iop_sap_in_rw_gio;
141#define REG_RD_ADDR_iop_sap_in_rw_gio 8
142#define REG_WR_ADDR_iop_sap_in_rw_gio 8
143
144
145/* Constants */
146enum {
147 regk_iop_sap_in_and = 0x00000002,
148 regk_iop_sap_in_ext_clk200 = 0x00000003,
149 regk_iop_sap_in_gio1 = 0x00000000,
150 regk_iop_sap_in_gio13 = 0x00000005,
151 regk_iop_sap_in_gio18 = 0x00000003,
152 regk_iop_sap_in_gio19 = 0x00000004,
153 regk_iop_sap_in_gio21 = 0x00000006,
154 regk_iop_sap_in_gio23 = 0x00000005,
155 regk_iop_sap_in_gio29 = 0x00000007,
156 regk_iop_sap_in_gio5 = 0x00000004,
157 regk_iop_sap_in_gio6 = 0x00000001,
158 regk_iop_sap_in_gio7 = 0x00000002,
159 regk_iop_sap_in_inv = 0x00000001,
160 regk_iop_sap_in_neg = 0x00000002,
161 regk_iop_sap_in_no = 0x00000000,
162 regk_iop_sap_in_no_del_ext_clk200 = 0x00000001,
163 regk_iop_sap_in_none = 0x00000000,
164 regk_iop_sap_in_or = 0x00000003,
165 regk_iop_sap_in_pos = 0x00000001,
166 regk_iop_sap_in_pos_neg = 0x00000003,
167 regk_iop_sap_in_rw_bus0_sync_default = 0x02020202,
168 regk_iop_sap_in_rw_bus1_sync_default = 0x02020202,
169 regk_iop_sap_in_rw_gio_default = 0x00000002,
170 regk_iop_sap_in_rw_gio_size = 0x00000020,
171 regk_iop_sap_in_timer_grp0_tmr3 = 0x00000006,
172 regk_iop_sap_in_timer_grp1_tmr3 = 0x00000004,
173 regk_iop_sap_in_timer_grp2_tmr3 = 0x00000005,
174 regk_iop_sap_in_timer_grp3_tmr3 = 0x00000007,
175 regk_iop_sap_in_tmr_clk200 = 0x00000000,
176 regk_iop_sap_in_two_clk200 = 0x00000002,
177 regk_iop_sap_in_yes = 0x00000001
178};
179#endif /* __iop_sap_in_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h
new file mode 100644
index 000000000000..273936996183
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h
@@ -0,0 +1,306 @@
1#ifndef __iop_sap_out_defs_h
2#define __iop_sap_out_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_sap_out.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:08:46 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_out_defs.h ../../inst/io_proc/rtl/iop_sap_out.r
11 * id: $Id: iop_sap_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_sap_out */
86
87/* Register rw_gen_gated, scope iop_sap_out, type rw */
88typedef struct {
89 unsigned int clk0_src : 2;
90 unsigned int clk0_gate_src : 2;
91 unsigned int clk0_force_src : 3;
92 unsigned int clk1_src : 2;
93 unsigned int clk1_gate_src : 2;
94 unsigned int clk1_force_src : 3;
95 unsigned int clk2_src : 2;
96 unsigned int clk2_gate_src : 2;
97 unsigned int clk2_force_src : 3;
98 unsigned int clk3_src : 2;
99 unsigned int clk3_gate_src : 2;
100 unsigned int clk3_force_src : 3;
101 unsigned int dummy1 : 4;
102} reg_iop_sap_out_rw_gen_gated;
103#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0
104#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0
105
106/* Register rw_bus0, scope iop_sap_out, type rw */
107typedef struct {
108 unsigned int byte0_clk_sel : 3;
109 unsigned int byte0_gated_clk : 2;
110 unsigned int byte0_clk_inv : 1;
111 unsigned int byte1_clk_sel : 3;
112 unsigned int byte1_gated_clk : 2;
113 unsigned int byte1_clk_inv : 1;
114 unsigned int byte2_clk_sel : 3;
115 unsigned int byte2_gated_clk : 2;
116 unsigned int byte2_clk_inv : 1;
117 unsigned int byte3_clk_sel : 3;
118 unsigned int byte3_gated_clk : 2;
119 unsigned int byte3_clk_inv : 1;
120 unsigned int dummy1 : 8;
121} reg_iop_sap_out_rw_bus0;
122#define REG_RD_ADDR_iop_sap_out_rw_bus0 4
123#define REG_WR_ADDR_iop_sap_out_rw_bus0 4
124
125/* Register rw_bus1, scope iop_sap_out, type rw */
126typedef struct {
127 unsigned int byte0_clk_sel : 3;
128 unsigned int byte0_gated_clk : 2;
129 unsigned int byte0_clk_inv : 1;
130 unsigned int byte1_clk_sel : 3;
131 unsigned int byte1_gated_clk : 2;
132 unsigned int byte1_clk_inv : 1;
133 unsigned int byte2_clk_sel : 3;
134 unsigned int byte2_gated_clk : 2;
135 unsigned int byte2_clk_inv : 1;
136 unsigned int byte3_clk_sel : 3;
137 unsigned int byte3_gated_clk : 2;
138 unsigned int byte3_clk_inv : 1;
139 unsigned int dummy1 : 8;
140} reg_iop_sap_out_rw_bus1;
141#define REG_RD_ADDR_iop_sap_out_rw_bus1 8
142#define REG_WR_ADDR_iop_sap_out_rw_bus1 8
143
144/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */
145typedef struct {
146 unsigned int byte0_clk_sel : 3;
147 unsigned int byte0_clk_ext : 3;
148 unsigned int byte0_gated_clk : 2;
149 unsigned int byte0_clk_inv : 1;
150 unsigned int byte0_logic : 2;
151 unsigned int byte1_clk_sel : 3;
152 unsigned int byte1_clk_ext : 3;
153 unsigned int byte1_gated_clk : 2;
154 unsigned int byte1_clk_inv : 1;
155 unsigned int byte1_logic : 2;
156 unsigned int dummy1 : 10;
157} reg_iop_sap_out_rw_bus0_lo_oe;
158#define REG_RD_ADDR_iop_sap_out_rw_bus0_lo_oe 12
159#define REG_WR_ADDR_iop_sap_out_rw_bus0_lo_oe 12
160
161/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */
162typedef struct {
163 unsigned int byte2_clk_sel : 3;
164 unsigned int byte2_clk_ext : 3;
165 unsigned int byte2_gated_clk : 2;
166 unsigned int byte2_clk_inv : 1;
167 unsigned int byte2_logic : 2;
168 unsigned int byte3_clk_sel : 3;
169 unsigned int byte3_clk_ext : 3;
170 unsigned int byte3_gated_clk : 2;
171 unsigned int byte3_clk_inv : 1;
172 unsigned int byte3_logic : 2;
173 unsigned int dummy1 : 10;
174} reg_iop_sap_out_rw_bus0_hi_oe;
175#define REG_RD_ADDR_iop_sap_out_rw_bus0_hi_oe 16
176#define REG_WR_ADDR_iop_sap_out_rw_bus0_hi_oe 16
177
178/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */
179typedef struct {
180 unsigned int byte0_clk_sel : 3;
181 unsigned int byte0_clk_ext : 3;
182 unsigned int byte0_gated_clk : 2;
183 unsigned int byte0_clk_inv : 1;
184 unsigned int byte0_logic : 2;
185 unsigned int byte1_clk_sel : 3;
186 unsigned int byte1_clk_ext : 3;
187 unsigned int byte1_gated_clk : 2;
188 unsigned int byte1_clk_inv : 1;
189 unsigned int byte1_logic : 2;
190 unsigned int dummy1 : 10;
191} reg_iop_sap_out_rw_bus1_lo_oe;
192#define REG_RD_ADDR_iop_sap_out_rw_bus1_lo_oe 20
193#define REG_WR_ADDR_iop_sap_out_rw_bus1_lo_oe 20
194
195/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */
196typedef struct {
197 unsigned int byte2_clk_sel : 3;
198 unsigned int byte2_clk_ext : 3;
199 unsigned int byte2_gated_clk : 2;
200 unsigned int byte2_clk_inv : 1;
201 unsigned int byte2_logic : 2;
202 unsigned int byte3_clk_sel : 3;
203 unsigned int byte3_clk_ext : 3;
204 unsigned int byte3_gated_clk : 2;
205 unsigned int byte3_clk_inv : 1;
206 unsigned int byte3_logic : 2;
207 unsigned int dummy1 : 10;
208} reg_iop_sap_out_rw_bus1_hi_oe;
209#define REG_RD_ADDR_iop_sap_out_rw_bus1_hi_oe 24
210#define REG_WR_ADDR_iop_sap_out_rw_bus1_hi_oe 24
211
212#define STRIDE_iop_sap_out_rw_gio 4
213/* Register rw_gio, scope iop_sap_out, type rw */
214typedef struct {
215 unsigned int out_clk_sel : 3;
216 unsigned int out_clk_ext : 4;
217 unsigned int out_gated_clk : 2;
218 unsigned int out_clk_inv : 1;
219 unsigned int out_logic : 1;
220 unsigned int oe_clk_sel : 3;
221 unsigned int oe_clk_ext : 3;
222 unsigned int oe_gated_clk : 2;
223 unsigned int oe_clk_inv : 1;
224 unsigned int oe_logic : 2;
225 unsigned int dummy1 : 10;
226} reg_iop_sap_out_rw_gio;
227#define REG_RD_ADDR_iop_sap_out_rw_gio 28
228#define REG_WR_ADDR_iop_sap_out_rw_gio 28
229
230
231/* Constants */
232enum {
233 regk_iop_sap_out_and = 0x00000002,
234 regk_iop_sap_out_clk0 = 0x00000000,
235 regk_iop_sap_out_clk1 = 0x00000001,
236 regk_iop_sap_out_clk12 = 0x00000002,
237 regk_iop_sap_out_clk2 = 0x00000002,
238 regk_iop_sap_out_clk200 = 0x00000001,
239 regk_iop_sap_out_clk3 = 0x00000003,
240 regk_iop_sap_out_ext = 0x00000003,
241 regk_iop_sap_out_gated = 0x00000004,
242 regk_iop_sap_out_gio1 = 0x00000000,
243 regk_iop_sap_out_gio13 = 0x00000002,
244 regk_iop_sap_out_gio13_clk = 0x0000000c,
245 regk_iop_sap_out_gio15 = 0x00000001,
246 regk_iop_sap_out_gio18 = 0x00000003,
247 regk_iop_sap_out_gio18_clk = 0x0000000d,
248 regk_iop_sap_out_gio1_clk = 0x00000008,
249 regk_iop_sap_out_gio21_clk = 0x0000000e,
250 regk_iop_sap_out_gio23 = 0x00000002,
251 regk_iop_sap_out_gio29_clk = 0x0000000f,
252 regk_iop_sap_out_gio31 = 0x00000003,
253 regk_iop_sap_out_gio5 = 0x00000001,
254 regk_iop_sap_out_gio5_clk = 0x00000009,
255 regk_iop_sap_out_gio6_clk = 0x0000000a,
256 regk_iop_sap_out_gio7 = 0x00000000,
257 regk_iop_sap_out_gio7_clk = 0x0000000b,
258 regk_iop_sap_out_gio_in13 = 0x00000001,
259 regk_iop_sap_out_gio_in21 = 0x00000002,
260 regk_iop_sap_out_gio_in29 = 0x00000003,
261 regk_iop_sap_out_gio_in5 = 0x00000000,
262 regk_iop_sap_out_inv = 0x00000001,
263 regk_iop_sap_out_nand = 0x00000003,
264 regk_iop_sap_out_no = 0x00000000,
265 regk_iop_sap_out_none = 0x00000000,
266 regk_iop_sap_out_rw_bus0_default = 0x00000000,
267 regk_iop_sap_out_rw_bus0_hi_oe_default = 0x00000000,
268 regk_iop_sap_out_rw_bus0_lo_oe_default = 0x00000000,
269 regk_iop_sap_out_rw_bus1_default = 0x00000000,
270 regk_iop_sap_out_rw_bus1_hi_oe_default = 0x00000000,
271 regk_iop_sap_out_rw_bus1_lo_oe_default = 0x00000000,
272 regk_iop_sap_out_rw_gen_gated_default = 0x00000000,
273 regk_iop_sap_out_rw_gio_default = 0x00000000,
274 regk_iop_sap_out_rw_gio_size = 0x00000020,
275 regk_iop_sap_out_spu0_gio0 = 0x00000002,
276 regk_iop_sap_out_spu0_gio1 = 0x00000003,
277 regk_iop_sap_out_spu0_gio12 = 0x00000004,
278 regk_iop_sap_out_spu0_gio13 = 0x00000004,
279 regk_iop_sap_out_spu0_gio14 = 0x00000004,
280 regk_iop_sap_out_spu0_gio15 = 0x00000004,
281 regk_iop_sap_out_spu0_gio2 = 0x00000002,
282 regk_iop_sap_out_spu0_gio3 = 0x00000003,
283 regk_iop_sap_out_spu0_gio4 = 0x00000002,
284 regk_iop_sap_out_spu0_gio5 = 0x00000003,
285 regk_iop_sap_out_spu0_gio6 = 0x00000002,
286 regk_iop_sap_out_spu0_gio7 = 0x00000003,
287 regk_iop_sap_out_spu1_gio0 = 0x00000005,
288 regk_iop_sap_out_spu1_gio1 = 0x00000006,
289 regk_iop_sap_out_spu1_gio12 = 0x00000007,
290 regk_iop_sap_out_spu1_gio13 = 0x00000007,
291 regk_iop_sap_out_spu1_gio14 = 0x00000007,
292 regk_iop_sap_out_spu1_gio15 = 0x00000007,
293 regk_iop_sap_out_spu1_gio2 = 0x00000005,
294 regk_iop_sap_out_spu1_gio3 = 0x00000006,
295 regk_iop_sap_out_spu1_gio4 = 0x00000005,
296 regk_iop_sap_out_spu1_gio5 = 0x00000006,
297 regk_iop_sap_out_spu1_gio6 = 0x00000005,
298 regk_iop_sap_out_spu1_gio7 = 0x00000006,
299 regk_iop_sap_out_timer_grp0_tmr2 = 0x00000004,
300 regk_iop_sap_out_timer_grp1_tmr2 = 0x00000005,
301 regk_iop_sap_out_timer_grp2_tmr2 = 0x00000006,
302 regk_iop_sap_out_timer_grp3_tmr2 = 0x00000007,
303 regk_iop_sap_out_tmr = 0x00000005,
304 regk_iop_sap_out_yes = 0x00000001
305};
306#endif /* __iop_sap_out_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h
new file mode 100644
index 000000000000..4f0a9a81e737
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h
@@ -0,0 +1,160 @@
1#ifndef __iop_scrc_in_defs_h
2#define __iop_scrc_in_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_scrc_in.r
7 * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp
8 * last modfied: Mon Apr 11 16:08:46 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r
11 * id: $Id: iop_scrc_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_scrc_in */
86
87/* Register rw_cfg, scope iop_scrc_in, type rw */
88typedef struct {
89 unsigned int trig : 2;
90 unsigned int dummy1 : 30;
91} reg_iop_scrc_in_rw_cfg;
92#define REG_RD_ADDR_iop_scrc_in_rw_cfg 0
93#define REG_WR_ADDR_iop_scrc_in_rw_cfg 0
94
95/* Register rw_ctrl, scope iop_scrc_in, type rw */
96typedef struct {
97 unsigned int dif_in_en : 1;
98 unsigned int dummy1 : 31;
99} reg_iop_scrc_in_rw_ctrl;
100#define REG_RD_ADDR_iop_scrc_in_rw_ctrl 4
101#define REG_WR_ADDR_iop_scrc_in_rw_ctrl 4
102
103/* Register r_stat, scope iop_scrc_in, type r */
104typedef struct {
105 unsigned int err : 1;
106 unsigned int dummy1 : 31;
107} reg_iop_scrc_in_r_stat;
108#define REG_RD_ADDR_iop_scrc_in_r_stat 8
109
110/* Register rw_init_crc, scope iop_scrc_in, type rw */
111typedef unsigned int reg_iop_scrc_in_rw_init_crc;
112#define REG_RD_ADDR_iop_scrc_in_rw_init_crc 12
113#define REG_WR_ADDR_iop_scrc_in_rw_init_crc 12
114
115/* Register rs_computed_crc, scope iop_scrc_in, type rs */
116typedef unsigned int reg_iop_scrc_in_rs_computed_crc;
117#define REG_RD_ADDR_iop_scrc_in_rs_computed_crc 16
118
119/* Register r_computed_crc, scope iop_scrc_in, type r */
120typedef unsigned int reg_iop_scrc_in_r_computed_crc;
121#define REG_RD_ADDR_iop_scrc_in_r_computed_crc 20
122
123/* Register rw_crc, scope iop_scrc_in, type rw */
124typedef unsigned int reg_iop_scrc_in_rw_crc;
125#define REG_RD_ADDR_iop_scrc_in_rw_crc 24
126#define REG_WR_ADDR_iop_scrc_in_rw_crc 24
127
128/* Register rw_correct_crc, scope iop_scrc_in, type rw */
129typedef unsigned int reg_iop_scrc_in_rw_correct_crc;
130#define REG_RD_ADDR_iop_scrc_in_rw_correct_crc 28
131#define REG_WR_ADDR_iop_scrc_in_rw_correct_crc 28
132
133/* Register rw_wr1bit, scope iop_scrc_in, type rw */
134typedef struct {
135 unsigned int data : 2;
136 unsigned int last : 2;
137 unsigned int dummy1 : 28;
138} reg_iop_scrc_in_rw_wr1bit;
139#define REG_RD_ADDR_iop_scrc_in_rw_wr1bit 32
140#define REG_WR_ADDR_iop_scrc_in_rw_wr1bit 32
141
142
143/* Constants */
144enum {
145 regk_iop_scrc_in_dif_in = 0x00000002,
146 regk_iop_scrc_in_hi = 0x00000000,
147 regk_iop_scrc_in_neg = 0x00000002,
148 regk_iop_scrc_in_no = 0x00000000,
149 regk_iop_scrc_in_pos = 0x00000001,
150 regk_iop_scrc_in_pos_neg = 0x00000003,
151 regk_iop_scrc_in_r_computed_crc_default = 0x00000000,
152 regk_iop_scrc_in_rs_computed_crc_default = 0x00000000,
153 regk_iop_scrc_in_rw_cfg_default = 0x00000000,
154 regk_iop_scrc_in_rw_ctrl_default = 0x00000000,
155 regk_iop_scrc_in_rw_init_crc_default = 0x00000000,
156 regk_iop_scrc_in_set0 = 0x00000000,
157 regk_iop_scrc_in_set1 = 0x00000001,
158 regk_iop_scrc_in_yes = 0x00000001
159};
160#endif /* __iop_scrc_in_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h
new file mode 100644
index 000000000000..fd1d6ea1d484
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h
@@ -0,0 +1,146 @@
1#ifndef __iop_scrc_out_defs_h
2#define __iop_scrc_out_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_scrc_out.r
7 * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp
8 * last modfied: Mon Apr 11 16:08:46 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_out_defs.h ../../inst/io_proc/rtl/iop_scrc_out.r
11 * id: $Id: iop_scrc_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_scrc_out */
86
87/* Register rw_cfg, scope iop_scrc_out, type rw */
88typedef struct {
89 unsigned int trig : 2;
90 unsigned int inv_crc : 1;
91 unsigned int dummy1 : 29;
92} reg_iop_scrc_out_rw_cfg;
93#define REG_RD_ADDR_iop_scrc_out_rw_cfg 0
94#define REG_WR_ADDR_iop_scrc_out_rw_cfg 0
95
96/* Register rw_ctrl, scope iop_scrc_out, type rw */
97typedef struct {
98 unsigned int strb_src : 1;
99 unsigned int out_src : 1;
100 unsigned int dummy1 : 30;
101} reg_iop_scrc_out_rw_ctrl;
102#define REG_RD_ADDR_iop_scrc_out_rw_ctrl 4
103#define REG_WR_ADDR_iop_scrc_out_rw_ctrl 4
104
105/* Register rw_init_crc, scope iop_scrc_out, type rw */
106typedef unsigned int reg_iop_scrc_out_rw_init_crc;
107#define REG_RD_ADDR_iop_scrc_out_rw_init_crc 8
108#define REG_WR_ADDR_iop_scrc_out_rw_init_crc 8
109
110/* Register rw_crc, scope iop_scrc_out, type rw */
111typedef unsigned int reg_iop_scrc_out_rw_crc;
112#define REG_RD_ADDR_iop_scrc_out_rw_crc 12
113#define REG_WR_ADDR_iop_scrc_out_rw_crc 12
114
115/* Register rw_data, scope iop_scrc_out, type rw */
116typedef struct {
117 unsigned int val : 1;
118 unsigned int dummy1 : 31;
119} reg_iop_scrc_out_rw_data;
120#define REG_RD_ADDR_iop_scrc_out_rw_data 16
121#define REG_WR_ADDR_iop_scrc_out_rw_data 16
122
123/* Register r_computed_crc, scope iop_scrc_out, type r */
124typedef unsigned int reg_iop_scrc_out_r_computed_crc;
125#define REG_RD_ADDR_iop_scrc_out_r_computed_crc 20
126
127
128/* Constants */
129enum {
130 regk_iop_scrc_out_crc = 0x00000001,
131 regk_iop_scrc_out_data = 0x00000000,
132 regk_iop_scrc_out_dif = 0x00000001,
133 regk_iop_scrc_out_hi = 0x00000000,
134 regk_iop_scrc_out_neg = 0x00000002,
135 regk_iop_scrc_out_no = 0x00000000,
136 regk_iop_scrc_out_pos = 0x00000001,
137 regk_iop_scrc_out_pos_neg = 0x00000003,
138 regk_iop_scrc_out_reg = 0x00000000,
139 regk_iop_scrc_out_rw_cfg_default = 0x00000000,
140 regk_iop_scrc_out_rw_crc_default = 0x00000000,
141 regk_iop_scrc_out_rw_ctrl_default = 0x00000000,
142 regk_iop_scrc_out_rw_data_default = 0x00000000,
143 regk_iop_scrc_out_rw_init_crc_default = 0x00000000,
144 regk_iop_scrc_out_yes = 0x00000001
145};
146#endif /* __iop_scrc_out_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h
new file mode 100644
index 000000000000..0fda26e2f06f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h
@@ -0,0 +1,453 @@
1#ifndef __iop_spu_defs_h
2#define __iop_spu_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_spu.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:08:46 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r
11 * id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_spu */
86
87#define STRIDE_iop_spu_rw_r 4
88/* Register rw_r, scope iop_spu, type rw */
89typedef unsigned int reg_iop_spu_rw_r;
90#define REG_RD_ADDR_iop_spu_rw_r 0
91#define REG_WR_ADDR_iop_spu_rw_r 0
92
93/* Register rw_seq_pc, scope iop_spu, type rw */
94typedef struct {
95 unsigned int addr : 12;
96 unsigned int dummy1 : 20;
97} reg_iop_spu_rw_seq_pc;
98#define REG_RD_ADDR_iop_spu_rw_seq_pc 64
99#define REG_WR_ADDR_iop_spu_rw_seq_pc 64
100
101/* Register rw_fsm_pc, scope iop_spu, type rw */
102typedef struct {
103 unsigned int addr : 12;
104 unsigned int dummy1 : 20;
105} reg_iop_spu_rw_fsm_pc;
106#define REG_RD_ADDR_iop_spu_rw_fsm_pc 68
107#define REG_WR_ADDR_iop_spu_rw_fsm_pc 68
108
109/* Register rw_ctrl, scope iop_spu, type rw */
110typedef struct {
111 unsigned int fsm : 1;
112 unsigned int en : 1;
113 unsigned int dummy1 : 30;
114} reg_iop_spu_rw_ctrl;
115#define REG_RD_ADDR_iop_spu_rw_ctrl 72
116#define REG_WR_ADDR_iop_spu_rw_ctrl 72
117
118/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
119typedef struct {
120 unsigned int val0 : 5;
121 unsigned int src0 : 3;
122 unsigned int val1 : 5;
123 unsigned int src1 : 3;
124 unsigned int val2 : 5;
125 unsigned int src2 : 3;
126 unsigned int val3 : 5;
127 unsigned int src3 : 3;
128} reg_iop_spu_rw_fsm_inputs3_0;
129#define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76
130#define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76
131
132/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
133typedef struct {
134 unsigned int val4 : 5;
135 unsigned int src4 : 3;
136 unsigned int val5 : 5;
137 unsigned int src5 : 3;
138 unsigned int val6 : 5;
139 unsigned int src6 : 3;
140 unsigned int val7 : 5;
141 unsigned int src7 : 3;
142} reg_iop_spu_rw_fsm_inputs7_4;
143#define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80
144#define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80
145
146/* Register rw_gio_out, scope iop_spu, type rw */
147typedef unsigned int reg_iop_spu_rw_gio_out;
148#define REG_RD_ADDR_iop_spu_rw_gio_out 84
149#define REG_WR_ADDR_iop_spu_rw_gio_out 84
150
151/* Register rw_bus0_out, scope iop_spu, type rw */
152typedef unsigned int reg_iop_spu_rw_bus0_out;
153#define REG_RD_ADDR_iop_spu_rw_bus0_out 88
154#define REG_WR_ADDR_iop_spu_rw_bus0_out 88
155
156/* Register rw_bus1_out, scope iop_spu, type rw */
157typedef unsigned int reg_iop_spu_rw_bus1_out;
158#define REG_RD_ADDR_iop_spu_rw_bus1_out 92
159#define REG_WR_ADDR_iop_spu_rw_bus1_out 92
160
161/* Register r_gio_in, scope iop_spu, type r */
162typedef unsigned int reg_iop_spu_r_gio_in;
163#define REG_RD_ADDR_iop_spu_r_gio_in 96
164
165/* Register r_bus0_in, scope iop_spu, type r */
166typedef unsigned int reg_iop_spu_r_bus0_in;
167#define REG_RD_ADDR_iop_spu_r_bus0_in 100
168
169/* Register r_bus1_in, scope iop_spu, type r */
170typedef unsigned int reg_iop_spu_r_bus1_in;
171#define REG_RD_ADDR_iop_spu_r_bus1_in 104
172
173/* Register rw_gio_out_set, scope iop_spu, type rw */
174typedef unsigned int reg_iop_spu_rw_gio_out_set;
175#define REG_RD_ADDR_iop_spu_rw_gio_out_set 108
176#define REG_WR_ADDR_iop_spu_rw_gio_out_set 108
177
178/* Register rw_gio_out_clr, scope iop_spu, type rw */
179typedef unsigned int reg_iop_spu_rw_gio_out_clr;
180#define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112
181#define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112
182
183/* Register rs_wr_stat, scope iop_spu, type rs */
184typedef struct {
185 unsigned int r0 : 1;
186 unsigned int r1 : 1;
187 unsigned int r2 : 1;
188 unsigned int r3 : 1;
189 unsigned int r4 : 1;
190 unsigned int r5 : 1;
191 unsigned int r6 : 1;
192 unsigned int r7 : 1;
193 unsigned int r8 : 1;
194 unsigned int r9 : 1;
195 unsigned int r10 : 1;
196 unsigned int r11 : 1;
197 unsigned int r12 : 1;
198 unsigned int r13 : 1;
199 unsigned int r14 : 1;
200 unsigned int r15 : 1;
201 unsigned int dummy1 : 16;
202} reg_iop_spu_rs_wr_stat;
203#define REG_RD_ADDR_iop_spu_rs_wr_stat 116
204
205/* Register r_wr_stat, scope iop_spu, type r */
206typedef struct {
207 unsigned int r0 : 1;
208 unsigned int r1 : 1;
209 unsigned int r2 : 1;
210 unsigned int r3 : 1;
211 unsigned int r4 : 1;
212 unsigned int r5 : 1;
213 unsigned int r6 : 1;
214 unsigned int r7 : 1;
215 unsigned int r8 : 1;
216 unsigned int r9 : 1;
217 unsigned int r10 : 1;
218 unsigned int r11 : 1;
219 unsigned int r12 : 1;
220 unsigned int r13 : 1;
221 unsigned int r14 : 1;
222 unsigned int r15 : 1;
223 unsigned int dummy1 : 16;
224} reg_iop_spu_r_wr_stat;
225#define REG_RD_ADDR_iop_spu_r_wr_stat 120
226
227/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */
228typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in;
229#define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124
230
231/* Register r_stat_in, scope iop_spu, type r */
232typedef struct {
233 unsigned int timer_grp_lo : 4;
234 unsigned int fifo_out_last : 1;
235 unsigned int fifo_out_rdy : 1;
236 unsigned int fifo_out_all : 1;
237 unsigned int fifo_in_rdy : 1;
238 unsigned int dmc_out_all : 1;
239 unsigned int dmc_out_dth : 1;
240 unsigned int dmc_out_eop : 1;
241 unsigned int dmc_out_dv : 1;
242 unsigned int dmc_out_last : 1;
243 unsigned int dmc_out_cmd_rq : 1;
244 unsigned int dmc_out_cmd_rdy : 1;
245 unsigned int pcrc_correct : 1;
246 unsigned int timer_grp_hi : 4;
247 unsigned int dmc_in_sth : 1;
248 unsigned int dmc_in_full : 1;
249 unsigned int dmc_in_cmd_rdy : 1;
250 unsigned int spu_gio_out : 4;
251 unsigned int sync_clk12 : 1;
252 unsigned int scrc_out_data : 1;
253 unsigned int scrc_in_err : 1;
254 unsigned int mc_busy : 1;
255 unsigned int mc_owned : 1;
256} reg_iop_spu_r_stat_in;
257#define REG_RD_ADDR_iop_spu_r_stat_in 128
258
259/* Register r_trigger_in, scope iop_spu, type r */
260typedef unsigned int reg_iop_spu_r_trigger_in;
261#define REG_RD_ADDR_iop_spu_r_trigger_in 132
262
263/* Register r_special_stat, scope iop_spu, type r */
264typedef struct {
265 unsigned int c_flag : 1;
266 unsigned int v_flag : 1;
267 unsigned int z_flag : 1;
268 unsigned int n_flag : 1;
269 unsigned int xor_bus0_r2_0 : 1;
270 unsigned int xor_bus1_r3_0 : 1;
271 unsigned int xor_bus0m_r2_0 : 1;
272 unsigned int xor_bus1m_r3_0 : 1;
273 unsigned int fsm_in0 : 1;
274 unsigned int fsm_in1 : 1;
275 unsigned int fsm_in2 : 1;
276 unsigned int fsm_in3 : 1;
277 unsigned int fsm_in4 : 1;
278 unsigned int fsm_in5 : 1;
279 unsigned int fsm_in6 : 1;
280 unsigned int fsm_in7 : 1;
281 unsigned int event0 : 1;
282 unsigned int event1 : 1;
283 unsigned int event2 : 1;
284 unsigned int event3 : 1;
285 unsigned int dummy1 : 12;
286} reg_iop_spu_r_special_stat;
287#define REG_RD_ADDR_iop_spu_r_special_stat 136
288
289/* Register rw_reg_access, scope iop_spu, type rw */
290typedef struct {
291 unsigned int addr : 13;
292 unsigned int dummy1 : 3;
293 unsigned int imm_hi : 16;
294} reg_iop_spu_rw_reg_access;
295#define REG_RD_ADDR_iop_spu_rw_reg_access 140
296#define REG_WR_ADDR_iop_spu_rw_reg_access 140
297
298#define STRIDE_iop_spu_rw_event_cfg 4
299/* Register rw_event_cfg, scope iop_spu, type rw */
300typedef struct {
301 unsigned int addr : 12;
302 unsigned int src : 2;
303 unsigned int eq_en : 1;
304 unsigned int eq_inv : 1;
305 unsigned int gt_en : 1;
306 unsigned int gt_inv : 1;
307 unsigned int dummy1 : 14;
308} reg_iop_spu_rw_event_cfg;
309#define REG_RD_ADDR_iop_spu_rw_event_cfg 144
310#define REG_WR_ADDR_iop_spu_rw_event_cfg 144
311
312#define STRIDE_iop_spu_rw_event_mask 4
313/* Register rw_event_mask, scope iop_spu, type rw */
314typedef unsigned int reg_iop_spu_rw_event_mask;
315#define REG_RD_ADDR_iop_spu_rw_event_mask 160
316#define REG_WR_ADDR_iop_spu_rw_event_mask 160
317
318#define STRIDE_iop_spu_rw_event_val 4
319/* Register rw_event_val, scope iop_spu, type rw */
320typedef unsigned int reg_iop_spu_rw_event_val;
321#define REG_RD_ADDR_iop_spu_rw_event_val 176
322#define REG_WR_ADDR_iop_spu_rw_event_val 176
323
324/* Register rw_event_ret, scope iop_spu, type rw */
325typedef struct {
326 unsigned int addr : 12;
327 unsigned int dummy1 : 20;
328} reg_iop_spu_rw_event_ret;
329#define REG_RD_ADDR_iop_spu_rw_event_ret 192
330#define REG_WR_ADDR_iop_spu_rw_event_ret 192
331
332/* Register r_trace, scope iop_spu, type r */
333typedef struct {
334 unsigned int fsm : 1;
335 unsigned int en : 1;
336 unsigned int c_flag : 1;
337 unsigned int v_flag : 1;
338 unsigned int z_flag : 1;
339 unsigned int n_flag : 1;
340 unsigned int seq_addr : 12;
341 unsigned int dummy1 : 2;
342 unsigned int fsm_addr : 12;
343} reg_iop_spu_r_trace;
344#define REG_RD_ADDR_iop_spu_r_trace 196
345
346/* Register r_fsm_trace, scope iop_spu, type r */
347typedef struct {
348 unsigned int fsm : 1;
349 unsigned int en : 1;
350 unsigned int tmr_done : 1;
351 unsigned int inp0 : 1;
352 unsigned int inp1 : 1;
353 unsigned int inp2 : 1;
354 unsigned int inp3 : 1;
355 unsigned int event0 : 1;
356 unsigned int event1 : 1;
357 unsigned int event2 : 1;
358 unsigned int event3 : 1;
359 unsigned int gio_out : 8;
360 unsigned int dummy1 : 1;
361 unsigned int fsm_addr : 12;
362} reg_iop_spu_r_fsm_trace;
363#define REG_RD_ADDR_iop_spu_r_fsm_trace 200
364
365#define STRIDE_iop_spu_rw_brp 4
366/* Register rw_brp, scope iop_spu, type rw */
367typedef struct {
368 unsigned int addr : 12;
369 unsigned int fsm : 1;
370 unsigned int en : 1;
371 unsigned int dummy1 : 18;
372} reg_iop_spu_rw_brp;
373#define REG_RD_ADDR_iop_spu_rw_brp 204
374#define REG_WR_ADDR_iop_spu_rw_brp 204
375
376
377/* Constants */
378enum {
379 regk_iop_spu_attn_hi = 0x00000005,
380 regk_iop_spu_attn_lo = 0x00000005,
381 regk_iop_spu_attn_r0 = 0x00000000,
382 regk_iop_spu_attn_r1 = 0x00000001,
383 regk_iop_spu_attn_r10 = 0x00000002,
384 regk_iop_spu_attn_r11 = 0x00000003,
385 regk_iop_spu_attn_r12 = 0x00000004,
386 regk_iop_spu_attn_r13 = 0x00000005,
387 regk_iop_spu_attn_r14 = 0x00000006,
388 regk_iop_spu_attn_r15 = 0x00000007,
389 regk_iop_spu_attn_r2 = 0x00000002,
390 regk_iop_spu_attn_r3 = 0x00000003,
391 regk_iop_spu_attn_r4 = 0x00000004,
392 regk_iop_spu_attn_r5 = 0x00000005,
393 regk_iop_spu_attn_r6 = 0x00000006,
394 regk_iop_spu_attn_r7 = 0x00000007,
395 regk_iop_spu_attn_r8 = 0x00000000,
396 regk_iop_spu_attn_r9 = 0x00000001,
397 regk_iop_spu_c = 0x00000000,
398 regk_iop_spu_flag = 0x00000002,
399 regk_iop_spu_gio_in = 0x00000000,
400 regk_iop_spu_gio_out = 0x00000005,
401 regk_iop_spu_gio_out0 = 0x00000008,
402 regk_iop_spu_gio_out1 = 0x00000009,
403 regk_iop_spu_gio_out2 = 0x0000000a,
404 regk_iop_spu_gio_out3 = 0x0000000b,
405 regk_iop_spu_gio_out4 = 0x0000000c,
406 regk_iop_spu_gio_out5 = 0x0000000d,
407 regk_iop_spu_gio_out6 = 0x0000000e,
408 regk_iop_spu_gio_out7 = 0x0000000f,
409 regk_iop_spu_n = 0x00000003,
410 regk_iop_spu_no = 0x00000000,
411 regk_iop_spu_r0 = 0x00000008,
412 regk_iop_spu_r1 = 0x00000009,
413 regk_iop_spu_r10 = 0x0000000a,
414 regk_iop_spu_r11 = 0x0000000b,
415 regk_iop_spu_r12 = 0x0000000c,
416 regk_iop_spu_r13 = 0x0000000d,
417 regk_iop_spu_r14 = 0x0000000e,
418 regk_iop_spu_r15 = 0x0000000f,
419 regk_iop_spu_r2 = 0x0000000a,
420 regk_iop_spu_r3 = 0x0000000b,
421 regk_iop_spu_r4 = 0x0000000c,
422 regk_iop_spu_r5 = 0x0000000d,
423 regk_iop_spu_r6 = 0x0000000e,
424 regk_iop_spu_r7 = 0x0000000f,
425 regk_iop_spu_r8 = 0x00000008,
426 regk_iop_spu_r9 = 0x00000009,
427 regk_iop_spu_reg_hi = 0x00000002,
428 regk_iop_spu_reg_lo = 0x00000002,
429 regk_iop_spu_rw_brp_default = 0x00000000,
430 regk_iop_spu_rw_brp_size = 0x00000004,
431 regk_iop_spu_rw_ctrl_default = 0x00000000,
432 regk_iop_spu_rw_event_cfg_size = 0x00000004,
433 regk_iop_spu_rw_event_mask_size = 0x00000004,
434 regk_iop_spu_rw_event_val_size = 0x00000004,
435 regk_iop_spu_rw_gio_out_default = 0x00000000,
436 regk_iop_spu_rw_r_size = 0x00000010,
437 regk_iop_spu_rw_reg_access_default = 0x00000000,
438 regk_iop_spu_stat_in = 0x00000002,
439 regk_iop_spu_statin_hi = 0x00000004,
440 regk_iop_spu_statin_lo = 0x00000004,
441 regk_iop_spu_trig = 0x00000003,
442 regk_iop_spu_trigger = 0x00000006,
443 regk_iop_spu_v = 0x00000001,
444 regk_iop_spu_wsts_gioout_spec = 0x00000001,
445 regk_iop_spu_xor = 0x00000003,
446 regk_iop_spu_xor_bus0_r2_0 = 0x00000000,
447 regk_iop_spu_xor_bus0m_r2_0 = 0x00000002,
448 regk_iop_spu_xor_bus1_r3_0 = 0x00000001,
449 regk_iop_spu_xor_bus1m_r3_0 = 0x00000003,
450 regk_iop_spu_yes = 0x00000001,
451 regk_iop_spu_z = 0x00000002
452};
453#endif /* __iop_spu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h
new file mode 100644
index 000000000000..d7b6d75884d2
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h
@@ -0,0 +1,1042 @@
1#ifndef __iop_sw_cfg_defs_h
2#define __iop_sw_cfg_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:10:19 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
11 * id: $Id: iop_sw_cfg_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_sw_cfg */
86
87/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
88typedef struct {
89 unsigned int cfg : 2;
90 unsigned int dummy1 : 30;
91} reg_iop_sw_cfg_rw_crc_par0_owner;
92#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0
93#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0
94
95/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
96typedef struct {
97 unsigned int cfg : 2;
98 unsigned int dummy1 : 30;
99} reg_iop_sw_cfg_rw_crc_par1_owner;
100#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4
101#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4
102
103/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
104typedef struct {
105 unsigned int cfg : 2;
106 unsigned int dummy1 : 30;
107} reg_iop_sw_cfg_rw_dmc_in0_owner;
108#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8
109#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8
110
111/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
112typedef struct {
113 unsigned int cfg : 2;
114 unsigned int dummy1 : 30;
115} reg_iop_sw_cfg_rw_dmc_in1_owner;
116#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12
117#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12
118
119/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
120typedef struct {
121 unsigned int cfg : 2;
122 unsigned int dummy1 : 30;
123} reg_iop_sw_cfg_rw_dmc_out0_owner;
124#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16
125#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16
126
127/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
128typedef struct {
129 unsigned int cfg : 2;
130 unsigned int dummy1 : 30;
131} reg_iop_sw_cfg_rw_dmc_out1_owner;
132#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20
133#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20
134
135/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
136typedef struct {
137 unsigned int cfg : 2;
138 unsigned int dummy1 : 30;
139} reg_iop_sw_cfg_rw_fifo_in0_owner;
140#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24
141#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24
142
143/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
144typedef struct {
145 unsigned int cfg : 2;
146 unsigned int dummy1 : 30;
147} reg_iop_sw_cfg_rw_fifo_in0_extra_owner;
148#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28
149#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28
150
151/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
152typedef struct {
153 unsigned int cfg : 2;
154 unsigned int dummy1 : 30;
155} reg_iop_sw_cfg_rw_fifo_in1_owner;
156#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32
157#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32
158
159/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
160typedef struct {
161 unsigned int cfg : 2;
162 unsigned int dummy1 : 30;
163} reg_iop_sw_cfg_rw_fifo_in1_extra_owner;
164#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36
165#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36
166
167/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
168typedef struct {
169 unsigned int cfg : 2;
170 unsigned int dummy1 : 30;
171} reg_iop_sw_cfg_rw_fifo_out0_owner;
172#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40
173#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40
174
175/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
176typedef struct {
177 unsigned int cfg : 2;
178 unsigned int dummy1 : 30;
179} reg_iop_sw_cfg_rw_fifo_out0_extra_owner;
180#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44
181#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44
182
183/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
184typedef struct {
185 unsigned int cfg : 2;
186 unsigned int dummy1 : 30;
187} reg_iop_sw_cfg_rw_fifo_out1_owner;
188#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48
189#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48
190
191/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
192typedef struct {
193 unsigned int cfg : 2;
194 unsigned int dummy1 : 30;
195} reg_iop_sw_cfg_rw_fifo_out1_extra_owner;
196#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52
197#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52
198
199/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
200typedef struct {
201 unsigned int cfg : 2;
202 unsigned int dummy1 : 30;
203} reg_iop_sw_cfg_rw_sap_in_owner;
204#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56
205#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56
206
207/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
208typedef struct {
209 unsigned int cfg : 2;
210 unsigned int dummy1 : 30;
211} reg_iop_sw_cfg_rw_sap_out_owner;
212#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60
213#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60
214
215/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
216typedef struct {
217 unsigned int cfg : 2;
218 unsigned int dummy1 : 30;
219} reg_iop_sw_cfg_rw_scrc_in0_owner;
220#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64
221#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64
222
223/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
224typedef struct {
225 unsigned int cfg : 2;
226 unsigned int dummy1 : 30;
227} reg_iop_sw_cfg_rw_scrc_in1_owner;
228#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68
229#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68
230
231/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
232typedef struct {
233 unsigned int cfg : 2;
234 unsigned int dummy1 : 30;
235} reg_iop_sw_cfg_rw_scrc_out0_owner;
236#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72
237#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72
238
239/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
240typedef struct {
241 unsigned int cfg : 2;
242 unsigned int dummy1 : 30;
243} reg_iop_sw_cfg_rw_scrc_out1_owner;
244#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76
245#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76
246
247/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
248typedef struct {
249 unsigned int cfg : 2;
250 unsigned int dummy1 : 30;
251} reg_iop_sw_cfg_rw_spu0_owner;
252#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80
253#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80
254
255/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
256typedef struct {
257 unsigned int cfg : 2;
258 unsigned int dummy1 : 30;
259} reg_iop_sw_cfg_rw_spu1_owner;
260#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84
261#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84
262
263/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
264typedef struct {
265 unsigned int cfg : 2;
266 unsigned int dummy1 : 30;
267} reg_iop_sw_cfg_rw_timer_grp0_owner;
268#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88
269#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88
270
271/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
272typedef struct {
273 unsigned int cfg : 2;
274 unsigned int dummy1 : 30;
275} reg_iop_sw_cfg_rw_timer_grp1_owner;
276#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92
277#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92
278
279/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
280typedef struct {
281 unsigned int cfg : 2;
282 unsigned int dummy1 : 30;
283} reg_iop_sw_cfg_rw_timer_grp2_owner;
284#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96
285#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96
286
287/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
288typedef struct {
289 unsigned int cfg : 2;
290 unsigned int dummy1 : 30;
291} reg_iop_sw_cfg_rw_timer_grp3_owner;
292#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100
293#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100
294
295/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
296typedef struct {
297 unsigned int cfg : 2;
298 unsigned int dummy1 : 30;
299} reg_iop_sw_cfg_rw_trigger_grp0_owner;
300#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104
301#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104
302
303/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
304typedef struct {
305 unsigned int cfg : 2;
306 unsigned int dummy1 : 30;
307} reg_iop_sw_cfg_rw_trigger_grp1_owner;
308#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108
309#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108
310
311/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
312typedef struct {
313 unsigned int cfg : 2;
314 unsigned int dummy1 : 30;
315} reg_iop_sw_cfg_rw_trigger_grp2_owner;
316#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112
317#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112
318
319/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
320typedef struct {
321 unsigned int cfg : 2;
322 unsigned int dummy1 : 30;
323} reg_iop_sw_cfg_rw_trigger_grp3_owner;
324#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116
325#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116
326
327/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
328typedef struct {
329 unsigned int cfg : 2;
330 unsigned int dummy1 : 30;
331} reg_iop_sw_cfg_rw_trigger_grp4_owner;
332#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120
333#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120
334
335/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
336typedef struct {
337 unsigned int cfg : 2;
338 unsigned int dummy1 : 30;
339} reg_iop_sw_cfg_rw_trigger_grp5_owner;
340#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124
341#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124
342
343/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
344typedef struct {
345 unsigned int cfg : 2;
346 unsigned int dummy1 : 30;
347} reg_iop_sw_cfg_rw_trigger_grp6_owner;
348#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128
349#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128
350
351/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
352typedef struct {
353 unsigned int cfg : 2;
354 unsigned int dummy1 : 30;
355} reg_iop_sw_cfg_rw_trigger_grp7_owner;
356#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132
357#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132
358
359/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
360typedef struct {
361 unsigned int byte0 : 8;
362 unsigned int byte1 : 8;
363 unsigned int byte2 : 8;
364 unsigned int byte3 : 8;
365} reg_iop_sw_cfg_rw_bus0_mask;
366#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136
367#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136
368
369/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
370typedef struct {
371 unsigned int byte0 : 1;
372 unsigned int byte1 : 1;
373 unsigned int byte2 : 1;
374 unsigned int byte3 : 1;
375 unsigned int dummy1 : 28;
376} reg_iop_sw_cfg_rw_bus0_oe_mask;
377#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140
378#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140
379
380/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
381typedef struct {
382 unsigned int byte0 : 8;
383 unsigned int byte1 : 8;
384 unsigned int byte2 : 8;
385 unsigned int byte3 : 8;
386} reg_iop_sw_cfg_rw_bus1_mask;
387#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144
388#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144
389
390/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
391typedef struct {
392 unsigned int byte0 : 1;
393 unsigned int byte1 : 1;
394 unsigned int byte2 : 1;
395 unsigned int byte3 : 1;
396 unsigned int dummy1 : 28;
397} reg_iop_sw_cfg_rw_bus1_oe_mask;
398#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148
399#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148
400
401/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
402typedef struct {
403 unsigned int val : 32;
404} reg_iop_sw_cfg_rw_gio_mask;
405#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152
406#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152
407
408/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
409typedef struct {
410 unsigned int val : 32;
411} reg_iop_sw_cfg_rw_gio_oe_mask;
412#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156
413#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156
414
415/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
416typedef struct {
417 unsigned int bus0_byte0 : 2;
418 unsigned int bus0_byte1 : 2;
419 unsigned int bus0_byte2 : 2;
420 unsigned int bus0_byte3 : 2;
421 unsigned int bus1_byte0 : 2;
422 unsigned int bus1_byte1 : 2;
423 unsigned int bus1_byte2 : 2;
424 unsigned int bus1_byte3 : 2;
425 unsigned int gio3_0 : 2;
426 unsigned int gio7_4 : 2;
427 unsigned int gio11_8 : 2;
428 unsigned int gio15_12 : 2;
429 unsigned int gio19_16 : 2;
430 unsigned int gio23_20 : 2;
431 unsigned int gio27_24 : 2;
432 unsigned int gio31_28 : 2;
433} reg_iop_sw_cfg_rw_pinmapping;
434#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160
435#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160
436
437/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
438typedef struct {
439 unsigned int bus0_lo : 3;
440 unsigned int bus0_hi : 3;
441 unsigned int bus0_lo_oe : 3;
442 unsigned int bus0_hi_oe : 3;
443 unsigned int bus1_lo : 3;
444 unsigned int bus1_hi : 3;
445 unsigned int bus1_lo_oe : 3;
446 unsigned int bus1_hi_oe : 3;
447 unsigned int dummy1 : 8;
448} reg_iop_sw_cfg_rw_bus_out_cfg;
449#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164
450#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164
451
452/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
453typedef struct {
454 unsigned int gio0 : 4;
455 unsigned int gio0_oe : 2;
456 unsigned int gio1 : 4;
457 unsigned int gio1_oe : 2;
458 unsigned int gio2 : 4;
459 unsigned int gio2_oe : 2;
460 unsigned int gio3 : 4;
461 unsigned int gio3_oe : 2;
462 unsigned int dummy1 : 8;
463} reg_iop_sw_cfg_rw_gio_out_grp0_cfg;
464#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168
465#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168
466
467/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
468typedef struct {
469 unsigned int gio4 : 4;
470 unsigned int gio4_oe : 2;
471 unsigned int gio5 : 4;
472 unsigned int gio5_oe : 2;
473 unsigned int gio6 : 4;
474 unsigned int gio6_oe : 2;
475 unsigned int gio7 : 4;
476 unsigned int gio7_oe : 2;
477 unsigned int dummy1 : 8;
478} reg_iop_sw_cfg_rw_gio_out_grp1_cfg;
479#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172
480#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172
481
482/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
483typedef struct {
484 unsigned int gio8 : 4;
485 unsigned int gio8_oe : 2;
486 unsigned int gio9 : 4;
487 unsigned int gio9_oe : 2;
488 unsigned int gio10 : 4;
489 unsigned int gio10_oe : 2;
490 unsigned int gio11 : 4;
491 unsigned int gio11_oe : 2;
492 unsigned int dummy1 : 8;
493} reg_iop_sw_cfg_rw_gio_out_grp2_cfg;
494#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176
495#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176
496
497/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
498typedef struct {
499 unsigned int gio12 : 4;
500 unsigned int gio12_oe : 2;
501 unsigned int gio13 : 4;
502 unsigned int gio13_oe : 2;
503 unsigned int gio14 : 4;
504 unsigned int gio14_oe : 2;
505 unsigned int gio15 : 4;
506 unsigned int gio15_oe : 2;
507 unsigned int dummy1 : 8;
508} reg_iop_sw_cfg_rw_gio_out_grp3_cfg;
509#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180
510#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180
511
512/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
513typedef struct {
514 unsigned int gio16 : 4;
515 unsigned int gio16_oe : 2;
516 unsigned int gio17 : 4;
517 unsigned int gio17_oe : 2;
518 unsigned int gio18 : 4;
519 unsigned int gio18_oe : 2;
520 unsigned int gio19 : 4;
521 unsigned int gio19_oe : 2;
522 unsigned int dummy1 : 8;
523} reg_iop_sw_cfg_rw_gio_out_grp4_cfg;
524#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184
525#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184
526
527/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
528typedef struct {
529 unsigned int gio20 : 4;
530 unsigned int gio20_oe : 2;
531 unsigned int gio21 : 4;
532 unsigned int gio21_oe : 2;
533 unsigned int gio22 : 4;
534 unsigned int gio22_oe : 2;
535 unsigned int gio23 : 4;
536 unsigned int gio23_oe : 2;
537 unsigned int dummy1 : 8;
538} reg_iop_sw_cfg_rw_gio_out_grp5_cfg;
539#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188
540#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188
541
542/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
543typedef struct {
544 unsigned int gio24 : 4;
545 unsigned int gio24_oe : 2;
546 unsigned int gio25 : 4;
547 unsigned int gio25_oe : 2;
548 unsigned int gio26 : 4;
549 unsigned int gio26_oe : 2;
550 unsigned int gio27 : 4;
551 unsigned int gio27_oe : 2;
552 unsigned int dummy1 : 8;
553} reg_iop_sw_cfg_rw_gio_out_grp6_cfg;
554#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192
555#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192
556
557/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
558typedef struct {
559 unsigned int gio28 : 4;
560 unsigned int gio28_oe : 2;
561 unsigned int gio29 : 4;
562 unsigned int gio29_oe : 2;
563 unsigned int gio30 : 4;
564 unsigned int gio30_oe : 2;
565 unsigned int gio31 : 4;
566 unsigned int gio31_oe : 2;
567 unsigned int dummy1 : 8;
568} reg_iop_sw_cfg_rw_gio_out_grp7_cfg;
569#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196
570#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196
571
572/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
573typedef struct {
574 unsigned int bus0_in : 2;
575 unsigned int bus1_in : 2;
576 unsigned int dummy1 : 28;
577} reg_iop_sw_cfg_rw_spu0_cfg;
578#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200
579#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200
580
581/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
582typedef struct {
583 unsigned int bus0_in : 2;
584 unsigned int bus1_in : 2;
585 unsigned int dummy1 : 28;
586} reg_iop_sw_cfg_rw_spu1_cfg;
587#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204
588#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204
589
590/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
591typedef struct {
592 unsigned int ext_clk : 3;
593 unsigned int tmr0_en : 1;
594 unsigned int tmr1_en : 1;
595 unsigned int tmr2_en : 1;
596 unsigned int tmr3_en : 1;
597 unsigned int tmr0_dis : 1;
598 unsigned int tmr1_dis : 1;
599 unsigned int tmr2_dis : 1;
600 unsigned int tmr3_dis : 1;
601 unsigned int dummy1 : 21;
602} reg_iop_sw_cfg_rw_timer_grp0_cfg;
603#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208
604#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208
605
606/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
607typedef struct {
608 unsigned int ext_clk : 3;
609 unsigned int tmr0_en : 1;
610 unsigned int tmr1_en : 1;
611 unsigned int tmr2_en : 1;
612 unsigned int tmr3_en : 1;
613 unsigned int tmr0_dis : 1;
614 unsigned int tmr1_dis : 1;
615 unsigned int tmr2_dis : 1;
616 unsigned int tmr3_dis : 1;
617 unsigned int dummy1 : 21;
618} reg_iop_sw_cfg_rw_timer_grp1_cfg;
619#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212
620#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212
621
622/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
623typedef struct {
624 unsigned int ext_clk : 3;
625 unsigned int tmr0_en : 1;
626 unsigned int tmr1_en : 1;
627 unsigned int tmr2_en : 1;
628 unsigned int tmr3_en : 1;
629 unsigned int tmr0_dis : 1;
630 unsigned int tmr1_dis : 1;
631 unsigned int tmr2_dis : 1;
632 unsigned int tmr3_dis : 1;
633 unsigned int dummy1 : 21;
634} reg_iop_sw_cfg_rw_timer_grp2_cfg;
635#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216
636#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216
637
638/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
639typedef struct {
640 unsigned int ext_clk : 3;
641 unsigned int tmr0_en : 1;
642 unsigned int tmr1_en : 1;
643 unsigned int tmr2_en : 1;
644 unsigned int tmr3_en : 1;
645 unsigned int tmr0_dis : 1;
646 unsigned int tmr1_dis : 1;
647 unsigned int tmr2_dis : 1;
648 unsigned int tmr3_dis : 1;
649 unsigned int dummy1 : 21;
650} reg_iop_sw_cfg_rw_timer_grp3_cfg;
651#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220
652#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220
653
654/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
655typedef struct {
656 unsigned int grp0_dis : 1;
657 unsigned int grp0_en : 1;
658 unsigned int grp1_dis : 1;
659 unsigned int grp1_en : 1;
660 unsigned int grp2_dis : 1;
661 unsigned int grp2_en : 1;
662 unsigned int grp3_dis : 1;
663 unsigned int grp3_en : 1;
664 unsigned int grp4_dis : 1;
665 unsigned int grp4_en : 1;
666 unsigned int grp5_dis : 1;
667 unsigned int grp5_en : 1;
668 unsigned int grp6_dis : 1;
669 unsigned int grp6_en : 1;
670 unsigned int grp7_dis : 1;
671 unsigned int grp7_en : 1;
672 unsigned int dummy1 : 16;
673} reg_iop_sw_cfg_rw_trigger_grps_cfg;
674#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224
675#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224
676
677/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
678typedef struct {
679 unsigned int dmc0_usr : 1;
680 unsigned int out_strb : 5;
681 unsigned int in_src : 3;
682 unsigned int in_size : 3;
683 unsigned int in_last : 2;
684 unsigned int in_strb : 4;
685 unsigned int out_src : 1;
686 unsigned int dummy1 : 13;
687} reg_iop_sw_cfg_rw_pdp0_cfg;
688#define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228
689#define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228
690
691/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
692typedef struct {
693 unsigned int dmc1_usr : 1;
694 unsigned int out_strb : 5;
695 unsigned int in_src : 3;
696 unsigned int in_size : 3;
697 unsigned int in_last : 2;
698 unsigned int in_strb : 4;
699 unsigned int out_src : 1;
700 unsigned int dummy1 : 13;
701} reg_iop_sw_cfg_rw_pdp1_cfg;
702#define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232
703#define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232
704
705/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
706typedef struct {
707 unsigned int sdp_out0_strb : 3;
708 unsigned int sdp_out1_strb : 3;
709 unsigned int sdp_in0_data : 3;
710 unsigned int sdp_in0_last : 2;
711 unsigned int sdp_in0_strb : 3;
712 unsigned int sdp_in1_data : 3;
713 unsigned int sdp_in1_last : 2;
714 unsigned int sdp_in1_strb : 3;
715 unsigned int dummy1 : 10;
716} reg_iop_sw_cfg_rw_sdp_cfg;
717#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236
718#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236
719
720
721/* Constants */
722enum {
723 regk_iop_sw_cfg_a = 0x00000001,
724 regk_iop_sw_cfg_b = 0x00000002,
725 regk_iop_sw_cfg_bus0 = 0x00000000,
726 regk_iop_sw_cfg_bus0_rot16 = 0x00000004,
727 regk_iop_sw_cfg_bus0_rot24 = 0x00000006,
728 regk_iop_sw_cfg_bus0_rot8 = 0x00000002,
729 regk_iop_sw_cfg_bus1 = 0x00000001,
730 regk_iop_sw_cfg_bus1_rot16 = 0x00000005,
731 regk_iop_sw_cfg_bus1_rot24 = 0x00000007,
732 regk_iop_sw_cfg_bus1_rot8 = 0x00000003,
733 regk_iop_sw_cfg_clk12 = 0x00000000,
734 regk_iop_sw_cfg_cpu = 0x00000000,
735 regk_iop_sw_cfg_dmc0 = 0x00000000,
736 regk_iop_sw_cfg_dmc1 = 0x00000001,
737 regk_iop_sw_cfg_gated_clk0 = 0x00000010,
738 regk_iop_sw_cfg_gated_clk1 = 0x00000011,
739 regk_iop_sw_cfg_gated_clk2 = 0x00000012,
740 regk_iop_sw_cfg_gated_clk3 = 0x00000013,
741 regk_iop_sw_cfg_gio0 = 0x00000004,
742 regk_iop_sw_cfg_gio1 = 0x00000001,
743 regk_iop_sw_cfg_gio2 = 0x00000005,
744 regk_iop_sw_cfg_gio3 = 0x00000002,
745 regk_iop_sw_cfg_gio4 = 0x00000006,
746 regk_iop_sw_cfg_gio5 = 0x00000003,
747 regk_iop_sw_cfg_gio6 = 0x00000007,
748 regk_iop_sw_cfg_gio7 = 0x00000004,
749 regk_iop_sw_cfg_gio_in0 = 0x00000000,
750 regk_iop_sw_cfg_gio_in1 = 0x00000001,
751 regk_iop_sw_cfg_gio_in10 = 0x00000002,
752 regk_iop_sw_cfg_gio_in11 = 0x00000003,
753 regk_iop_sw_cfg_gio_in14 = 0x00000004,
754 regk_iop_sw_cfg_gio_in15 = 0x00000005,
755 regk_iop_sw_cfg_gio_in18 = 0x00000002,
756 regk_iop_sw_cfg_gio_in19 = 0x00000003,
757 regk_iop_sw_cfg_gio_in20 = 0x00000004,
758 regk_iop_sw_cfg_gio_in21 = 0x00000005,
759 regk_iop_sw_cfg_gio_in26 = 0x00000006,
760 regk_iop_sw_cfg_gio_in27 = 0x00000007,
761 regk_iop_sw_cfg_gio_in28 = 0x00000006,
762 regk_iop_sw_cfg_gio_in29 = 0x00000007,
763 regk_iop_sw_cfg_gio_in4 = 0x00000000,
764 regk_iop_sw_cfg_gio_in5 = 0x00000001,
765 regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001,
766 regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000001,
767 regk_iop_sw_cfg_last_timer_grp2_tmr2 = 0x00000002,
768 regk_iop_sw_cfg_last_timer_grp2_tmr3 = 0x00000003,
769 regk_iop_sw_cfg_last_timer_grp3_tmr2 = 0x00000002,
770 regk_iop_sw_cfg_last_timer_grp3_tmr3 = 0x00000003,
771 regk_iop_sw_cfg_mpu = 0x00000001,
772 regk_iop_sw_cfg_none = 0x00000000,
773 regk_iop_sw_cfg_par0 = 0x00000000,
774 regk_iop_sw_cfg_par1 = 0x00000001,
775 regk_iop_sw_cfg_pdp_out0 = 0x00000002,
776 regk_iop_sw_cfg_pdp_out0_hi = 0x00000001,
777 regk_iop_sw_cfg_pdp_out0_hi_rot8 = 0x00000005,
778 regk_iop_sw_cfg_pdp_out0_lo = 0x00000000,
779 regk_iop_sw_cfg_pdp_out0_lo_rot8 = 0x00000004,
780 regk_iop_sw_cfg_pdp_out1 = 0x00000003,
781 regk_iop_sw_cfg_pdp_out1_hi = 0x00000003,
782 regk_iop_sw_cfg_pdp_out1_hi_rot8 = 0x00000005,
783 regk_iop_sw_cfg_pdp_out1_lo = 0x00000002,
784 regk_iop_sw_cfg_pdp_out1_lo_rot8 = 0x00000004,
785 regk_iop_sw_cfg_rw_bus0_mask_default = 0x00000000,
786 regk_iop_sw_cfg_rw_bus0_oe_mask_default = 0x00000000,
787 regk_iop_sw_cfg_rw_bus1_mask_default = 0x00000000,
788 regk_iop_sw_cfg_rw_bus1_oe_mask_default = 0x00000000,
789 regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000,
790 regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000,
791 regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000,
792 regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000,
793 regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000,
794 regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000,
795 regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000,
796 regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000,
797 regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000,
798 regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000,
799 regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000,
800 regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000,
801 regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000,
802 regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000,
803 regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000,
804 regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000,
805 regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000,
806 regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000,
807 regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000,
808 regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000,
809 regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000,
810 regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000,
811 regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000,
812 regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000,
813 regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000,
814 regk_iop_sw_cfg_rw_pdp0_cfg_default = 0x00000000,
815 regk_iop_sw_cfg_rw_pdp1_cfg_default = 0x00000000,
816 regk_iop_sw_cfg_rw_pinmapping_default = 0x55555555,
817 regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000,
818 regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000,
819 regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000,
820 regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000,
821 regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000,
822 regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000,
823 regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000,
824 regk_iop_sw_cfg_rw_spu0_cfg_default = 0x00000000,
825 regk_iop_sw_cfg_rw_spu0_owner_default = 0x00000000,
826 regk_iop_sw_cfg_rw_spu1_cfg_default = 0x00000000,
827 regk_iop_sw_cfg_rw_spu1_owner_default = 0x00000000,
828 regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000,
829 regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000,
830 regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000,
831 regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000,
832 regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000,
833 regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000,
834 regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000,
835 regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000,
836 regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000,
837 regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000,
838 regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000,
839 regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000,
840 regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000,
841 regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000,
842 regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000,
843 regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000,
844 regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000,
845 regk_iop_sw_cfg_sdp_out0 = 0x00000008,
846 regk_iop_sw_cfg_sdp_out1 = 0x00000009,
847 regk_iop_sw_cfg_size16 = 0x00000002,
848 regk_iop_sw_cfg_size24 = 0x00000003,
849 regk_iop_sw_cfg_size32 = 0x00000004,
850 regk_iop_sw_cfg_size8 = 0x00000001,
851 regk_iop_sw_cfg_spu0 = 0x00000002,
852 regk_iop_sw_cfg_spu0_bus_out0_hi = 0x00000006,
853 regk_iop_sw_cfg_spu0_bus_out0_lo = 0x00000006,
854 regk_iop_sw_cfg_spu0_bus_out1_hi = 0x00000007,
855 regk_iop_sw_cfg_spu0_bus_out1_lo = 0x00000007,
856 regk_iop_sw_cfg_spu0_g0 = 0x0000000e,
857 regk_iop_sw_cfg_spu0_g1 = 0x0000000e,
858 regk_iop_sw_cfg_spu0_g2 = 0x0000000e,
859 regk_iop_sw_cfg_spu0_g3 = 0x0000000e,
860 regk_iop_sw_cfg_spu0_g4 = 0x0000000e,
861 regk_iop_sw_cfg_spu0_g5 = 0x0000000e,
862 regk_iop_sw_cfg_spu0_g6 = 0x0000000e,
863 regk_iop_sw_cfg_spu0_g7 = 0x0000000e,
864 regk_iop_sw_cfg_spu0_gio0 = 0x00000000,
865 regk_iop_sw_cfg_spu0_gio1 = 0x00000001,
866 regk_iop_sw_cfg_spu0_gio2 = 0x00000000,
867 regk_iop_sw_cfg_spu0_gio5 = 0x00000005,
868 regk_iop_sw_cfg_spu0_gio6 = 0x00000006,
869 regk_iop_sw_cfg_spu0_gio7 = 0x00000007,
870 regk_iop_sw_cfg_spu0_gio_out0 = 0x00000008,
871 regk_iop_sw_cfg_spu0_gio_out1 = 0x00000009,
872 regk_iop_sw_cfg_spu0_gio_out2 = 0x0000000a,
873 regk_iop_sw_cfg_spu0_gio_out3 = 0x0000000b,
874 regk_iop_sw_cfg_spu0_gio_out4 = 0x0000000c,
875 regk_iop_sw_cfg_spu0_gio_out5 = 0x0000000d,
876 regk_iop_sw_cfg_spu0_gio_out6 = 0x0000000e,
877 regk_iop_sw_cfg_spu0_gio_out7 = 0x0000000f,
878 regk_iop_sw_cfg_spu0_gioout0 = 0x00000000,
879 regk_iop_sw_cfg_spu0_gioout1 = 0x00000000,
880 regk_iop_sw_cfg_spu0_gioout10 = 0x0000000e,
881 regk_iop_sw_cfg_spu0_gioout11 = 0x0000000e,
882 regk_iop_sw_cfg_spu0_gioout12 = 0x0000000e,
883 regk_iop_sw_cfg_spu0_gioout13 = 0x0000000e,
884 regk_iop_sw_cfg_spu0_gioout14 = 0x0000000e,
885 regk_iop_sw_cfg_spu0_gioout15 = 0x0000000e,
886 regk_iop_sw_cfg_spu0_gioout16 = 0x0000000e,
887 regk_iop_sw_cfg_spu0_gioout17 = 0x0000000e,
888 regk_iop_sw_cfg_spu0_gioout18 = 0x0000000e,
889 regk_iop_sw_cfg_spu0_gioout19 = 0x0000000e,
890 regk_iop_sw_cfg_spu0_gioout2 = 0x00000002,
891 regk_iop_sw_cfg_spu0_gioout20 = 0x0000000e,
892 regk_iop_sw_cfg_spu0_gioout21 = 0x0000000e,
893 regk_iop_sw_cfg_spu0_gioout22 = 0x0000000e,
894 regk_iop_sw_cfg_spu0_gioout23 = 0x0000000e,
895 regk_iop_sw_cfg_spu0_gioout24 = 0x0000000e,
896 regk_iop_sw_cfg_spu0_gioout25 = 0x0000000e,
897 regk_iop_sw_cfg_spu0_gioout26 = 0x0000000e,
898 regk_iop_sw_cfg_spu0_gioout27 = 0x0000000e,
899 regk_iop_sw_cfg_spu0_gioout28 = 0x0000000e,
900 regk_iop_sw_cfg_spu0_gioout29 = 0x0000000e,
901 regk_iop_sw_cfg_spu0_gioout3 = 0x00000002,
902 regk_iop_sw_cfg_spu0_gioout30 = 0x0000000e,
903 regk_iop_sw_cfg_spu0_gioout31 = 0x0000000e,
904 regk_iop_sw_cfg_spu0_gioout4 = 0x00000004,
905 regk_iop_sw_cfg_spu0_gioout5 = 0x00000004,
906 regk_iop_sw_cfg_spu0_gioout6 = 0x00000006,
907 regk_iop_sw_cfg_spu0_gioout7 = 0x00000006,
908 regk_iop_sw_cfg_spu0_gioout8 = 0x0000000e,
909 regk_iop_sw_cfg_spu0_gioout9 = 0x0000000e,
910 regk_iop_sw_cfg_spu1 = 0x00000003,
911 regk_iop_sw_cfg_spu1_bus_out0_hi = 0x00000006,
912 regk_iop_sw_cfg_spu1_bus_out0_lo = 0x00000006,
913 regk_iop_sw_cfg_spu1_bus_out1_hi = 0x00000007,
914 regk_iop_sw_cfg_spu1_bus_out1_lo = 0x00000007,
915 regk_iop_sw_cfg_spu1_g0 = 0x0000000f,
916 regk_iop_sw_cfg_spu1_g1 = 0x0000000f,
917 regk_iop_sw_cfg_spu1_g2 = 0x0000000f,
918 regk_iop_sw_cfg_spu1_g3 = 0x0000000f,
919 regk_iop_sw_cfg_spu1_g4 = 0x0000000f,
920 regk_iop_sw_cfg_spu1_g5 = 0x0000000f,
921 regk_iop_sw_cfg_spu1_g6 = 0x0000000f,
922 regk_iop_sw_cfg_spu1_g7 = 0x0000000f,
923 regk_iop_sw_cfg_spu1_gio0 = 0x00000002,
924 regk_iop_sw_cfg_spu1_gio1 = 0x00000003,
925 regk_iop_sw_cfg_spu1_gio2 = 0x00000002,
926 regk_iop_sw_cfg_spu1_gio5 = 0x00000005,
927 regk_iop_sw_cfg_spu1_gio6 = 0x00000006,
928 regk_iop_sw_cfg_spu1_gio7 = 0x00000007,
929 regk_iop_sw_cfg_spu1_gio_out0 = 0x00000008,
930 regk_iop_sw_cfg_spu1_gio_out1 = 0x00000009,
931 regk_iop_sw_cfg_spu1_gio_out2 = 0x0000000a,
932 regk_iop_sw_cfg_spu1_gio_out3 = 0x0000000b,
933 regk_iop_sw_cfg_spu1_gio_out4 = 0x0000000c,
934 regk_iop_sw_cfg_spu1_gio_out5 = 0x0000000d,
935 regk_iop_sw_cfg_spu1_gio_out6 = 0x0000000e,
936 regk_iop_sw_cfg_spu1_gio_out7 = 0x0000000f,
937 regk_iop_sw_cfg_spu1_gioout0 = 0x00000001,
938 regk_iop_sw_cfg_spu1_gioout1 = 0x00000001,
939 regk_iop_sw_cfg_spu1_gioout10 = 0x0000000f,
940 regk_iop_sw_cfg_spu1_gioout11 = 0x0000000f,
941 regk_iop_sw_cfg_spu1_gioout12 = 0x0000000f,
942 regk_iop_sw_cfg_spu1_gioout13 = 0x0000000f,
943 regk_iop_sw_cfg_spu1_gioout14 = 0x0000000f,
944 regk_iop_sw_cfg_spu1_gioout15 = 0x0000000f,
945 regk_iop_sw_cfg_spu1_gioout16 = 0x0000000f,
946 regk_iop_sw_cfg_spu1_gioout17 = 0x0000000f,
947 regk_iop_sw_cfg_spu1_gioout18 = 0x0000000f,
948 regk_iop_sw_cfg_spu1_gioout19 = 0x0000000f,
949 regk_iop_sw_cfg_spu1_gioout2 = 0x00000003,
950 regk_iop_sw_cfg_spu1_gioout20 = 0x0000000f,
951 regk_iop_sw_cfg_spu1_gioout21 = 0x0000000f,
952 regk_iop_sw_cfg_spu1_gioout22 = 0x0000000f,
953 regk_iop_sw_cfg_spu1_gioout23 = 0x0000000f,
954 regk_iop_sw_cfg_spu1_gioout24 = 0x0000000f,
955 regk_iop_sw_cfg_spu1_gioout25 = 0x0000000f,
956 regk_iop_sw_cfg_spu1_gioout26 = 0x0000000f,
957 regk_iop_sw_cfg_spu1_gioout27 = 0x0000000f,
958 regk_iop_sw_cfg_spu1_gioout28 = 0x0000000f,
959 regk_iop_sw_cfg_spu1_gioout29 = 0x0000000f,
960 regk_iop_sw_cfg_spu1_gioout3 = 0x00000003,
961 regk_iop_sw_cfg_spu1_gioout30 = 0x0000000f,
962 regk_iop_sw_cfg_spu1_gioout31 = 0x0000000f,
963 regk_iop_sw_cfg_spu1_gioout4 = 0x00000005,
964 regk_iop_sw_cfg_spu1_gioout5 = 0x00000005,
965 regk_iop_sw_cfg_spu1_gioout6 = 0x00000007,
966 regk_iop_sw_cfg_spu1_gioout7 = 0x00000007,
967 regk_iop_sw_cfg_spu1_gioout8 = 0x0000000f,
968 regk_iop_sw_cfg_spu1_gioout9 = 0x0000000f,
969 regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001,
970 regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002,
971 regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000001,
972 regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002,
973 regk_iop_sw_cfg_strb_timer_grp2_tmr0 = 0x00000003,
974 regk_iop_sw_cfg_strb_timer_grp2_tmr1 = 0x00000002,
975 regk_iop_sw_cfg_strb_timer_grp3_tmr0 = 0x00000003,
976 regk_iop_sw_cfg_strb_timer_grp3_tmr1 = 0x00000002,
977 regk_iop_sw_cfg_timer_grp0 = 0x00000000,
978 regk_iop_sw_cfg_timer_grp0_rot = 0x00000001,
979 regk_iop_sw_cfg_timer_grp0_strb0 = 0x0000000a,
980 regk_iop_sw_cfg_timer_grp0_strb1 = 0x0000000a,
981 regk_iop_sw_cfg_timer_grp0_strb2 = 0x0000000a,
982 regk_iop_sw_cfg_timer_grp0_strb3 = 0x0000000a,
983 regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000004,
984 regk_iop_sw_cfg_timer_grp0_tmr1 = 0x00000004,
985 regk_iop_sw_cfg_timer_grp1 = 0x00000000,
986 regk_iop_sw_cfg_timer_grp1_rot = 0x00000001,
987 regk_iop_sw_cfg_timer_grp1_strb0 = 0x0000000b,
988 regk_iop_sw_cfg_timer_grp1_strb1 = 0x0000000b,
989 regk_iop_sw_cfg_timer_grp1_strb2 = 0x0000000b,
990 regk_iop_sw_cfg_timer_grp1_strb3 = 0x0000000b,
991 regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000005,
992 regk_iop_sw_cfg_timer_grp1_tmr1 = 0x00000005,
993 regk_iop_sw_cfg_timer_grp2 = 0x00000000,
994 regk_iop_sw_cfg_timer_grp2_rot = 0x00000001,
995 regk_iop_sw_cfg_timer_grp2_strb0 = 0x0000000c,
996 regk_iop_sw_cfg_timer_grp2_strb1 = 0x0000000c,
997 regk_iop_sw_cfg_timer_grp2_strb2 = 0x0000000c,
998 regk_iop_sw_cfg_timer_grp2_strb3 = 0x0000000c,
999 regk_iop_sw_cfg_timer_grp2_tmr0 = 0x00000006,
1000 regk_iop_sw_cfg_timer_grp2_tmr1 = 0x00000006,
1001 regk_iop_sw_cfg_timer_grp3 = 0x00000000,
1002 regk_iop_sw_cfg_timer_grp3_rot = 0x00000001,
1003 regk_iop_sw_cfg_timer_grp3_strb0 = 0x0000000d,
1004 regk_iop_sw_cfg_timer_grp3_strb1 = 0x0000000d,
1005 regk_iop_sw_cfg_timer_grp3_strb2 = 0x0000000d,
1006 regk_iop_sw_cfg_timer_grp3_strb3 = 0x0000000d,
1007 regk_iop_sw_cfg_timer_grp3_tmr0 = 0x00000007,
1008 regk_iop_sw_cfg_timer_grp3_tmr1 = 0x00000007,
1009 regk_iop_sw_cfg_trig0_0 = 0x00000000,
1010 regk_iop_sw_cfg_trig0_1 = 0x00000000,
1011 regk_iop_sw_cfg_trig0_2 = 0x00000000,
1012 regk_iop_sw_cfg_trig0_3 = 0x00000000,
1013 regk_iop_sw_cfg_trig1_0 = 0x00000000,
1014 regk_iop_sw_cfg_trig1_1 = 0x00000000,
1015 regk_iop_sw_cfg_trig1_2 = 0x00000000,
1016 regk_iop_sw_cfg_trig1_3 = 0x00000000,
1017 regk_iop_sw_cfg_trig2_0 = 0x00000000,
1018 regk_iop_sw_cfg_trig2_1 = 0x00000000,
1019 regk_iop_sw_cfg_trig2_2 = 0x00000000,
1020 regk_iop_sw_cfg_trig2_3 = 0x00000000,
1021 regk_iop_sw_cfg_trig3_0 = 0x00000000,
1022 regk_iop_sw_cfg_trig3_1 = 0x00000000,
1023 regk_iop_sw_cfg_trig3_2 = 0x00000000,
1024 regk_iop_sw_cfg_trig3_3 = 0x00000000,
1025 regk_iop_sw_cfg_trig4_0 = 0x00000001,
1026 regk_iop_sw_cfg_trig4_1 = 0x00000001,
1027 regk_iop_sw_cfg_trig4_2 = 0x00000001,
1028 regk_iop_sw_cfg_trig4_3 = 0x00000001,
1029 regk_iop_sw_cfg_trig5_0 = 0x00000001,
1030 regk_iop_sw_cfg_trig5_1 = 0x00000001,
1031 regk_iop_sw_cfg_trig5_2 = 0x00000001,
1032 regk_iop_sw_cfg_trig5_3 = 0x00000001,
1033 regk_iop_sw_cfg_trig6_0 = 0x00000001,
1034 regk_iop_sw_cfg_trig6_1 = 0x00000001,
1035 regk_iop_sw_cfg_trig6_2 = 0x00000001,
1036 regk_iop_sw_cfg_trig6_3 = 0x00000001,
1037 regk_iop_sw_cfg_trig7_0 = 0x00000001,
1038 regk_iop_sw_cfg_trig7_1 = 0x00000001,
1039 regk_iop_sw_cfg_trig7_2 = 0x00000001,
1040 regk_iop_sw_cfg_trig7_3 = 0x00000001
1041};
1042#endif /* __iop_sw_cfg_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h
new file mode 100644
index 000000000000..5fed844b19e2
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h
@@ -0,0 +1,853 @@
1#ifndef __iop_sw_cpu_defs_h
2#define __iop_sw_cpu_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:10:19 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
11 * id: $Id: iop_sw_cpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_sw_cpu */
86
87/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
88typedef struct {
89 unsigned int keep_owner : 1;
90 unsigned int cmd : 2;
91 unsigned int size : 3;
92 unsigned int wr_spu0_mem : 1;
93 unsigned int wr_spu1_mem : 1;
94 unsigned int dummy1 : 24;
95} reg_iop_sw_cpu_rw_mc_ctrl;
96#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 0
97#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 0
98
99/* Register rw_mc_data, scope iop_sw_cpu, type rw */
100typedef struct {
101 unsigned int val : 32;
102} reg_iop_sw_cpu_rw_mc_data;
103#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 4
104#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 4
105
106/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
107typedef unsigned int reg_iop_sw_cpu_rw_mc_addr;
108#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 8
109#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 8
110
111/* Register rs_mc_data, scope iop_sw_cpu, type rs */
112typedef unsigned int reg_iop_sw_cpu_rs_mc_data;
113#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 12
114
115/* Register r_mc_data, scope iop_sw_cpu, type r */
116typedef unsigned int reg_iop_sw_cpu_r_mc_data;
117#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 16
118
119/* Register r_mc_stat, scope iop_sw_cpu, type r */
120typedef struct {
121 unsigned int busy_cpu : 1;
122 unsigned int busy_mpu : 1;
123 unsigned int busy_spu0 : 1;
124 unsigned int busy_spu1 : 1;
125 unsigned int owned_by_cpu : 1;
126 unsigned int owned_by_mpu : 1;
127 unsigned int owned_by_spu0 : 1;
128 unsigned int owned_by_spu1 : 1;
129 unsigned int dummy1 : 24;
130} reg_iop_sw_cpu_r_mc_stat;
131#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 20
132
133/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */
134typedef struct {
135 unsigned int byte0 : 8;
136 unsigned int byte1 : 8;
137 unsigned int byte2 : 8;
138 unsigned int byte3 : 8;
139} reg_iop_sw_cpu_rw_bus0_clr_mask;
140#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24
141#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24
142
143/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */
144typedef struct {
145 unsigned int byte0 : 8;
146 unsigned int byte1 : 8;
147 unsigned int byte2 : 8;
148 unsigned int byte3 : 8;
149} reg_iop_sw_cpu_rw_bus0_set_mask;
150#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask 28
151#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask 28
152
153/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */
154typedef struct {
155 unsigned int byte0 : 1;
156 unsigned int byte1 : 1;
157 unsigned int byte2 : 1;
158 unsigned int byte3 : 1;
159 unsigned int dummy1 : 28;
160} reg_iop_sw_cpu_rw_bus0_oe_clr_mask;
161#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32
162#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32
163
164/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */
165typedef struct {
166 unsigned int byte0 : 1;
167 unsigned int byte1 : 1;
168 unsigned int byte2 : 1;
169 unsigned int byte3 : 1;
170 unsigned int dummy1 : 28;
171} reg_iop_sw_cpu_rw_bus0_oe_set_mask;
172#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36
173#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36
174
175/* Register r_bus0_in, scope iop_sw_cpu, type r */
176typedef unsigned int reg_iop_sw_cpu_r_bus0_in;
177#define REG_RD_ADDR_iop_sw_cpu_r_bus0_in 40
178
179/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */
180typedef struct {
181 unsigned int byte0 : 8;
182 unsigned int byte1 : 8;
183 unsigned int byte2 : 8;
184 unsigned int byte3 : 8;
185} reg_iop_sw_cpu_rw_bus1_clr_mask;
186#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44
187#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44
188
189/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */
190typedef struct {
191 unsigned int byte0 : 8;
192 unsigned int byte1 : 8;
193 unsigned int byte2 : 8;
194 unsigned int byte3 : 8;
195} reg_iop_sw_cpu_rw_bus1_set_mask;
196#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask 48
197#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask 48
198
199/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */
200typedef struct {
201 unsigned int byte0 : 1;
202 unsigned int byte1 : 1;
203 unsigned int byte2 : 1;
204 unsigned int byte3 : 1;
205 unsigned int dummy1 : 28;
206} reg_iop_sw_cpu_rw_bus1_oe_clr_mask;
207#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52
208#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52
209
210/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */
211typedef struct {
212 unsigned int byte0 : 1;
213 unsigned int byte1 : 1;
214 unsigned int byte2 : 1;
215 unsigned int byte3 : 1;
216 unsigned int dummy1 : 28;
217} reg_iop_sw_cpu_rw_bus1_oe_set_mask;
218#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56
219#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56
220
221/* Register r_bus1_in, scope iop_sw_cpu, type r */
222typedef unsigned int reg_iop_sw_cpu_r_bus1_in;
223#define REG_RD_ADDR_iop_sw_cpu_r_bus1_in 60
224
225/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
226typedef struct {
227 unsigned int val : 32;
228} reg_iop_sw_cpu_rw_gio_clr_mask;
229#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 64
230#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 64
231
232/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
233typedef struct {
234 unsigned int val : 32;
235} reg_iop_sw_cpu_rw_gio_set_mask;
236#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 68
237#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 68
238
239/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
240typedef struct {
241 unsigned int val : 32;
242} reg_iop_sw_cpu_rw_gio_oe_clr_mask;
243#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72
244#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72
245
246/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
247typedef struct {
248 unsigned int val : 32;
249} reg_iop_sw_cpu_rw_gio_oe_set_mask;
250#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76
251#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76
252
253/* Register r_gio_in, scope iop_sw_cpu, type r */
254typedef unsigned int reg_iop_sw_cpu_r_gio_in;
255#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 80
256
257/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
258typedef struct {
259 unsigned int mpu_0 : 1;
260 unsigned int mpu_1 : 1;
261 unsigned int mpu_2 : 1;
262 unsigned int mpu_3 : 1;
263 unsigned int mpu_4 : 1;
264 unsigned int mpu_5 : 1;
265 unsigned int mpu_6 : 1;
266 unsigned int mpu_7 : 1;
267 unsigned int mpu_8 : 1;
268 unsigned int mpu_9 : 1;
269 unsigned int mpu_10 : 1;
270 unsigned int mpu_11 : 1;
271 unsigned int mpu_12 : 1;
272 unsigned int mpu_13 : 1;
273 unsigned int mpu_14 : 1;
274 unsigned int mpu_15 : 1;
275 unsigned int spu0_0 : 1;
276 unsigned int spu0_1 : 1;
277 unsigned int spu0_2 : 1;
278 unsigned int spu0_3 : 1;
279 unsigned int spu0_4 : 1;
280 unsigned int spu0_5 : 1;
281 unsigned int spu0_6 : 1;
282 unsigned int spu0_7 : 1;
283 unsigned int spu1_8 : 1;
284 unsigned int spu1_9 : 1;
285 unsigned int spu1_10 : 1;
286 unsigned int spu1_11 : 1;
287 unsigned int spu1_12 : 1;
288 unsigned int spu1_13 : 1;
289 unsigned int spu1_14 : 1;
290 unsigned int spu1_15 : 1;
291} reg_iop_sw_cpu_rw_intr0_mask;
292#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 84
293#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 84
294
295/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
296typedef struct {
297 unsigned int mpu_0 : 1;
298 unsigned int mpu_1 : 1;
299 unsigned int mpu_2 : 1;
300 unsigned int mpu_3 : 1;
301 unsigned int mpu_4 : 1;
302 unsigned int mpu_5 : 1;
303 unsigned int mpu_6 : 1;
304 unsigned int mpu_7 : 1;
305 unsigned int mpu_8 : 1;
306 unsigned int mpu_9 : 1;
307 unsigned int mpu_10 : 1;
308 unsigned int mpu_11 : 1;
309 unsigned int mpu_12 : 1;
310 unsigned int mpu_13 : 1;
311 unsigned int mpu_14 : 1;
312 unsigned int mpu_15 : 1;
313 unsigned int spu0_0 : 1;
314 unsigned int spu0_1 : 1;
315 unsigned int spu0_2 : 1;
316 unsigned int spu0_3 : 1;
317 unsigned int spu0_4 : 1;
318 unsigned int spu0_5 : 1;
319 unsigned int spu0_6 : 1;
320 unsigned int spu0_7 : 1;
321 unsigned int spu1_8 : 1;
322 unsigned int spu1_9 : 1;
323 unsigned int spu1_10 : 1;
324 unsigned int spu1_11 : 1;
325 unsigned int spu1_12 : 1;
326 unsigned int spu1_13 : 1;
327 unsigned int spu1_14 : 1;
328 unsigned int spu1_15 : 1;
329} reg_iop_sw_cpu_rw_ack_intr0;
330#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 88
331#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 88
332
333/* Register r_intr0, scope iop_sw_cpu, type r */
334typedef struct {
335 unsigned int mpu_0 : 1;
336 unsigned int mpu_1 : 1;
337 unsigned int mpu_2 : 1;
338 unsigned int mpu_3 : 1;
339 unsigned int mpu_4 : 1;
340 unsigned int mpu_5 : 1;
341 unsigned int mpu_6 : 1;
342 unsigned int mpu_7 : 1;
343 unsigned int mpu_8 : 1;
344 unsigned int mpu_9 : 1;
345 unsigned int mpu_10 : 1;
346 unsigned int mpu_11 : 1;
347 unsigned int mpu_12 : 1;
348 unsigned int mpu_13 : 1;
349 unsigned int mpu_14 : 1;
350 unsigned int mpu_15 : 1;
351 unsigned int spu0_0 : 1;
352 unsigned int spu0_1 : 1;
353 unsigned int spu0_2 : 1;
354 unsigned int spu0_3 : 1;
355 unsigned int spu0_4 : 1;
356 unsigned int spu0_5 : 1;
357 unsigned int spu0_6 : 1;
358 unsigned int spu0_7 : 1;
359 unsigned int spu1_8 : 1;
360 unsigned int spu1_9 : 1;
361 unsigned int spu1_10 : 1;
362 unsigned int spu1_11 : 1;
363 unsigned int spu1_12 : 1;
364 unsigned int spu1_13 : 1;
365 unsigned int spu1_14 : 1;
366 unsigned int spu1_15 : 1;
367} reg_iop_sw_cpu_r_intr0;
368#define REG_RD_ADDR_iop_sw_cpu_r_intr0 92
369
370/* Register r_masked_intr0, scope iop_sw_cpu, type r */
371typedef struct {
372 unsigned int mpu_0 : 1;
373 unsigned int mpu_1 : 1;
374 unsigned int mpu_2 : 1;
375 unsigned int mpu_3 : 1;
376 unsigned int mpu_4 : 1;
377 unsigned int mpu_5 : 1;
378 unsigned int mpu_6 : 1;
379 unsigned int mpu_7 : 1;
380 unsigned int mpu_8 : 1;
381 unsigned int mpu_9 : 1;
382 unsigned int mpu_10 : 1;
383 unsigned int mpu_11 : 1;
384 unsigned int mpu_12 : 1;
385 unsigned int mpu_13 : 1;
386 unsigned int mpu_14 : 1;
387 unsigned int mpu_15 : 1;
388 unsigned int spu0_0 : 1;
389 unsigned int spu0_1 : 1;
390 unsigned int spu0_2 : 1;
391 unsigned int spu0_3 : 1;
392 unsigned int spu0_4 : 1;
393 unsigned int spu0_5 : 1;
394 unsigned int spu0_6 : 1;
395 unsigned int spu0_7 : 1;
396 unsigned int spu1_8 : 1;
397 unsigned int spu1_9 : 1;
398 unsigned int spu1_10 : 1;
399 unsigned int spu1_11 : 1;
400 unsigned int spu1_12 : 1;
401 unsigned int spu1_13 : 1;
402 unsigned int spu1_14 : 1;
403 unsigned int spu1_15 : 1;
404} reg_iop_sw_cpu_r_masked_intr0;
405#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 96
406
407/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
408typedef struct {
409 unsigned int mpu_16 : 1;
410 unsigned int mpu_17 : 1;
411 unsigned int mpu_18 : 1;
412 unsigned int mpu_19 : 1;
413 unsigned int mpu_20 : 1;
414 unsigned int mpu_21 : 1;
415 unsigned int mpu_22 : 1;
416 unsigned int mpu_23 : 1;
417 unsigned int mpu_24 : 1;
418 unsigned int mpu_25 : 1;
419 unsigned int mpu_26 : 1;
420 unsigned int mpu_27 : 1;
421 unsigned int mpu_28 : 1;
422 unsigned int mpu_29 : 1;
423 unsigned int mpu_30 : 1;
424 unsigned int mpu_31 : 1;
425 unsigned int spu0_8 : 1;
426 unsigned int spu0_9 : 1;
427 unsigned int spu0_10 : 1;
428 unsigned int spu0_11 : 1;
429 unsigned int spu0_12 : 1;
430 unsigned int spu0_13 : 1;
431 unsigned int spu0_14 : 1;
432 unsigned int spu0_15 : 1;
433 unsigned int spu1_0 : 1;
434 unsigned int spu1_1 : 1;
435 unsigned int spu1_2 : 1;
436 unsigned int spu1_3 : 1;
437 unsigned int spu1_4 : 1;
438 unsigned int spu1_5 : 1;
439 unsigned int spu1_6 : 1;
440 unsigned int spu1_7 : 1;
441} reg_iop_sw_cpu_rw_intr1_mask;
442#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100
443#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100
444
445/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
446typedef struct {
447 unsigned int mpu_16 : 1;
448 unsigned int mpu_17 : 1;
449 unsigned int mpu_18 : 1;
450 unsigned int mpu_19 : 1;
451 unsigned int mpu_20 : 1;
452 unsigned int mpu_21 : 1;
453 unsigned int mpu_22 : 1;
454 unsigned int mpu_23 : 1;
455 unsigned int mpu_24 : 1;
456 unsigned int mpu_25 : 1;
457 unsigned int mpu_26 : 1;
458 unsigned int mpu_27 : 1;
459 unsigned int mpu_28 : 1;
460 unsigned int mpu_29 : 1;
461 unsigned int mpu_30 : 1;
462 unsigned int mpu_31 : 1;
463 unsigned int spu0_8 : 1;
464 unsigned int spu0_9 : 1;
465 unsigned int spu0_10 : 1;
466 unsigned int spu0_11 : 1;
467 unsigned int spu0_12 : 1;
468 unsigned int spu0_13 : 1;
469 unsigned int spu0_14 : 1;
470 unsigned int spu0_15 : 1;
471 unsigned int spu1_0 : 1;
472 unsigned int spu1_1 : 1;
473 unsigned int spu1_2 : 1;
474 unsigned int spu1_3 : 1;
475 unsigned int spu1_4 : 1;
476 unsigned int spu1_5 : 1;
477 unsigned int spu1_6 : 1;
478 unsigned int spu1_7 : 1;
479} reg_iop_sw_cpu_rw_ack_intr1;
480#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104
481#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104
482
483/* Register r_intr1, scope iop_sw_cpu, type r */
484typedef struct {
485 unsigned int mpu_16 : 1;
486 unsigned int mpu_17 : 1;
487 unsigned int mpu_18 : 1;
488 unsigned int mpu_19 : 1;
489 unsigned int mpu_20 : 1;
490 unsigned int mpu_21 : 1;
491 unsigned int mpu_22 : 1;
492 unsigned int mpu_23 : 1;
493 unsigned int mpu_24 : 1;
494 unsigned int mpu_25 : 1;
495 unsigned int mpu_26 : 1;
496 unsigned int mpu_27 : 1;
497 unsigned int mpu_28 : 1;
498 unsigned int mpu_29 : 1;
499 unsigned int mpu_30 : 1;
500 unsigned int mpu_31 : 1;
501 unsigned int spu0_8 : 1;
502 unsigned int spu0_9 : 1;
503 unsigned int spu0_10 : 1;
504 unsigned int spu0_11 : 1;
505 unsigned int spu0_12 : 1;
506 unsigned int spu0_13 : 1;
507 unsigned int spu0_14 : 1;
508 unsigned int spu0_15 : 1;
509 unsigned int spu1_0 : 1;
510 unsigned int spu1_1 : 1;
511 unsigned int spu1_2 : 1;
512 unsigned int spu1_3 : 1;
513 unsigned int spu1_4 : 1;
514 unsigned int spu1_5 : 1;
515 unsigned int spu1_6 : 1;
516 unsigned int spu1_7 : 1;
517} reg_iop_sw_cpu_r_intr1;
518#define REG_RD_ADDR_iop_sw_cpu_r_intr1 108
519
520/* Register r_masked_intr1, scope iop_sw_cpu, type r */
521typedef struct {
522 unsigned int mpu_16 : 1;
523 unsigned int mpu_17 : 1;
524 unsigned int mpu_18 : 1;
525 unsigned int mpu_19 : 1;
526 unsigned int mpu_20 : 1;
527 unsigned int mpu_21 : 1;
528 unsigned int mpu_22 : 1;
529 unsigned int mpu_23 : 1;
530 unsigned int mpu_24 : 1;
531 unsigned int mpu_25 : 1;
532 unsigned int mpu_26 : 1;
533 unsigned int mpu_27 : 1;
534 unsigned int mpu_28 : 1;
535 unsigned int mpu_29 : 1;
536 unsigned int mpu_30 : 1;
537 unsigned int mpu_31 : 1;
538 unsigned int spu0_8 : 1;
539 unsigned int spu0_9 : 1;
540 unsigned int spu0_10 : 1;
541 unsigned int spu0_11 : 1;
542 unsigned int spu0_12 : 1;
543 unsigned int spu0_13 : 1;
544 unsigned int spu0_14 : 1;
545 unsigned int spu0_15 : 1;
546 unsigned int spu1_0 : 1;
547 unsigned int spu1_1 : 1;
548 unsigned int spu1_2 : 1;
549 unsigned int spu1_3 : 1;
550 unsigned int spu1_4 : 1;
551 unsigned int spu1_5 : 1;
552 unsigned int spu1_6 : 1;
553 unsigned int spu1_7 : 1;
554} reg_iop_sw_cpu_r_masked_intr1;
555#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112
556
557/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
558typedef struct {
559 unsigned int mpu_0 : 1;
560 unsigned int mpu_1 : 1;
561 unsigned int mpu_2 : 1;
562 unsigned int mpu_3 : 1;
563 unsigned int mpu_4 : 1;
564 unsigned int mpu_5 : 1;
565 unsigned int mpu_6 : 1;
566 unsigned int mpu_7 : 1;
567 unsigned int spu0_0 : 1;
568 unsigned int spu0_1 : 1;
569 unsigned int spu0_2 : 1;
570 unsigned int spu0_3 : 1;
571 unsigned int spu0_4 : 1;
572 unsigned int spu0_5 : 1;
573 unsigned int spu0_6 : 1;
574 unsigned int spu0_7 : 1;
575 unsigned int dmc_in0 : 1;
576 unsigned int dmc_out0 : 1;
577 unsigned int fifo_in0 : 1;
578 unsigned int fifo_out0 : 1;
579 unsigned int fifo_in0_extra : 1;
580 unsigned int fifo_out0_extra : 1;
581 unsigned int trigger_grp0 : 1;
582 unsigned int trigger_grp1 : 1;
583 unsigned int trigger_grp2 : 1;
584 unsigned int trigger_grp3 : 1;
585 unsigned int trigger_grp4 : 1;
586 unsigned int trigger_grp5 : 1;
587 unsigned int trigger_grp6 : 1;
588 unsigned int trigger_grp7 : 1;
589 unsigned int timer_grp0 : 1;
590 unsigned int timer_grp1 : 1;
591} reg_iop_sw_cpu_rw_intr2_mask;
592#define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116
593#define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116
594
595/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
596typedef struct {
597 unsigned int mpu_0 : 1;
598 unsigned int mpu_1 : 1;
599 unsigned int mpu_2 : 1;
600 unsigned int mpu_3 : 1;
601 unsigned int mpu_4 : 1;
602 unsigned int mpu_5 : 1;
603 unsigned int mpu_6 : 1;
604 unsigned int mpu_7 : 1;
605 unsigned int spu0_0 : 1;
606 unsigned int spu0_1 : 1;
607 unsigned int spu0_2 : 1;
608 unsigned int spu0_3 : 1;
609 unsigned int spu0_4 : 1;
610 unsigned int spu0_5 : 1;
611 unsigned int spu0_6 : 1;
612 unsigned int spu0_7 : 1;
613 unsigned int dummy1 : 16;
614} reg_iop_sw_cpu_rw_ack_intr2;
615#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120
616#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120
617
618/* Register r_intr2, scope iop_sw_cpu, type r */
619typedef struct {
620 unsigned int mpu_0 : 1;
621 unsigned int mpu_1 : 1;
622 unsigned int mpu_2 : 1;
623 unsigned int mpu_3 : 1;
624 unsigned int mpu_4 : 1;
625 unsigned int mpu_5 : 1;
626 unsigned int mpu_6 : 1;
627 unsigned int mpu_7 : 1;
628 unsigned int spu0_0 : 1;
629 unsigned int spu0_1 : 1;
630 unsigned int spu0_2 : 1;
631 unsigned int spu0_3 : 1;
632 unsigned int spu0_4 : 1;
633 unsigned int spu0_5 : 1;
634 unsigned int spu0_6 : 1;
635 unsigned int spu0_7 : 1;
636 unsigned int dmc_in0 : 1;
637 unsigned int dmc_out0 : 1;
638 unsigned int fifo_in0 : 1;
639 unsigned int fifo_out0 : 1;
640 unsigned int fifo_in0_extra : 1;
641 unsigned int fifo_out0_extra : 1;
642 unsigned int trigger_grp0 : 1;
643 unsigned int trigger_grp1 : 1;
644 unsigned int trigger_grp2 : 1;
645 unsigned int trigger_grp3 : 1;
646 unsigned int trigger_grp4 : 1;
647 unsigned int trigger_grp5 : 1;
648 unsigned int trigger_grp6 : 1;
649 unsigned int trigger_grp7 : 1;
650 unsigned int timer_grp0 : 1;
651 unsigned int timer_grp1 : 1;
652} reg_iop_sw_cpu_r_intr2;
653#define REG_RD_ADDR_iop_sw_cpu_r_intr2 124
654
655/* Register r_masked_intr2, scope iop_sw_cpu, type r */
656typedef struct {
657 unsigned int mpu_0 : 1;
658 unsigned int mpu_1 : 1;
659 unsigned int mpu_2 : 1;
660 unsigned int mpu_3 : 1;
661 unsigned int mpu_4 : 1;
662 unsigned int mpu_5 : 1;
663 unsigned int mpu_6 : 1;
664 unsigned int mpu_7 : 1;
665 unsigned int spu0_0 : 1;
666 unsigned int spu0_1 : 1;
667 unsigned int spu0_2 : 1;
668 unsigned int spu0_3 : 1;
669 unsigned int spu0_4 : 1;
670 unsigned int spu0_5 : 1;
671 unsigned int spu0_6 : 1;
672 unsigned int spu0_7 : 1;
673 unsigned int dmc_in0 : 1;
674 unsigned int dmc_out0 : 1;
675 unsigned int fifo_in0 : 1;
676 unsigned int fifo_out0 : 1;
677 unsigned int fifo_in0_extra : 1;
678 unsigned int fifo_out0_extra : 1;
679 unsigned int trigger_grp0 : 1;
680 unsigned int trigger_grp1 : 1;
681 unsigned int trigger_grp2 : 1;
682 unsigned int trigger_grp3 : 1;
683 unsigned int trigger_grp4 : 1;
684 unsigned int trigger_grp5 : 1;
685 unsigned int trigger_grp6 : 1;
686 unsigned int trigger_grp7 : 1;
687 unsigned int timer_grp0 : 1;
688 unsigned int timer_grp1 : 1;
689} reg_iop_sw_cpu_r_masked_intr2;
690#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128
691
692/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */
693typedef struct {
694 unsigned int mpu_16 : 1;
695 unsigned int mpu_17 : 1;
696 unsigned int mpu_18 : 1;
697 unsigned int mpu_19 : 1;
698 unsigned int mpu_20 : 1;
699 unsigned int mpu_21 : 1;
700 unsigned int mpu_22 : 1;
701 unsigned int mpu_23 : 1;
702 unsigned int spu1_0 : 1;
703 unsigned int spu1_1 : 1;
704 unsigned int spu1_2 : 1;
705 unsigned int spu1_3 : 1;
706 unsigned int spu1_4 : 1;
707 unsigned int spu1_5 : 1;
708 unsigned int spu1_6 : 1;
709 unsigned int spu1_7 : 1;
710 unsigned int dmc_in1 : 1;
711 unsigned int dmc_out1 : 1;
712 unsigned int fifo_in1 : 1;
713 unsigned int fifo_out1 : 1;
714 unsigned int fifo_in1_extra : 1;
715 unsigned int fifo_out1_extra : 1;
716 unsigned int trigger_grp0 : 1;
717 unsigned int trigger_grp1 : 1;
718 unsigned int trigger_grp2 : 1;
719 unsigned int trigger_grp3 : 1;
720 unsigned int trigger_grp4 : 1;
721 unsigned int trigger_grp5 : 1;
722 unsigned int trigger_grp6 : 1;
723 unsigned int trigger_grp7 : 1;
724 unsigned int timer_grp2 : 1;
725 unsigned int timer_grp3 : 1;
726} reg_iop_sw_cpu_rw_intr3_mask;
727#define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132
728#define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132
729
730/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */
731typedef struct {
732 unsigned int mpu_16 : 1;
733 unsigned int mpu_17 : 1;
734 unsigned int mpu_18 : 1;
735 unsigned int mpu_19 : 1;
736 unsigned int mpu_20 : 1;
737 unsigned int mpu_21 : 1;
738 unsigned int mpu_22 : 1;
739 unsigned int mpu_23 : 1;
740 unsigned int spu1_0 : 1;
741 unsigned int spu1_1 : 1;
742 unsigned int spu1_2 : 1;
743 unsigned int spu1_3 : 1;
744 unsigned int spu1_4 : 1;
745 unsigned int spu1_5 : 1;
746 unsigned int spu1_6 : 1;
747 unsigned int spu1_7 : 1;
748 unsigned int dummy1 : 16;
749} reg_iop_sw_cpu_rw_ack_intr3;
750#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136
751#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136
752
753/* Register r_intr3, scope iop_sw_cpu, type r */
754typedef struct {
755 unsigned int mpu_16 : 1;
756 unsigned int mpu_17 : 1;
757 unsigned int mpu_18 : 1;
758 unsigned int mpu_19 : 1;
759 unsigned int mpu_20 : 1;
760 unsigned int mpu_21 : 1;
761 unsigned int mpu_22 : 1;
762 unsigned int mpu_23 : 1;
763 unsigned int spu1_0 : 1;
764 unsigned int spu1_1 : 1;
765 unsigned int spu1_2 : 1;
766 unsigned int spu1_3 : 1;
767 unsigned int spu1_4 : 1;
768 unsigned int spu1_5 : 1;
769 unsigned int spu1_6 : 1;
770 unsigned int spu1_7 : 1;
771 unsigned int dmc_in1 : 1;
772 unsigned int dmc_out1 : 1;
773 unsigned int fifo_in1 : 1;
774 unsigned int fifo_out1 : 1;
775 unsigned int fifo_in1_extra : 1;
776 unsigned int fifo_out1_extra : 1;
777 unsigned int trigger_grp0 : 1;
778 unsigned int trigger_grp1 : 1;
779 unsigned int trigger_grp2 : 1;
780 unsigned int trigger_grp3 : 1;
781 unsigned int trigger_grp4 : 1;
782 unsigned int trigger_grp5 : 1;
783 unsigned int trigger_grp6 : 1;
784 unsigned int trigger_grp7 : 1;
785 unsigned int timer_grp2 : 1;
786 unsigned int timer_grp3 : 1;
787} reg_iop_sw_cpu_r_intr3;
788#define REG_RD_ADDR_iop_sw_cpu_r_intr3 140
789
790/* Register r_masked_intr3, scope iop_sw_cpu, type r */
791typedef struct {
792 unsigned int mpu_16 : 1;
793 unsigned int mpu_17 : 1;
794 unsigned int mpu_18 : 1;
795 unsigned int mpu_19 : 1;
796 unsigned int mpu_20 : 1;
797 unsigned int mpu_21 : 1;
798 unsigned int mpu_22 : 1;
799 unsigned int mpu_23 : 1;
800 unsigned int spu1_0 : 1;
801 unsigned int spu1_1 : 1;
802 unsigned int spu1_2 : 1;
803 unsigned int spu1_3 : 1;
804 unsigned int spu1_4 : 1;
805 unsigned int spu1_5 : 1;
806 unsigned int spu1_6 : 1;
807 unsigned int spu1_7 : 1;
808 unsigned int dmc_in1 : 1;
809 unsigned int dmc_out1 : 1;
810 unsigned int fifo_in1 : 1;
811 unsigned int fifo_out1 : 1;
812 unsigned int fifo_in1_extra : 1;
813 unsigned int fifo_out1_extra : 1;
814 unsigned int trigger_grp0 : 1;
815 unsigned int trigger_grp1 : 1;
816 unsigned int trigger_grp2 : 1;
817 unsigned int trigger_grp3 : 1;
818 unsigned int trigger_grp4 : 1;
819 unsigned int trigger_grp5 : 1;
820 unsigned int trigger_grp6 : 1;
821 unsigned int trigger_grp7 : 1;
822 unsigned int timer_grp2 : 1;
823 unsigned int timer_grp3 : 1;
824} reg_iop_sw_cpu_r_masked_intr3;
825#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144
826
827
828/* Constants */
829enum {
830 regk_iop_sw_cpu_copy = 0x00000000,
831 regk_iop_sw_cpu_no = 0x00000000,
832 regk_iop_sw_cpu_rd = 0x00000002,
833 regk_iop_sw_cpu_reg_copy = 0x00000001,
834 regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000,
835 regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000,
836 regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000,
837 regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000,
838 regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000,
839 regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000,
840 regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000,
841 regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000,
842 regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000,
843 regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000,
844 regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000,
845 regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000,
846 regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000,
847 regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000,
848 regk_iop_sw_cpu_rw_intr2_mask_default = 0x00000000,
849 regk_iop_sw_cpu_rw_intr3_mask_default = 0x00000000,
850 regk_iop_sw_cpu_wr = 0x00000003,
851 regk_iop_sw_cpu_yes = 0x00000001
852};
853#endif /* __iop_sw_cpu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h
new file mode 100644
index 000000000000..da718f2a8cad
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h
@@ -0,0 +1,893 @@
1#ifndef __iop_sw_mpu_defs_h
2#define __iop_sw_mpu_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:10:19 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
11 * id: $Id: iop_sw_mpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_sw_mpu */
86
87/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
88typedef struct {
89 unsigned int cfg : 2;
90 unsigned int dummy1 : 30;
91} reg_iop_sw_mpu_rw_sw_cfg_owner;
92#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
93#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
94
95/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
96typedef struct {
97 unsigned int keep_owner : 1;
98 unsigned int cmd : 2;
99 unsigned int size : 3;
100 unsigned int wr_spu0_mem : 1;
101 unsigned int wr_spu1_mem : 1;
102 unsigned int dummy1 : 24;
103} reg_iop_sw_mpu_rw_mc_ctrl;
104#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4
105#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4
106
107/* Register rw_mc_data, scope iop_sw_mpu, type rw */
108typedef struct {
109 unsigned int val : 32;
110} reg_iop_sw_mpu_rw_mc_data;
111#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8
112#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8
113
114/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
115typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
116#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12
117#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12
118
119/* Register rs_mc_data, scope iop_sw_mpu, type rs */
120typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
121#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16
122
123/* Register r_mc_data, scope iop_sw_mpu, type r */
124typedef unsigned int reg_iop_sw_mpu_r_mc_data;
125#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20
126
127/* Register r_mc_stat, scope iop_sw_mpu, type r */
128typedef struct {
129 unsigned int busy_cpu : 1;
130 unsigned int busy_mpu : 1;
131 unsigned int busy_spu0 : 1;
132 unsigned int busy_spu1 : 1;
133 unsigned int owned_by_cpu : 1;
134 unsigned int owned_by_mpu : 1;
135 unsigned int owned_by_spu0 : 1;
136 unsigned int owned_by_spu1 : 1;
137 unsigned int dummy1 : 24;
138} reg_iop_sw_mpu_r_mc_stat;
139#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24
140
141/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
142typedef struct {
143 unsigned int byte0 : 8;
144 unsigned int byte1 : 8;
145 unsigned int byte2 : 8;
146 unsigned int byte3 : 8;
147} reg_iop_sw_mpu_rw_bus0_clr_mask;
148#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
149#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
150
151/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
152typedef struct {
153 unsigned int byte0 : 8;
154 unsigned int byte1 : 8;
155 unsigned int byte2 : 8;
156 unsigned int byte3 : 8;
157} reg_iop_sw_mpu_rw_bus0_set_mask;
158#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
159#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
160
161/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
162typedef struct {
163 unsigned int byte0 : 1;
164 unsigned int byte1 : 1;
165 unsigned int byte2 : 1;
166 unsigned int byte3 : 1;
167 unsigned int dummy1 : 28;
168} reg_iop_sw_mpu_rw_bus0_oe_clr_mask;
169#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
170#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
171
172/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
173typedef struct {
174 unsigned int byte0 : 1;
175 unsigned int byte1 : 1;
176 unsigned int byte2 : 1;
177 unsigned int byte3 : 1;
178 unsigned int dummy1 : 28;
179} reg_iop_sw_mpu_rw_bus0_oe_set_mask;
180#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
181#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
182
183/* Register r_bus0_in, scope iop_sw_mpu, type r */
184typedef unsigned int reg_iop_sw_mpu_r_bus0_in;
185#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44
186
187/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
188typedef struct {
189 unsigned int byte0 : 8;
190 unsigned int byte1 : 8;
191 unsigned int byte2 : 8;
192 unsigned int byte3 : 8;
193} reg_iop_sw_mpu_rw_bus1_clr_mask;
194#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
195#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
196
197/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
198typedef struct {
199 unsigned int byte0 : 8;
200 unsigned int byte1 : 8;
201 unsigned int byte2 : 8;
202 unsigned int byte3 : 8;
203} reg_iop_sw_mpu_rw_bus1_set_mask;
204#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
205#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
206
207/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
208typedef struct {
209 unsigned int byte0 : 1;
210 unsigned int byte1 : 1;
211 unsigned int byte2 : 1;
212 unsigned int byte3 : 1;
213 unsigned int dummy1 : 28;
214} reg_iop_sw_mpu_rw_bus1_oe_clr_mask;
215#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
216#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
217
218/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
219typedef struct {
220 unsigned int byte0 : 1;
221 unsigned int byte1 : 1;
222 unsigned int byte2 : 1;
223 unsigned int byte3 : 1;
224 unsigned int dummy1 : 28;
225} reg_iop_sw_mpu_rw_bus1_oe_set_mask;
226#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
227#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
228
229/* Register r_bus1_in, scope iop_sw_mpu, type r */
230typedef unsigned int reg_iop_sw_mpu_r_bus1_in;
231#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64
232
233/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
234typedef struct {
235 unsigned int val : 32;
236} reg_iop_sw_mpu_rw_gio_clr_mask;
237#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
238#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
239
240/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
241typedef struct {
242 unsigned int val : 32;
243} reg_iop_sw_mpu_rw_gio_set_mask;
244#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72
245#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72
246
247/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
248typedef struct {
249 unsigned int val : 32;
250} reg_iop_sw_mpu_rw_gio_oe_clr_mask;
251#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
252#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
253
254/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
255typedef struct {
256 unsigned int val : 32;
257} reg_iop_sw_mpu_rw_gio_oe_set_mask;
258#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
259#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
260
261/* Register r_gio_in, scope iop_sw_mpu, type r */
262typedef unsigned int reg_iop_sw_mpu_r_gio_in;
263#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84
264
265/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
266typedef struct {
267 unsigned int intr0 : 1;
268 unsigned int intr1 : 1;
269 unsigned int intr2 : 1;
270 unsigned int intr3 : 1;
271 unsigned int intr4 : 1;
272 unsigned int intr5 : 1;
273 unsigned int intr6 : 1;
274 unsigned int intr7 : 1;
275 unsigned int intr8 : 1;
276 unsigned int intr9 : 1;
277 unsigned int intr10 : 1;
278 unsigned int intr11 : 1;
279 unsigned int intr12 : 1;
280 unsigned int intr13 : 1;
281 unsigned int intr14 : 1;
282 unsigned int intr15 : 1;
283 unsigned int intr16 : 1;
284 unsigned int intr17 : 1;
285 unsigned int intr18 : 1;
286 unsigned int intr19 : 1;
287 unsigned int intr20 : 1;
288 unsigned int intr21 : 1;
289 unsigned int intr22 : 1;
290 unsigned int intr23 : 1;
291 unsigned int intr24 : 1;
292 unsigned int intr25 : 1;
293 unsigned int intr26 : 1;
294 unsigned int intr27 : 1;
295 unsigned int intr28 : 1;
296 unsigned int intr29 : 1;
297 unsigned int intr30 : 1;
298 unsigned int intr31 : 1;
299} reg_iop_sw_mpu_rw_cpu_intr;
300#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88
301#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88
302
303/* Register r_cpu_intr, scope iop_sw_mpu, type r */
304typedef struct {
305 unsigned int intr0 : 1;
306 unsigned int intr1 : 1;
307 unsigned int intr2 : 1;
308 unsigned int intr3 : 1;
309 unsigned int intr4 : 1;
310 unsigned int intr5 : 1;
311 unsigned int intr6 : 1;
312 unsigned int intr7 : 1;
313 unsigned int intr8 : 1;
314 unsigned int intr9 : 1;
315 unsigned int intr10 : 1;
316 unsigned int intr11 : 1;
317 unsigned int intr12 : 1;
318 unsigned int intr13 : 1;
319 unsigned int intr14 : 1;
320 unsigned int intr15 : 1;
321 unsigned int intr16 : 1;
322 unsigned int intr17 : 1;
323 unsigned int intr18 : 1;
324 unsigned int intr19 : 1;
325 unsigned int intr20 : 1;
326 unsigned int intr21 : 1;
327 unsigned int intr22 : 1;
328 unsigned int intr23 : 1;
329 unsigned int intr24 : 1;
330 unsigned int intr25 : 1;
331 unsigned int intr26 : 1;
332 unsigned int intr27 : 1;
333 unsigned int intr28 : 1;
334 unsigned int intr29 : 1;
335 unsigned int intr30 : 1;
336 unsigned int intr31 : 1;
337} reg_iop_sw_mpu_r_cpu_intr;
338#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92
339
340/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
341typedef struct {
342 unsigned int spu0_intr0 : 1;
343 unsigned int spu1_intr0 : 1;
344 unsigned int trigger_grp0 : 1;
345 unsigned int trigger_grp4 : 1;
346 unsigned int timer_grp0 : 1;
347 unsigned int fifo_out0 : 1;
348 unsigned int fifo_out0_extra : 1;
349 unsigned int dmc_out0 : 1;
350 unsigned int spu0_intr1 : 1;
351 unsigned int spu1_intr1 : 1;
352 unsigned int trigger_grp1 : 1;
353 unsigned int trigger_grp5 : 1;
354 unsigned int timer_grp1 : 1;
355 unsigned int fifo_in0 : 1;
356 unsigned int fifo_in0_extra : 1;
357 unsigned int dmc_in0 : 1;
358 unsigned int spu0_intr2 : 1;
359 unsigned int spu1_intr2 : 1;
360 unsigned int trigger_grp2 : 1;
361 unsigned int trigger_grp6 : 1;
362 unsigned int timer_grp2 : 1;
363 unsigned int fifo_out1 : 1;
364 unsigned int fifo_out1_extra : 1;
365 unsigned int dmc_out1 : 1;
366 unsigned int spu0_intr3 : 1;
367 unsigned int spu1_intr3 : 1;
368 unsigned int trigger_grp3 : 1;
369 unsigned int trigger_grp7 : 1;
370 unsigned int timer_grp3 : 1;
371 unsigned int fifo_in1 : 1;
372 unsigned int fifo_in1_extra : 1;
373 unsigned int dmc_in1 : 1;
374} reg_iop_sw_mpu_rw_intr_grp0_mask;
375#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
376#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
377
378/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
379typedef struct {
380 unsigned int spu0_intr0 : 1;
381 unsigned int spu1_intr0 : 1;
382 unsigned int dummy1 : 6;
383 unsigned int spu0_intr1 : 1;
384 unsigned int spu1_intr1 : 1;
385 unsigned int dummy2 : 6;
386 unsigned int spu0_intr2 : 1;
387 unsigned int spu1_intr2 : 1;
388 unsigned int dummy3 : 6;
389 unsigned int spu0_intr3 : 1;
390 unsigned int spu1_intr3 : 1;
391 unsigned int dummy4 : 6;
392} reg_iop_sw_mpu_rw_ack_intr_grp0;
393#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
394#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
395
396/* Register r_intr_grp0, scope iop_sw_mpu, type r */
397typedef struct {
398 unsigned int spu0_intr0 : 1;
399 unsigned int spu1_intr0 : 1;
400 unsigned int trigger_grp0 : 1;
401 unsigned int trigger_grp4 : 1;
402 unsigned int timer_grp0 : 1;
403 unsigned int fifo_out0 : 1;
404 unsigned int fifo_out0_extra : 1;
405 unsigned int dmc_out0 : 1;
406 unsigned int spu0_intr1 : 1;
407 unsigned int spu1_intr1 : 1;
408 unsigned int trigger_grp1 : 1;
409 unsigned int trigger_grp5 : 1;
410 unsigned int timer_grp1 : 1;
411 unsigned int fifo_in0 : 1;
412 unsigned int fifo_in0_extra : 1;
413 unsigned int dmc_in0 : 1;
414 unsigned int spu0_intr2 : 1;
415 unsigned int spu1_intr2 : 1;
416 unsigned int trigger_grp2 : 1;
417 unsigned int trigger_grp6 : 1;
418 unsigned int timer_grp2 : 1;
419 unsigned int fifo_out1 : 1;
420 unsigned int fifo_out1_extra : 1;
421 unsigned int dmc_out1 : 1;
422 unsigned int spu0_intr3 : 1;
423 unsigned int spu1_intr3 : 1;
424 unsigned int trigger_grp3 : 1;
425 unsigned int trigger_grp7 : 1;
426 unsigned int timer_grp3 : 1;
427 unsigned int fifo_in1 : 1;
428 unsigned int fifo_in1_extra : 1;
429 unsigned int dmc_in1 : 1;
430} reg_iop_sw_mpu_r_intr_grp0;
431#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104
432
433/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
434typedef struct {
435 unsigned int spu0_intr0 : 1;
436 unsigned int spu1_intr0 : 1;
437 unsigned int trigger_grp0 : 1;
438 unsigned int trigger_grp4 : 1;
439 unsigned int timer_grp0 : 1;
440 unsigned int fifo_out0 : 1;
441 unsigned int fifo_out0_extra : 1;
442 unsigned int dmc_out0 : 1;
443 unsigned int spu0_intr1 : 1;
444 unsigned int spu1_intr1 : 1;
445 unsigned int trigger_grp1 : 1;
446 unsigned int trigger_grp5 : 1;
447 unsigned int timer_grp1 : 1;
448 unsigned int fifo_in0 : 1;
449 unsigned int fifo_in0_extra : 1;
450 unsigned int dmc_in0 : 1;
451 unsigned int spu0_intr2 : 1;
452 unsigned int spu1_intr2 : 1;
453 unsigned int trigger_grp2 : 1;
454 unsigned int trigger_grp6 : 1;
455 unsigned int timer_grp2 : 1;
456 unsigned int fifo_out1 : 1;
457 unsigned int fifo_out1_extra : 1;
458 unsigned int dmc_out1 : 1;
459 unsigned int spu0_intr3 : 1;
460 unsigned int spu1_intr3 : 1;
461 unsigned int trigger_grp3 : 1;
462 unsigned int trigger_grp7 : 1;
463 unsigned int timer_grp3 : 1;
464 unsigned int fifo_in1 : 1;
465 unsigned int fifo_in1_extra : 1;
466 unsigned int dmc_in1 : 1;
467} reg_iop_sw_mpu_r_masked_intr_grp0;
468#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108
469
470/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
471typedef struct {
472 unsigned int spu0_intr4 : 1;
473 unsigned int spu1_intr4 : 1;
474 unsigned int trigger_grp0 : 1;
475 unsigned int trigger_grp5 : 1;
476 unsigned int timer_grp0 : 1;
477 unsigned int fifo_in0 : 1;
478 unsigned int fifo_in0_extra : 1;
479 unsigned int dmc_out0 : 1;
480 unsigned int spu0_intr5 : 1;
481 unsigned int spu1_intr5 : 1;
482 unsigned int trigger_grp1 : 1;
483 unsigned int trigger_grp6 : 1;
484 unsigned int timer_grp1 : 1;
485 unsigned int fifo_out1 : 1;
486 unsigned int fifo_out0_extra : 1;
487 unsigned int dmc_in0 : 1;
488 unsigned int spu0_intr6 : 1;
489 unsigned int spu1_intr6 : 1;
490 unsigned int trigger_grp2 : 1;
491 unsigned int trigger_grp7 : 1;
492 unsigned int timer_grp2 : 1;
493 unsigned int fifo_in1 : 1;
494 unsigned int fifo_in1_extra : 1;
495 unsigned int dmc_out1 : 1;
496 unsigned int spu0_intr7 : 1;
497 unsigned int spu1_intr7 : 1;
498 unsigned int trigger_grp3 : 1;
499 unsigned int trigger_grp4 : 1;
500 unsigned int timer_grp3 : 1;
501 unsigned int fifo_out0 : 1;
502 unsigned int fifo_out1_extra : 1;
503 unsigned int dmc_in1 : 1;
504} reg_iop_sw_mpu_rw_intr_grp1_mask;
505#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
506#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
507
508/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
509typedef struct {
510 unsigned int spu0_intr4 : 1;
511 unsigned int spu1_intr4 : 1;
512 unsigned int dummy1 : 6;
513 unsigned int spu0_intr5 : 1;
514 unsigned int spu1_intr5 : 1;
515 unsigned int dummy2 : 6;
516 unsigned int spu0_intr6 : 1;
517 unsigned int spu1_intr6 : 1;
518 unsigned int dummy3 : 6;
519 unsigned int spu0_intr7 : 1;
520 unsigned int spu1_intr7 : 1;
521 unsigned int dummy4 : 6;
522} reg_iop_sw_mpu_rw_ack_intr_grp1;
523#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
524#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
525
526/* Register r_intr_grp1, scope iop_sw_mpu, type r */
527typedef struct {
528 unsigned int spu0_intr4 : 1;
529 unsigned int spu1_intr4 : 1;
530 unsigned int trigger_grp0 : 1;
531 unsigned int trigger_grp5 : 1;
532 unsigned int timer_grp0 : 1;
533 unsigned int fifo_in0 : 1;
534 unsigned int fifo_in0_extra : 1;
535 unsigned int dmc_out0 : 1;
536 unsigned int spu0_intr5 : 1;
537 unsigned int spu1_intr5 : 1;
538 unsigned int trigger_grp1 : 1;
539 unsigned int trigger_grp6 : 1;
540 unsigned int timer_grp1 : 1;
541 unsigned int fifo_out1 : 1;
542 unsigned int fifo_out0_extra : 1;
543 unsigned int dmc_in0 : 1;
544 unsigned int spu0_intr6 : 1;
545 unsigned int spu1_intr6 : 1;
546 unsigned int trigger_grp2 : 1;
547 unsigned int trigger_grp7 : 1;
548 unsigned int timer_grp2 : 1;
549 unsigned int fifo_in1 : 1;
550 unsigned int fifo_in1_extra : 1;
551 unsigned int dmc_out1 : 1;
552 unsigned int spu0_intr7 : 1;
553 unsigned int spu1_intr7 : 1;
554 unsigned int trigger_grp3 : 1;
555 unsigned int trigger_grp4 : 1;
556 unsigned int timer_grp3 : 1;
557 unsigned int fifo_out0 : 1;
558 unsigned int fifo_out1_extra : 1;
559 unsigned int dmc_in1 : 1;
560} reg_iop_sw_mpu_r_intr_grp1;
561#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120
562
563/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
564typedef struct {
565 unsigned int spu0_intr4 : 1;
566 unsigned int spu1_intr4 : 1;
567 unsigned int trigger_grp0 : 1;
568 unsigned int trigger_grp5 : 1;
569 unsigned int timer_grp0 : 1;
570 unsigned int fifo_in0 : 1;
571 unsigned int fifo_in0_extra : 1;
572 unsigned int dmc_out0 : 1;
573 unsigned int spu0_intr5 : 1;
574 unsigned int spu1_intr5 : 1;
575 unsigned int trigger_grp1 : 1;
576 unsigned int trigger_grp6 : 1;
577 unsigned int timer_grp1 : 1;
578 unsigned int fifo_out1 : 1;
579 unsigned int fifo_out0_extra : 1;
580 unsigned int dmc_in0 : 1;
581 unsigned int spu0_intr6 : 1;
582 unsigned int spu1_intr6 : 1;
583 unsigned int trigger_grp2 : 1;
584 unsigned int trigger_grp7 : 1;
585 unsigned int timer_grp2 : 1;
586 unsigned int fifo_in1 : 1;
587 unsigned int fifo_in1_extra : 1;
588 unsigned int dmc_out1 : 1;
589 unsigned int spu0_intr7 : 1;
590 unsigned int spu1_intr7 : 1;
591 unsigned int trigger_grp3 : 1;
592 unsigned int trigger_grp4 : 1;
593 unsigned int timer_grp3 : 1;
594 unsigned int fifo_out0 : 1;
595 unsigned int fifo_out1_extra : 1;
596 unsigned int dmc_in1 : 1;
597} reg_iop_sw_mpu_r_masked_intr_grp1;
598#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124
599
600/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
601typedef struct {
602 unsigned int spu0_intr8 : 1;
603 unsigned int spu1_intr8 : 1;
604 unsigned int trigger_grp0 : 1;
605 unsigned int trigger_grp6 : 1;
606 unsigned int timer_grp0 : 1;
607 unsigned int fifo_out1 : 1;
608 unsigned int fifo_out1_extra : 1;
609 unsigned int dmc_out0 : 1;
610 unsigned int spu0_intr9 : 1;
611 unsigned int spu1_intr9 : 1;
612 unsigned int trigger_grp1 : 1;
613 unsigned int trigger_grp7 : 1;
614 unsigned int timer_grp1 : 1;
615 unsigned int fifo_in1 : 1;
616 unsigned int fifo_in1_extra : 1;
617 unsigned int dmc_in0 : 1;
618 unsigned int spu0_intr10 : 1;
619 unsigned int spu1_intr10 : 1;
620 unsigned int trigger_grp2 : 1;
621 unsigned int trigger_grp4 : 1;
622 unsigned int timer_grp2 : 1;
623 unsigned int fifo_out0 : 1;
624 unsigned int fifo_out0_extra : 1;
625 unsigned int dmc_out1 : 1;
626 unsigned int spu0_intr11 : 1;
627 unsigned int spu1_intr11 : 1;
628 unsigned int trigger_grp3 : 1;
629 unsigned int trigger_grp5 : 1;
630 unsigned int timer_grp3 : 1;
631 unsigned int fifo_in0 : 1;
632 unsigned int fifo_in0_extra : 1;
633 unsigned int dmc_in1 : 1;
634} reg_iop_sw_mpu_rw_intr_grp2_mask;
635#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
636#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
637
638/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
639typedef struct {
640 unsigned int spu0_intr8 : 1;
641 unsigned int spu1_intr8 : 1;
642 unsigned int dummy1 : 6;
643 unsigned int spu0_intr9 : 1;
644 unsigned int spu1_intr9 : 1;
645 unsigned int dummy2 : 6;
646 unsigned int spu0_intr10 : 1;
647 unsigned int spu1_intr10 : 1;
648 unsigned int dummy3 : 6;
649 unsigned int spu0_intr11 : 1;
650 unsigned int spu1_intr11 : 1;
651 unsigned int dummy4 : 6;
652} reg_iop_sw_mpu_rw_ack_intr_grp2;
653#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
654#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
655
656/* Register r_intr_grp2, scope iop_sw_mpu, type r */
657typedef struct {
658 unsigned int spu0_intr8 : 1;
659 unsigned int spu1_intr8 : 1;
660 unsigned int trigger_grp0 : 1;
661 unsigned int trigger_grp6 : 1;
662 unsigned int timer_grp0 : 1;
663 unsigned int fifo_out1 : 1;
664 unsigned int fifo_out1_extra : 1;
665 unsigned int dmc_out0 : 1;
666 unsigned int spu0_intr9 : 1;
667 unsigned int spu1_intr9 : 1;
668 unsigned int trigger_grp1 : 1;
669 unsigned int trigger_grp7 : 1;
670 unsigned int timer_grp1 : 1;
671 unsigned int fifo_in1 : 1;
672 unsigned int fifo_in1_extra : 1;
673 unsigned int dmc_in0 : 1;
674 unsigned int spu0_intr10 : 1;
675 unsigned int spu1_intr10 : 1;
676 unsigned int trigger_grp2 : 1;
677 unsigned int trigger_grp4 : 1;
678 unsigned int timer_grp2 : 1;
679 unsigned int fifo_out0 : 1;
680 unsigned int fifo_out0_extra : 1;
681 unsigned int dmc_out1 : 1;
682 unsigned int spu0_intr11 : 1;
683 unsigned int spu1_intr11 : 1;
684 unsigned int trigger_grp3 : 1;
685 unsigned int trigger_grp5 : 1;
686 unsigned int timer_grp3 : 1;
687 unsigned int fifo_in0 : 1;
688 unsigned int fifo_in0_extra : 1;
689 unsigned int dmc_in1 : 1;
690} reg_iop_sw_mpu_r_intr_grp2;
691#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136
692
693/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
694typedef struct {
695 unsigned int spu0_intr8 : 1;
696 unsigned int spu1_intr8 : 1;
697 unsigned int trigger_grp0 : 1;
698 unsigned int trigger_grp6 : 1;
699 unsigned int timer_grp0 : 1;
700 unsigned int fifo_out1 : 1;
701 unsigned int fifo_out1_extra : 1;
702 unsigned int dmc_out0 : 1;
703 unsigned int spu0_intr9 : 1;
704 unsigned int spu1_intr9 : 1;
705 unsigned int trigger_grp1 : 1;
706 unsigned int trigger_grp7 : 1;
707 unsigned int timer_grp1 : 1;
708 unsigned int fifo_in1 : 1;
709 unsigned int fifo_in1_extra : 1;
710 unsigned int dmc_in0 : 1;
711 unsigned int spu0_intr10 : 1;
712 unsigned int spu1_intr10 : 1;
713 unsigned int trigger_grp2 : 1;
714 unsigned int trigger_grp4 : 1;
715 unsigned int timer_grp2 : 1;
716 unsigned int fifo_out0 : 1;
717 unsigned int fifo_out0_extra : 1;
718 unsigned int dmc_out1 : 1;
719 unsigned int spu0_intr11 : 1;
720 unsigned int spu1_intr11 : 1;
721 unsigned int trigger_grp3 : 1;
722 unsigned int trigger_grp5 : 1;
723 unsigned int timer_grp3 : 1;
724 unsigned int fifo_in0 : 1;
725 unsigned int fifo_in0_extra : 1;
726 unsigned int dmc_in1 : 1;
727} reg_iop_sw_mpu_r_masked_intr_grp2;
728#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140
729
730/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
731typedef struct {
732 unsigned int spu0_intr12 : 1;
733 unsigned int spu1_intr12 : 1;
734 unsigned int trigger_grp0 : 1;
735 unsigned int trigger_grp7 : 1;
736 unsigned int timer_grp0 : 1;
737 unsigned int fifo_in1 : 1;
738 unsigned int fifo_in1_extra : 1;
739 unsigned int dmc_out0 : 1;
740 unsigned int spu0_intr13 : 1;
741 unsigned int spu1_intr13 : 1;
742 unsigned int trigger_grp1 : 1;
743 unsigned int trigger_grp4 : 1;
744 unsigned int timer_grp1 : 1;
745 unsigned int fifo_out0 : 1;
746 unsigned int fifo_out0_extra : 1;
747 unsigned int dmc_in0 : 1;
748 unsigned int spu0_intr14 : 1;
749 unsigned int spu1_intr14 : 1;
750 unsigned int trigger_grp2 : 1;
751 unsigned int trigger_grp5 : 1;
752 unsigned int timer_grp2 : 1;
753 unsigned int fifo_in0 : 1;
754 unsigned int fifo_in0_extra : 1;
755 unsigned int dmc_out1 : 1;
756 unsigned int spu0_intr15 : 1;
757 unsigned int spu1_intr15 : 1;
758 unsigned int trigger_grp3 : 1;
759 unsigned int trigger_grp6 : 1;
760 unsigned int timer_grp3 : 1;
761 unsigned int fifo_out1 : 1;
762 unsigned int fifo_out1_extra : 1;
763 unsigned int dmc_in1 : 1;
764} reg_iop_sw_mpu_rw_intr_grp3_mask;
765#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
766#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
767
768/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
769typedef struct {
770 unsigned int spu0_intr12 : 1;
771 unsigned int spu1_intr12 : 1;
772 unsigned int dummy1 : 6;
773 unsigned int spu0_intr13 : 1;
774 unsigned int spu1_intr13 : 1;
775 unsigned int dummy2 : 6;
776 unsigned int spu0_intr14 : 1;
777 unsigned int spu1_intr14 : 1;
778 unsigned int dummy3 : 6;
779 unsigned int spu0_intr15 : 1;
780 unsigned int spu1_intr15 : 1;
781 unsigned int dummy4 : 6;
782} reg_iop_sw_mpu_rw_ack_intr_grp3;
783#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
784#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
785
786/* Register r_intr_grp3, scope iop_sw_mpu, type r */
787typedef struct {
788 unsigned int spu0_intr12 : 1;
789 unsigned int spu1_intr12 : 1;
790 unsigned int trigger_grp0 : 1;
791 unsigned int trigger_grp7 : 1;
792 unsigned int timer_grp0 : 1;
793 unsigned int fifo_in1 : 1;
794 unsigned int fifo_in1_extra : 1;
795 unsigned int dmc_out0 : 1;
796 unsigned int spu0_intr13 : 1;
797 unsigned int spu1_intr13 : 1;
798 unsigned int trigger_grp1 : 1;
799 unsigned int trigger_grp4 : 1;
800 unsigned int timer_grp1 : 1;
801 unsigned int fifo_out0 : 1;
802 unsigned int fifo_out0_extra : 1;
803 unsigned int dmc_in0 : 1;
804 unsigned int spu0_intr14 : 1;
805 unsigned int spu1_intr14 : 1;
806 unsigned int trigger_grp2 : 1;
807 unsigned int trigger_grp5 : 1;
808 unsigned int timer_grp2 : 1;
809 unsigned int fifo_in0 : 1;
810 unsigned int fifo_in0_extra : 1;
811 unsigned int dmc_out1 : 1;
812 unsigned int spu0_intr15 : 1;
813 unsigned int spu1_intr15 : 1;
814 unsigned int trigger_grp3 : 1;
815 unsigned int trigger_grp6 : 1;
816 unsigned int timer_grp3 : 1;
817 unsigned int fifo_out1 : 1;
818 unsigned int fifo_out1_extra : 1;
819 unsigned int dmc_in1 : 1;
820} reg_iop_sw_mpu_r_intr_grp3;
821#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152
822
823/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
824typedef struct {
825 unsigned int spu0_intr12 : 1;
826 unsigned int spu1_intr12 : 1;
827 unsigned int trigger_grp0 : 1;
828 unsigned int trigger_grp7 : 1;
829 unsigned int timer_grp0 : 1;
830 unsigned int fifo_in1 : 1;
831 unsigned int fifo_in1_extra : 1;
832 unsigned int dmc_out0 : 1;
833 unsigned int spu0_intr13 : 1;
834 unsigned int spu1_intr13 : 1;
835 unsigned int trigger_grp1 : 1;
836 unsigned int trigger_grp4 : 1;
837 unsigned int timer_grp1 : 1;
838 unsigned int fifo_out0 : 1;
839 unsigned int fifo_out0_extra : 1;
840 unsigned int dmc_in0 : 1;
841 unsigned int spu0_intr14 : 1;
842 unsigned int spu1_intr14 : 1;
843 unsigned int trigger_grp2 : 1;
844 unsigned int trigger_grp5 : 1;
845 unsigned int timer_grp2 : 1;
846 unsigned int fifo_in0 : 1;
847 unsigned int fifo_in0_extra : 1;
848 unsigned int dmc_out1 : 1;
849 unsigned int spu0_intr15 : 1;
850 unsigned int spu1_intr15 : 1;
851 unsigned int trigger_grp3 : 1;
852 unsigned int trigger_grp6 : 1;
853 unsigned int timer_grp3 : 1;
854 unsigned int fifo_out1 : 1;
855 unsigned int fifo_out1_extra : 1;
856 unsigned int dmc_in1 : 1;
857} reg_iop_sw_mpu_r_masked_intr_grp3;
858#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156
859
860
861/* Constants */
862enum {
863 regk_iop_sw_mpu_copy = 0x00000000,
864 regk_iop_sw_mpu_cpu = 0x00000000,
865 regk_iop_sw_mpu_mpu = 0x00000001,
866 regk_iop_sw_mpu_no = 0x00000000,
867 regk_iop_sw_mpu_nop = 0x00000000,
868 regk_iop_sw_mpu_rd = 0x00000002,
869 regk_iop_sw_mpu_reg_copy = 0x00000001,
870 regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000,
871 regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000,
872 regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000,
873 regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000,
874 regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000,
875 regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000,
876 regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000,
877 regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000,
878 regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000,
879 regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
880 regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
881 regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000,
882 regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
883 regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
884 regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
885 regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
886 regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000,
887 regk_iop_sw_mpu_set = 0x00000001,
888 regk_iop_sw_mpu_spu0 = 0x00000002,
889 regk_iop_sw_mpu_spu1 = 0x00000003,
890 regk_iop_sw_mpu_wr = 0x00000003,
891 regk_iop_sw_mpu_yes = 0x00000001
892};
893#endif /* __iop_sw_mpu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h
new file mode 100644
index 000000000000..b59dde4bd0d1
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h
@@ -0,0 +1,552 @@
1#ifndef __iop_sw_spu_defs_h
2#define __iop_sw_spu_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:10:19 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
11 * id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_sw_spu */
86
87/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
88typedef struct {
89 unsigned int keep_owner : 1;
90 unsigned int cmd : 2;
91 unsigned int size : 3;
92 unsigned int wr_spu0_mem : 1;
93 unsigned int wr_spu1_mem : 1;
94 unsigned int dummy1 : 24;
95} reg_iop_sw_spu_rw_mc_ctrl;
96#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0
97#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0
98
99/* Register rw_mc_data, scope iop_sw_spu, type rw */
100typedef struct {
101 unsigned int val : 32;
102} reg_iop_sw_spu_rw_mc_data;
103#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4
104#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4
105
106/* Register rw_mc_addr, scope iop_sw_spu, type rw */
107typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
108#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8
109#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8
110
111/* Register rs_mc_data, scope iop_sw_spu, type rs */
112typedef unsigned int reg_iop_sw_spu_rs_mc_data;
113#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12
114
115/* Register r_mc_data, scope iop_sw_spu, type r */
116typedef unsigned int reg_iop_sw_spu_r_mc_data;
117#define REG_RD_ADDR_iop_sw_spu_r_mc_data 16
118
119/* Register r_mc_stat, scope iop_sw_spu, type r */
120typedef struct {
121 unsigned int busy_cpu : 1;
122 unsigned int busy_mpu : 1;
123 unsigned int busy_spu0 : 1;
124 unsigned int busy_spu1 : 1;
125 unsigned int owned_by_cpu : 1;
126 unsigned int owned_by_mpu : 1;
127 unsigned int owned_by_spu0 : 1;
128 unsigned int owned_by_spu1 : 1;
129 unsigned int dummy1 : 24;
130} reg_iop_sw_spu_r_mc_stat;
131#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20
132
133/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
134typedef struct {
135 unsigned int byte0 : 8;
136 unsigned int byte1 : 8;
137 unsigned int byte2 : 8;
138 unsigned int byte3 : 8;
139} reg_iop_sw_spu_rw_bus0_clr_mask;
140#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
141#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
142
143/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
144typedef struct {
145 unsigned int byte0 : 8;
146 unsigned int byte1 : 8;
147 unsigned int byte2 : 8;
148 unsigned int byte3 : 8;
149} reg_iop_sw_spu_rw_bus0_set_mask;
150#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28
151#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28
152
153/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
154typedef struct {
155 unsigned int byte0 : 1;
156 unsigned int byte1 : 1;
157 unsigned int byte2 : 1;
158 unsigned int byte3 : 1;
159 unsigned int dummy1 : 28;
160} reg_iop_sw_spu_rw_bus0_oe_clr_mask;
161#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
162#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
163
164/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
165typedef struct {
166 unsigned int byte0 : 1;
167 unsigned int byte1 : 1;
168 unsigned int byte2 : 1;
169 unsigned int byte3 : 1;
170 unsigned int dummy1 : 28;
171} reg_iop_sw_spu_rw_bus0_oe_set_mask;
172#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
173#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
174
175/* Register r_bus0_in, scope iop_sw_spu, type r */
176typedef unsigned int reg_iop_sw_spu_r_bus0_in;
177#define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40
178
179/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
180typedef struct {
181 unsigned int byte0 : 8;
182 unsigned int byte1 : 8;
183 unsigned int byte2 : 8;
184 unsigned int byte3 : 8;
185} reg_iop_sw_spu_rw_bus1_clr_mask;
186#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
187#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
188
189/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
190typedef struct {
191 unsigned int byte0 : 8;
192 unsigned int byte1 : 8;
193 unsigned int byte2 : 8;
194 unsigned int byte3 : 8;
195} reg_iop_sw_spu_rw_bus1_set_mask;
196#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48
197#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48
198
199/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
200typedef struct {
201 unsigned int byte0 : 1;
202 unsigned int byte1 : 1;
203 unsigned int byte2 : 1;
204 unsigned int byte3 : 1;
205 unsigned int dummy1 : 28;
206} reg_iop_sw_spu_rw_bus1_oe_clr_mask;
207#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
208#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
209
210/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
211typedef struct {
212 unsigned int byte0 : 1;
213 unsigned int byte1 : 1;
214 unsigned int byte2 : 1;
215 unsigned int byte3 : 1;
216 unsigned int dummy1 : 28;
217} reg_iop_sw_spu_rw_bus1_oe_set_mask;
218#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
219#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
220
221/* Register r_bus1_in, scope iop_sw_spu, type r */
222typedef unsigned int reg_iop_sw_spu_r_bus1_in;
223#define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60
224
225/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
226typedef struct {
227 unsigned int val : 32;
228} reg_iop_sw_spu_rw_gio_clr_mask;
229#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64
230#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64
231
232/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
233typedef struct {
234 unsigned int val : 32;
235} reg_iop_sw_spu_rw_gio_set_mask;
236#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68
237#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68
238
239/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
240typedef struct {
241 unsigned int val : 32;
242} reg_iop_sw_spu_rw_gio_oe_clr_mask;
243#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
244#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
245
246/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
247typedef struct {
248 unsigned int val : 32;
249} reg_iop_sw_spu_rw_gio_oe_set_mask;
250#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
251#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
252
253/* Register r_gio_in, scope iop_sw_spu, type r */
254typedef unsigned int reg_iop_sw_spu_r_gio_in;
255#define REG_RD_ADDR_iop_sw_spu_r_gio_in 80
256
257/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
258typedef struct {
259 unsigned int byte0 : 8;
260 unsigned int byte1 : 8;
261 unsigned int dummy1 : 16;
262} reg_iop_sw_spu_rw_bus0_clr_mask_lo;
263#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
264#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
265
266/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
267typedef struct {
268 unsigned int byte2 : 8;
269 unsigned int byte3 : 8;
270 unsigned int dummy1 : 16;
271} reg_iop_sw_spu_rw_bus0_clr_mask_hi;
272#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
273#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
274
275/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
276typedef struct {
277 unsigned int byte0 : 8;
278 unsigned int byte1 : 8;
279 unsigned int dummy1 : 16;
280} reg_iop_sw_spu_rw_bus0_set_mask_lo;
281#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
282#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
283
284/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
285typedef struct {
286 unsigned int byte2 : 8;
287 unsigned int byte3 : 8;
288 unsigned int dummy1 : 16;
289} reg_iop_sw_spu_rw_bus0_set_mask_hi;
290#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
291#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
292
293/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
294typedef struct {
295 unsigned int byte0 : 8;
296 unsigned int byte1 : 8;
297 unsigned int dummy1 : 16;
298} reg_iop_sw_spu_rw_bus1_clr_mask_lo;
299#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
300#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
301
302/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
303typedef struct {
304 unsigned int byte2 : 8;
305 unsigned int byte3 : 8;
306 unsigned int dummy1 : 16;
307} reg_iop_sw_spu_rw_bus1_clr_mask_hi;
308#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
309#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
310
311/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
312typedef struct {
313 unsigned int byte0 : 8;
314 unsigned int byte1 : 8;
315 unsigned int dummy1 : 16;
316} reg_iop_sw_spu_rw_bus1_set_mask_lo;
317#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
318#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
319
320/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
321typedef struct {
322 unsigned int byte2 : 8;
323 unsigned int byte3 : 8;
324 unsigned int dummy1 : 16;
325} reg_iop_sw_spu_rw_bus1_set_mask_hi;
326#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
327#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
328
329/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
330typedef struct {
331 unsigned int val : 16;
332 unsigned int dummy1 : 16;
333} reg_iop_sw_spu_rw_gio_clr_mask_lo;
334#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
335#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
336
337/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
338typedef struct {
339 unsigned int val : 16;
340 unsigned int dummy1 : 16;
341} reg_iop_sw_spu_rw_gio_clr_mask_hi;
342#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
343#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
344
345/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
346typedef struct {
347 unsigned int val : 16;
348 unsigned int dummy1 : 16;
349} reg_iop_sw_spu_rw_gio_set_mask_lo;
350#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
351#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
352
353/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
354typedef struct {
355 unsigned int val : 16;
356 unsigned int dummy1 : 16;
357} reg_iop_sw_spu_rw_gio_set_mask_hi;
358#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
359#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
360
361/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
362typedef struct {
363 unsigned int val : 16;
364 unsigned int dummy1 : 16;
365} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
366#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
367#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
368
369/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
370typedef struct {
371 unsigned int val : 16;
372 unsigned int dummy1 : 16;
373} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
374#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
375#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
376
377/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
378typedef struct {
379 unsigned int val : 16;
380 unsigned int dummy1 : 16;
381} reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
382#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
383#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
384
385/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
386typedef struct {
387 unsigned int val : 16;
388 unsigned int dummy1 : 16;
389} reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
390#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
391#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
392
393/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
394typedef struct {
395 unsigned int intr0 : 1;
396 unsigned int intr1 : 1;
397 unsigned int intr2 : 1;
398 unsigned int intr3 : 1;
399 unsigned int intr4 : 1;
400 unsigned int intr5 : 1;
401 unsigned int intr6 : 1;
402 unsigned int intr7 : 1;
403 unsigned int intr8 : 1;
404 unsigned int intr9 : 1;
405 unsigned int intr10 : 1;
406 unsigned int intr11 : 1;
407 unsigned int intr12 : 1;
408 unsigned int intr13 : 1;
409 unsigned int intr14 : 1;
410 unsigned int intr15 : 1;
411 unsigned int dummy1 : 16;
412} reg_iop_sw_spu_rw_cpu_intr;
413#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148
414#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148
415
416/* Register r_cpu_intr, scope iop_sw_spu, type r */
417typedef struct {
418 unsigned int intr0 : 1;
419 unsigned int intr1 : 1;
420 unsigned int intr2 : 1;
421 unsigned int intr3 : 1;
422 unsigned int intr4 : 1;
423 unsigned int intr5 : 1;
424 unsigned int intr6 : 1;
425 unsigned int intr7 : 1;
426 unsigned int intr8 : 1;
427 unsigned int intr9 : 1;
428 unsigned int intr10 : 1;
429 unsigned int intr11 : 1;
430 unsigned int intr12 : 1;
431 unsigned int intr13 : 1;
432 unsigned int intr14 : 1;
433 unsigned int intr15 : 1;
434 unsigned int dummy1 : 16;
435} reg_iop_sw_spu_r_cpu_intr;
436#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152
437
438/* Register r_hw_intr, scope iop_sw_spu, type r */
439typedef struct {
440 unsigned int trigger_grp0 : 1;
441 unsigned int trigger_grp1 : 1;
442 unsigned int trigger_grp2 : 1;
443 unsigned int trigger_grp3 : 1;
444 unsigned int trigger_grp4 : 1;
445 unsigned int trigger_grp5 : 1;
446 unsigned int trigger_grp6 : 1;
447 unsigned int trigger_grp7 : 1;
448 unsigned int timer_grp0 : 1;
449 unsigned int timer_grp1 : 1;
450 unsigned int timer_grp2 : 1;
451 unsigned int timer_grp3 : 1;
452 unsigned int fifo_out0 : 1;
453 unsigned int fifo_out0_extra : 1;
454 unsigned int fifo_in0 : 1;
455 unsigned int fifo_in0_extra : 1;
456 unsigned int fifo_out1 : 1;
457 unsigned int fifo_out1_extra : 1;
458 unsigned int fifo_in1 : 1;
459 unsigned int fifo_in1_extra : 1;
460 unsigned int dmc_out0 : 1;
461 unsigned int dmc_in0 : 1;
462 unsigned int dmc_out1 : 1;
463 unsigned int dmc_in1 : 1;
464 unsigned int dummy1 : 8;
465} reg_iop_sw_spu_r_hw_intr;
466#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156
467
468/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
469typedef struct {
470 unsigned int intr0 : 1;
471 unsigned int intr1 : 1;
472 unsigned int intr2 : 1;
473 unsigned int intr3 : 1;
474 unsigned int intr4 : 1;
475 unsigned int intr5 : 1;
476 unsigned int intr6 : 1;
477 unsigned int intr7 : 1;
478 unsigned int intr8 : 1;
479 unsigned int intr9 : 1;
480 unsigned int intr10 : 1;
481 unsigned int intr11 : 1;
482 unsigned int intr12 : 1;
483 unsigned int intr13 : 1;
484 unsigned int intr14 : 1;
485 unsigned int intr15 : 1;
486 unsigned int dummy1 : 16;
487} reg_iop_sw_spu_rw_mpu_intr;
488#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160
489#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160
490
491/* Register r_mpu_intr, scope iop_sw_spu, type r */
492typedef struct {
493 unsigned int intr0 : 1;
494 unsigned int intr1 : 1;
495 unsigned int intr2 : 1;
496 unsigned int intr3 : 1;
497 unsigned int intr4 : 1;
498 unsigned int intr5 : 1;
499 unsigned int intr6 : 1;
500 unsigned int intr7 : 1;
501 unsigned int intr8 : 1;
502 unsigned int intr9 : 1;
503 unsigned int intr10 : 1;
504 unsigned int intr11 : 1;
505 unsigned int intr12 : 1;
506 unsigned int intr13 : 1;
507 unsigned int intr14 : 1;
508 unsigned int intr15 : 1;
509 unsigned int other_spu_intr0 : 1;
510 unsigned int other_spu_intr1 : 1;
511 unsigned int other_spu_intr2 : 1;
512 unsigned int other_spu_intr3 : 1;
513 unsigned int other_spu_intr4 : 1;
514 unsigned int other_spu_intr5 : 1;
515 unsigned int other_spu_intr6 : 1;
516 unsigned int other_spu_intr7 : 1;
517 unsigned int other_spu_intr8 : 1;
518 unsigned int other_spu_intr9 : 1;
519 unsigned int other_spu_intr10 : 1;
520 unsigned int other_spu_intr11 : 1;
521 unsigned int other_spu_intr12 : 1;
522 unsigned int other_spu_intr13 : 1;
523 unsigned int other_spu_intr14 : 1;
524 unsigned int other_spu_intr15 : 1;
525} reg_iop_sw_spu_r_mpu_intr;
526#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164
527
528
529/* Constants */
530enum {
531 regk_iop_sw_spu_copy = 0x00000000,
532 regk_iop_sw_spu_no = 0x00000000,
533 regk_iop_sw_spu_nop = 0x00000000,
534 regk_iop_sw_spu_rd = 0x00000002,
535 regk_iop_sw_spu_reg_copy = 0x00000001,
536 regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000,
537 regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000,
538 regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000,
539 regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000,
540 regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000,
541 regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000,
542 regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000,
543 regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000,
544 regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000,
545 regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
546 regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
547 regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000,
548 regk_iop_sw_spu_set = 0x00000001,
549 regk_iop_sw_spu_wr = 0x00000003,
550 regk_iop_sw_spu_yes = 0x00000001
551};
552#endif /* __iop_sw_spu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h
new file mode 100644
index 000000000000..c994114f3b51
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h
@@ -0,0 +1,249 @@
1#ifndef __iop_timer_grp_defs_h
2#define __iop_timer_grp_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_timer_grp.r
7 * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
8 * last modfied: Mon Apr 11 16:08:46 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r
11 * id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_timer_grp */
86
87/* Register rw_cfg, scope iop_timer_grp, type rw */
88typedef struct {
89 unsigned int clk_src : 1;
90 unsigned int trig : 2;
91 unsigned int clk_gen_div : 8;
92 unsigned int clk_div : 8;
93 unsigned int dummy1 : 13;
94} reg_iop_timer_grp_rw_cfg;
95#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0
96#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0
97
98/* Register rw_half_period, scope iop_timer_grp, type rw */
99typedef struct {
100 unsigned int quota_lo : 15;
101 unsigned int quota_hi : 15;
102 unsigned int quota_hi_sel : 1;
103 unsigned int dummy1 : 1;
104} reg_iop_timer_grp_rw_half_period;
105#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4
106#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4
107
108/* Register rw_half_period_len, scope iop_timer_grp, type rw */
109typedef unsigned int reg_iop_timer_grp_rw_half_period_len;
110#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8
111#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8
112
113#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
114/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
115typedef struct {
116 unsigned int clk_src : 3;
117 unsigned int strb : 2;
118 unsigned int run_mode : 2;
119 unsigned int out_mode : 1;
120 unsigned int active_on_tmr : 2;
121 unsigned int inv : 1;
122 unsigned int en_by_tmr : 2;
123 unsigned int dis_by_tmr : 2;
124 unsigned int en_only_by_reg : 1;
125 unsigned int dis_only_by_reg : 1;
126 unsigned int rst_at_en_strb : 1;
127 unsigned int dummy1 : 14;
128} reg_iop_timer_grp_rw_tmr_cfg;
129#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12
130#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12
131
132#define STRIDE_iop_timer_grp_rw_tmr_len 4
133/* Register rw_tmr_len, scope iop_timer_grp, type rw */
134typedef struct {
135 unsigned int val : 16;
136 unsigned int dummy1 : 16;
137} reg_iop_timer_grp_rw_tmr_len;
138#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44
139#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44
140
141/* Register rw_cmd, scope iop_timer_grp, type rw */
142typedef struct {
143 unsigned int rst : 4;
144 unsigned int en : 4;
145 unsigned int dis : 4;
146 unsigned int strb : 4;
147 unsigned int dummy1 : 16;
148} reg_iop_timer_grp_rw_cmd;
149#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60
150#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60
151
152/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
153typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt;
154#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64
155
156#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
157/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
158typedef struct {
159 unsigned int val : 16;
160 unsigned int dummy1 : 16;
161} reg_iop_timer_grp_rs_tmr_cnt;
162#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68
163
164#define STRIDE_iop_timer_grp_r_tmr_cnt 8
165/* Register r_tmr_cnt, scope iop_timer_grp, type r */
166typedef struct {
167 unsigned int val : 16;
168 unsigned int dummy1 : 16;
169} reg_iop_timer_grp_r_tmr_cnt;
170#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72
171
172/* Register rw_intr_mask, scope iop_timer_grp, type rw */
173typedef struct {
174 unsigned int tmr0 : 1;
175 unsigned int tmr1 : 1;
176 unsigned int tmr2 : 1;
177 unsigned int tmr3 : 1;
178 unsigned int dummy1 : 28;
179} reg_iop_timer_grp_rw_intr_mask;
180#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100
181#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100
182
183/* Register rw_ack_intr, scope iop_timer_grp, type rw */
184typedef struct {
185 unsigned int tmr0 : 1;
186 unsigned int tmr1 : 1;
187 unsigned int tmr2 : 1;
188 unsigned int tmr3 : 1;
189 unsigned int dummy1 : 28;
190} reg_iop_timer_grp_rw_ack_intr;
191#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104
192#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104
193
194/* Register r_intr, scope iop_timer_grp, type r */
195typedef struct {
196 unsigned int tmr0 : 1;
197 unsigned int tmr1 : 1;
198 unsigned int tmr2 : 1;
199 unsigned int tmr3 : 1;
200 unsigned int dummy1 : 28;
201} reg_iop_timer_grp_r_intr;
202#define REG_RD_ADDR_iop_timer_grp_r_intr 108
203
204/* Register r_masked_intr, scope iop_timer_grp, type r */
205typedef struct {
206 unsigned int tmr0 : 1;
207 unsigned int tmr1 : 1;
208 unsigned int tmr2 : 1;
209 unsigned int tmr3 : 1;
210 unsigned int dummy1 : 28;
211} reg_iop_timer_grp_r_masked_intr;
212#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112
213
214
215/* Constants */
216enum {
217 regk_iop_timer_grp_clk200 = 0x00000000,
218 regk_iop_timer_grp_clk_gen = 0x00000002,
219 regk_iop_timer_grp_complete = 0x00000002,
220 regk_iop_timer_grp_div_clk200 = 0x00000001,
221 regk_iop_timer_grp_div_clk_gen = 0x00000003,
222 regk_iop_timer_grp_ext = 0x00000001,
223 regk_iop_timer_grp_hi = 0x00000000,
224 regk_iop_timer_grp_long_period = 0x00000001,
225 regk_iop_timer_grp_neg = 0x00000002,
226 regk_iop_timer_grp_no = 0x00000000,
227 regk_iop_timer_grp_once = 0x00000003,
228 regk_iop_timer_grp_pause = 0x00000001,
229 regk_iop_timer_grp_pos = 0x00000001,
230 regk_iop_timer_grp_pos_neg = 0x00000003,
231 regk_iop_timer_grp_pulse = 0x00000000,
232 regk_iop_timer_grp_r_tmr_cnt_size = 0x00000004,
233 regk_iop_timer_grp_rs_tmr_cnt_size = 0x00000004,
234 regk_iop_timer_grp_rw_cfg_default = 0x00000002,
235 regk_iop_timer_grp_rw_intr_mask_default = 0x00000000,
236 regk_iop_timer_grp_rw_tmr_cfg_default0 = 0x00018000,
237 regk_iop_timer_grp_rw_tmr_cfg_default1 = 0x0001a900,
238 regk_iop_timer_grp_rw_tmr_cfg_default2 = 0x0001d200,
239 regk_iop_timer_grp_rw_tmr_cfg_default3 = 0x0001fb00,
240 regk_iop_timer_grp_rw_tmr_cfg_size = 0x00000004,
241 regk_iop_timer_grp_rw_tmr_len_default = 0x00000000,
242 regk_iop_timer_grp_rw_tmr_len_size = 0x00000004,
243 regk_iop_timer_grp_short_period = 0x00000000,
244 regk_iop_timer_grp_stop = 0x00000000,
245 regk_iop_timer_grp_tmr = 0x00000004,
246 regk_iop_timer_grp_toggle = 0x00000001,
247 regk_iop_timer_grp_yes = 0x00000001
248};
249#endif /* __iop_timer_grp_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h
new file mode 100644
index 000000000000..36e44282399d
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h
@@ -0,0 +1,170 @@
1#ifndef __iop_trigger_grp_defs_h
2#define __iop_trigger_grp_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/iop_trigger_grp.r
7 * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp
8 * last modfied: Mon Apr 11 16:08:46 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r
11 * id: $Id: iop_trigger_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_trigger_grp */
86
87#define STRIDE_iop_trigger_grp_rw_cfg 4
88/* Register rw_cfg, scope iop_trigger_grp, type rw */
89typedef struct {
90 unsigned int action : 2;
91 unsigned int once : 1;
92 unsigned int trig : 3;
93 unsigned int en_only_by_reg : 1;
94 unsigned int dis_only_by_reg : 1;
95 unsigned int dummy1 : 24;
96} reg_iop_trigger_grp_rw_cfg;
97#define REG_RD_ADDR_iop_trigger_grp_rw_cfg 0
98#define REG_WR_ADDR_iop_trigger_grp_rw_cfg 0
99
100/* Register rw_cmd, scope iop_trigger_grp, type rw */
101typedef struct {
102 unsigned int dis : 4;
103 unsigned int en : 4;
104 unsigned int dummy1 : 24;
105} reg_iop_trigger_grp_rw_cmd;
106#define REG_RD_ADDR_iop_trigger_grp_rw_cmd 16
107#define REG_WR_ADDR_iop_trigger_grp_rw_cmd 16
108
109/* Register rw_intr_mask, scope iop_trigger_grp, type rw */
110typedef struct {
111 unsigned int trig0 : 1;
112 unsigned int trig1 : 1;
113 unsigned int trig2 : 1;
114 unsigned int trig3 : 1;
115 unsigned int dummy1 : 28;
116} reg_iop_trigger_grp_rw_intr_mask;
117#define REG_RD_ADDR_iop_trigger_grp_rw_intr_mask 20
118#define REG_WR_ADDR_iop_trigger_grp_rw_intr_mask 20
119
120/* Register rw_ack_intr, scope iop_trigger_grp, type rw */
121typedef struct {
122 unsigned int trig0 : 1;
123 unsigned int trig1 : 1;
124 unsigned int trig2 : 1;
125 unsigned int trig3 : 1;
126 unsigned int dummy1 : 28;
127} reg_iop_trigger_grp_rw_ack_intr;
128#define REG_RD_ADDR_iop_trigger_grp_rw_ack_intr 24
129#define REG_WR_ADDR_iop_trigger_grp_rw_ack_intr 24
130
131/* Register r_intr, scope iop_trigger_grp, type r */
132typedef struct {
133 unsigned int trig0 : 1;
134 unsigned int trig1 : 1;
135 unsigned int trig2 : 1;
136 unsigned int trig3 : 1;
137 unsigned int dummy1 : 28;
138} reg_iop_trigger_grp_r_intr;
139#define REG_RD_ADDR_iop_trigger_grp_r_intr 28
140
141/* Register r_masked_intr, scope iop_trigger_grp, type r */
142typedef struct {
143 unsigned int trig0 : 1;
144 unsigned int trig1 : 1;
145 unsigned int trig2 : 1;
146 unsigned int trig3 : 1;
147 unsigned int dummy1 : 28;
148} reg_iop_trigger_grp_r_masked_intr;
149#define REG_RD_ADDR_iop_trigger_grp_r_masked_intr 32
150
151
152/* Constants */
153enum {
154 regk_iop_trigger_grp_fall = 0x00000002,
155 regk_iop_trigger_grp_fall_lo = 0x00000006,
156 regk_iop_trigger_grp_no = 0x00000000,
157 regk_iop_trigger_grp_off = 0x00000000,
158 regk_iop_trigger_grp_pulse = 0x00000000,
159 regk_iop_trigger_grp_rise = 0x00000001,
160 regk_iop_trigger_grp_rise_fall = 0x00000003,
161 regk_iop_trigger_grp_rise_fall_hi = 0x00000007,
162 regk_iop_trigger_grp_rise_fall_lo = 0x00000004,
163 regk_iop_trigger_grp_rise_hi = 0x00000005,
164 regk_iop_trigger_grp_rw_cfg_default = 0x000000c0,
165 regk_iop_trigger_grp_rw_cfg_size = 0x00000004,
166 regk_iop_trigger_grp_rw_intr_mask_default = 0x00000000,
167 regk_iop_trigger_grp_toggle = 0x00000003,
168 regk_iop_trigger_grp_yes = 0x00000001
169};
170#endif /* __iop_trigger_grp_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h
new file mode 100644
index 000000000000..b8d6a910c71c
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h
@@ -0,0 +1,99 @@
1#ifndef __iop_version_defs_h
2#define __iop_version_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/io_proc/rtl/guinness/iop_version.r
7 * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp
8 * last modfied: Mon Apr 11 16:08:44 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_version_defs.h ../../inst/io_proc/rtl/guinness/iop_version.r
11 * id: $Id: iop_version_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope iop_version */
86
87/* Register r_version, scope iop_version, type r */
88typedef struct {
89 unsigned int nr : 8;
90 unsigned int dummy1 : 24;
91} reg_iop_version_r_version;
92#define REG_RD_ADDR_iop_version_r_version 0
93
94
95/* Constants */
96enum {
97 regk_iop_version_v1_0 = 0x00000001
98};
99#endif /* __iop_version_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h b/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h
new file mode 100644
index 000000000000..7b167e3c0572
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h
@@ -0,0 +1,104 @@
1#ifndef __irq_nmi_defs_h
2#define __irq_nmi_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../mod/irq_nmi.r
7 * id: <not found>
8 * last modfied: Thu Jan 22 09:22:43 2004
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile irq_nmi_defs.h ../../mod/irq_nmi.r
11 * id: $Id: irq_nmi_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope irq_nmi */
86
87/* Register rw_cmd, scope irq_nmi, type rw */
88typedef struct {
89 unsigned int delay : 16;
90 unsigned int op : 2;
91 unsigned int dummy1 : 14;
92} reg_irq_nmi_rw_cmd;
93#define REG_RD_ADDR_irq_nmi_rw_cmd 0
94#define REG_WR_ADDR_irq_nmi_rw_cmd 0
95
96
97/* Constants */
98enum {
99 regk_irq_nmi_ack_irq = 0x00000002,
100 regk_irq_nmi_ack_nmi = 0x00000003,
101 regk_irq_nmi_irq = 0x00000000,
102 regk_irq_nmi_nmi = 0x00000001
103};
104#endif /* __irq_nmi_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h b/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h
new file mode 100644
index 000000000000..a11fdd3cd907
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h
@@ -0,0 +1,205 @@
1#ifndef __marb_bp_defs_h
2#define __marb_bp_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/memarb/rtl/guinness/marb_top.r
7 * id: <not found>
8 * last modfied: Fri Nov 7 15:36:04 2003
9 *
10 * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r
11 * id: $Id: marb_bp_defs.h,v 1.2 2004/06/04 07:15:33 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74/* C-code for register scope marb_bp */
75
76/* Register rw_first_addr, scope marb_bp, type rw */
77typedef unsigned int reg_marb_bp_rw_first_addr;
78#define REG_RD_ADDR_marb_bp_rw_first_addr 0
79#define REG_WR_ADDR_marb_bp_rw_first_addr 0
80
81/* Register rw_last_addr, scope marb_bp, type rw */
82typedef unsigned int reg_marb_bp_rw_last_addr;
83#define REG_RD_ADDR_marb_bp_rw_last_addr 4
84#define REG_WR_ADDR_marb_bp_rw_last_addr 4
85
86/* Register rw_op, scope marb_bp, type rw */
87typedef struct {
88 unsigned int read : 1;
89 unsigned int write : 1;
90 unsigned int read_excl : 1;
91 unsigned int pri_write : 1;
92 unsigned int us_read : 1;
93 unsigned int us_write : 1;
94 unsigned int us_read_excl : 1;
95 unsigned int us_pri_write : 1;
96 unsigned int dummy1 : 24;
97} reg_marb_bp_rw_op;
98#define REG_RD_ADDR_marb_bp_rw_op 8
99#define REG_WR_ADDR_marb_bp_rw_op 8
100
101/* Register rw_clients, scope marb_bp, type rw */
102typedef struct {
103 unsigned int dma0 : 1;
104 unsigned int dma1 : 1;
105 unsigned int dma2 : 1;
106 unsigned int dma3 : 1;
107 unsigned int dma4 : 1;
108 unsigned int dma5 : 1;
109 unsigned int dma6 : 1;
110 unsigned int dma7 : 1;
111 unsigned int dma8 : 1;
112 unsigned int dma9 : 1;
113 unsigned int cpui : 1;
114 unsigned int cpud : 1;
115 unsigned int iop : 1;
116 unsigned int slave : 1;
117 unsigned int dummy1 : 18;
118} reg_marb_bp_rw_clients;
119#define REG_RD_ADDR_marb_bp_rw_clients 12
120#define REG_WR_ADDR_marb_bp_rw_clients 12
121
122/* Register rw_options, scope marb_bp, type rw */
123typedef struct {
124 unsigned int wrap : 1;
125 unsigned int dummy1 : 31;
126} reg_marb_bp_rw_options;
127#define REG_RD_ADDR_marb_bp_rw_options 16
128#define REG_WR_ADDR_marb_bp_rw_options 16
129
130/* Register r_break_addr, scope marb_bp, type r */
131typedef unsigned int reg_marb_bp_r_break_addr;
132#define REG_RD_ADDR_marb_bp_r_break_addr 20
133
134/* Register r_break_op, scope marb_bp, type r */
135typedef struct {
136 unsigned int read : 1;
137 unsigned int write : 1;
138 unsigned int read_excl : 1;
139 unsigned int pri_write : 1;
140 unsigned int us_read : 1;
141 unsigned int us_write : 1;
142 unsigned int us_read_excl : 1;
143 unsigned int us_pri_write : 1;
144 unsigned int dummy1 : 24;
145} reg_marb_bp_r_break_op;
146#define REG_RD_ADDR_marb_bp_r_break_op 24
147
148/* Register r_break_clients, scope marb_bp, type r */
149typedef struct {
150 unsigned int dma0 : 1;
151 unsigned int dma1 : 1;
152 unsigned int dma2 : 1;
153 unsigned int dma3 : 1;
154 unsigned int dma4 : 1;
155 unsigned int dma5 : 1;
156 unsigned int dma6 : 1;
157 unsigned int dma7 : 1;
158 unsigned int dma8 : 1;
159 unsigned int dma9 : 1;
160 unsigned int cpui : 1;
161 unsigned int cpud : 1;
162 unsigned int iop : 1;
163 unsigned int slave : 1;
164 unsigned int dummy1 : 18;
165} reg_marb_bp_r_break_clients;
166#define REG_RD_ADDR_marb_bp_r_break_clients 28
167
168/* Register r_break_first_client, scope marb_bp, type r */
169typedef struct {
170 unsigned int dma0 : 1;
171 unsigned int dma1 : 1;
172 unsigned int dma2 : 1;
173 unsigned int dma3 : 1;
174 unsigned int dma4 : 1;
175 unsigned int dma5 : 1;
176 unsigned int dma6 : 1;
177 unsigned int dma7 : 1;
178 unsigned int dma8 : 1;
179 unsigned int dma9 : 1;
180 unsigned int cpui : 1;
181 unsigned int cpud : 1;
182 unsigned int iop : 1;
183 unsigned int slave : 1;
184 unsigned int dummy1 : 18;
185} reg_marb_bp_r_break_first_client;
186#define REG_RD_ADDR_marb_bp_r_break_first_client 32
187
188/* Register r_break_size, scope marb_bp, type r */
189typedef unsigned int reg_marb_bp_r_break_size;
190#define REG_RD_ADDR_marb_bp_r_break_size 36
191
192/* Register rw_ack, scope marb_bp, type rw */
193typedef unsigned int reg_marb_bp_rw_ack;
194#define REG_RD_ADDR_marb_bp_rw_ack 40
195#define REG_WR_ADDR_marb_bp_rw_ack 40
196
197
198/* Constants */
199enum {
200 regk_marb_bp_no = 0x00000000,
201 regk_marb_bp_rw_op_default = 0x00000000,
202 regk_marb_bp_rw_options_default = 0x00000000,
203 regk_marb_bp_yes = 0x00000001
204};
205#endif /* __marb_bp_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/marb_defs.h b/include/asm-cris/arch-v32/hwregs/marb_defs.h
new file mode 100644
index 000000000000..71e8af0bb3a4
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/marb_defs.h
@@ -0,0 +1,475 @@
1#ifndef __marb_defs_h
2#define __marb_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/memarb/rtl/guinness/marb_top.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:12:16 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
11 * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope marb */
86
87#define STRIDE_marb_rw_int_slots 4
88/* Register rw_int_slots, scope marb, type rw */
89typedef struct {
90 unsigned int owner : 4;
91 unsigned int dummy1 : 28;
92} reg_marb_rw_int_slots;
93#define REG_RD_ADDR_marb_rw_int_slots 0
94#define REG_WR_ADDR_marb_rw_int_slots 0
95
96#define STRIDE_marb_rw_ext_slots 4
97/* Register rw_ext_slots, scope marb, type rw */
98typedef struct {
99 unsigned int owner : 4;
100 unsigned int dummy1 : 28;
101} reg_marb_rw_ext_slots;
102#define REG_RD_ADDR_marb_rw_ext_slots 256
103#define REG_WR_ADDR_marb_rw_ext_slots 256
104
105#define STRIDE_marb_rw_regs_slots 4
106/* Register rw_regs_slots, scope marb, type rw */
107typedef struct {
108 unsigned int owner : 4;
109 unsigned int dummy1 : 28;
110} reg_marb_rw_regs_slots;
111#define REG_RD_ADDR_marb_rw_regs_slots 512
112#define REG_WR_ADDR_marb_rw_regs_slots 512
113
114/* Register rw_intr_mask, scope marb, type rw */
115typedef struct {
116 unsigned int bp0 : 1;
117 unsigned int bp1 : 1;
118 unsigned int bp2 : 1;
119 unsigned int bp3 : 1;
120 unsigned int dummy1 : 28;
121} reg_marb_rw_intr_mask;
122#define REG_RD_ADDR_marb_rw_intr_mask 528
123#define REG_WR_ADDR_marb_rw_intr_mask 528
124
125/* Register rw_ack_intr, scope marb, type rw */
126typedef struct {
127 unsigned int bp0 : 1;
128 unsigned int bp1 : 1;
129 unsigned int bp2 : 1;
130 unsigned int bp3 : 1;
131 unsigned int dummy1 : 28;
132} reg_marb_rw_ack_intr;
133#define REG_RD_ADDR_marb_rw_ack_intr 532
134#define REG_WR_ADDR_marb_rw_ack_intr 532
135
136/* Register r_intr, scope marb, type r */
137typedef struct {
138 unsigned int bp0 : 1;
139 unsigned int bp1 : 1;
140 unsigned int bp2 : 1;
141 unsigned int bp3 : 1;
142 unsigned int dummy1 : 28;
143} reg_marb_r_intr;
144#define REG_RD_ADDR_marb_r_intr 536
145
146/* Register r_masked_intr, scope marb, type r */
147typedef struct {
148 unsigned int bp0 : 1;
149 unsigned int bp1 : 1;
150 unsigned int bp2 : 1;
151 unsigned int bp3 : 1;
152 unsigned int dummy1 : 28;
153} reg_marb_r_masked_intr;
154#define REG_RD_ADDR_marb_r_masked_intr 540
155
156/* Register rw_stop_mask, scope marb, type rw */
157typedef struct {
158 unsigned int dma0 : 1;
159 unsigned int dma1 : 1;
160 unsigned int dma2 : 1;
161 unsigned int dma3 : 1;
162 unsigned int dma4 : 1;
163 unsigned int dma5 : 1;
164 unsigned int dma6 : 1;
165 unsigned int dma7 : 1;
166 unsigned int dma8 : 1;
167 unsigned int dma9 : 1;
168 unsigned int cpui : 1;
169 unsigned int cpud : 1;
170 unsigned int iop : 1;
171 unsigned int slave : 1;
172 unsigned int dummy1 : 18;
173} reg_marb_rw_stop_mask;
174#define REG_RD_ADDR_marb_rw_stop_mask 544
175#define REG_WR_ADDR_marb_rw_stop_mask 544
176
177/* Register r_stopped, scope marb, type r */
178typedef struct {
179 unsigned int dma0 : 1;
180 unsigned int dma1 : 1;
181 unsigned int dma2 : 1;
182 unsigned int dma3 : 1;
183 unsigned int dma4 : 1;
184 unsigned int dma5 : 1;
185 unsigned int dma6 : 1;
186 unsigned int dma7 : 1;
187 unsigned int dma8 : 1;
188 unsigned int dma9 : 1;
189 unsigned int cpui : 1;
190 unsigned int cpud : 1;
191 unsigned int iop : 1;
192 unsigned int slave : 1;
193 unsigned int dummy1 : 18;
194} reg_marb_r_stopped;
195#define REG_RD_ADDR_marb_r_stopped 548
196
197/* Register rw_no_snoop, scope marb, type rw */
198typedef struct {
199 unsigned int dma0 : 1;
200 unsigned int dma1 : 1;
201 unsigned int dma2 : 1;
202 unsigned int dma3 : 1;
203 unsigned int dma4 : 1;
204 unsigned int dma5 : 1;
205 unsigned int dma6 : 1;
206 unsigned int dma7 : 1;
207 unsigned int dma8 : 1;
208 unsigned int dma9 : 1;
209 unsigned int cpui : 1;
210 unsigned int cpud : 1;
211 unsigned int iop : 1;
212 unsigned int slave : 1;
213 unsigned int dummy1 : 18;
214} reg_marb_rw_no_snoop;
215#define REG_RD_ADDR_marb_rw_no_snoop 832
216#define REG_WR_ADDR_marb_rw_no_snoop 832
217
218/* Register rw_no_snoop_rq, scope marb, type rw */
219typedef struct {
220 unsigned int dummy1 : 10;
221 unsigned int cpui : 1;
222 unsigned int cpud : 1;
223 unsigned int dummy2 : 20;
224} reg_marb_rw_no_snoop_rq;
225#define REG_RD_ADDR_marb_rw_no_snoop_rq 836
226#define REG_WR_ADDR_marb_rw_no_snoop_rq 836
227
228
229/* Constants */
230enum {
231 regk_marb_cpud = 0x0000000b,
232 regk_marb_cpui = 0x0000000a,
233 regk_marb_dma0 = 0x00000000,
234 regk_marb_dma1 = 0x00000001,
235 regk_marb_dma2 = 0x00000002,
236 regk_marb_dma3 = 0x00000003,
237 regk_marb_dma4 = 0x00000004,
238 regk_marb_dma5 = 0x00000005,
239 regk_marb_dma6 = 0x00000006,
240 regk_marb_dma7 = 0x00000007,
241 regk_marb_dma8 = 0x00000008,
242 regk_marb_dma9 = 0x00000009,
243 regk_marb_iop = 0x0000000c,
244 regk_marb_no = 0x00000000,
245 regk_marb_r_stopped_default = 0x00000000,
246 regk_marb_rw_ext_slots_default = 0x00000000,
247 regk_marb_rw_ext_slots_size = 0x00000040,
248 regk_marb_rw_int_slots_default = 0x00000000,
249 regk_marb_rw_int_slots_size = 0x00000040,
250 regk_marb_rw_intr_mask_default = 0x00000000,
251 regk_marb_rw_no_snoop_default = 0x00000000,
252 regk_marb_rw_no_snoop_rq_default = 0x00000000,
253 regk_marb_rw_regs_slots_default = 0x00000000,
254 regk_marb_rw_regs_slots_size = 0x00000004,
255 regk_marb_rw_stop_mask_default = 0x00000000,
256 regk_marb_slave = 0x0000000d,
257 regk_marb_yes = 0x00000001
258};
259#endif /* __marb_defs_h */
260#ifndef __marb_bp_defs_h
261#define __marb_bp_defs_h
262
263/*
264 * This file is autogenerated from
265 * file: ../../inst/memarb/rtl/guinness/marb_top.r
266 * id: <not found>
267 * last modfied: Mon Apr 11 16:12:16 2005
268 *
269 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
270 * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
271 * Any changes here will be lost.
272 *
273 * -*- buffer-read-only: t -*-
274 */
275/* Main access macros */
276#ifndef REG_RD
277#define REG_RD( scope, inst, reg ) \
278 REG_READ( reg_##scope##_##reg, \
279 (inst) + REG_RD_ADDR_##scope##_##reg )
280#endif
281
282#ifndef REG_WR
283#define REG_WR( scope, inst, reg, val ) \
284 REG_WRITE( reg_##scope##_##reg, \
285 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
286#endif
287
288#ifndef REG_RD_VECT
289#define REG_RD_VECT( scope, inst, reg, index ) \
290 REG_READ( reg_##scope##_##reg, \
291 (inst) + REG_RD_ADDR_##scope##_##reg + \
292 (index) * STRIDE_##scope##_##reg )
293#endif
294
295#ifndef REG_WR_VECT
296#define REG_WR_VECT( scope, inst, reg, index, val ) \
297 REG_WRITE( reg_##scope##_##reg, \
298 (inst) + REG_WR_ADDR_##scope##_##reg + \
299 (index) * STRIDE_##scope##_##reg, (val) )
300#endif
301
302#ifndef REG_RD_INT
303#define REG_RD_INT( scope, inst, reg ) \
304 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
305#endif
306
307#ifndef REG_WR_INT
308#define REG_WR_INT( scope, inst, reg, val ) \
309 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
310#endif
311
312#ifndef REG_RD_INT_VECT
313#define REG_RD_INT_VECT( scope, inst, reg, index ) \
314 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
315 (index) * STRIDE_##scope##_##reg )
316#endif
317
318#ifndef REG_WR_INT_VECT
319#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
320 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
321 (index) * STRIDE_##scope##_##reg, (val) )
322#endif
323
324#ifndef REG_TYPE_CONV
325#define REG_TYPE_CONV( type, orgtype, val ) \
326 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
327#endif
328
329#ifndef reg_page_size
330#define reg_page_size 8192
331#endif
332
333#ifndef REG_ADDR
334#define REG_ADDR( scope, inst, reg ) \
335 ( (inst) + REG_RD_ADDR_##scope##_##reg )
336#endif
337
338#ifndef REG_ADDR_VECT
339#define REG_ADDR_VECT( scope, inst, reg, index ) \
340 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
341 (index) * STRIDE_##scope##_##reg )
342#endif
343
344/* C-code for register scope marb_bp */
345
346/* Register rw_first_addr, scope marb_bp, type rw */
347typedef unsigned int reg_marb_bp_rw_first_addr;
348#define REG_RD_ADDR_marb_bp_rw_first_addr 0
349#define REG_WR_ADDR_marb_bp_rw_first_addr 0
350
351/* Register rw_last_addr, scope marb_bp, type rw */
352typedef unsigned int reg_marb_bp_rw_last_addr;
353#define REG_RD_ADDR_marb_bp_rw_last_addr 4
354#define REG_WR_ADDR_marb_bp_rw_last_addr 4
355
356/* Register rw_op, scope marb_bp, type rw */
357typedef struct {
358 unsigned int rd : 1;
359 unsigned int wr : 1;
360 unsigned int rd_excl : 1;
361 unsigned int pri_wr : 1;
362 unsigned int us_rd : 1;
363 unsigned int us_wr : 1;
364 unsigned int us_rd_excl : 1;
365 unsigned int us_pri_wr : 1;
366 unsigned int dummy1 : 24;
367} reg_marb_bp_rw_op;
368#define REG_RD_ADDR_marb_bp_rw_op 8
369#define REG_WR_ADDR_marb_bp_rw_op 8
370
371/* Register rw_clients, scope marb_bp, type rw */
372typedef struct {
373 unsigned int dma0 : 1;
374 unsigned int dma1 : 1;
375 unsigned int dma2 : 1;
376 unsigned int dma3 : 1;
377 unsigned int dma4 : 1;
378 unsigned int dma5 : 1;
379 unsigned int dma6 : 1;
380 unsigned int dma7 : 1;
381 unsigned int dma8 : 1;
382 unsigned int dma9 : 1;
383 unsigned int cpui : 1;
384 unsigned int cpud : 1;
385 unsigned int iop : 1;
386 unsigned int slave : 1;
387 unsigned int dummy1 : 18;
388} reg_marb_bp_rw_clients;
389#define REG_RD_ADDR_marb_bp_rw_clients 12
390#define REG_WR_ADDR_marb_bp_rw_clients 12
391
392/* Register rw_options, scope marb_bp, type rw */
393typedef struct {
394 unsigned int wrap : 1;
395 unsigned int dummy1 : 31;
396} reg_marb_bp_rw_options;
397#define REG_RD_ADDR_marb_bp_rw_options 16
398#define REG_WR_ADDR_marb_bp_rw_options 16
399
400/* Register r_brk_addr, scope marb_bp, type r */
401typedef unsigned int reg_marb_bp_r_brk_addr;
402#define REG_RD_ADDR_marb_bp_r_brk_addr 20
403
404/* Register r_brk_op, scope marb_bp, type r */
405typedef struct {
406 unsigned int rd : 1;
407 unsigned int wr : 1;
408 unsigned int rd_excl : 1;
409 unsigned int pri_wr : 1;
410 unsigned int us_rd : 1;
411 unsigned int us_wr : 1;
412 unsigned int us_rd_excl : 1;
413 unsigned int us_pri_wr : 1;
414 unsigned int dummy1 : 24;
415} reg_marb_bp_r_brk_op;
416#define REG_RD_ADDR_marb_bp_r_brk_op 24
417
418/* Register r_brk_clients, scope marb_bp, type r */
419typedef struct {
420 unsigned int dma0 : 1;
421 unsigned int dma1 : 1;
422 unsigned int dma2 : 1;
423 unsigned int dma3 : 1;
424 unsigned int dma4 : 1;
425 unsigned int dma5 : 1;
426 unsigned int dma6 : 1;
427 unsigned int dma7 : 1;
428 unsigned int dma8 : 1;
429 unsigned int dma9 : 1;
430 unsigned int cpui : 1;
431 unsigned int cpud : 1;
432 unsigned int iop : 1;
433 unsigned int slave : 1;
434 unsigned int dummy1 : 18;
435} reg_marb_bp_r_brk_clients;
436#define REG_RD_ADDR_marb_bp_r_brk_clients 28
437
438/* Register r_brk_first_client, scope marb_bp, type r */
439typedef struct {
440 unsigned int dma0 : 1;
441 unsigned int dma1 : 1;
442 unsigned int dma2 : 1;
443 unsigned int dma3 : 1;
444 unsigned int dma4 : 1;
445 unsigned int dma5 : 1;
446 unsigned int dma6 : 1;
447 unsigned int dma7 : 1;
448 unsigned int dma8 : 1;
449 unsigned int dma9 : 1;
450 unsigned int cpui : 1;
451 unsigned int cpud : 1;
452 unsigned int iop : 1;
453 unsigned int slave : 1;
454 unsigned int dummy1 : 18;
455} reg_marb_bp_r_brk_first_client;
456#define REG_RD_ADDR_marb_bp_r_brk_first_client 32
457
458/* Register r_brk_size, scope marb_bp, type r */
459typedef unsigned int reg_marb_bp_r_brk_size;
460#define REG_RD_ADDR_marb_bp_r_brk_size 36
461
462/* Register rw_ack, scope marb_bp, type rw */
463typedef unsigned int reg_marb_bp_rw_ack;
464#define REG_RD_ADDR_marb_bp_rw_ack 40
465#define REG_WR_ADDR_marb_bp_rw_ack 40
466
467
468/* Constants */
469enum {
470 regk_marb_bp_no = 0x00000000,
471 regk_marb_bp_rw_op_default = 0x00000000,
472 regk_marb_bp_rw_options_default = 0x00000000,
473 regk_marb_bp_yes = 0x00000001
474};
475#endif /* __marb_bp_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/hwregs/pinmux_defs.h
new file mode 100644
index 000000000000..9d91c2de1b07
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/pinmux_defs.h
@@ -0,0 +1,357 @@
1#ifndef __pinmux_defs_h
2#define __pinmux_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r
7 * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
8 * last modfied: Mon Apr 11 16:09:11 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
11 * id: $Id: pinmux_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope pinmux */
86
87/* Register rw_pa, scope pinmux, type rw */
88typedef struct {
89 unsigned int pa0 : 1;
90 unsigned int pa1 : 1;
91 unsigned int pa2 : 1;
92 unsigned int pa3 : 1;
93 unsigned int pa4 : 1;
94 unsigned int pa5 : 1;
95 unsigned int pa6 : 1;
96 unsigned int pa7 : 1;
97 unsigned int csp2_n : 1;
98 unsigned int csp3_n : 1;
99 unsigned int csp5_n : 1;
100 unsigned int csp6_n : 1;
101 unsigned int hsh4 : 1;
102 unsigned int hsh5 : 1;
103 unsigned int hsh6 : 1;
104 unsigned int hsh7 : 1;
105 unsigned int dummy1 : 16;
106} reg_pinmux_rw_pa;
107#define REG_RD_ADDR_pinmux_rw_pa 0
108#define REG_WR_ADDR_pinmux_rw_pa 0
109
110/* Register rw_hwprot, scope pinmux, type rw */
111typedef struct {
112 unsigned int ser1 : 1;
113 unsigned int ser2 : 1;
114 unsigned int ser3 : 1;
115 unsigned int sser0 : 1;
116 unsigned int sser1 : 1;
117 unsigned int ata0 : 1;
118 unsigned int ata1 : 1;
119 unsigned int ata2 : 1;
120 unsigned int ata3 : 1;
121 unsigned int ata : 1;
122 unsigned int eth1 : 1;
123 unsigned int eth1_mgm : 1;
124 unsigned int timer : 1;
125 unsigned int p21 : 1;
126 unsigned int dummy1 : 18;
127} reg_pinmux_rw_hwprot;
128#define REG_RD_ADDR_pinmux_rw_hwprot 4
129#define REG_WR_ADDR_pinmux_rw_hwprot 4
130
131/* Register rw_pb_gio, scope pinmux, type rw */
132typedef struct {
133 unsigned int pb0 : 1;
134 unsigned int pb1 : 1;
135 unsigned int pb2 : 1;
136 unsigned int pb3 : 1;
137 unsigned int pb4 : 1;
138 unsigned int pb5 : 1;
139 unsigned int pb6 : 1;
140 unsigned int pb7 : 1;
141 unsigned int pb8 : 1;
142 unsigned int pb9 : 1;
143 unsigned int pb10 : 1;
144 unsigned int pb11 : 1;
145 unsigned int pb12 : 1;
146 unsigned int pb13 : 1;
147 unsigned int pb14 : 1;
148 unsigned int pb15 : 1;
149 unsigned int pb16 : 1;
150 unsigned int pb17 : 1;
151 unsigned int dummy1 : 14;
152} reg_pinmux_rw_pb_gio;
153#define REG_RD_ADDR_pinmux_rw_pb_gio 8
154#define REG_WR_ADDR_pinmux_rw_pb_gio 8
155
156/* Register rw_pb_iop, scope pinmux, type rw */
157typedef struct {
158 unsigned int pb0 : 1;
159 unsigned int pb1 : 1;
160 unsigned int pb2 : 1;
161 unsigned int pb3 : 1;
162 unsigned int pb4 : 1;
163 unsigned int pb5 : 1;
164 unsigned int pb6 : 1;
165 unsigned int pb7 : 1;
166 unsigned int pb8 : 1;
167 unsigned int pb9 : 1;
168 unsigned int pb10 : 1;
169 unsigned int pb11 : 1;
170 unsigned int pb12 : 1;
171 unsigned int pb13 : 1;
172 unsigned int pb14 : 1;
173 unsigned int pb15 : 1;
174 unsigned int pb16 : 1;
175 unsigned int pb17 : 1;
176 unsigned int dummy1 : 14;
177} reg_pinmux_rw_pb_iop;
178#define REG_RD_ADDR_pinmux_rw_pb_iop 12
179#define REG_WR_ADDR_pinmux_rw_pb_iop 12
180
181/* Register rw_pc_gio, scope pinmux, type rw */
182typedef struct {
183 unsigned int pc0 : 1;
184 unsigned int pc1 : 1;
185 unsigned int pc2 : 1;
186 unsigned int pc3 : 1;
187 unsigned int pc4 : 1;
188 unsigned int pc5 : 1;
189 unsigned int pc6 : 1;
190 unsigned int pc7 : 1;
191 unsigned int pc8 : 1;
192 unsigned int pc9 : 1;
193 unsigned int pc10 : 1;
194 unsigned int pc11 : 1;
195 unsigned int pc12 : 1;
196 unsigned int pc13 : 1;
197 unsigned int pc14 : 1;
198 unsigned int pc15 : 1;
199 unsigned int pc16 : 1;
200 unsigned int pc17 : 1;
201 unsigned int dummy1 : 14;
202} reg_pinmux_rw_pc_gio;
203#define REG_RD_ADDR_pinmux_rw_pc_gio 16
204#define REG_WR_ADDR_pinmux_rw_pc_gio 16
205
206/* Register rw_pc_iop, scope pinmux, type rw */
207typedef struct {
208 unsigned int pc0 : 1;
209 unsigned int pc1 : 1;
210 unsigned int pc2 : 1;
211 unsigned int pc3 : 1;
212 unsigned int pc4 : 1;
213 unsigned int pc5 : 1;
214 unsigned int pc6 : 1;
215 unsigned int pc7 : 1;
216 unsigned int pc8 : 1;
217 unsigned int pc9 : 1;
218 unsigned int pc10 : 1;
219 unsigned int pc11 : 1;
220 unsigned int pc12 : 1;
221 unsigned int pc13 : 1;
222 unsigned int pc14 : 1;
223 unsigned int pc15 : 1;
224 unsigned int pc16 : 1;
225 unsigned int pc17 : 1;
226 unsigned int dummy1 : 14;
227} reg_pinmux_rw_pc_iop;
228#define REG_RD_ADDR_pinmux_rw_pc_iop 20
229#define REG_WR_ADDR_pinmux_rw_pc_iop 20
230
231/* Register rw_pd_gio, scope pinmux, type rw */
232typedef struct {
233 unsigned int pd0 : 1;
234 unsigned int pd1 : 1;
235 unsigned int pd2 : 1;
236 unsigned int pd3 : 1;
237 unsigned int pd4 : 1;
238 unsigned int pd5 : 1;
239 unsigned int pd6 : 1;
240 unsigned int pd7 : 1;
241 unsigned int pd8 : 1;
242 unsigned int pd9 : 1;
243 unsigned int pd10 : 1;
244 unsigned int pd11 : 1;
245 unsigned int pd12 : 1;
246 unsigned int pd13 : 1;
247 unsigned int pd14 : 1;
248 unsigned int pd15 : 1;
249 unsigned int pd16 : 1;
250 unsigned int pd17 : 1;
251 unsigned int dummy1 : 14;
252} reg_pinmux_rw_pd_gio;
253#define REG_RD_ADDR_pinmux_rw_pd_gio 24
254#define REG_WR_ADDR_pinmux_rw_pd_gio 24
255
256/* Register rw_pd_iop, scope pinmux, type rw */
257typedef struct {
258 unsigned int pd0 : 1;
259 unsigned int pd1 : 1;
260 unsigned int pd2 : 1;
261 unsigned int pd3 : 1;
262 unsigned int pd4 : 1;
263 unsigned int pd5 : 1;
264 unsigned int pd6 : 1;
265 unsigned int pd7 : 1;
266 unsigned int pd8 : 1;
267 unsigned int pd9 : 1;
268 unsigned int pd10 : 1;
269 unsigned int pd11 : 1;
270 unsigned int pd12 : 1;
271 unsigned int pd13 : 1;
272 unsigned int pd14 : 1;
273 unsigned int pd15 : 1;
274 unsigned int pd16 : 1;
275 unsigned int pd17 : 1;
276 unsigned int dummy1 : 14;
277} reg_pinmux_rw_pd_iop;
278#define REG_RD_ADDR_pinmux_rw_pd_iop 28
279#define REG_WR_ADDR_pinmux_rw_pd_iop 28
280
281/* Register rw_pe_gio, scope pinmux, type rw */
282typedef struct {
283 unsigned int pe0 : 1;
284 unsigned int pe1 : 1;
285 unsigned int pe2 : 1;
286 unsigned int pe3 : 1;
287 unsigned int pe4 : 1;
288 unsigned int pe5 : 1;
289 unsigned int pe6 : 1;
290 unsigned int pe7 : 1;
291 unsigned int pe8 : 1;
292 unsigned int pe9 : 1;
293 unsigned int pe10 : 1;
294 unsigned int pe11 : 1;
295 unsigned int pe12 : 1;
296 unsigned int pe13 : 1;
297 unsigned int pe14 : 1;
298 unsigned int pe15 : 1;
299 unsigned int pe16 : 1;
300 unsigned int pe17 : 1;
301 unsigned int dummy1 : 14;
302} reg_pinmux_rw_pe_gio;
303#define REG_RD_ADDR_pinmux_rw_pe_gio 32
304#define REG_WR_ADDR_pinmux_rw_pe_gio 32
305
306/* Register rw_pe_iop, scope pinmux, type rw */
307typedef struct {
308 unsigned int pe0 : 1;
309 unsigned int pe1 : 1;
310 unsigned int pe2 : 1;
311 unsigned int pe3 : 1;
312 unsigned int pe4 : 1;
313 unsigned int pe5 : 1;
314 unsigned int pe6 : 1;
315 unsigned int pe7 : 1;
316 unsigned int pe8 : 1;
317 unsigned int pe9 : 1;
318 unsigned int pe10 : 1;
319 unsigned int pe11 : 1;
320 unsigned int pe12 : 1;
321 unsigned int pe13 : 1;
322 unsigned int pe14 : 1;
323 unsigned int pe15 : 1;
324 unsigned int pe16 : 1;
325 unsigned int pe17 : 1;
326 unsigned int dummy1 : 14;
327} reg_pinmux_rw_pe_iop;
328#define REG_RD_ADDR_pinmux_rw_pe_iop 36
329#define REG_WR_ADDR_pinmux_rw_pe_iop 36
330
331/* Register rw_usb_phy, scope pinmux, type rw */
332typedef struct {
333 unsigned int en_usb0 : 1;
334 unsigned int en_usb1 : 1;
335 unsigned int dummy1 : 30;
336} reg_pinmux_rw_usb_phy;
337#define REG_RD_ADDR_pinmux_rw_usb_phy 40
338#define REG_WR_ADDR_pinmux_rw_usb_phy 40
339
340
341/* Constants */
342enum {
343 regk_pinmux_no = 0x00000000,
344 regk_pinmux_rw_hwprot_default = 0x00000000,
345 regk_pinmux_rw_pa_default = 0x00000000,
346 regk_pinmux_rw_pb_gio_default = 0x00000000,
347 regk_pinmux_rw_pb_iop_default = 0x00000000,
348 regk_pinmux_rw_pc_gio_default = 0x00000000,
349 regk_pinmux_rw_pc_iop_default = 0x00000000,
350 regk_pinmux_rw_pd_gio_default = 0x00000000,
351 regk_pinmux_rw_pd_iop_default = 0x00000000,
352 regk_pinmux_rw_pe_gio_default = 0x00000000,
353 regk_pinmux_rw_pe_iop_default = 0x00000000,
354 regk_pinmux_rw_usb_phy_default = 0x00000000,
355 regk_pinmux_yes = 0x00000001
356};
357#endif /* __pinmux_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/reg_map.h b/include/asm-cris/arch-v32/hwregs/reg_map.h
new file mode 100644
index 000000000000..e31502838ec6
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/reg_map.h
@@ -0,0 +1,103 @@
1#ifndef __reg_map_h
2#define __reg_map_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../mod/fakereg.rmap
7 * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
8 * last modified: Wed Feb 11 20:53:25 2004
9 * file: ../../rtl/global.rmap
10 * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
11 * last modified: Mon Aug 18 17:08:23 2003
12 * file: ../../mod/modreg.rmap
13 * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
14 * last modified: Fri Feb 20 16:40:04 2004
15 *
16 * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
17 * id: $Id: reg_map.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
18 * Any changes here will be lost.
19 *
20 * -*- buffer-read-only: t -*-
21 */
22typedef enum {
23 regi_ata = 0xb0032000,
24 regi_bif_core = 0xb0014000,
25 regi_bif_dma = 0xb0016000,
26 regi_bif_slave = 0xb0018000,
27 regi_config = 0xb003c000,
28 regi_dma0 = 0xb0000000,
29 regi_dma1 = 0xb0002000,
30 regi_dma2 = 0xb0004000,
31 regi_dma3 = 0xb0006000,
32 regi_dma4 = 0xb0008000,
33 regi_dma5 = 0xb000a000,
34 regi_dma6 = 0xb000c000,
35 regi_dma7 = 0xb000e000,
36 regi_dma8 = 0xb0010000,
37 regi_dma9 = 0xb0012000,
38 regi_eth0 = 0xb0034000,
39 regi_eth1 = 0xb0036000,
40 regi_gio = 0xb001a000,
41 regi_iop = 0xb0020000,
42 regi_iop_version = 0xb0020000,
43 regi_iop_fifo_in0_extra = 0xb0020040,
44 regi_iop_fifo_in1_extra = 0xb0020080,
45 regi_iop_fifo_out0_extra = 0xb00200c0,
46 regi_iop_fifo_out1_extra = 0xb0020100,
47 regi_iop_trigger_grp0 = 0xb0020140,
48 regi_iop_trigger_grp1 = 0xb0020180,
49 regi_iop_trigger_grp2 = 0xb00201c0,
50 regi_iop_trigger_grp3 = 0xb0020200,
51 regi_iop_trigger_grp4 = 0xb0020240,
52 regi_iop_trigger_grp5 = 0xb0020280,
53 regi_iop_trigger_grp6 = 0xb00202c0,
54 regi_iop_trigger_grp7 = 0xb0020300,
55 regi_iop_crc_par0 = 0xb0020380,
56 regi_iop_crc_par1 = 0xb0020400,
57 regi_iop_dmc_in0 = 0xb0020480,
58 regi_iop_dmc_in1 = 0xb0020500,
59 regi_iop_dmc_out0 = 0xb0020580,
60 regi_iop_dmc_out1 = 0xb0020600,
61 regi_iop_fifo_in0 = 0xb0020680,
62 regi_iop_fifo_in1 = 0xb0020700,
63 regi_iop_fifo_out0 = 0xb0020780,
64 regi_iop_fifo_out1 = 0xb0020800,
65 regi_iop_scrc_in0 = 0xb0020880,
66 regi_iop_scrc_in1 = 0xb0020900,
67 regi_iop_scrc_out0 = 0xb0020980,
68 regi_iop_scrc_out1 = 0xb0020a00,
69 regi_iop_timer_grp0 = 0xb0020a80,
70 regi_iop_timer_grp1 = 0xb0020b00,
71 regi_iop_timer_grp2 = 0xb0020b80,
72 regi_iop_timer_grp3 = 0xb0020c00,
73 regi_iop_sap_in = 0xb0020d00,
74 regi_iop_sap_out = 0xb0020e00,
75 regi_iop_spu0 = 0xb0020f00,
76 regi_iop_spu1 = 0xb0021000,
77 regi_iop_sw_cfg = 0xb0021100,
78 regi_iop_sw_cpu = 0xb0021200,
79 regi_iop_sw_mpu = 0xb0021300,
80 regi_iop_sw_spu0 = 0xb0021400,
81 regi_iop_sw_spu1 = 0xb0021500,
82 regi_iop_mpu = 0xb0021600,
83 regi_irq = 0xb001c000,
84 regi_irq2 = 0xb005c000,
85 regi_marb = 0xb003e000,
86 regi_marb_bp0 = 0xb003e240,
87 regi_marb_bp1 = 0xb003e280,
88 regi_marb_bp2 = 0xb003e2c0,
89 regi_marb_bp3 = 0xb003e300,
90 regi_pinmux = 0xb0038000,
91 regi_ser0 = 0xb0026000,
92 regi_ser1 = 0xb0028000,
93 regi_ser2 = 0xb002a000,
94 regi_ser3 = 0xb002c000,
95 regi_sser0 = 0xb0022000,
96 regi_sser1 = 0xb0024000,
97 regi_strcop = 0xb0030000,
98 regi_strmux = 0xb003a000,
99 regi_timer = 0xb001e000,
100 regi_timer2 = 0xb005e000,
101 regi_trace = 0xb0040000,
102} reg_scope_instances;
103#endif /* __reg_map_h */
diff --git a/include/asm-cris/arch-v32/hwregs/reg_rdwr.h b/include/asm-cris/arch-v32/hwregs/reg_rdwr.h
new file mode 100644
index 000000000000..44e60233c68f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/reg_rdwr.h
@@ -0,0 +1,15 @@
1/* $Id: reg_rdwr.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
2 *
3 * Read/write register macros used by *_defs.h
4 */
5
6#ifndef reg_rdwr_h
7#define reg_rdwr_h
8
9
10#define REG_READ(type, addr) *((volatile type *) (addr))
11
12#define REG_WRITE(type, addr, val) \
13 do { *((volatile type *) (addr)) = (val); } while(0)
14
15#endif
diff --git a/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h b/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h
new file mode 100644
index 000000000000..d9f0e924fb23
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h
@@ -0,0 +1,173 @@
1#ifndef __rt_trace_defs_h
2#define __rt_trace_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/rt_trace/rtl/rt_regs.r
7 * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp
8 * last modfied: Mon Apr 11 16:09:14 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile rt_trace_defs.h ../../inst/rt_trace/rtl/rt_regs.r
11 * id: $Id: rt_trace_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope rt_trace */
86
87/* Register rw_cfg, scope rt_trace, type rw */
88typedef struct {
89 unsigned int en : 1;
90 unsigned int mode : 1;
91 unsigned int owner : 1;
92 unsigned int wp : 1;
93 unsigned int stall : 1;
94 unsigned int dummy1 : 3;
95 unsigned int wp_start : 7;
96 unsigned int dummy2 : 1;
97 unsigned int wp_stop : 7;
98 unsigned int dummy3 : 9;
99} reg_rt_trace_rw_cfg;
100#define REG_RD_ADDR_rt_trace_rw_cfg 0
101#define REG_WR_ADDR_rt_trace_rw_cfg 0
102
103/* Register rw_tap_ctrl, scope rt_trace, type rw */
104typedef struct {
105 unsigned int ack_data : 1;
106 unsigned int ack_guru : 1;
107 unsigned int dummy1 : 30;
108} reg_rt_trace_rw_tap_ctrl;
109#define REG_RD_ADDR_rt_trace_rw_tap_ctrl 4
110#define REG_WR_ADDR_rt_trace_rw_tap_ctrl 4
111
112/* Register r_tap_stat, scope rt_trace, type r */
113typedef struct {
114 unsigned int dav : 1;
115 unsigned int empty : 1;
116 unsigned int dummy1 : 30;
117} reg_rt_trace_r_tap_stat;
118#define REG_RD_ADDR_rt_trace_r_tap_stat 8
119
120/* Register rw_tap_data, scope rt_trace, type rw */
121typedef unsigned int reg_rt_trace_rw_tap_data;
122#define REG_RD_ADDR_rt_trace_rw_tap_data 12
123#define REG_WR_ADDR_rt_trace_rw_tap_data 12
124
125/* Register rw_tap_hdata, scope rt_trace, type rw */
126typedef struct {
127 unsigned int op : 4;
128 unsigned int sub_op : 4;
129 unsigned int dummy1 : 24;
130} reg_rt_trace_rw_tap_hdata;
131#define REG_RD_ADDR_rt_trace_rw_tap_hdata 16
132#define REG_WR_ADDR_rt_trace_rw_tap_hdata 16
133
134/* Register r_redir, scope rt_trace, type r */
135typedef unsigned int reg_rt_trace_r_redir;
136#define REG_RD_ADDR_rt_trace_r_redir 20
137
138
139/* Constants */
140enum {
141 regk_rt_trace_brk = 0x0000000c,
142 regk_rt_trace_dbg = 0x00000003,
143 regk_rt_trace_dbgdi = 0x00000004,
144 regk_rt_trace_dbgdo = 0x00000005,
145 regk_rt_trace_gmode = 0x00000000,
146 regk_rt_trace_no = 0x00000000,
147 regk_rt_trace_nop = 0x00000000,
148 regk_rt_trace_normal = 0x00000000,
149 regk_rt_trace_rdmem = 0x00000007,
150 regk_rt_trace_rdmemb = 0x00000009,
151 regk_rt_trace_rdpreg = 0x00000002,
152 regk_rt_trace_rdreg = 0x00000001,
153 regk_rt_trace_rdsreg = 0x00000003,
154 regk_rt_trace_redir = 0x00000006,
155 regk_rt_trace_ret = 0x0000000b,
156 regk_rt_trace_rw_cfg_default = 0x00000000,
157 regk_rt_trace_trcfg = 0x00000001,
158 regk_rt_trace_wp = 0x00000001,
159 regk_rt_trace_wp0 = 0x00000001,
160 regk_rt_trace_wp1 = 0x00000002,
161 regk_rt_trace_wp2 = 0x00000004,
162 regk_rt_trace_wp3 = 0x00000008,
163 regk_rt_trace_wp4 = 0x00000010,
164 regk_rt_trace_wp5 = 0x00000020,
165 regk_rt_trace_wp6 = 0x00000040,
166 regk_rt_trace_wrmem = 0x00000008,
167 regk_rt_trace_wrmemb = 0x0000000a,
168 regk_rt_trace_wrpreg = 0x00000005,
169 regk_rt_trace_wrreg = 0x00000004,
170 regk_rt_trace_wrsreg = 0x00000006,
171 regk_rt_trace_yes = 0x00000001
172};
173#endif /* __rt_trace_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/ser_defs.h b/include/asm-cris/arch-v32/hwregs/ser_defs.h
new file mode 100644
index 000000000000..01c2fab97d43
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/ser_defs.h
@@ -0,0 +1,308 @@
1#ifndef __ser_defs_h
2#define __ser_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/ser/rtl/ser_regs.r
7 * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp
8 * last modfied: Mon Apr 11 16:09:21 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r
11 * id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope ser */
86
87/* Register rw_tr_ctrl, scope ser, type rw */
88typedef struct {
89 unsigned int base_freq : 3;
90 unsigned int en : 1;
91 unsigned int par : 2;
92 unsigned int par_en : 1;
93 unsigned int data_bits : 1;
94 unsigned int stop_bits : 1;
95 unsigned int stop : 1;
96 unsigned int rts_delay : 3;
97 unsigned int rts_setup : 1;
98 unsigned int auto_rts : 1;
99 unsigned int txd : 1;
100 unsigned int auto_cts : 1;
101 unsigned int dummy1 : 15;
102} reg_ser_rw_tr_ctrl;
103#define REG_RD_ADDR_ser_rw_tr_ctrl 0
104#define REG_WR_ADDR_ser_rw_tr_ctrl 0
105
106/* Register rw_tr_dma_en, scope ser, type rw */
107typedef struct {
108 unsigned int en : 1;
109 unsigned int dummy1 : 31;
110} reg_ser_rw_tr_dma_en;
111#define REG_RD_ADDR_ser_rw_tr_dma_en 4
112#define REG_WR_ADDR_ser_rw_tr_dma_en 4
113
114/* Register rw_rec_ctrl, scope ser, type rw */
115typedef struct {
116 unsigned int base_freq : 3;
117 unsigned int en : 1;
118 unsigned int par : 2;
119 unsigned int par_en : 1;
120 unsigned int data_bits : 1;
121 unsigned int dma_mode : 1;
122 unsigned int dma_err : 1;
123 unsigned int sampling : 1;
124 unsigned int timeout : 3;
125 unsigned int auto_eop : 1;
126 unsigned int half_duplex : 1;
127 unsigned int rts_n : 1;
128 unsigned int loopback : 1;
129 unsigned int dummy1 : 14;
130} reg_ser_rw_rec_ctrl;
131#define REG_RD_ADDR_ser_rw_rec_ctrl 8
132#define REG_WR_ADDR_ser_rw_rec_ctrl 8
133
134/* Register rw_tr_baud_div, scope ser, type rw */
135typedef struct {
136 unsigned int div : 16;
137 unsigned int dummy1 : 16;
138} reg_ser_rw_tr_baud_div;
139#define REG_RD_ADDR_ser_rw_tr_baud_div 12
140#define REG_WR_ADDR_ser_rw_tr_baud_div 12
141
142/* Register rw_rec_baud_div, scope ser, type rw */
143typedef struct {
144 unsigned int div : 16;
145 unsigned int dummy1 : 16;
146} reg_ser_rw_rec_baud_div;
147#define REG_RD_ADDR_ser_rw_rec_baud_div 16
148#define REG_WR_ADDR_ser_rw_rec_baud_div 16
149
150/* Register rw_xoff, scope ser, type rw */
151typedef struct {
152 unsigned int chr : 8;
153 unsigned int automatic : 1;
154 unsigned int dummy1 : 23;
155} reg_ser_rw_xoff;
156#define REG_RD_ADDR_ser_rw_xoff 20
157#define REG_WR_ADDR_ser_rw_xoff 20
158
159/* Register rw_xoff_clr, scope ser, type rw */
160typedef struct {
161 unsigned int clr : 1;
162 unsigned int dummy1 : 31;
163} reg_ser_rw_xoff_clr;
164#define REG_RD_ADDR_ser_rw_xoff_clr 24
165#define REG_WR_ADDR_ser_rw_xoff_clr 24
166
167/* Register rw_dout, scope ser, type rw */
168typedef struct {
169 unsigned int data : 8;
170 unsigned int dummy1 : 24;
171} reg_ser_rw_dout;
172#define REG_RD_ADDR_ser_rw_dout 28
173#define REG_WR_ADDR_ser_rw_dout 28
174
175/* Register rs_stat_din, scope ser, type rs */
176typedef struct {
177 unsigned int data : 8;
178 unsigned int dummy1 : 8;
179 unsigned int dav : 1;
180 unsigned int framing_err : 1;
181 unsigned int par_err : 1;
182 unsigned int orun : 1;
183 unsigned int rec_err : 1;
184 unsigned int rxd : 1;
185 unsigned int tr_idle : 1;
186 unsigned int tr_empty : 1;
187 unsigned int tr_rdy : 1;
188 unsigned int cts_n : 1;
189 unsigned int xoff_detect : 1;
190 unsigned int rts_n : 1;
191 unsigned int txd : 1;
192 unsigned int dummy2 : 3;
193} reg_ser_rs_stat_din;
194#define REG_RD_ADDR_ser_rs_stat_din 32
195
196/* Register r_stat_din, scope ser, type r */
197typedef struct {
198 unsigned int data : 8;
199 unsigned int dummy1 : 8;
200 unsigned int dav : 1;
201 unsigned int framing_err : 1;
202 unsigned int par_err : 1;
203 unsigned int orun : 1;
204 unsigned int rec_err : 1;
205 unsigned int rxd : 1;
206 unsigned int tr_idle : 1;
207 unsigned int tr_empty : 1;
208 unsigned int tr_rdy : 1;
209 unsigned int cts_n : 1;
210 unsigned int xoff_detect : 1;
211 unsigned int rts_n : 1;
212 unsigned int txd : 1;
213 unsigned int dummy2 : 3;
214} reg_ser_r_stat_din;
215#define REG_RD_ADDR_ser_r_stat_din 36
216
217/* Register rw_rec_eop, scope ser, type rw */
218typedef struct {
219 unsigned int set : 1;
220 unsigned int dummy1 : 31;
221} reg_ser_rw_rec_eop;
222#define REG_RD_ADDR_ser_rw_rec_eop 40
223#define REG_WR_ADDR_ser_rw_rec_eop 40
224
225/* Register rw_intr_mask, scope ser, type rw */
226typedef struct {
227 unsigned int tr_rdy : 1;
228 unsigned int tr_empty : 1;
229 unsigned int tr_idle : 1;
230 unsigned int dav : 1;
231 unsigned int dummy1 : 28;
232} reg_ser_rw_intr_mask;
233#define REG_RD_ADDR_ser_rw_intr_mask 44
234#define REG_WR_ADDR_ser_rw_intr_mask 44
235
236/* Register rw_ack_intr, scope ser, type rw */
237typedef struct {
238 unsigned int tr_rdy : 1;
239 unsigned int tr_empty : 1;
240 unsigned int tr_idle : 1;
241 unsigned int dav : 1;
242 unsigned int dummy1 : 28;
243} reg_ser_rw_ack_intr;
244#define REG_RD_ADDR_ser_rw_ack_intr 48
245#define REG_WR_ADDR_ser_rw_ack_intr 48
246
247/* Register r_intr, scope ser, type r */
248typedef struct {
249 unsigned int tr_rdy : 1;
250 unsigned int tr_empty : 1;
251 unsigned int tr_idle : 1;
252 unsigned int dav : 1;
253 unsigned int dummy1 : 28;
254} reg_ser_r_intr;
255#define REG_RD_ADDR_ser_r_intr 52
256
257/* Register r_masked_intr, scope ser, type r */
258typedef struct {
259 unsigned int tr_rdy : 1;
260 unsigned int tr_empty : 1;
261 unsigned int tr_idle : 1;
262 unsigned int dav : 1;
263 unsigned int dummy1 : 28;
264} reg_ser_r_masked_intr;
265#define REG_RD_ADDR_ser_r_masked_intr 56
266
267
268/* Constants */
269enum {
270 regk_ser_active = 0x00000000,
271 regk_ser_bits1 = 0x00000000,
272 regk_ser_bits2 = 0x00000001,
273 regk_ser_bits7 = 0x00000001,
274 regk_ser_bits8 = 0x00000000,
275 regk_ser_del0_5 = 0x00000000,
276 regk_ser_del1 = 0x00000001,
277 regk_ser_del1_5 = 0x00000002,
278 regk_ser_del2 = 0x00000003,
279 regk_ser_del2_5 = 0x00000004,
280 regk_ser_del3 = 0x00000005,
281 regk_ser_del3_5 = 0x00000006,
282 regk_ser_del4 = 0x00000007,
283 regk_ser_even = 0x00000000,
284 regk_ser_ext = 0x00000001,
285 regk_ser_f100 = 0x00000007,
286 regk_ser_f29_493 = 0x00000004,
287 regk_ser_f32 = 0x00000005,
288 regk_ser_f32_768 = 0x00000006,
289 regk_ser_ignore = 0x00000001,
290 regk_ser_inactive = 0x00000001,
291 regk_ser_majority = 0x00000001,
292 regk_ser_mark = 0x00000002,
293 regk_ser_middle = 0x00000000,
294 regk_ser_no = 0x00000000,
295 regk_ser_odd = 0x00000001,
296 regk_ser_off = 0x00000000,
297 regk_ser_rw_intr_mask_default = 0x00000000,
298 regk_ser_rw_rec_baud_div_default = 0x00000000,
299 regk_ser_rw_rec_ctrl_default = 0x00010000,
300 regk_ser_rw_tr_baud_div_default = 0x00000000,
301 regk_ser_rw_tr_ctrl_default = 0x00008000,
302 regk_ser_rw_tr_dma_en_default = 0x00000000,
303 regk_ser_rw_xoff_default = 0x00000000,
304 regk_ser_space = 0x00000003,
305 regk_ser_stop = 0x00000000,
306 regk_ser_yes = 0x00000001
307};
308#endif /* __ser_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/sser_defs.h b/include/asm-cris/arch-v32/hwregs/sser_defs.h
new file mode 100644
index 000000000000..8d1dab218b91
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/sser_defs.h
@@ -0,0 +1,331 @@
1#ifndef __sser_defs_h
2#define __sser_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/syncser/rtl/sser_regs.r
7 * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp
8 * last modfied: Mon Apr 11 16:09:48 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r
11 * id: $Id: sser_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope sser */
86
87/* Register rw_cfg, scope sser, type rw */
88typedef struct {
89 unsigned int clk_div : 16;
90 unsigned int base_freq : 3;
91 unsigned int gate_clk : 1;
92 unsigned int clkgate_ctrl : 1;
93 unsigned int clkgate_in : 1;
94 unsigned int clk_dir : 1;
95 unsigned int clk_od_mode : 1;
96 unsigned int out_clk_pol : 1;
97 unsigned int out_clk_src : 2;
98 unsigned int clk_in_sel : 1;
99 unsigned int hold_pol : 1;
100 unsigned int prepare : 1;
101 unsigned int en : 1;
102 unsigned int dummy1 : 1;
103} reg_sser_rw_cfg;
104#define REG_RD_ADDR_sser_rw_cfg 0
105#define REG_WR_ADDR_sser_rw_cfg 0
106
107/* Register rw_frm_cfg, scope sser, type rw */
108typedef struct {
109 unsigned int wordrate : 10;
110 unsigned int rec_delay : 3;
111 unsigned int tr_delay : 3;
112 unsigned int early_wend : 1;
113 unsigned int level : 2;
114 unsigned int type : 1;
115 unsigned int clk_pol : 1;
116 unsigned int fr_in_rxclk : 1;
117 unsigned int clk_src : 1;
118 unsigned int out_off : 1;
119 unsigned int out_on : 1;
120 unsigned int frame_pin_dir : 1;
121 unsigned int frame_pin_use : 2;
122 unsigned int status_pin_dir : 1;
123 unsigned int status_pin_use : 2;
124 unsigned int dummy1 : 1;
125} reg_sser_rw_frm_cfg;
126#define REG_RD_ADDR_sser_rw_frm_cfg 4
127#define REG_WR_ADDR_sser_rw_frm_cfg 4
128
129/* Register rw_tr_cfg, scope sser, type rw */
130typedef struct {
131 unsigned int tr_en : 1;
132 unsigned int stop : 1;
133 unsigned int urun_stop : 1;
134 unsigned int eop_stop : 1;
135 unsigned int sample_size : 6;
136 unsigned int sh_dir : 1;
137 unsigned int clk_pol : 1;
138 unsigned int clk_src : 1;
139 unsigned int use_dma : 1;
140 unsigned int mode : 2;
141 unsigned int frm_src : 1;
142 unsigned int use60958 : 1;
143 unsigned int iec60958_ckdiv : 2;
144 unsigned int rate_ctrl : 1;
145 unsigned int use_md : 1;
146 unsigned int dual_i2s : 1;
147 unsigned int data_pin_use : 2;
148 unsigned int od_mode : 1;
149 unsigned int bulk_wspace : 2;
150 unsigned int dummy1 : 4;
151} reg_sser_rw_tr_cfg;
152#define REG_RD_ADDR_sser_rw_tr_cfg 8
153#define REG_WR_ADDR_sser_rw_tr_cfg 8
154
155/* Register rw_rec_cfg, scope sser, type rw */
156typedef struct {
157 unsigned int rec_en : 1;
158 unsigned int force_eop : 1;
159 unsigned int stop : 1;
160 unsigned int orun_stop : 1;
161 unsigned int eop_stop : 1;
162 unsigned int sample_size : 6;
163 unsigned int sh_dir : 1;
164 unsigned int clk_pol : 1;
165 unsigned int clk_src : 1;
166 unsigned int use_dma : 1;
167 unsigned int mode : 2;
168 unsigned int frm_src : 2;
169 unsigned int use60958 : 1;
170 unsigned int iec60958_ui_len : 5;
171 unsigned int slave2_en : 1;
172 unsigned int slave3_en : 1;
173 unsigned int fifo_thr : 2;
174 unsigned int dummy1 : 3;
175} reg_sser_rw_rec_cfg;
176#define REG_RD_ADDR_sser_rw_rec_cfg 12
177#define REG_WR_ADDR_sser_rw_rec_cfg 12
178
179/* Register rw_tr_data, scope sser, type rw */
180typedef struct {
181 unsigned int data : 16;
182 unsigned int md : 1;
183 unsigned int dummy1 : 15;
184} reg_sser_rw_tr_data;
185#define REG_RD_ADDR_sser_rw_tr_data 16
186#define REG_WR_ADDR_sser_rw_tr_data 16
187
188/* Register r_rec_data, scope sser, type r */
189typedef struct {
190 unsigned int data : 16;
191 unsigned int md : 1;
192 unsigned int ext_clk : 1;
193 unsigned int status_in : 1;
194 unsigned int frame_in : 1;
195 unsigned int din : 1;
196 unsigned int data_in : 1;
197 unsigned int clk_in : 1;
198 unsigned int dummy1 : 9;
199} reg_sser_r_rec_data;
200#define REG_RD_ADDR_sser_r_rec_data 20
201
202/* Register rw_extra, scope sser, type rw */
203typedef struct {
204 unsigned int clkoff_cycles : 20;
205 unsigned int clkoff_en : 1;
206 unsigned int clkon_en : 1;
207 unsigned int dout_delay : 5;
208 unsigned int dummy1 : 5;
209} reg_sser_rw_extra;
210#define REG_RD_ADDR_sser_rw_extra 24
211#define REG_WR_ADDR_sser_rw_extra 24
212
213/* Register rw_intr_mask, scope sser, type rw */
214typedef struct {
215 unsigned int trdy : 1;
216 unsigned int rdav : 1;
217 unsigned int tidle : 1;
218 unsigned int rstop : 1;
219 unsigned int urun : 1;
220 unsigned int orun : 1;
221 unsigned int md_rec : 1;
222 unsigned int md_sent : 1;
223 unsigned int r958err : 1;
224 unsigned int dummy1 : 23;
225} reg_sser_rw_intr_mask;
226#define REG_RD_ADDR_sser_rw_intr_mask 28
227#define REG_WR_ADDR_sser_rw_intr_mask 28
228
229/* Register rw_ack_intr, scope sser, type rw */
230typedef struct {
231 unsigned int trdy : 1;
232 unsigned int rdav : 1;
233 unsigned int tidle : 1;
234 unsigned int rstop : 1;
235 unsigned int urun : 1;
236 unsigned int orun : 1;
237 unsigned int md_rec : 1;
238 unsigned int md_sent : 1;
239 unsigned int r958err : 1;
240 unsigned int dummy1 : 23;
241} reg_sser_rw_ack_intr;
242#define REG_RD_ADDR_sser_rw_ack_intr 32
243#define REG_WR_ADDR_sser_rw_ack_intr 32
244
245/* Register r_intr, scope sser, type r */
246typedef struct {
247 unsigned int trdy : 1;
248 unsigned int rdav : 1;
249 unsigned int tidle : 1;
250 unsigned int rstop : 1;
251 unsigned int urun : 1;
252 unsigned int orun : 1;
253 unsigned int md_rec : 1;
254 unsigned int md_sent : 1;
255 unsigned int r958err : 1;
256 unsigned int dummy1 : 23;
257} reg_sser_r_intr;
258#define REG_RD_ADDR_sser_r_intr 36
259
260/* Register r_masked_intr, scope sser, type r */
261typedef struct {
262 unsigned int trdy : 1;
263 unsigned int rdav : 1;
264 unsigned int tidle : 1;
265 unsigned int rstop : 1;
266 unsigned int urun : 1;
267 unsigned int orun : 1;
268 unsigned int md_rec : 1;
269 unsigned int md_sent : 1;
270 unsigned int r958err : 1;
271 unsigned int dummy1 : 23;
272} reg_sser_r_masked_intr;
273#define REG_RD_ADDR_sser_r_masked_intr 40
274
275
276/* Constants */
277enum {
278 regk_sser_both = 0x00000002,
279 regk_sser_bulk = 0x00000001,
280 regk_sser_clk100 = 0x00000000,
281 regk_sser_clk_in = 0x00000000,
282 regk_sser_const0 = 0x00000003,
283 regk_sser_dout = 0x00000002,
284 regk_sser_edge = 0x00000000,
285 regk_sser_ext = 0x00000001,
286 regk_sser_ext_clk = 0x00000001,
287 regk_sser_f100 = 0x00000000,
288 regk_sser_f29_493 = 0x00000004,
289 regk_sser_f32 = 0x00000005,
290 regk_sser_f32_768 = 0x00000006,
291 regk_sser_frm = 0x00000003,
292 regk_sser_gio0 = 0x00000000,
293 regk_sser_gio1 = 0x00000001,
294 regk_sser_hispeed = 0x00000001,
295 regk_sser_hold = 0x00000002,
296 regk_sser_in = 0x00000000,
297 regk_sser_inf = 0x00000003,
298 regk_sser_intern = 0x00000000,
299 regk_sser_intern_clk = 0x00000001,
300 regk_sser_intern_tb = 0x00000000,
301 regk_sser_iso = 0x00000000,
302 regk_sser_level = 0x00000001,
303 regk_sser_lospeed = 0x00000000,
304 regk_sser_lsbfirst = 0x00000000,
305 regk_sser_msbfirst = 0x00000001,
306 regk_sser_neg = 0x00000001,
307 regk_sser_neg_lo = 0x00000000,
308 regk_sser_no = 0x00000000,
309 regk_sser_no_clk = 0x00000007,
310 regk_sser_nojitter = 0x00000002,
311 regk_sser_out = 0x00000001,
312 regk_sser_pos = 0x00000000,
313 regk_sser_pos_hi = 0x00000001,
314 regk_sser_rec = 0x00000000,
315 regk_sser_rw_cfg_default = 0x00000000,
316 regk_sser_rw_extra_default = 0x00000000,
317 regk_sser_rw_frm_cfg_default = 0x00000000,
318 regk_sser_rw_intr_mask_default = 0x00000000,
319 regk_sser_rw_rec_cfg_default = 0x00000000,
320 regk_sser_rw_tr_cfg_default = 0x01800000,
321 regk_sser_rw_tr_data_default = 0x00000000,
322 regk_sser_thr16 = 0x00000001,
323 regk_sser_thr32 = 0x00000002,
324 regk_sser_thr8 = 0x00000000,
325 regk_sser_tr = 0x00000001,
326 regk_sser_ts_out = 0x00000003,
327 regk_sser_tx_bulk = 0x00000002,
328 regk_sser_wiresave = 0x00000002,
329 regk_sser_yes = 0x00000001
330};
331#endif /* __sser_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/strcop.h b/include/asm-cris/arch-v32/hwregs/strcop.h
new file mode 100644
index 000000000000..35131ba466f3
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/strcop.h
@@ -0,0 +1,57 @@
1// $Id: strcop.h,v 1.3 2003/10/22 13:27:12 henriken Exp $
2
3// Streamcop meta-data configuration structs
4
5struct strcop_meta_out {
6 unsigned char csumsel : 3;
7 unsigned char ciphsel : 3;
8 unsigned char ciphconf : 2;
9 unsigned char hashsel : 3;
10 unsigned char hashconf : 1;
11 unsigned char hashmode : 1;
12 unsigned char decrypt : 1;
13 unsigned char dlkey : 1;
14 unsigned char cbcmode : 1;
15};
16
17struct strcop_meta_in {
18 unsigned char dmasel : 3;
19 unsigned char sync : 1;
20 unsigned char res1 : 5;
21 unsigned char res2;
22};
23
24// Source definitions
25
26enum {
27 src_none = 0,
28 src_dma = 1,
29 src_des = 2,
30 src_sha1 = 3,
31 src_csum = 4,
32 src_aes = 5,
33 src_md5 = 6,
34 src_res = 7
35};
36
37// Cipher definitions
38
39enum {
40 ciph_des = 0,
41 ciph_3des = 1,
42 ciph_aes = 2
43};
44
45// Hash definitions
46
47enum {
48 hash_sha1 = 0,
49 hash_md5 = 1
50};
51
52enum {
53 hash_noiv = 0,
54 hash_iv = 1
55};
56
57
diff --git a/include/asm-cris/arch-v32/hwregs/strcop_defs.h b/include/asm-cris/arch-v32/hwregs/strcop_defs.h
new file mode 100644
index 000000000000..bd145a49b2c4
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/strcop_defs.h
@@ -0,0 +1,109 @@
1#ifndef __strcop_defs_h
2#define __strcop_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/strcop/rtl/strcop_regs.r
7 * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp
8 * last modfied: Mon Apr 11 16:09:38 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strcop_defs.h ../../inst/strcop/rtl/strcop_regs.r
11 * id: $Id: strcop_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope strcop */
86
87/* Register rw_cfg, scope strcop, type rw */
88typedef struct {
89 unsigned int td3 : 1;
90 unsigned int td2 : 1;
91 unsigned int td1 : 1;
92 unsigned int ipend : 1;
93 unsigned int ignore_sync : 1;
94 unsigned int en : 1;
95 unsigned int dummy1 : 26;
96} reg_strcop_rw_cfg;
97#define REG_RD_ADDR_strcop_rw_cfg 0
98#define REG_WR_ADDR_strcop_rw_cfg 0
99
100
101/* Constants */
102enum {
103 regk_strcop_big = 0x00000001,
104 regk_strcop_d = 0x00000001,
105 regk_strcop_e = 0x00000000,
106 regk_strcop_little = 0x00000000,
107 regk_strcop_rw_cfg_default = 0x00000002
108};
109#endif /* __strcop_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/hwregs/strmux_defs.h
new file mode 100644
index 000000000000..67474855c499
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/strmux_defs.h
@@ -0,0 +1,127 @@
1#ifndef __strmux_defs_h
2#define __strmux_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/strmux/rtl/guinness/strmux_regs.r
7 * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
8 * last modfied: Mon Apr 11 16:09:43 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r
11 * id: $Id: strmux_defs.h,v 1.5 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope strmux */
86
87/* Register rw_cfg, scope strmux, type rw */
88typedef struct {
89 unsigned int dma0 : 3;
90 unsigned int dma1 : 3;
91 unsigned int dma2 : 3;
92 unsigned int dma3 : 3;
93 unsigned int dma4 : 3;
94 unsigned int dma5 : 3;
95 unsigned int dma6 : 3;
96 unsigned int dma7 : 3;
97 unsigned int dma8 : 3;
98 unsigned int dma9 : 3;
99 unsigned int dummy1 : 2;
100} reg_strmux_rw_cfg;
101#define REG_RD_ADDR_strmux_rw_cfg 0
102#define REG_WR_ADDR_strmux_rw_cfg 0
103
104
105/* Constants */
106enum {
107 regk_strmux_ata = 0x00000003,
108 regk_strmux_eth0 = 0x00000001,
109 regk_strmux_eth1 = 0x00000004,
110 regk_strmux_ext0 = 0x00000001,
111 regk_strmux_ext1 = 0x00000001,
112 regk_strmux_ext2 = 0x00000001,
113 regk_strmux_ext3 = 0x00000001,
114 regk_strmux_iop0 = 0x00000002,
115 regk_strmux_iop1 = 0x00000001,
116 regk_strmux_off = 0x00000000,
117 regk_strmux_p21 = 0x00000004,
118 regk_strmux_rw_cfg_default = 0x00000000,
119 regk_strmux_ser0 = 0x00000002,
120 regk_strmux_ser1 = 0x00000002,
121 regk_strmux_ser2 = 0x00000004,
122 regk_strmux_ser3 = 0x00000003,
123 regk_strmux_sser0 = 0x00000003,
124 regk_strmux_sser1 = 0x00000003,
125 regk_strmux_strcop = 0x00000002
126};
127#endif /* __strmux_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/supp_reg.h b/include/asm-cris/arch-v32/hwregs/supp_reg.h
new file mode 100644
index 000000000000..ffe49625ae36
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/supp_reg.h
@@ -0,0 +1,78 @@
1#ifndef __SUPP_REG_H__
2#define __SUPP_REG_H__
3
4/* Macros for reading and writing support/special registers. */
5
6#ifndef STRINGIFYFY
7#define STRINGIFYFY(i) #i
8#endif
9
10#ifndef STRINGIFY
11#define STRINGIFY(i) STRINGIFYFY(i)
12#endif
13
14#define SPEC_REG_BZ "BZ"
15#define SPEC_REG_VR "VR"
16#define SPEC_REG_PID "PID"
17#define SPEC_REG_SRS "SRS"
18#define SPEC_REG_WZ "WZ"
19#define SPEC_REG_EXS "EXS"
20#define SPEC_REG_EDA "EDA"
21#define SPEC_REG_MOF "MOF"
22#define SPEC_REG_DZ "DZ"
23#define SPEC_REG_EBP "EBP"
24#define SPEC_REG_ERP "ERP"
25#define SPEC_REG_SRP "SRP"
26#define SPEC_REG_NRP "NRP"
27#define SPEC_REG_CCS "CCS"
28#define SPEC_REG_USP "USP"
29#define SPEC_REG_SPC "SPC"
30
31#define RW_MM_CFG 0
32#define RW_MM_KBASE_LO 1
33#define RW_MM_KBASE_HI 2
34#define RW_MM_CAUSE 3
35#define RW_MM_TLB_SEL 4
36#define RW_MM_TLB_LO 5
37#define RW_MM_TLB_HI 6
38#define RW_MM_TLB_PGD 7
39
40#define BANK_GC 0
41#define BANK_IM 1
42#define BANK_DM 2
43#define BANK_BP 3
44
45#define RW_GC_CFG 0
46#define RW_GC_CCS 1
47#define RW_GC_SRS 2
48#define RW_GC_NRP 3
49#define RW_GC_EXS 4
50#define RW_GC_R0 8
51#define RW_GC_R1 9
52
53#define SPEC_REG_WR(r,v) \
54__asm__ __volatile__ ("move %0, $" r : : "r" (v));
55
56#define SPEC_REG_RD(r,v) \
57__asm__ __volatile__ ("move $" r ",%0" : "=r" (v));
58
59#define NOP() \
60 __asm__ __volatile__ ("nop");
61
62#define SUPP_BANK_SEL(b) \
63 SPEC_REG_WR(SPEC_REG_SRS,b); \
64 NOP(); \
65 NOP(); \
66 NOP();
67
68#define SUPP_REG_WR(r,v) \
69__asm__ __volatile__ ("move %0, $S" STRINGIFYFY(r) "\n\t" \
70 "nop\n\t" \
71 "nop\n\t" \
72 "nop\n\t" \
73 : : "r" (v));
74
75#define SUPP_REG_RD(r,v) \
76__asm__ __volatile__ ("move $S" STRINGIFYFY(r) ",%0" : "=r" (v));
77
78#endif /* __SUPP_REG_H__ */
diff --git a/include/asm-cris/arch-v32/hwregs/timer_defs.h b/include/asm-cris/arch-v32/hwregs/timer_defs.h
new file mode 100644
index 000000000000..20c8c89ec076
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/timer_defs.h
@@ -0,0 +1,266 @@
1#ifndef __timer_defs_h
2#define __timer_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/timer/rtl/timer_regs.r
7 * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
8 * last modfied: Mon Apr 11 16:09:53 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r
11 * id: $Id: timer_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope timer */
86
87/* Register rw_tmr0_div, scope timer, type rw */
88typedef unsigned int reg_timer_rw_tmr0_div;
89#define REG_RD_ADDR_timer_rw_tmr0_div 0
90#define REG_WR_ADDR_timer_rw_tmr0_div 0
91
92/* Register r_tmr0_data, scope timer, type r */
93typedef unsigned int reg_timer_r_tmr0_data;
94#define REG_RD_ADDR_timer_r_tmr0_data 4
95
96/* Register rw_tmr0_ctrl, scope timer, type rw */
97typedef struct {
98 unsigned int op : 2;
99 unsigned int freq : 3;
100 unsigned int dummy1 : 27;
101} reg_timer_rw_tmr0_ctrl;
102#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
103#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
104
105/* Register rw_tmr1_div, scope timer, type rw */
106typedef unsigned int reg_timer_rw_tmr1_div;
107#define REG_RD_ADDR_timer_rw_tmr1_div 16
108#define REG_WR_ADDR_timer_rw_tmr1_div 16
109
110/* Register r_tmr1_data, scope timer, type r */
111typedef unsigned int reg_timer_r_tmr1_data;
112#define REG_RD_ADDR_timer_r_tmr1_data 20
113
114/* Register rw_tmr1_ctrl, scope timer, type rw */
115typedef struct {
116 unsigned int op : 2;
117 unsigned int freq : 3;
118 unsigned int dummy1 : 27;
119} reg_timer_rw_tmr1_ctrl;
120#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
121#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
122
123/* Register rs_cnt_data, scope timer, type rs */
124typedef struct {
125 unsigned int tmr : 24;
126 unsigned int cnt : 8;
127} reg_timer_rs_cnt_data;
128#define REG_RD_ADDR_timer_rs_cnt_data 32
129
130/* Register r_cnt_data, scope timer, type r */
131typedef struct {
132 unsigned int tmr : 24;
133 unsigned int cnt : 8;
134} reg_timer_r_cnt_data;
135#define REG_RD_ADDR_timer_r_cnt_data 36
136
137/* Register rw_cnt_cfg, scope timer, type rw */
138typedef struct {
139 unsigned int clk : 2;
140 unsigned int dummy1 : 30;
141} reg_timer_rw_cnt_cfg;
142#define REG_RD_ADDR_timer_rw_cnt_cfg 40
143#define REG_WR_ADDR_timer_rw_cnt_cfg 40
144
145/* Register rw_trig, scope timer, type rw */
146typedef unsigned int reg_timer_rw_trig;
147#define REG_RD_ADDR_timer_rw_trig 48
148#define REG_WR_ADDR_timer_rw_trig 48
149
150/* Register rw_trig_cfg, scope timer, type rw */
151typedef struct {
152 unsigned int tmr : 2;
153 unsigned int dummy1 : 30;
154} reg_timer_rw_trig_cfg;
155#define REG_RD_ADDR_timer_rw_trig_cfg 52
156#define REG_WR_ADDR_timer_rw_trig_cfg 52
157
158/* Register r_time, scope timer, type r */
159typedef unsigned int reg_timer_r_time;
160#define REG_RD_ADDR_timer_r_time 56
161
162/* Register rw_out, scope timer, type rw */
163typedef struct {
164 unsigned int tmr : 2;
165 unsigned int dummy1 : 30;
166} reg_timer_rw_out;
167#define REG_RD_ADDR_timer_rw_out 60
168#define REG_WR_ADDR_timer_rw_out 60
169
170/* Register rw_wd_ctrl, scope timer, type rw */
171typedef struct {
172 unsigned int cnt : 8;
173 unsigned int cmd : 1;
174 unsigned int key : 7;
175 unsigned int dummy1 : 16;
176} reg_timer_rw_wd_ctrl;
177#define REG_RD_ADDR_timer_rw_wd_ctrl 64
178#define REG_WR_ADDR_timer_rw_wd_ctrl 64
179
180/* Register r_wd_stat, scope timer, type r */
181typedef struct {
182 unsigned int cnt : 8;
183 unsigned int cmd : 1;
184 unsigned int dummy1 : 23;
185} reg_timer_r_wd_stat;
186#define REG_RD_ADDR_timer_r_wd_stat 68
187
188/* Register rw_intr_mask, scope timer, type rw */
189typedef struct {
190 unsigned int tmr0 : 1;
191 unsigned int tmr1 : 1;
192 unsigned int cnt : 1;
193 unsigned int trig : 1;
194 unsigned int dummy1 : 28;
195} reg_timer_rw_intr_mask;
196#define REG_RD_ADDR_timer_rw_intr_mask 72
197#define REG_WR_ADDR_timer_rw_intr_mask 72
198
199/* Register rw_ack_intr, scope timer, type rw */
200typedef struct {
201 unsigned int tmr0 : 1;
202 unsigned int tmr1 : 1;
203 unsigned int cnt : 1;
204 unsigned int trig : 1;
205 unsigned int dummy1 : 28;
206} reg_timer_rw_ack_intr;
207#define REG_RD_ADDR_timer_rw_ack_intr 76
208#define REG_WR_ADDR_timer_rw_ack_intr 76
209
210/* Register r_intr, scope timer, type r */
211typedef struct {
212 unsigned int tmr0 : 1;
213 unsigned int tmr1 : 1;
214 unsigned int cnt : 1;
215 unsigned int trig : 1;
216 unsigned int dummy1 : 28;
217} reg_timer_r_intr;
218#define REG_RD_ADDR_timer_r_intr 80
219
220/* Register r_masked_intr, scope timer, type r */
221typedef struct {
222 unsigned int tmr0 : 1;
223 unsigned int tmr1 : 1;
224 unsigned int cnt : 1;
225 unsigned int trig : 1;
226 unsigned int dummy1 : 28;
227} reg_timer_r_masked_intr;
228#define REG_RD_ADDR_timer_r_masked_intr 84
229
230/* Register rw_test, scope timer, type rw */
231typedef struct {
232 unsigned int dis : 1;
233 unsigned int en : 1;
234 unsigned int dummy1 : 30;
235} reg_timer_rw_test;
236#define REG_RD_ADDR_timer_rw_test 88
237#define REG_WR_ADDR_timer_rw_test 88
238
239
240/* Constants */
241enum {
242 regk_timer_ext = 0x00000001,
243 regk_timer_f100 = 0x00000007,
244 regk_timer_f29_493 = 0x00000004,
245 regk_timer_f32 = 0x00000005,
246 regk_timer_f32_768 = 0x00000006,
247 regk_timer_hold = 0x00000001,
248 regk_timer_ld = 0x00000000,
249 regk_timer_no = 0x00000000,
250 regk_timer_off = 0x00000000,
251 regk_timer_run = 0x00000002,
252 regk_timer_rw_cnt_cfg_default = 0x00000000,
253 regk_timer_rw_intr_mask_default = 0x00000000,
254 regk_timer_rw_out_default = 0x00000000,
255 regk_timer_rw_test_default = 0x00000000,
256 regk_timer_rw_tmr0_ctrl_default = 0x00000000,
257 regk_timer_rw_tmr1_ctrl_default = 0x00000000,
258 regk_timer_rw_trig_cfg_default = 0x00000000,
259 regk_timer_start = 0x00000001,
260 regk_timer_stop = 0x00000000,
261 regk_timer_time = 0x00000001,
262 regk_timer_tmr0 = 0x00000002,
263 regk_timer_tmr1 = 0x00000003,
264 regk_timer_yes = 0x00000001
265};
266#endif /* __timer_defs_h */
diff --git a/include/asm-cris/arch-v32/ide.h b/include/asm-cris/arch-v32/ide.h
new file mode 100644
index 000000000000..24f5604f566a
--- /dev/null
+++ b/include/asm-cris/arch-v32/ide.h
@@ -0,0 +1,61 @@
1/*
2 * linux/include/asm-cris/ide.h
3 *
4 * Copyright (C) 2000-2004 Axis Communications AB
5 *
6 * Authors: Bjorn Wesen, Mikael Starvik
7 *
8 */
9
10/*
11 * This file contains the ETRAX FS specific IDE code.
12 */
13
14#ifndef __ASMCRIS_IDE_H
15#define __ASMCRIS_IDE_H
16
17#ifdef __KERNEL__
18
19#include <asm/arch/hwregs/intr_vect.h>
20#include <asm/arch/hwregs/ata_defs.h>
21#include <asm/io.h>
22#include <asm-generic/ide_iops.h>
23
24
25/* ETRAX FS can support 4 IDE busses on the same pins (serialized) */
26
27#define MAX_HWIFS 4
28
29extern __inline__ int ide_default_irq(unsigned long base)
30{
31 /* all IDE busses share the same IRQ,
32 * this has the side-effect that ide-probe.c will cluster our 4 interfaces
33 * together in a hwgroup, and will serialize accesses. this is good, because
34 * we can't access more than one interface at the same time on ETRAX100.
35 */
36 return ATA_INTR_VECT;
37}
38
39extern __inline__ unsigned long ide_default_io_base(int index)
40{
41 reg_ata_rw_ctrl2 ctrl2 = {.sel = index};
42 /* we have no real I/O base address per interface, since all go through the
43 * same register. but in a bitfield in that register, we have the i/f number.
44 * so we can use the io_base to remember that bitfield.
45 */
46 ctrl2.sel = index;
47
48 return REG_TYPE_CONV(unsigned long, reg_ata_rw_ctrl2, ctrl2);
49}
50
51/* some configuration options we don't need */
52
53#undef SUPPORT_VLB_SYNC
54#define SUPPORT_VLB_SYNC 0
55
56#define IDE_ARCH_ACK_INTR
57#define ide_ack_intr(hwif) (hwif)->hw.ack_intr(hwif)
58
59#endif /* __KERNEL__ */
60
61#endif /* __ASMCRIS_IDE_H */
diff --git a/include/asm-cris/arch-v32/intmem.h b/include/asm-cris/arch-v32/intmem.h
new file mode 100644
index 000000000000..c0ada33bf90f
--- /dev/null
+++ b/include/asm-cris/arch-v32/intmem.h
@@ -0,0 +1,9 @@
1#ifndef _ASM_CRIS_INTMEM_H
2#define _ASM_CRIS_INTMEM_H
3
4void* crisv32_intmem_alloc(unsigned size, unsigned align);
5void crisv32_intmem_free(void* addr);
6void* crisv32_intmem_phys_to_virt(unsigned long addr);
7unsigned long crisv32_intmem_virt_to_phys(void *addr);
8
9#endif /* _ASM_CRIS_ARCH_INTMEM_H */
diff --git a/include/asm-cris/arch-v32/io.h b/include/asm-cris/arch-v32/io.h
new file mode 100644
index 000000000000..4c80263ec634
--- /dev/null
+++ b/include/asm-cris/arch-v32/io.h
@@ -0,0 +1,98 @@
1#ifndef _ASM_ARCH_CRIS_IO_H
2#define _ASM_ARCH_CRIS_IO_H
3
4#include <asm/arch/hwregs/reg_map.h>
5#include <asm/arch/hwregs/reg_rdwr.h>
6#include <asm/arch/hwregs/gio_defs.h>
7#include <linux/config.h>
8
9enum crisv32_io_dir
10{
11 crisv32_io_dir_in = 0,
12 crisv32_io_dir_out = 1
13};
14
15struct crisv32_ioport
16{
17 unsigned long* oe;
18 unsigned long* data;
19 unsigned long* data_in;
20 unsigned int pin_count;
21};
22
23struct crisv32_iopin
24{
25 struct crisv32_ioport* port;
26 int bit;
27};
28
29extern struct crisv32_ioport crisv32_ioports[];
30
31extern struct crisv32_iopin crisv32_led1_green;
32extern struct crisv32_iopin crisv32_led1_red;
33extern struct crisv32_iopin crisv32_led2_green;
34extern struct crisv32_iopin crisv32_led2_red;
35extern struct crisv32_iopin crisv32_led3_green;
36extern struct crisv32_iopin crisv32_led3_red;
37
38extern inline void crisv32_io_set(struct crisv32_iopin* iopin,
39 int val)
40{
41 if (val)
42 *iopin->port->data |= iopin->bit;
43 else
44 *iopin->port->data &= ~iopin->bit;
45}
46
47extern inline void crisv32_io_set_dir(struct crisv32_iopin* iopin,
48 enum crisv32_io_dir dir)
49{
50 if (dir == crisv32_io_dir_in)
51 *iopin->port->oe &= ~iopin->bit;
52 else
53 *iopin->port->oe |= iopin->bit;
54}
55
56extern inline int crisv32_io_rd(struct crisv32_iopin* iopin)
57{
58 return ((*iopin->port->data_in & iopin->bit) ? 1 : 0);
59}
60
61int crisv32_io_get(struct crisv32_iopin* iopin,
62 unsigned int port, unsigned int pin);
63int crisv32_io_get_name(struct crisv32_iopin* iopin,
64 char* name);
65
66#define LED_OFF 0x00
67#define LED_GREEN 0x01
68#define LED_RED 0x02
69#define LED_ORANGE (LED_GREEN | LED_RED)
70
71#define LED_NETWORK_SET(x) \
72 do { \
73 LED_NETWORK_SET_G((x) & LED_GREEN); \
74 LED_NETWORK_SET_R((x) & LED_RED); \
75 } while (0)
76#define LED_ACTIVE_SET(x) \
77 do { \
78 LED_ACTIVE_SET_G((x) & LED_GREEN); \
79 LED_ACTIVE_SET_R((x) & LED_RED); \
80 } while (0)
81
82#define LED_NETWORK_SET_G(x) \
83 crisv32_io_set(&crisv32_led1_green, !(x));
84#define LED_NETWORK_SET_R(x) \
85 crisv32_io_set(&crisv32_led1_red, !(x));
86#define LED_ACTIVE_SET_G(x) \
87 crisv32_io_set(&crisv32_led2_green, !(x));
88#define LED_ACTIVE_SET_R(x) \
89 crisv32_io_set(&crisv32_led2_red, !(x));
90#define LED_DISK_WRITE(x) \
91 do{\
92 crisv32_io_set(&crisv32_led3_green, !(x)); \
93 crisv32_io_set(&crisv32_led3_red, !(x)); \
94 }while(0)
95#define LED_DISK_READ(x) \
96 crisv32_io_set(&crisv32_led3_green, !(x));
97
98#endif
diff --git a/include/asm-cris/arch-v32/irq.h b/include/asm-cris/arch-v32/irq.h
new file mode 100644
index 000000000000..d35aa8174c2f
--- /dev/null
+++ b/include/asm-cris/arch-v32/irq.h
@@ -0,0 +1,120 @@
1#ifndef _ASM_ARCH_IRQ_H
2#define _ASM_ARCH_IRQ_H
3
4#include <linux/config.h>
5#include "hwregs/intr_vect.h"
6
7/* Number of non-cpu interrupts. */
8#define NR_IRQS 0x50 /* Exceptions + IRQs */
9#define NR_REAL_IRQS 0x20 /* IRQs */
10#define FIRST_IRQ 0x31 /* Exception number for first IRQ */
11
12#ifndef __ASSEMBLY__
13/* Global IRQ vector. */
14typedef void (*irqvectptr)(void);
15
16struct etrax_interrupt_vector {
17 irqvectptr v[256];
18};
19
20extern struct etrax_interrupt_vector *etrax_irv; /* head.S */
21
22void mask_irq(int irq);
23void unmask_irq(int irq);
24
25void set_exception_vector(int n, irqvectptr addr);
26
27/* Save registers so that they match pt_regs. */
28#define SAVE_ALL \
29 "subq 12,$sp\n\t" \
30 "move $erp,[$sp]\n\t" \
31 "subq 4,$sp\n\t" \
32 "move $srp,[$sp]\n\t" \
33 "subq 4,$sp\n\t" \
34 "move $ccs,[$sp]\n\t" \
35 "subq 4,$sp\n\t" \
36 "move $spc,[$sp]\n\t" \
37 "subq 4,$sp\n\t" \
38 "move $mof,[$sp]\n\t" \
39 "subq 4,$sp\n\t" \
40 "move $srs,[$sp]\n\t" \
41 "subq 4,$sp\n\t" \
42 "move.d $acr,[$sp]\n\t" \
43 "subq 14*4,$sp\n\t" \
44 "movem $r13,[$sp]\n\t" \
45 "subq 4,$sp\n\t" \
46 "move.d $r10,[$sp]\n"
47
48#define STR2(x) #x
49#define STR(x) STR2(x)
50
51#define IRQ_NAME2(nr) nr##_interrupt(void)
52#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
53
54/*
55 * The reason for setting the S-bit when debugging the kernel is that we want
56 * hardware breakpoints to remain active while we are in an exception handler.
57 * Note that we cannot simply copy S1, since we may come here from user-space,
58 * or any context where the S-bit wasn't set.
59 */
60#ifdef CONFIG_ETRAX_KGDB
61#define KGDB_FIXUP \
62 "move $ccs, $r10\n\t" \
63 "or.d (1<<9), $r10\n\t" \
64 "move $r10, $ccs\n\t"
65#else
66#define KGDB_FIXUP ""
67#endif
68
69/*
70 * Make sure the causing IRQ is blocked, then call do_IRQ. After that, unblock
71 * and jump to ret_from_intr which is found in entry.S.
72 *
73 * The reason for blocking the IRQ is to allow an sti() before the handler,
74 * which will acknowledge the interrupt, is run. The actual blocking is made
75 * by crisv32_do_IRQ.
76 */
77#define BUILD_IRQ(nr, mask) \
78void IRQ_NAME(nr); \
79__asm__ ( \
80 ".text\n\t" \
81 "IRQ" #nr "_interrupt:\n\t" \
82 SAVE_ALL \
83 KGDB_FIXUP \
84 "move.d "#nr",$r10\n\t" \
85 "move.d $sp,$r12\n\t" \
86 "jsr crisv32_do_IRQ\n\t" \
87 "moveq 1, $r11\n\t" \
88 "jump ret_from_intr\n\t" \
89 "nop\n\t");
90/*
91 * This is subtle. The timer interrupt is crucial and it should not be disabled
92 * for too long. However, if it had been a normal interrupt as per BUILD_IRQ, it
93 * would have been BLOCK'ed, and then softirq's are run before we return here to
94 * UNBLOCK. If the softirq's take too much time to run, the timer irq won't run
95 * and the watchdog will kill us.
96 *
97 * Furthermore, if a lot of other irq's occur before we return here, the
98 * multiple_irq handler is run and it prioritizes the timer interrupt. However
99 * if we had BLOCK'edit here, we would not get the multiple_irq at all.
100 *
101 * The non-blocking here is based on the knowledge that the timer interrupt is
102 * registred as a fast interrupt (SA_INTERRUPT) so that we _know_ there will not
103 * be an sti() before the timer irq handler is run to acknowledge the interrupt.
104 */
105#define BUILD_TIMER_IRQ(nr, mask) \
106void IRQ_NAME(nr); \
107__asm__ ( \
108 ".text\n\t" \
109 "IRQ" #nr "_interrupt:\n\t" \
110 SAVE_ALL \
111 KGDB_FIXUP \
112 "move.d "#nr",$r10\n\t" \
113 "move.d $sp,$r12\n\t" \
114 "jsr crisv32_do_IRQ\n\t" \
115 "moveq 0,$r11\n\t" \
116 "jump ret_from_intr\n\t" \
117 "nop\n\t");
118
119#endif /* __ASSEMBLY__ */
120#endif /* _ASM_ARCH_IRQ_H */
diff --git a/include/asm-cris/arch-v32/juliette.h b/include/asm-cris/arch-v32/juliette.h
new file mode 100644
index 000000000000..f1f81725e57b
--- /dev/null
+++ b/include/asm-cris/arch-v32/juliette.h
@@ -0,0 +1,326 @@
1#ifndef _ASM_JULIETTE_H
2#define _ASM_JULIETTE_H
3
4/* juliette _IOC_TYPE, bits 8 to 15 in ioctl cmd */
5
6#define JULIOCTYPE 42
7
8/* supported ioctl _IOC_NR's */
9
10#define JULSTARTDMA 0x1 /* start a picture asynchronously */
11
12/* set parameters */
13
14#define SETDEFAULT 0x2 /* CCD/VIDEO/SS1M */
15#define SETPARAMETERS 0x3 /* CCD/VIDEO */
16#define SETSIZE 0x4 /* CCD/VIDEO/SS1M */
17#define SETCOMPRESSION 0x5 /* CCD/VIDEO/SS1M */
18#define SETCOLORLEVEL 0x6 /* CCD/VIDEO */
19#define SETBRIGHTNESS 0x7 /* CCD */
20#define SETROTATION 0x8 /* CCD */
21#define SETTEXT 0x9 /* CCD/VIDEO/SS1M */
22#define SETCLOCK 0xa /* CCD/VIDEO/SS1M */
23#define SETDATE 0xb /* CCD/VIDEO/SS1M */
24#define SETTIMEFORMAT 0xc /* CCD/VIDEO/SS1M */
25#define SETDATEFORMAT 0xd /* VIDEO */
26#define SETTEXTALIGNMENT 0xe /* VIDEO */
27#define SETFPS 0xf /* CCD/VIDEO/SS1M */
28#define SETVGA 0xff /* VIDEO */
29#define SETCOMMENT 0xfe /* CCD/VIDEO */
30
31/* get parameters */
32
33#define GETDRIVERTYPE 0x10 /* CCD/VIDEO/SS1M */
34#define GETNBROFCAMERAS 0x11 /* CCD/VIDEO/SS1M */
35#define GETPARAMETERS 0x12 /* CCD/VIDEO/SS1M */
36#define GETBUFFERSIZE 0x13 /* CCD/VIDEO/SS1M */
37#define GETVIDEOTYPE 0x14 /* VIDEO/SS1M */
38#define GETVIDEOSIGNAL 0x15 /* VIDEO */
39#define GETMODULATION 0x16 /* VIDEO */
40#define GETDCYVALUES 0xa0 /* CCD /SS1M */
41#define GETDCYWIDTH 0xa1 /* CCD /SS1M */
42#define GETDCYHEIGHT 0xa2 /* CCD /SS1M */
43#define GETSIZE 0xa3 /* CCD/VIDEO */
44#define GETCOMPRESSION 0xa4 /* CCD/VIDEO */
45
46/* detect and get parameters */
47
48#define DETECTMODULATION 0x17 /* VIDEO */
49#define DETECTVIDEOTYPE 0x18 /* VIDEO */
50#define DETECTVIDEOSIGNAL 0x19 /* VIDEO */
51
52/* configure default parameters */
53
54#define CONFIGUREDEFAULT 0x20 /* CCD/VIDEO/SS1M */
55#define DEFSIZE 0x21 /* CCD/VIDEO/SS1M */
56#define DEFCOMPRESSION 0x22 /* CCD/VIDEO/SS1M */
57#define DEFCOLORLEVEL 0x23 /* CCD/VIDEO */
58#define DEFBRIGHTNESS 0x24 /* CCD */
59#define DEFROTATION 0x25 /* CCD */
60#define DEFWHITEBALANCE 0x26 /* CCD */
61#define DEFEXPOSURE 0x27 /* CCD */
62#define DEFAUTOEXPWINDOW 0x28 /* CCD */
63#define DEFTEXT 0x29 /* CCD/VIDEO/SS1M */
64#define DEFCLOCK 0x2a /* CCD/VIDEO/SS1M */
65#define DEFDATE 0x2b /* CCD/VIDEO/SS1M */
66#define DEFTIMEFORMAT 0x2c /* CCD/VIDEO/SS1M */
67#define DEFDATEFORMAT 0x2d /* VIDEO */
68#define DEFTEXTALIGNMENT 0x2e /* VIDEO */
69#define DEFFPS 0x2f /* CCD/VIDEO/SS1M */
70#define DEFTEXTSTRING 0x30 /* CCD/VIDEO/SS1M */
71#define DEFHEADERINFO 0x31 /* CCD/VIDEO/SS1M */
72#define DEFWEXAR 0x32 /* CCD */
73#define DEFLINEDELAY 0x33 /* CCD */
74#define DEFDISABLEDVIDEO 0x34 /* VIDEO */
75#define DEFVIDEOTYPE 0x35 /* VIDEO */
76#define DEFMODULATION 0x36 /* VIDEO */
77#define DEFXOFFSET 0x37 /* VIDEO */
78#define DEFYOFFSET 0x38 /* VIDEO */
79#define DEFYCMODE 0x39 /* VIDEO */
80#define DEFVCRMODE 0x3a /* VIDEO */
81#define DEFSTOREDCYVALUES 0x3b /* CCD/VIDEO/SS1M */
82#define DEFWCDS 0x3c /* CCD */
83#define DEFVGA 0x3d /* VIDEO */
84#define DEFCOMMENT 0x3e /* CCD/VIDEO */
85#define DEFCOMMENTSIZE 0x3f /* CCD/VIDEO */
86#define DEFCOMMENTTEXT 0x50 /* CCD/VIDEO */
87#define DEFSTOREDCYTEXT 0x51 /* VIDEO */
88
89
90#define JULABORTDMA 0x70 /* Abort current DMA transfer */
91
92/* juliette general i/o port */
93
94#define JIO_READBITS 0x40 /* read and return current port bits */
95#define JIO_SETBITS 0x41 /* set bits marked by 1 in the argument */
96#define JIO_CLRBITS 0x42 /* clr bits marked by 1 in the argument */
97#define JIO_READDIR 0x43 /* read direction, 0=input 1=output */
98#define JIO_SETINPUT 0x44 /* set direction, 0=unchanged 1=input
99 returns current dir */
100#define JIO_SETOUTPUT 0x45 /* set direction, 0=unchanged 1=output
101 returns current dir */
102
103/**** YumYum internal adresses ****/
104
105/* Juliette buffer addresses */
106
107#define BUFFER1_VIDEO 0x1100
108#define BUFFER2_VIDEO 0x2800
109#define ACDC_BUFF_VIDEO 0x0aaa
110#define BUFFER1 0x1700
111#define BUFFER2 0x2b01
112#define ACDC_BUFFER 0x1200
113#define BUFFER1_SS1M 0x1100
114#define BUFFER2_SS1M 0x2800
115#define ACDC_BUFF_SS1M 0x0900
116
117/* Juliette parameter memory addresses */
118
119#define PA_BUFFER_CNT 0x3f09 /* CCD/VIDEO */
120#define PA_CCD_BUFFER 0x3f10 /* CCD */
121#define PA_VIDEO_BUFFER 0x3f10 /* VIDEO */
122#define PA_DCT_BUFFER 0x3f11 /* CCD/VIDEO */
123#define PA_TEMP 0x3f12 /* CCD/VIDEO */
124#define PA_VIDEOLINE_RD 0x3f13 /* VIDEO */
125#define PA_VIDEOLINE_WR 0x3f14 /* VIDEO */
126#define PA_VI_HDELAY0 0x3f15 /* VIDEO */
127#define PA_VI_VDELAY0 0x3f16 /* VIDEO */
128#define PA_VI_HDELAY1 0x3f17 /* VIDEO */
129#define PA_VI_VDELAY1 0x3f18 /* VIDEO */
130#define PA_VI_HDELAY2 0x3f19 /* VIDEO */
131#define PA_VI_VDELAY2 0x3f1a /* VIDEO */
132#define PA_VI_HDELAY3 0x3f1b /* VIDEO */
133#define PA_VI_VDELAY3 0x3f1c /* VIDEO */
134#define PA_VI_CTRL 0x3f20 /* VIDEO */
135#define PA_JPEG_CTRL 0x3f22 /* CCD/VIDEO */
136#define PA_BUFFER_SIZE 0x3f24 /* CCD/VIDEO */
137#define PA_PAL_NTSC 0x3f25 /* VIDEO */
138#define PA_MACROBLOCKS 0x3f26 /* CCD/VIDEO */
139#define PA_COLOR 0x3f27 /* VIDEO */
140#define PA_MEMCH1CNT2 0x3f28 /* CCD/VIDEO */
141#define PA_MEMCH1CNT3 0x3f29 /* VIDEO */
142#define PA_MEMCH1STR2 0x3f2a /* CCD/VIDEO */
143#define PA_MEMCH1STR3 0x3f2b /* VIDEO */
144#define PA_BUFFERS 0x3f2c /* CCD/VIDEO */
145#define PA_PROGRAM 0x3f2d /* CCD/VIDEO */
146#define PA_ROTATION 0x3f2e /* CCD */
147#define PA_PC 0x3f30 /* CCD/VIDEO */
148#define PA_PC2 0x3f31 /* VIDEO */
149#define PA_ODD_LINE 0x3f32 /* VIDEO */
150#define PA_EXP_DELAY 0x3f34 /* CCD */
151#define PA_MACROBLOCK_CNT 0x3f35 /* CCD/VIDEO */
152#define PA_DRAM_PTR1_L 0x3f36 /* CCD/VIDEO */
153#define PA_CLPOB_CNT 0x3f37 /* CCD */
154#define PA_DRAM_PTR1_H 0x3f38 /* CCD/VIDEO */
155#define PA_DRAM_PTR2_L 0x3f3a /* VIDEO */
156#define PA_DRAM_PTR2_H 0x3f3c /* VIDEO */
157#define PA_CCD_LINE_CNT 0x3f3f /* CCD */
158#define PA_VIDEO_LINE_CNT 0x3f3f /* VIDEO */
159#define PA_TEXT 0x3f41 /* CCD/VIDEO */
160#define PA_CAMERA_CHANGED 0x3f42 /* VIDEO */
161#define PA_TEXTALIGNMENT 0x3f43 /* VIDEO */
162#define PA_DISABLED 0x3f44 /* VIDEO */
163#define PA_MACROBLOCKTEXT 0x3f45 /* VIDEO */
164#define PA_VGA 0x3f46 /* VIDEO */
165#define PA_ZERO 0x3ffe /* VIDEO */
166#define PA_NULL 0x3fff /* CCD/VIDEO */
167
168typedef enum {
169 jpeg = 0,
170 dummy = 1
171} request_type;
172
173typedef enum {
174 hugesize = 0,
175 fullsize = 1,
176 halfsize = 2,
177 fieldsize = 3
178} size_type;
179
180typedef enum {
181 min = 0,
182 low = 1,
183 medium = 2,
184 high = 3,
185 very_high = 4,
186 very_low = 5,
187 q1 = 6,
188 q2 = 7,
189 q3 = 8,
190 q4 = 9,
191 q5 = 10,
192 q6 = 11
193} compr_type;
194
195typedef enum {
196 deg_0 = 0,
197 deg_180 = 1,
198 deg_90 = 2,
199 deg_270 = 3
200} rotation_type;
201
202typedef enum {
203 auto_white = 0,
204 hold = 1,
205 fixed_outdoor = 2,
206 fixed_indoor = 3,
207 fixed_fluor = 4
208} white_balance_type;
209
210typedef enum {
211 auto_exp = 0,
212 fixed_exp = 1
213} exposure_type;
214
215typedef enum {
216 no_window = 0,
217 center = 1,
218 top = 2,
219 lower = 3,
220 left = 4,
221 right = 5,
222 spot = 6,
223 cw = 7
224} exp_window_type;
225
226typedef enum {
227 h_24 = 0,
228 h_12 = 1,
229 h_24P = 2
230} hour_type;
231
232typedef enum {
233 standard = 0,
234 YYYY_MM_DD = 1,
235 Www_Mmm_DD_YYYY = 2,
236 Www_DD_MM_YYYY = 3
237} date_type;
238
239typedef enum {
240 left_align = 0,
241 center_align = 1,
242 right_align = 2
243} alignment_type;
244
245typedef enum {
246 off = 0,
247 on = 1,
248 no = 0,
249 yes = 1
250} enable_type;
251
252typedef enum {
253 disabled = 0,
254 enabled = 1,
255 extended = 2
256} comment_type;
257
258typedef enum {
259 pal = 0,
260 ntsc = 1
261} video_type;
262
263typedef enum {
264 pal_bghi_ntsc_m = 0,
265 ntsc_4_43_50hz_pal_4_43_60hz = 1,
266 pal_n_ntsc_4_43_60hz = 2,
267 ntsc_n_pal_m = 3,
268 secam_pal_4_43_60hz = 4
269} modulation_type;
270
271typedef enum {
272 cam0 = 0,
273 cam1 = 1,
274 cam2 = 2,
275 cam3 = 3,
276 quad = 32
277} camera_type;
278
279typedef enum {
280 video_driver = 0,
281 ccd_driver = 1
282} driver_type;
283
284struct jul_param {
285 request_type req_type;
286 size_type size;
287 compr_type compression;
288 rotation_type rotation;
289 int color_level;
290 int brightness;
291 white_balance_type white_balance;
292 exposure_type exposure;
293 exp_window_type auto_exp_window;
294 hour_type time_format;
295 date_type date_format;
296 alignment_type text_alignment;
297 enable_type text;
298 enable_type clock;
299 enable_type date;
300 enable_type fps;
301 enable_type vga;
302 enable_type comment;
303};
304
305struct video_param {
306 enable_type disabled;
307 modulation_type modulation;
308 video_type video;
309 enable_type signal;
310 enable_type vcr;
311 int xoffset;
312 int yoffset;
313};
314
315/* The juliette_request structure is used during the JULSTARTDMA asynchronous
316 * picture-taking ioctl call as an argument to specify a buffer which will get
317 * the final picture.
318 */
319
320struct juliette_request {
321 char *buf; /* Pointer to the buffer to hold picture data */
322 unsigned int buflen; /* Length of the above buffer */
323 unsigned int size; /* Resulting length, 0 if the picture is not ready */
324};
325
326#endif
diff --git a/include/asm-cris/arch-v32/memmap.h b/include/asm-cris/arch-v32/memmap.h
new file mode 100644
index 000000000000..d29df5644d3e
--- /dev/null
+++ b/include/asm-cris/arch-v32/memmap.h
@@ -0,0 +1,24 @@
1#ifndef _ASM_ARCH_MEMMAP_H
2#define _ASM_ARCH_MEMMAP_H
3
4#define MEM_CSE0_START (0x00000000)
5#define MEM_CSE0_SIZE (0x04000000)
6#define MEM_CSE1_START (0x04000000)
7#define MEM_CSE1_SIZE (0x04000000)
8#define MEM_CSR0_START (0x08000000)
9#define MEM_CSR1_START (0x0c000000)
10#define MEM_CSP0_START (0x10000000)
11#define MEM_CSP1_START (0x14000000)
12#define MEM_CSP2_START (0x18000000)
13#define MEM_CSP3_START (0x1c000000)
14#define MEM_CSP4_START (0x20000000)
15#define MEM_CSP5_START (0x24000000)
16#define MEM_CSP6_START (0x28000000)
17#define MEM_CSP7_START (0x2c000000)
18#define MEM_INTMEM_START (0x38000000)
19#define MEM_INTMEM_SIZE (0x00020000)
20#define MEM_DRAM_START (0x40000000)
21
22#define MEM_NON_CACHEABLE (0x80000000)
23
24#endif
diff --git a/include/asm-cris/arch-v32/mmu.h b/include/asm-cris/arch-v32/mmu.h
new file mode 100644
index 000000000000..6bcdc3fdf7dc
--- /dev/null
+++ b/include/asm-cris/arch-v32/mmu.h
@@ -0,0 +1,111 @@
1#ifndef _ASM_CRIS_ARCH_MMU_H
2#define _ASM_CRIS_ARCH_MMU_H
3
4/* MMU context type. */
5typedef struct
6{
7 unsigned int page_id;
8} mm_context_t;
9
10/* Kernel memory segments. */
11#define KSEG_F 0xf0000000UL
12#define KSEG_E 0xe0000000UL
13#define KSEG_D 0xd0000000UL
14#define KSEG_C 0xc0000000UL
15#define KSEG_B 0xb0000000UL
16#define KSEG_A 0xa0000000UL
17#define KSEG_9 0x90000000UL
18#define KSEG_8 0x80000000UL
19#define KSEG_7 0x70000000UL
20#define KSEG_6 0x60000000UL
21#define KSEG_5 0x50000000UL
22#define KSEG_4 0x40000000UL
23#define KSEG_3 0x30000000UL
24#define KSEG_2 0x20000000UL
25#define KSEG_1 0x10000000UL
26#define KSEG_0 0x00000000UL
27
28/*
29 * CRISv32 PTE bits:
30 *
31 * Bit: 31-13 12-5 4 3 2 1 0
32 * +-----+------+--------+-------+--------+-------+---------+
33 * | pfn | zero | global | valid | kernel | write | execute |
34 * +-----+------+--------+-------+--------+-------+---------+
35 */
36
37/*
38 * Defines for accessing the bits. Also define some synonyms for use with
39 * the software-based defined bits below.
40 */
41#define _PAGE_EXECUTE (1 << 0) /* Execution bit. */
42#define _PAGE_WE (1 << 1) /* Write bit. */
43#define _PAGE_SILENT_WRITE (1 << 1) /* Same as above. */
44#define _PAGE_KERNEL (1 << 2) /* Kernel mode page. */
45#define _PAGE_VALID (1 << 3) /* Page is valid. */
46#define _PAGE_SILENT_READ (1 << 3) /* Same as above. */
47#define _PAGE_GLOBAL (1 << 4) /* Global page. */
48
49/*
50 * The hardware doesn't care about these bits, but the kernel uses them in
51 * software.
52 */
53#define _PAGE_PRESENT (1 << 5) /* Page is present in memory. */
54#define _PAGE_FILE (1 << 6) /* 1=pagecache, 0=swap (when !present) */
55#define _PAGE_ACCESSED (1 << 6) /* Simulated in software using valid bit. */
56#define _PAGE_MODIFIED (1 << 7) /* Simulated in software using we bit. */
57#define _PAGE_READ (1 << 8) /* Read enabled. */
58#define _PAGE_WRITE (1 << 9) /* Write enabled. */
59
60/* Define some higher level generic page attributes. */
61#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
62#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
63
64#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE)
65#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED)
66
67#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
68#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
69 _PAGE_ACCESSED)
70#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
71 _PAGE_ACCESSED | _PAGE_EXECUTE)
72
73#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE)
74#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE | _PAGE_ACCESSED)
75
76#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE)
77#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE)
78#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \
79 _PAGE_PRESENT | __READABLE | __WRITEABLE)
80#define PAGE_KERNEL_EXEC __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | _PAGE_EXECUTE | \
81 _PAGE_PRESENT | __READABLE | __WRITEABLE)
82#define PAGE_SIGNAL_TRAMPOLINE __pgprot(_PAGE_GLOBAL | _PAGE_EXECUTE | \
83 _PAGE_PRESENT | __READABLE)
84
85#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL)
86
87/* CRISv32 can do page protection for execute.
88 * Write permissions imply read permissions.
89 * Note that the numbers are in Execute-Write-Read order!
90 */
91#define __P000 PAGE_NONE
92#define __P001 PAGE_READONLY
93#define __P010 PAGE_COPY
94#define __P011 PAGE_COPY
95#define __P100 PAGE_READONLY_EXEC
96#define __P101 PAGE_READONLY_EXEC
97#define __P110 PAGE_COPY_EXEC
98#define __P111 PAGE_COPY_EXEC
99
100#define __S000 PAGE_NONE
101#define __S001 PAGE_READONLY
102#define __S010 PAGE_SHARED
103#define __S011 PAGE_SHARED
104#define __S100 PAGE_READONLY_EXEC
105#define __S101 PAGE_READONLY_EXEC
106#define __S110 PAGE_SHARED_EXEC
107#define __S111 PAGE_SHARED_EXEC
108
109#define PTE_FILE_MAX_BITS 25
110
111#endif /* _ASM_CRIS_ARCH_MMU_H */
diff --git a/include/asm-cris/arch-v32/offset.h b/include/asm-cris/arch-v32/offset.h
new file mode 100644
index 000000000000..597419b033f9
--- /dev/null
+++ b/include/asm-cris/arch-v32/offset.h
@@ -0,0 +1,35 @@
1#ifndef __ASM_OFFSETS_H__
2#define __ASM_OFFSETS_H__
3/*
4 * DO NOT MODIFY.
5 *
6 * This file was generated by arch/cris/Makefile
7 *
8 */
9
10#define PT_orig_r10 0 /* offsetof(struct pt_regs, orig_r10) */
11#define PT_r13 56 /* offsetof(struct pt_regs, r13) */
12#define PT_r12 52 /* offsetof(struct pt_regs, r12) */
13#define PT_r11 48 /* offsetof(struct pt_regs, r11) */
14#define PT_r10 44 /* offsetof(struct pt_regs, r10) */
15#define PT_r9 40 /* offsetof(struct pt_regs, r9) */
16#define PT_acr 60 /* offsetof(struct pt_regs, acr) */
17#define PT_srs 64 /* offsetof(struct pt_regs, srs) */
18#define PT_mof 68 /* offsetof(struct pt_regs, mof) */
19#define PT_ccs 76 /* offsetof(struct pt_regs, ccs) */
20#define PT_srp 80 /* offsetof(struct pt_regs, srp) */
21
22#define TI_task 0 /* offsetof(struct thread_info, task) */
23#define TI_flags 8 /* offsetof(struct thread_info, flags) */
24#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */
25
26#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */
27#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */
28#define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */
29
30#define TASK_pid 149 /* offsetof(struct task_struct, pid) */
31
32#define LCLONE_VM 256 /* CLONE_VM */
33#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */
34
35#endif
diff --git a/include/asm-cris/arch-v32/page.h b/include/asm-cris/arch-v32/page.h
new file mode 100644
index 000000000000..77827bc17cca
--- /dev/null
+++ b/include/asm-cris/arch-v32/page.h
@@ -0,0 +1,28 @@
1#ifndef _ASM_CRIS_ARCH_PAGE_H
2#define _ASM_CRIS_ARCH_PAGE_H
3
4#include <linux/config.h>
5
6#ifdef __KERNEL__
7
8#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram. */
9
10/*
11 * Macros to convert between physical and virtual addresses. By stripiing a
12 * selected bit it's possible to convert between KSEG_x and 0x40000000 where the
13 * DRAM really resides. DRAM is virtually at 0xc.
14 */
15#ifndef CONFIG_ETRAXFS_SIM
16#define __pa(x) ((unsigned long)(x) & 0x7fffffff)
17#define __va(x) ((void *)((unsigned long)(x) | 0x80000000))
18#else
19#define __pa(x) ((unsigned long)(x) & 0x3fffffff)
20#define __va(x) ((void *)((unsigned long)(x) | 0xc0000000))
21#endif
22
23#define VM_STACK_DEFAULT_FLAGS (VM_READ | VM_WRITE | \
24 VM_MAYREAD | VM_MAYWRITE)
25
26#endif /* __KERNEL__ */
27
28#endif /* _ASM_CRIS_ARCH_PAGE_H */
diff --git a/include/asm-cris/arch-v32/pgtable.h b/include/asm-cris/arch-v32/pgtable.h
new file mode 100644
index 000000000000..08cb7ff7e4e7
--- /dev/null
+++ b/include/asm-cris/arch-v32/pgtable.h
@@ -0,0 +1,9 @@
1#ifndef _ASM_CRIS_ARCH_PGTABLE_H
2#define _ASM_CRIS_ARCH_PGTABLE_H
3
4/* Define the kernels virtual memory area. */
5#define VMALLOC_START KSEG_D
6#define VMALLOC_END KSEG_E
7#define VMALLOC_VMADDR(x) ((unsigned long)(x))
8
9#endif /* _ASM_CRIS_ARCH_PGTABLE_H */
diff --git a/include/asm-cris/arch-v32/pinmux.h b/include/asm-cris/arch-v32/pinmux.h
new file mode 100644
index 000000000000..a66dc9970919
--- /dev/null
+++ b/include/asm-cris/arch-v32/pinmux.h
@@ -0,0 +1,39 @@
1#ifndef _ASM_CRIS_ARCH_PINMUX_H
2#define _ASM_CRIS_ARCH_PINMUX_H
3
4#define PORT_B 0
5#define PORT_C 1
6#define PORT_D 2
7#define PORT_E 3
8
9enum pin_mode
10{
11 pinmux_none = 0,
12 pinmux_fixed,
13 pinmux_gpio,
14 pinmux_iop
15};
16
17enum fixed_function
18{
19 pinmux_ser1,
20 pinmux_ser2,
21 pinmux_ser3,
22 pinmux_sser0,
23 pinmux_sser1,
24 pinmux_ata0,
25 pinmux_ata1,
26 pinmux_ata2,
27 pinmux_ata3,
28 pinmux_ata,
29 pinmux_eth1,
30 pinmux_timer
31};
32
33int crisv32_pinmux_init(void);
34int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
35int crisv32_pinmux_alloc_fixed(enum fixed_function function);
36int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
37void crisv32_pinmux_dump(void);
38
39#endif
diff --git a/include/asm-cris/arch-v32/processor.h b/include/asm-cris/arch-v32/processor.h
new file mode 100644
index 000000000000..8c939bf27987
--- /dev/null
+++ b/include/asm-cris/arch-v32/processor.h
@@ -0,0 +1,60 @@
1#ifndef _ASM_CRIS_ARCH_PROCESSOR_H
2#define _ASM_CRIS_ARCH_PROCESSOR_H
3
4#include <linux/config.h>
5
6/* Return current instruction pointer. */
7#define current_text_addr() \
8 ({void *pc; __asm__ __volatile__ ("lapcq .,%0" : "=rm" (pc)); pc;})
9
10/*
11 * Since CRIS doesn't do hardware task-switching this hasn't really anything to
12 * do with the proccessor itself, it's just here for legacy reasons. This is
13 * used when task-switching using _resume defined in entry.S. The offsets here
14 * are hardcoded into _resume, so if this struct is changed, entry.S needs to be
15 * changed as well.
16 */
17struct thread_struct {
18 unsigned long ksp; /* Kernel stack pointer. */
19 unsigned long usp; /* User stack pointer. */
20 unsigned long ccs; /* Saved flags register. */
21};
22
23/*
24 * User-space process size. This is hardcoded into a few places, so don't
25 * changed it unless everything's clear!
26 */
27#ifndef CONFIG_ETRAXFS_SIM
28#define TASK_SIZE (0xB0000000UL)
29#else
30#define TASK_SIZE (0xA0000000UL)
31#endif
32
33/* CCS I=1, enable interrupts. */
34#define INIT_THREAD { 0, 0, (1 << I_CCS_BITNR) }
35
36#define KSTK_EIP(tsk) \
37({ \
38 unsigned long eip = 0; \
39 unsigned long regs = (unsigned long)user_regs(tsk); \
40 if (regs > PAGE_SIZE && virt_addr_valid(regs)) \
41 eip = ((struct pt_regs *)regs)->erp; \
42 eip; \
43})
44
45/*
46 * Give the thread a program location, set user-mode and switch user
47 * stackpointer.
48 */
49#define start_thread(regs, ip, usp) \
50do { \
51 set_fs(USER_DS); \
52 regs->erp = ip; \
53 regs->ccs |= 1 << (U_CCS_BITNR + CCS_SHIFT); \
54 wrusp(usp); \
55} while(0)
56
57/* Nothing special to do for v32 when handling a kernel bus fault fixup. */
58#define arch_fixup(regs) {};
59
60#endif /* _ASM_CRIS_ARCH_PROCESSOR_H */
diff --git a/include/asm-cris/arch-v32/ptrace.h b/include/asm-cris/arch-v32/ptrace.h
new file mode 100644
index 000000000000..516cc7062d94
--- /dev/null
+++ b/include/asm-cris/arch-v32/ptrace.h
@@ -0,0 +1,114 @@
1#ifndef _CRIS_ARCH_PTRACE_H
2#define _CRIS_ARCH_PTRACE_H
3
4/* Register numbers in the ptrace system call interface */
5
6#define PT_ORIG_R10 0
7#define PT_R0 1
8#define PT_R1 2
9#define PT_R2 3
10#define PT_R3 4
11#define PT_R4 5
12#define PT_R5 6
13#define PT_R6 7
14#define PT_R7 8
15#define PT_R8 9
16#define PT_R9 10
17#define PT_R10 11
18#define PT_R11 12
19#define PT_R12 13
20#define PT_R13 14
21#define PT_ACR 15
22#define PT_SRS 16
23#define PT_MOF 17
24#define PT_SPC 18
25#define PT_CCS 19
26#define PT_SRP 20
27#define PT_ERP 21 /* This is actually the debugged process' PC */
28#define PT_EXS 22
29#define PT_EDA 23
30#define PT_USP 24 /* special case - USP is not in the pt_regs */
31#define PT_PPC 25 /* special case - pseudo PC */
32#define PT_BP 26 /* Base number for BP registers. */
33#define PT_BP_CTRL 26 /* BP control register. */
34#define PT_MAX 40
35
36/* Condition code bit numbers. */
37#define C_CCS_BITNR 0
38#define V_CCS_BITNR 1
39#define Z_CCS_BITNR 2
40#define N_CCS_BITNR 3
41#define X_CCS_BITNR 4
42#define I_CCS_BITNR 5
43#define U_CCS_BITNR 6
44#define P_CCS_BITNR 7
45#define R_CCS_BITNR 8
46#define S_CCS_BITNR 9
47#define M_CCS_BITNR 30
48#define Q_CCS_BITNR 31
49#define CCS_SHIFT 10 /* Shift count for each level in CCS */
50
51/* pt_regs not only specifices the format in the user-struct during
52 * ptrace but is also the frame format used in the kernel prologue/epilogues
53 * themselves
54 */
55
56struct pt_regs {
57 unsigned long orig_r10;
58 /* pushed by movem r13, [sp] in SAVE_ALL. */
59 unsigned long r0;
60 unsigned long r1;
61 unsigned long r2;
62 unsigned long r3;
63 unsigned long r4;
64 unsigned long r5;
65 unsigned long r6;
66 unsigned long r7;
67 unsigned long r8;
68 unsigned long r9;
69 unsigned long r10;
70 unsigned long r11;
71 unsigned long r12;
72 unsigned long r13;
73 unsigned long acr;
74 unsigned long srs;
75 unsigned long mof;
76 unsigned long spc;
77 unsigned long ccs;
78 unsigned long srp;
79 unsigned long erp; /* This is actually the debugged process' PC */
80 /* For debugging purposes; saved only when needed. */
81 unsigned long exs;
82 unsigned long eda;
83};
84
85/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S)
86 * when doing a context-switch. it is used (apart from in resume) when a new
87 * thread is made and we need to make _resume (which is starting it for the
88 * first time) realise what is going on.
89 *
90 * Actually, the use is very close to the thread struct (TSS) in that both the
91 * switch_stack and the TSS are used to keep thread stuff when switching in
92 * _resume.
93 */
94
95struct switch_stack {
96 unsigned long r0;
97 unsigned long r1;
98 unsigned long r2;
99 unsigned long r3;
100 unsigned long r4;
101 unsigned long r5;
102 unsigned long r6;
103 unsigned long r7;
104 unsigned long r8;
105 unsigned long r9;
106 unsigned long return_ip; /* ip that _resume will return to */
107};
108
109#define user_mode(regs) (((regs)->ccs & (1 << (U_CCS_BITNR + CCS_SHIFT))) != 0)
110#define instruction_pointer(regs) ((regs)->erp)
111extern void show_regs(struct pt_regs *);
112#define profile_pc(regs) instruction_pointer(regs)
113
114#endif
diff --git a/include/asm-cris/arch-v32/spinlock.h b/include/asm-cris/arch-v32/spinlock.h
new file mode 100644
index 000000000000..52df72a62232
--- /dev/null
+++ b/include/asm-cris/arch-v32/spinlock.h
@@ -0,0 +1,163 @@
1#ifndef __ASM_ARCH_SPINLOCK_H
2#define __ASM_ARCH_SPINLOCK_H
3
4#include <asm/system.h>
5
6#define RW_LOCK_BIAS 0x01000000
7#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 }
8#define spin_lock_init(x) do { *(x) = SPIN_LOCK_UNLOCKED; } while(0)
9
10#define spin_is_locked(x) (*(volatile signed char *)(&(x)->lock) <= 0)
11#define spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x))
12
13extern void cris_spin_unlock(void *l, int val);
14extern void cris_spin_lock(void *l);
15extern int cris_spin_trylock(void* l);
16
17static inline void _raw_spin_unlock(spinlock_t *lock)
18{
19 __asm__ volatile ("move.d %1,%0" \
20 : "=m" (lock->lock) \
21 : "r" (1) \
22 : "memory");
23}
24
25static inline int _raw_spin_trylock(spinlock_t *lock)
26{
27 return cris_spin_trylock((void*)&lock->lock);
28}
29
30static inline void _raw_spin_lock(spinlock_t *lock)
31{
32 cris_spin_lock((void*)&lock->lock);
33}
34
35static inline void _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags)
36{
37 _raw_spin_lock(lock);
38}
39
40/*
41 * Read-write spinlocks, allowing multiple readers
42 * but only one writer.
43 *
44 * NOTE! it is quite common to have readers in interrupts
45 * but no interrupt writers. For those circumstances we
46 * can "mix" irq-safe locks - any writer needs to get a
47 * irq-safe write-lock, but readers can get non-irqsafe
48 * read-locks.
49 */
50typedef struct {
51 spinlock_t lock;
52 volatile int counter;
53#ifdef CONFIG_PREEMPT
54 unsigned int break_lock;
55#endif
56} rwlock_t;
57
58#define RW_LOCK_UNLOCKED (rwlock_t) { {1}, 0 }
59
60#define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while (0)
61
62/**
63 * read_can_lock - would read_trylock() succeed?
64 * @lock: the rwlock in question.
65 */
66#define read_can_lock(x) ((int)(x)->counter >= 0)
67
68/**
69 * write_can_lock - would write_trylock() succeed?
70 * @lock: the rwlock in question.
71 */
72#define write_can_lock(x) ((x)->counter == 0)
73
74#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
75
76/* read_lock, read_unlock are pretty straightforward. Of course it somehow
77 * sucks we end up saving/restoring flags twice for read_lock_irqsave aso. */
78
79static __inline__ void _raw_read_lock(rwlock_t *rw)
80{
81 unsigned long flags;
82 local_irq_save(flags);
83 _raw_spin_lock(&rw->lock);
84
85 rw->counter++;
86
87 _raw_spin_unlock(&rw->lock);
88 local_irq_restore(flags);
89}
90
91static __inline__ void _raw_read_unlock(rwlock_t *rw)
92{
93 unsigned long flags;
94 local_irq_save(flags);
95 _raw_spin_lock(&rw->lock);
96
97 rw->counter--;
98
99 _raw_spin_unlock(&rw->lock);
100 local_irq_restore(flags);
101}
102
103/* write_lock is less trivial. We optimistically grab the lock and check
104 * if we surprised any readers. If so we release the lock and wait till
105 * they're all gone before trying again
106 *
107 * Also note that we don't use the _irqsave / _irqrestore suffixes here.
108 * If we're called with interrupts enabled and we've got readers (or other
109 * writers) in interrupt handlers someone fucked up and we'd dead-lock
110 * sooner or later anyway. prumpf */
111
112static __inline__ void _raw_write_lock(rwlock_t *rw)
113{
114retry:
115 _raw_spin_lock(&rw->lock);
116
117 if(rw->counter != 0) {
118 /* this basically never happens */
119 _raw_spin_unlock(&rw->lock);
120
121 while(rw->counter != 0);
122
123 goto retry;
124 }
125
126 /* got it. now leave without unlocking */
127 rw->counter = -1; /* remember we are locked */
128}
129
130/* write_unlock is absolutely trivial - we don't have to wait for anything */
131
132static __inline__ void _raw_write_unlock(rwlock_t *rw)
133{
134 rw->counter = 0;
135 _raw_spin_unlock(&rw->lock);
136}
137
138static __inline__ int _raw_write_trylock(rwlock_t *rw)
139{
140 _raw_spin_lock(&rw->lock);
141 if (rw->counter != 0) {
142 /* this basically never happens */
143 _raw_spin_unlock(&rw->lock);
144
145 return 0;
146 }
147
148 /* got it. now leave without unlocking */
149 rw->counter = -1; /* remember we are locked */
150 return 1;
151}
152
153static __inline__ int is_read_locked(rwlock_t *rw)
154{
155 return rw->counter > 0;
156}
157
158static __inline__ int is_write_locked(rwlock_t *rw)
159{
160 return rw->counter < 0;
161}
162
163#endif /* __ASM_ARCH_SPINLOCK_H */
diff --git a/include/asm-cris/arch-v32/system.h b/include/asm-cris/arch-v32/system.h
new file mode 100644
index 000000000000..b9afbb95e0bb
--- /dev/null
+++ b/include/asm-cris/arch-v32/system.h
@@ -0,0 +1,79 @@
1#ifndef _ASM_CRIS_ARCH_SYSTEM_H
2#define _ASM_CRIS_ARCH_SYSTEM_H
3
4#include <linux/config.h>
5
6/* Read the CPU version register. */
7extern inline unsigned long rdvr(void)
8{
9 unsigned char vr;
10
11 __asm__ __volatile__ ("move $vr, %0" : "=rm" (vr));
12 return vr;
13}
14
15#define cris_machine_name "crisv32"
16
17/* Read the user-mode stack pointer. */
18extern inline unsigned long rdusp(void)
19{
20 unsigned long usp;
21
22 __asm__ __volatile__ ("move $usp, %0" : "=rm" (usp));
23 return usp;
24}
25
26/* Read the current stack pointer. */
27extern inline unsigned long rdsp(void)
28{
29 unsigned long sp;
30
31 __asm__ __volatile__ ("move.d $sp, %0" : "=rm" (sp));
32 return sp;
33}
34
35/* Write the user-mode stack pointer. */
36#define wrusp(usp) __asm__ __volatile__ ("move %0, $usp" : : "rm" (usp))
37
38#define nop() __asm__ __volatile__ ("nop");
39
40#define xchg(ptr,x) \
41 ((__typeof__(*(ptr)))__xchg((unsigned long) (x),(ptr),sizeof(*(ptr))))
42
43#define tas(ptr) (xchg((ptr),1))
44
45struct __xchg_dummy { unsigned long a[100]; };
46#define __xg(x) ((struct __xchg_dummy *)(x))
47
48/* Used for interrupt control. */
49#define local_save_flags(x) \
50 __asm__ __volatile__ ("move $ccs, %0" : "=rm" (x) : : "memory");
51
52#define local_irq_restore(x) \
53 __asm__ __volatile__ ("move %0, $ccs" : : "rm" (x) : "memory");
54
55#define local_irq_disable() __asm__ __volatile__ ("di" : : : "memory");
56#define local_irq_enable() __asm__ __volatile__ ("ei" : : : "memory");
57
58#define irqs_disabled() \
59({ \
60 unsigned long flags; \
61 \
62 local_save_flags(flags);\
63 !(flags & (1 << I_CCS_BITNR)); \
64})
65
66/* Used for spinlocks, etc. */
67#define local_irq_save(x) \
68 __asm__ __volatile__ ("move $ccs, %0\n\tdi" : "=rm" (x) : : "memory");
69
70#ifdef CONFIG_SMP
71typedef struct {
72 volatile unsigned int lock __attribute__ ((aligned(4)));
73#ifdef CONFIG_PREEMPT
74 unsigned int break_lock;
75#endif
76} spinlock_t;
77#endif
78
79#endif /* _ASM_CRIS_ARCH_SYSTEM_H */
diff --git a/include/asm-cris/arch-v32/thread_info.h b/include/asm-cris/arch-v32/thread_info.h
new file mode 100644
index 000000000000..a7a182307da0
--- /dev/null
+++ b/include/asm-cris/arch-v32/thread_info.h
@@ -0,0 +1,13 @@
1#ifndef _ASM_CRIS_ARCH_THREAD_INFO_H
2#define _ASM_CRIS_ARCH_THREAD_INFO_H
3
4/* Return a thread_info struct. */
5extern inline struct thread_info *current_thread_info(void)
6{
7 struct thread_info *ti;
8
9 __asm__ __volatile__ ("and.d $sp, %0" : "=r" (ti) : "0" (~8191UL));
10 return ti;
11}
12
13#endif /* _ASM_CRIS_ARCH_THREAD_INFO_H */
diff --git a/include/asm-cris/arch-v32/timex.h b/include/asm-cris/arch-v32/timex.h
new file mode 100644
index 000000000000..4d0fd23b21e9
--- /dev/null
+++ b/include/asm-cris/arch-v32/timex.h
@@ -0,0 +1,31 @@
1#ifndef _ASM_CRIS_ARCH_TIMEX_H
2#define _ASM_CRIS_ARCH_TIMEX_H
3
4#include <asm/arch/hwregs/reg_map.h>
5#include <asm/arch/hwregs/reg_rdwr.h>
6#include <asm/arch/hwregs/timer_defs.h>
7
8/*
9 * The clock runs at 100MHz, we divide it by 1000000. If you change anything
10 * here you must check time.c as well.
11 */
12
13#define CLOCK_TICK_RATE 100000000 /* Underlying frequency of the HZ timer */
14
15/* The timer0 values gives 10 ns resolution but interrupts at HZ. */
16#define TIMER0_FREQ (CLOCK_TICK_RATE)
17#define TIMER0_DIV (TIMER0_FREQ/(HZ))
18
19/* Convert the value in step of 10 ns to 1us without overflow: */
20#define GET_JIFFIES_USEC() \
21 ( (TIMER0_DIV - REG_RD(timer, regi_timer, r_tmr0_data)) /100 )
22
23extern unsigned long get_ns_in_jiffie(void);
24
25extern inline unsigned long get_us_in_jiffie_highres(void)
26{
27 return get_ns_in_jiffie() / 1000;
28}
29
30#endif
31
diff --git a/include/asm-cris/arch-v32/tlb.h b/include/asm-cris/arch-v32/tlb.h
new file mode 100644
index 000000000000..4effb1253660
--- /dev/null
+++ b/include/asm-cris/arch-v32/tlb.h
@@ -0,0 +1,14 @@
1#ifndef _CRIS_ARCH_TLB_H
2#define _CRIS_ARCH_TLB_H
3
4/*
5 * The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used
6 * to store the "process" it belongs to (=> fast mm context switch). The
7 * last page_id is never used so we can make TLB entries that never matches.
8 */
9#define NUM_TLB_ENTRIES 64
10#define NUM_PAGEID 256
11#define INVALID_PAGEID 255
12#define NO_CONTEXT -1
13
14#endif /* _CRIS_ARCH_TLB_H */
diff --git a/include/asm-cris/arch-v32/uaccess.h b/include/asm-cris/arch-v32/uaccess.h
new file mode 100644
index 000000000000..055a0bdbe835
--- /dev/null
+++ b/include/asm-cris/arch-v32/uaccess.h
@@ -0,0 +1,748 @@
1/*
2 * Authors: Hans-Peter Nilsson (hp@axis.com)
3 *
4 */
5#ifndef _CRIS_ARCH_UACCESS_H
6#define _CRIS_ARCH_UACCESS_H
7
8/*
9 * We don't tell gcc that we are accessing memory, but this is OK
10 * because we do not write to any memory gcc knows about, so there
11 * are no aliasing issues.
12 *
13 * Note that PC at a fault is the address *at* the faulting
14 * instruction for CRISv32.
15 */
16#define __put_user_asm(x, addr, err, op) \
17 __asm__ __volatile__( \
18 "2: "op" %1,[%2]\n" \
19 "4:\n" \
20 " .section .fixup,\"ax\"\n" \
21 "3: move.d %3,%0\n" \
22 " jump 4b\n" \
23 " nop\n" \
24 " .previous\n" \
25 " .section __ex_table,\"a\"\n" \
26 " .dword 2b,3b\n" \
27 " .previous\n" \
28 : "=r" (err) \
29 : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err))
30
31#define __put_user_asm_64(x, addr, err) do { \
32 int dummy_for_put_user_asm_64_; \
33 __asm__ __volatile__( \
34 "2: move.d %M2,[%1+]\n" \
35 "4: move.d %H2,[%1]\n" \
36 "5:\n" \
37 " .section .fixup,\"ax\"\n" \
38 "3: move.d %4,%0\n" \
39 " jump 5b\n" \
40 " .previous\n" \
41 " .section __ex_table,\"a\"\n" \
42 " .dword 2b,3b\n" \
43 " .dword 4b,3b\n" \
44 " .previous\n" \
45 : "=r" (err), "=b" (dummy_for_put_user_asm_64_) \
46 : "r" (x), "1" (addr), "g" (-EFAULT), \
47 "0" (err)); \
48 } while (0)
49
50/* See comment before __put_user_asm. */
51
52#define __get_user_asm(x, addr, err, op) \
53 __asm__ __volatile__( \
54 "2: "op" [%2],%1\n" \
55 "4:\n" \
56 " .section .fixup,\"ax\"\n" \
57 "3: move.d %3,%0\n" \
58 " jump 4b\n" \
59 " moveq 0,%1\n" \
60 " .previous\n" \
61 " .section __ex_table,\"a\"\n" \
62 " .dword 2b,3b\n" \
63 " .previous\n" \
64 : "=r" (err), "=r" (x) \
65 : "r" (addr), "g" (-EFAULT), "0" (err))
66
67#define __get_user_asm_64(x, addr, err) do { \
68 int dummy_for_get_user_asm_64_; \
69 __asm__ __volatile__( \
70 "2: move.d [%2+],%M1\n" \
71 "4: move.d [%2],%H1\n" \
72 "5:\n" \
73 " .section .fixup,\"ax\"\n" \
74 "3: move.d %4,%0\n" \
75 " jump 5b\n" \
76 " moveq 0,%1\n" \
77 " .previous\n" \
78 " .section __ex_table,\"a\"\n" \
79 " .dword 2b,3b\n" \
80 " .dword 4b,3b\n" \
81 " .previous\n" \
82 : "=r" (err), "=r" (x), \
83 "=b" (dummy_for_get_user_asm_64_) \
84 : "2" (addr), "g" (-EFAULT), "0" (err));\
85 } while (0)
86
87/*
88 * Copy a null terminated string from userspace.
89 *
90 * Must return:
91 * -EFAULT for an exception
92 * count if we hit the buffer limit
93 * bytes copied if we hit a null byte
94 * (without the null byte)
95 */
96extern inline long
97__do_strncpy_from_user(char *dst, const char *src, long count)
98{
99 long res;
100
101 if (count == 0)
102 return 0;
103
104 /*
105 * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop.
106 * So do we.
107 *
108 * This code is deduced from:
109 *
110 * char tmp2;
111 * long tmp1, tmp3;
112 * tmp1 = count;
113 * while ((*dst++ = (tmp2 = *src++)) != 0
114 * && --tmp1)
115 * ;
116 *
117 * res = count - tmp1;
118 *
119 * with tweaks.
120 */
121
122 __asm__ __volatile__ (
123 " move.d %3,%0\n"
124 "5: move.b [%2+],$acr\n"
125 "1: beq 2f\n"
126 " move.b $acr,[%1+]\n"
127
128 " subq 1,%0\n"
129 "2: bne 1b\n"
130 " move.b [%2+],$acr\n"
131
132 " sub.d %3,%0\n"
133 " neg.d %0,%0\n"
134 "3:\n"
135 " .section .fixup,\"ax\"\n"
136 "4: move.d %7,%0\n"
137 " jump 3b\n"
138 " nop\n"
139
140 /* The address for a fault at the first move is trivial.
141 The address for a fault at the second move is that of
142 the preceding branch insn, since the move insn is in
143 its delay-slot. That address is also a branch
144 target. Just so you don't get confused... */
145 " .previous\n"
146 " .section __ex_table,\"a\"\n"
147 " .dword 5b,4b\n"
148 " .dword 2b,4b\n"
149 " .previous"
150 : "=r" (res), "=b" (dst), "=b" (src), "=r" (count)
151 : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT)
152 : "acr");
153
154 return res;
155}
156
157/* A few copy asms to build up the more complex ones from.
158
159 Note again, a post-increment is performed regardless of whether a bus
160 fault occurred in that instruction, and PC for a faulted insn is the
161 address for the insn, or for the preceding branch when in a delay-slot. */
162
163#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \
164 __asm__ __volatile__ ( \
165 COPY \
166 "1:\n" \
167 " .section .fixup,\"ax\"\n" \
168 FIXUP \
169 " .previous\n" \
170 " .section __ex_table,\"a\"\n" \
171 TENTRY \
172 " .previous\n" \
173 : "=b" (to), "=b" (from), "=r" (ret) \
174 : "0" (to), "1" (from), "2" (ret) \
175 : "acr", "memory")
176
177#define __asm_copy_from_user_1(to, from, ret) \
178 __asm_copy_user_cont(to, from, ret, \
179 "2: move.b [%1+],$acr\n" \
180 " move.b $acr,[%0+]\n", \
181 "3: addq 1,%2\n" \
182 " jump 1b\n" \
183 " clear.b [%0+]\n", \
184 " .dword 2b,3b\n")
185
186#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
187 __asm_copy_user_cont(to, from, ret, \
188 COPY \
189 "2: move.w [%1+],$acr\n" \
190 " move.w $acr,[%0+]\n", \
191 FIXUP \
192 "3: addq 2,%2\n" \
193 " jump 1b\n" \
194 " clear.w [%0+]\n", \
195 TENTRY \
196 " .dword 2b,3b\n")
197
198#define __asm_copy_from_user_2(to, from, ret) \
199 __asm_copy_from_user_2x_cont(to, from, ret, "", "", "")
200
201#define __asm_copy_from_user_3(to, from, ret) \
202 __asm_copy_from_user_2x_cont(to, from, ret, \
203 "4: move.b [%1+],$acr\n" \
204 " move.b $acr,[%0+]\n", \
205 "5: addq 1,%2\n" \
206 " clear.b [%0+]\n", \
207 " .dword 4b,5b\n")
208
209#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
210 __asm_copy_user_cont(to, from, ret, \
211 COPY \
212 "2: move.d [%1+],$acr\n" \
213 " move.d $acr,[%0+]\n", \
214 FIXUP \
215 "3: addq 4,%2\n" \
216 " jump 1b\n" \
217 " clear.d [%0+]\n", \
218 TENTRY \
219 " .dword 2b,3b\n")
220
221#define __asm_copy_from_user_4(to, from, ret) \
222 __asm_copy_from_user_4x_cont(to, from, ret, "", "", "")
223
224#define __asm_copy_from_user_5(to, from, ret) \
225 __asm_copy_from_user_4x_cont(to, from, ret, \
226 "4: move.b [%1+],$acr\n" \
227 " move.b $acr,[%0+]\n", \
228 "5: addq 1,%2\n" \
229 " clear.b [%0+]\n", \
230 " .dword 4b,5b\n")
231
232#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
233 __asm_copy_from_user_4x_cont(to, from, ret, \
234 COPY \
235 "4: move.w [%1+],$acr\n" \
236 " move.w $acr,[%0+]\n", \
237 FIXUP \
238 "5: addq 2,%2\n" \
239 " clear.w [%0+]\n", \
240 TENTRY \
241 " .dword 4b,5b\n")
242
243#define __asm_copy_from_user_6(to, from, ret) \
244 __asm_copy_from_user_6x_cont(to, from, ret, "", "", "")
245
246#define __asm_copy_from_user_7(to, from, ret) \
247 __asm_copy_from_user_6x_cont(to, from, ret, \
248 "6: move.b [%1+],$acr\n" \
249 " move.b $acr,[%0+]\n", \
250 "7: addq 1,%2\n" \
251 " clear.b [%0+]\n", \
252 " .dword 6b,7b\n")
253
254#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
255 __asm_copy_from_user_4x_cont(to, from, ret, \
256 COPY \
257 "4: move.d [%1+],$acr\n" \
258 " move.d $acr,[%0+]\n", \
259 FIXUP \
260 "5: addq 4,%2\n" \
261 " clear.d [%0+]\n", \
262 TENTRY \
263 " .dword 4b,5b\n")
264
265#define __asm_copy_from_user_8(to, from, ret) \
266 __asm_copy_from_user_8x_cont(to, from, ret, "", "", "")
267
268#define __asm_copy_from_user_9(to, from, ret) \
269 __asm_copy_from_user_8x_cont(to, from, ret, \
270 "6: move.b [%1+],$acr\n" \
271 " move.b $acr,[%0+]\n", \
272 "7: addq 1,%2\n" \
273 " clear.b [%0+]\n", \
274 " .dword 6b,7b\n")
275
276#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
277 __asm_copy_from_user_8x_cont(to, from, ret, \
278 COPY \
279 "6: move.w [%1+],$acr\n" \
280 " move.w $acr,[%0+]\n", \
281 FIXUP \
282 "7: addq 2,%2\n" \
283 " clear.w [%0+]\n", \
284 TENTRY \
285 " .dword 6b,7b\n")
286
287#define __asm_copy_from_user_10(to, from, ret) \
288 __asm_copy_from_user_10x_cont(to, from, ret, "", "", "")
289
290#define __asm_copy_from_user_11(to, from, ret) \
291 __asm_copy_from_user_10x_cont(to, from, ret, \
292 "8: move.b [%1+],$acr\n" \
293 " move.b $acr,[%0+]\n", \
294 "9: addq 1,%2\n" \
295 " clear.b [%0+]\n", \
296 " .dword 8b,9b\n")
297
298#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
299 __asm_copy_from_user_8x_cont(to, from, ret, \
300 COPY \
301 "6: move.d [%1+],$acr\n" \
302 " move.d $acr,[%0+]\n", \
303 FIXUP \
304 "7: addq 4,%2\n" \
305 " clear.d [%0+]\n", \
306 TENTRY \
307 " .dword 6b,7b\n")
308
309#define __asm_copy_from_user_12(to, from, ret) \
310 __asm_copy_from_user_12x_cont(to, from, ret, "", "", "")
311
312#define __asm_copy_from_user_13(to, from, ret) \
313 __asm_copy_from_user_12x_cont(to, from, ret, \
314 "8: move.b [%1+],$acr\n" \
315 " move.b $acr,[%0+]\n", \
316 "9: addq 1,%2\n" \
317 " clear.b [%0+]\n", \
318 " .dword 8b,9b\n")
319
320#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
321 __asm_copy_from_user_12x_cont(to, from, ret, \
322 COPY \
323 "8: move.w [%1+],$acr\n" \
324 " move.w $acr,[%0+]\n", \
325 FIXUP \
326 "9: addq 2,%2\n" \
327 " clear.w [%0+]\n", \
328 TENTRY \
329 " .dword 8b,9b\n")
330
331#define __asm_copy_from_user_14(to, from, ret) \
332 __asm_copy_from_user_14x_cont(to, from, ret, "", "", "")
333
334#define __asm_copy_from_user_15(to, from, ret) \
335 __asm_copy_from_user_14x_cont(to, from, ret, \
336 "10: move.b [%1+],$acr\n" \
337 " move.b $acr,[%0+]\n", \
338 "11: addq 1,%2\n" \
339 " clear.b [%0+]\n", \
340 " .dword 10b,11b\n")
341
342#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
343 __asm_copy_from_user_12x_cont(to, from, ret, \
344 COPY \
345 "8: move.d [%1+],$acr\n" \
346 " move.d $acr,[%0+]\n", \
347 FIXUP \
348 "9: addq 4,%2\n" \
349 " clear.d [%0+]\n", \
350 TENTRY \
351 " .dword 8b,9b\n")
352
353#define __asm_copy_from_user_16(to, from, ret) \
354 __asm_copy_from_user_16x_cont(to, from, ret, "", "", "")
355
356#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
357 __asm_copy_from_user_16x_cont(to, from, ret, \
358 COPY \
359 "10: move.d [%1+],$acr\n" \
360 " move.d $acr,[%0+]\n", \
361 FIXUP \
362 "11: addq 4,%2\n" \
363 " clear.d [%0+]\n", \
364 TENTRY \
365 " .dword 10b,11b\n")
366
367#define __asm_copy_from_user_20(to, from, ret) \
368 __asm_copy_from_user_20x_cont(to, from, ret, "", "", "")
369
370#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
371 __asm_copy_from_user_20x_cont(to, from, ret, \
372 COPY \
373 "12: move.d [%1+],$acr\n" \
374 " move.d $acr,[%0+]\n", \
375 FIXUP \
376 "13: addq 4,%2\n" \
377 " clear.d [%0+]\n", \
378 TENTRY \
379 " .dword 12b,13b\n")
380
381#define __asm_copy_from_user_24(to, from, ret) \
382 __asm_copy_from_user_24x_cont(to, from, ret, "", "", "")
383
384/* And now, the to-user ones. */
385
386#define __asm_copy_to_user_1(to, from, ret) \
387 __asm_copy_user_cont(to, from, ret, \
388 " move.b [%1+],$acr\n" \
389 "2: move.b $acr,[%0+]\n", \
390 "3: jump 1b\n" \
391 " addq 1,%2\n", \
392 " .dword 2b,3b\n")
393
394#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
395 __asm_copy_user_cont(to, from, ret, \
396 COPY \
397 " move.w [%1+],$acr\n" \
398 "2: move.w $acr,[%0+]\n", \
399 FIXUP \
400 "3: jump 1b\n" \
401 " addq 2,%2\n", \
402 TENTRY \
403 " .dword 2b,3b\n")
404
405#define __asm_copy_to_user_2(to, from, ret) \
406 __asm_copy_to_user_2x_cont(to, from, ret, "", "", "")
407
408#define __asm_copy_to_user_3(to, from, ret) \
409 __asm_copy_to_user_2x_cont(to, from, ret, \
410 " move.b [%1+],$acr\n" \
411 "4: move.b $acr,[%0+]\n", \
412 "5: addq 1,%2\n", \
413 " .dword 4b,5b\n")
414
415#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
416 __asm_copy_user_cont(to, from, ret, \
417 COPY \
418 " move.d [%1+],$acr\n" \
419 "2: move.d $acr,[%0+]\n", \
420 FIXUP \
421 "3: jump 1b\n" \
422 " addq 4,%2\n", \
423 TENTRY \
424 " .dword 2b,3b\n")
425
426#define __asm_copy_to_user_4(to, from, ret) \
427 __asm_copy_to_user_4x_cont(to, from, ret, "", "", "")
428
429#define __asm_copy_to_user_5(to, from, ret) \
430 __asm_copy_to_user_4x_cont(to, from, ret, \
431 " move.b [%1+],$acr\n" \
432 "4: move.b $acr,[%0+]\n", \
433 "5: addq 1,%2\n", \
434 " .dword 4b,5b\n")
435
436#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
437 __asm_copy_to_user_4x_cont(to, from, ret, \
438 COPY \
439 " move.w [%1+],$acr\n" \
440 "4: move.w $acr,[%0+]\n", \
441 FIXUP \
442 "5: addq 2,%2\n", \
443 TENTRY \
444 " .dword 4b,5b\n")
445
446#define __asm_copy_to_user_6(to, from, ret) \
447 __asm_copy_to_user_6x_cont(to, from, ret, "", "", "")
448
449#define __asm_copy_to_user_7(to, from, ret) \
450 __asm_copy_to_user_6x_cont(to, from, ret, \
451 " move.b [%1+],$acr\n" \
452 "6: move.b $acr,[%0+]\n", \
453 "7: addq 1,%2\n", \
454 " .dword 6b,7b\n")
455
456#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
457 __asm_copy_to_user_4x_cont(to, from, ret, \
458 COPY \
459 " move.d [%1+],$acr\n" \
460 "4: move.d $acr,[%0+]\n", \
461 FIXUP \
462 "5: addq 4,%2\n", \
463 TENTRY \
464 " .dword 4b,5b\n")
465
466#define __asm_copy_to_user_8(to, from, ret) \
467 __asm_copy_to_user_8x_cont(to, from, ret, "", "", "")
468
469#define __asm_copy_to_user_9(to, from, ret) \
470 __asm_copy_to_user_8x_cont(to, from, ret, \
471 " move.b [%1+],$acr\n" \
472 "6: move.b $acr,[%0+]\n", \
473 "7: addq 1,%2\n", \
474 " .dword 6b,7b\n")
475
476#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
477 __asm_copy_to_user_8x_cont(to, from, ret, \
478 COPY \
479 " move.w [%1+],$acr\n" \
480 "6: move.w $acr,[%0+]\n", \
481 FIXUP \
482 "7: addq 2,%2\n", \
483 TENTRY \
484 " .dword 6b,7b\n")
485
486#define __asm_copy_to_user_10(to, from, ret) \
487 __asm_copy_to_user_10x_cont(to, from, ret, "", "", "")
488
489#define __asm_copy_to_user_11(to, from, ret) \
490 __asm_copy_to_user_10x_cont(to, from, ret, \
491 " move.b [%1+],$acr\n" \
492 "8: move.b $acr,[%0+]\n", \
493 "9: addq 1,%2\n", \
494 " .dword 8b,9b\n")
495
496#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
497 __asm_copy_to_user_8x_cont(to, from, ret, \
498 COPY \
499 " move.d [%1+],$acr\n" \
500 "6: move.d $acr,[%0+]\n", \
501 FIXUP \
502 "7: addq 4,%2\n", \
503 TENTRY \
504 " .dword 6b,7b\n")
505
506#define __asm_copy_to_user_12(to, from, ret) \
507 __asm_copy_to_user_12x_cont(to, from, ret, "", "", "")
508
509#define __asm_copy_to_user_13(to, from, ret) \
510 __asm_copy_to_user_12x_cont(to, from, ret, \
511 " move.b [%1+],$acr\n" \
512 "8: move.b $acr,[%0+]\n", \
513 "9: addq 1,%2\n", \
514 " .dword 8b,9b\n")
515
516#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
517 __asm_copy_to_user_12x_cont(to, from, ret, \
518 COPY \
519 " move.w [%1+],$acr\n" \
520 "8: move.w $acr,[%0+]\n", \
521 FIXUP \
522 "9: addq 2,%2\n", \
523 TENTRY \
524 " .dword 8b,9b\n")
525
526#define __asm_copy_to_user_14(to, from, ret) \
527 __asm_copy_to_user_14x_cont(to, from, ret, "", "", "")
528
529#define __asm_copy_to_user_15(to, from, ret) \
530 __asm_copy_to_user_14x_cont(to, from, ret, \
531 " move.b [%1+],$acr\n" \
532 "10: move.b $acr,[%0+]\n", \
533 "11: addq 1,%2\n", \
534 " .dword 10b,11b\n")
535
536#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
537 __asm_copy_to_user_12x_cont(to, from, ret, \
538 COPY \
539 " move.d [%1+],$acr\n" \
540 "8: move.d $acr,[%0+]\n", \
541 FIXUP \
542 "9: addq 4,%2\n", \
543 TENTRY \
544 " .dword 8b,9b\n")
545
546#define __asm_copy_to_user_16(to, from, ret) \
547 __asm_copy_to_user_16x_cont(to, from, ret, "", "", "")
548
549#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
550 __asm_copy_to_user_16x_cont(to, from, ret, \
551 COPY \
552 " move.d [%1+],$acr\n" \
553 "10: move.d $acr,[%0+]\n", \
554 FIXUP \
555 "11: addq 4,%2\n", \
556 TENTRY \
557 " .dword 10b,11b\n")
558
559#define __asm_copy_to_user_20(to, from, ret) \
560 __asm_copy_to_user_20x_cont(to, from, ret, "", "", "")
561
562#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
563 __asm_copy_to_user_20x_cont(to, from, ret, \
564 COPY \
565 " move.d [%1+],$acr\n" \
566 "12: move.d $acr,[%0+]\n", \
567 FIXUP \
568 "13: addq 4,%2\n", \
569 TENTRY \
570 " .dword 12b,13b\n")
571
572#define __asm_copy_to_user_24(to, from, ret) \
573 __asm_copy_to_user_24x_cont(to, from, ret, "", "", "")
574
575/* Define a few clearing asms with exception handlers. */
576
577/* This frame-asm is like the __asm_copy_user_cont one, but has one less
578 input. */
579
580#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \
581 __asm__ __volatile__ ( \
582 CLEAR \
583 "1:\n" \
584 " .section .fixup,\"ax\"\n" \
585 FIXUP \
586 " .previous\n" \
587 " .section __ex_table,\"a\"\n" \
588 TENTRY \
589 " .previous" \
590 : "=b" (to), "=r" (ret) \
591 : "0" (to), "1" (ret) \
592 : "memory")
593
594#define __asm_clear_1(to, ret) \
595 __asm_clear(to, ret, \
596 "2: clear.b [%0+]\n", \
597 "3: jump 1b\n" \
598 " addq 1,%1\n", \
599 " .dword 2b,3b\n")
600
601#define __asm_clear_2(to, ret) \
602 __asm_clear(to, ret, \
603 "2: clear.w [%0+]\n", \
604 "3: jump 1b\n" \
605 " addq 2,%1\n", \
606 " .dword 2b,3b\n")
607
608#define __asm_clear_3(to, ret) \
609 __asm_clear(to, ret, \
610 "2: clear.w [%0+]\n" \
611 "3: clear.b [%0+]\n", \
612 "4: addq 2,%1\n" \
613 "5: jump 1b\n" \
614 " addq 1,%1\n", \
615 " .dword 2b,4b\n" \
616 " .dword 3b,5b\n")
617
618#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
619 __asm_clear(to, ret, \
620 CLEAR \
621 "2: clear.d [%0+]\n", \
622 FIXUP \
623 "3: jump 1b\n" \
624 " addq 4,%1\n", \
625 TENTRY \
626 " .dword 2b,3b\n")
627
628#define __asm_clear_4(to, ret) \
629 __asm_clear_4x_cont(to, ret, "", "", "")
630
631#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
632 __asm_clear_4x_cont(to, ret, \
633 CLEAR \
634 "4: clear.d [%0+]\n", \
635 FIXUP \
636 "5: addq 4,%1\n", \
637 TENTRY \
638 " .dword 4b,5b\n")
639
640#define __asm_clear_8(to, ret) \
641 __asm_clear_8x_cont(to, ret, "", "", "")
642
643#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
644 __asm_clear_8x_cont(to, ret, \
645 CLEAR \
646 "6: clear.d [%0+]\n", \
647 FIXUP \
648 "7: addq 4,%1\n", \
649 TENTRY \
650 " .dword 6b,7b\n")
651
652#define __asm_clear_12(to, ret) \
653 __asm_clear_12x_cont(to, ret, "", "", "")
654
655#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
656 __asm_clear_12x_cont(to, ret, \
657 CLEAR \
658 "8: clear.d [%0+]\n", \
659 FIXUP \
660 "9: addq 4,%1\n", \
661 TENTRY \
662 " .dword 8b,9b\n")
663
664#define __asm_clear_16(to, ret) \
665 __asm_clear_16x_cont(to, ret, "", "", "")
666
667#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
668 __asm_clear_16x_cont(to, ret, \
669 CLEAR \
670 "10: clear.d [%0+]\n", \
671 FIXUP \
672 "11: addq 4,%1\n", \
673 TENTRY \
674 " .dword 10b,11b\n")
675
676#define __asm_clear_20(to, ret) \
677 __asm_clear_20x_cont(to, ret, "", "", "")
678
679#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
680 __asm_clear_20x_cont(to, ret, \
681 CLEAR \
682 "12: clear.d [%0+]\n", \
683 FIXUP \
684 "13: addq 4,%1\n", \
685 TENTRY \
686 " .dword 12b,13b\n")
687
688#define __asm_clear_24(to, ret) \
689 __asm_clear_24x_cont(to, ret, "", "", "")
690
691/*
692 * Return the size of a string (including the ending 0)
693 *
694 * Return length of string in userspace including terminating 0
695 * or 0 for error. Return a value greater than N if too long.
696 */
697
698extern inline long
699strnlen_user(const char *s, long n)
700{
701 long res, tmp1;
702
703 if (!access_ok(VERIFY_READ, s, 0))
704 return 0;
705
706 /*
707 * This code is deduced from:
708 *
709 * tmp1 = n;
710 * while (tmp1-- > 0 && *s++)
711 * ;
712 *
713 * res = n - tmp1;
714 *
715 * (with tweaks).
716 */
717
718 __asm__ __volatile__ (
719 " move.d %1,$acr\n"
720 " cmpq 0,$acr\n"
721 "0:\n"
722 " ble 1f\n"
723 " subq 1,$acr\n"
724
725 "4: test.b [%0+]\n"
726 " bne 0b\n"
727 " cmpq 0,$acr\n"
728 "1:\n"
729 " move.d %1,%0\n"
730 " sub.d $acr,%0\n"
731 "2:\n"
732 " .section .fixup,\"ax\"\n"
733
734 "3: jump 2b\n"
735 " clear.d %0\n"
736
737 " .previous\n"
738 " .section __ex_table,\"a\"\n"
739 " .dword 4b,3b\n"
740 " .previous\n"
741 : "=r" (res), "=r" (tmp1)
742 : "0" (s), "1" (n)
743 : "acr");
744
745 return res;
746}
747
748#endif
diff --git a/include/asm-cris/arch-v32/unistd.h b/include/asm-cris/arch-v32/unistd.h
new file mode 100644
index 000000000000..5d369d4439d9
--- /dev/null
+++ b/include/asm-cris/arch-v32/unistd.h
@@ -0,0 +1,148 @@
1#ifndef _ASM_CRIS_ARCH_UNISTD_H_
2#define _ASM_CRIS_ARCH_UNISTD_H_
3
4/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
5/*
6 * Don't remove the .ifnc tests; they are an insurance against
7 * any hard-to-spot gcc register allocation bugs.
8 */
9#define _syscall0(type,name) \
10type name(void) \
11{ \
12 register long __a __asm__ ("r10"); \
13 register long __n_ __asm__ ("r9") = (__NR_##name); \
14 __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
15 ".err\n\t" \
16 ".endif\n\t" \
17 "break 13" \
18 : "=r" (__a) \
19 : "r" (__n_)); \
20 if (__a >= 0) \
21 return (type) __a; \
22 errno = -__a; \
23 return (type) -1; \
24}
25
26#define _syscall1(type,name,type1,arg1) \
27type name(type1 arg1) \
28{ \
29 register long __a __asm__ ("r10") = (long) arg1; \
30 register long __n_ __asm__ ("r9") = (__NR_##name); \
31 __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
32 ".err\n\t" \
33 ".endif\n\t" \
34 "break 13" \
35 : "=r" (__a) \
36 : "r" (__n_), "0" (__a)); \
37 if (__a >= 0) \
38 return (type) __a; \
39 errno = -__a; \
40 return (type) -1; \
41}
42
43#define _syscall2(type,name,type1,arg1,type2,arg2) \
44type name(type1 arg1,type2 arg2) \
45{ \
46 register long __a __asm__ ("r10") = (long) arg1; \
47 register long __b __asm__ ("r11") = (long) arg2; \
48 register long __n_ __asm__ ("r9") = (__NR_##name); \
49 __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \
50 ".err\n\t" \
51 ".endif\n\t" \
52 "break 13" \
53 : "=r" (__a) \
54 : "r" (__n_), "0" (__a), "r" (__b)); \
55 if (__a >= 0) \
56 return (type) __a; \
57 errno = -__a; \
58 return (type) -1; \
59}
60
61#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
62type name(type1 arg1,type2 arg2,type3 arg3) \
63{ \
64 register long __a __asm__ ("r10") = (long) arg1; \
65 register long __b __asm__ ("r11") = (long) arg2; \
66 register long __c __asm__ ("r12") = (long) arg3; \
67 register long __n_ __asm__ ("r9") = (__NR_##name); \
68 __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \
69 ".err\n\t" \
70 ".endif\n\t" \
71 "break 13" \
72 : "=r" (__a) \
73 : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \
74 if (__a >= 0) \
75 return (type) __a; \
76 errno = -__a; \
77 return (type) -1; \
78}
79
80#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
81type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
82{ \
83 register long __a __asm__ ("r10") = (long) arg1; \
84 register long __b __asm__ ("r11") = (long) arg2; \
85 register long __c __asm__ ("r12") = (long) arg3; \
86 register long __d __asm__ ("r13") = (long) arg4; \
87 register long __n_ __asm__ ("r9") = (__NR_##name); \
88 __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
89 ".err\n\t" \
90 ".endif\n\t" \
91 "break 13" \
92 : "=r" (__a) \
93 : "r" (__n_), "0" (__a), "r" (__b), \
94 "r" (__c), "r" (__d)); \
95 if (__a >= 0) \
96 return (type) __a; \
97 errno = -__a; \
98 return (type) -1; \
99}
100
101#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
102 type5,arg5) \
103type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \
104{ \
105 register long __a __asm__ ("r10") = (long) arg1; \
106 register long __b __asm__ ("r11") = (long) arg2; \
107 register long __c __asm__ ("r12") = (long) arg3; \
108 register long __d __asm__ ("r13") = (long) arg4; \
109 register long __e __asm__ ("mof") = (long) arg5; \
110 register long __n_ __asm__ ("r9") = (__NR_##name); \
111 __asm__ __volatile__ (".ifnc %0%1%3%4%5%6,$r10$r9$r11$r12$r13$mof\n\t" \
112 ".err\n\t" \
113 ".endif\n\t" \
114 "break 13" \
115 : "=r" (__a) \
116 : "r" (__n_), "0" (__a), "r" (__b), \
117 "r" (__c), "r" (__d), "h" (__e)); \
118 if (__a >= 0) \
119 return (type) __a; \
120 errno = -__a; \
121 return (type) -1; \
122}
123
124#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
125 type5,arg5,type6,arg6) \
126type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \
127{ \
128 register long __a __asm__ ("r10") = (long) arg1; \
129 register long __b __asm__ ("r11") = (long) arg2; \
130 register long __c __asm__ ("r12") = (long) arg3; \
131 register long __d __asm__ ("r13") = (long) arg4; \
132 register long __e __asm__ ("mof") = (long) arg5; \
133 register long __f __asm__ ("srp") = (long) arg6; \
134 register long __n_ __asm__ ("r9") = (__NR_##name); \
135 __asm__ __volatile__ (".ifnc %0%1%3%4%5%6%7,$r10$r9$r11$r12$r13$mof$srp\n\t" \
136 ".err\n\t" \
137 ".endif\n\t" \
138 "break 13" \
139 : "=r" (__a) \
140 : "r" (__n_), "0" (__a), "r" (__b), \
141 "r" (__c), "r" (__d), "h" (__e), "x" (__f)); \
142 if (__a >= 0) \
143 return (type) __a; \
144 errno = -__a; \
145 return (type) -1; \
146}
147
148#endif
diff --git a/include/asm-cris/arch-v32/user.h b/include/asm-cris/arch-v32/user.h
new file mode 100644
index 000000000000..03fa1f3c3c00
--- /dev/null
+++ b/include/asm-cris/arch-v32/user.h
@@ -0,0 +1,41 @@
1#ifndef _ASM_CRIS_ARCH_USER_H
2#define _ASM_CRIS_ARCH_USER_H
3
4/* User-mode register used for core dumps. */
5
6struct user_regs_struct {
7 unsigned long r0; /* General registers. */
8 unsigned long r1;
9 unsigned long r2;
10 unsigned long r3;
11 unsigned long r4;
12 unsigned long r5;
13 unsigned long r6;
14 unsigned long r7;
15 unsigned long r8;
16 unsigned long r9;
17 unsigned long r10;
18 unsigned long r11;
19 unsigned long r12;
20 unsigned long r13;
21 unsigned long sp; /* R14, Stack pointer. */
22 unsigned long acr; /* R15, Address calculation register. */
23 unsigned long bz; /* P0, Constant zero (8-bits). */
24 unsigned long vr; /* P1, Version register (8-bits). */
25 unsigned long pid; /* P2, Process ID (8-bits). */
26 unsigned long srs; /* P3, Support register select (8-bits). */
27 unsigned long wz; /* P4, Constant zero (16-bits). */
28 unsigned long exs; /* P5, Exception status. */
29 unsigned long eda; /* P6, Exception data address. */
30 unsigned long mof; /* P7, Multiply overflow regiter. */
31 unsigned long dz; /* P8, Constant zero (32-bits). */
32 unsigned long ebp; /* P9, Exception base pointer. */
33 unsigned long erp; /* P10, Exception return pointer. */
34 unsigned long srp; /* P11, Subroutine return pointer. */
35 unsigned long nrp; /* P12, NMI return pointer. */
36 unsigned long ccs; /* P13, Condition code stack. */
37 unsigned long usp; /* P14, User mode stack pointer. */
38 unsigned long spc; /* P15, Single step PC. */
39};
40
41#endif /* _ASM_CRIS_ARCH_USER_H */
diff --git a/include/asm-cris/atomic.h b/include/asm-cris/atomic.h
index b3dfea5a71e4..70605b09e8b7 100644
--- a/include/asm-cris/atomic.h
+++ b/include/asm-cris/atomic.h
@@ -4,21 +4,14 @@
4#define __ASM_CRIS_ATOMIC__ 4#define __ASM_CRIS_ATOMIC__
5 5
6#include <asm/system.h> 6#include <asm/system.h>
7#include <asm/arch/atomic.h>
7 8
8/* 9/*
9 * Atomic operations that C can't guarantee us. Useful for 10 * Atomic operations that C can't guarantee us. Useful for
10 * resource counting etc.. 11 * resource counting etc..
11 */ 12 */
12 13
13/* 14typedef struct { volatile int counter; } atomic_t;
14 * Make sure gcc doesn't try to be clever and move things around
15 * on us. We need to use _exactly_ the address the user gave us,
16 * not some alias that contains the same information.
17 */
18
19#define __atomic_fool_gcc(x) (*(struct { int a[100]; } *)x)
20
21typedef struct { int counter; } atomic_t;
22 15
23#define ATOMIC_INIT(i) { (i) } 16#define ATOMIC_INIT(i) { (i) }
24 17
@@ -30,29 +23,26 @@ typedef struct { int counter; } atomic_t;
30extern __inline__ void atomic_add(int i, volatile atomic_t *v) 23extern __inline__ void atomic_add(int i, volatile atomic_t *v)
31{ 24{
32 unsigned long flags; 25 unsigned long flags;
33 local_save_flags(flags); 26 cris_atomic_save(v, flags);
34 local_irq_disable();
35 v->counter += i; 27 v->counter += i;
36 local_irq_restore(flags); 28 cris_atomic_restore(v, flags);
37} 29}
38 30
39extern __inline__ void atomic_sub(int i, volatile atomic_t *v) 31extern __inline__ void atomic_sub(int i, volatile atomic_t *v)
40{ 32{
41 unsigned long flags; 33 unsigned long flags;
42 local_save_flags(flags); 34 cris_atomic_save(v, flags);
43 local_irq_disable();
44 v->counter -= i; 35 v->counter -= i;
45 local_irq_restore(flags); 36 cris_atomic_restore(v, flags);
46} 37}
47 38
48extern __inline__ int atomic_add_return(int i, volatile atomic_t *v) 39extern __inline__ int atomic_add_return(int i, volatile atomic_t *v)
49{ 40{
50 unsigned long flags; 41 unsigned long flags;
51 int retval; 42 int retval;
52 local_save_flags(flags); 43 cris_atomic_save(v, flags);
53 local_irq_disable();
54 retval = (v->counter += i); 44 retval = (v->counter += i);
55 local_irq_restore(flags); 45 cris_atomic_restore(v, flags);
56 return retval; 46 return retval;
57} 47}
58 48
@@ -62,10 +52,9 @@ extern __inline__ int atomic_sub_return(int i, volatile atomic_t *v)
62{ 52{
63 unsigned long flags; 53 unsigned long flags;
64 int retval; 54 int retval;
65 local_save_flags(flags); 55 cris_atomic_save(v, flags);
66 local_irq_disable();
67 retval = (v->counter -= i); 56 retval = (v->counter -= i);
68 local_irq_restore(flags); 57 cris_atomic_restore(v, flags);
69 return retval; 58 return retval;
70} 59}
71 60
@@ -73,39 +62,35 @@ extern __inline__ int atomic_sub_and_test(int i, volatile atomic_t *v)
73{ 62{
74 int retval; 63 int retval;
75 unsigned long flags; 64 unsigned long flags;
76 local_save_flags(flags); 65 cris_atomic_save(v, flags);
77 local_irq_disable();
78 retval = (v->counter -= i) == 0; 66 retval = (v->counter -= i) == 0;
79 local_irq_restore(flags); 67 cris_atomic_restore(v, flags);
80 return retval; 68 return retval;
81} 69}
82 70
83extern __inline__ void atomic_inc(volatile atomic_t *v) 71extern __inline__ void atomic_inc(volatile atomic_t *v)
84{ 72{
85 unsigned long flags; 73 unsigned long flags;
86 local_save_flags(flags); 74 cris_atomic_save(v, flags);
87 local_irq_disable();
88 (v->counter)++; 75 (v->counter)++;
89 local_irq_restore(flags); 76 cris_atomic_restore(v, flags);
90} 77}
91 78
92extern __inline__ void atomic_dec(volatile atomic_t *v) 79extern __inline__ void atomic_dec(volatile atomic_t *v)
93{ 80{
94 unsigned long flags; 81 unsigned long flags;
95 local_save_flags(flags); 82 cris_atomic_save(v, flags);
96 local_irq_disable();
97 (v->counter)--; 83 (v->counter)--;
98 local_irq_restore(flags); 84 cris_atomic_restore(v, flags);
99} 85}
100 86
101extern __inline__ int atomic_inc_return(volatile atomic_t *v) 87extern __inline__ int atomic_inc_return(volatile atomic_t *v)
102{ 88{
103 unsigned long flags; 89 unsigned long flags;
104 int retval; 90 int retval;
105 local_save_flags(flags); 91 cris_atomic_save(v, flags);
106 local_irq_disable();
107 retval = (v->counter)++; 92 retval = (v->counter)++;
108 local_irq_restore(flags); 93 cris_atomic_restore(v, flags);
109 return retval; 94 return retval;
110} 95}
111 96
@@ -113,20 +98,18 @@ extern __inline__ int atomic_dec_return(volatile atomic_t *v)
113{ 98{
114 unsigned long flags; 99 unsigned long flags;
115 int retval; 100 int retval;
116 local_save_flags(flags); 101 cris_atomic_save(v, flags);
117 local_irq_disable();
118 retval = (v->counter)--; 102 retval = (v->counter)--;
119 local_irq_restore(flags); 103 cris_atomic_restore(v, flags);
120 return retval; 104 return retval;
121} 105}
122extern __inline__ int atomic_dec_and_test(volatile atomic_t *v) 106extern __inline__ int atomic_dec_and_test(volatile atomic_t *v)
123{ 107{
124 int retval; 108 int retval;
125 unsigned long flags; 109 unsigned long flags;
126 local_save_flags(flags); 110 cris_atomic_save(v, flags);
127 local_irq_disable();
128 retval = --(v->counter) == 0; 111 retval = --(v->counter) == 0;
129 local_irq_restore(flags); 112 cris_atomic_restore(v, flags);
130 return retval; 113 return retval;
131} 114}
132 115
@@ -134,10 +117,9 @@ extern __inline__ int atomic_inc_and_test(volatile atomic_t *v)
134{ 117{
135 int retval; 118 int retval;
136 unsigned long flags; 119 unsigned long flags;
137 local_save_flags(flags); 120 cris_atomic_save(v, flags);
138 local_irq_disable();
139 retval = ++(v->counter) == 0; 121 retval = ++(v->counter) == 0;
140 local_irq_restore(flags); 122 cris_atomic_restore(v, flags);
141 return retval; 123 return retval;
142} 124}
143 125
diff --git a/include/asm-cris/axisflashmap.h b/include/asm-cris/axisflashmap.h
index 600bb8715d89..7a8d3114e682 100644
--- a/include/asm-cris/axisflashmap.h
+++ b/include/asm-cris/axisflashmap.h
@@ -40,4 +40,7 @@ struct partitiontable_entry {
40#define PARTITION_TYPE_KERNEL 0x0002 40#define PARTITION_TYPE_KERNEL 0x0002
41#define PARTITION_TYPE_JFFS 0x0003 41#define PARTITION_TYPE_JFFS 0x0003
42 42
43/* The master mtd for the entire flash. */
44extern struct mtd_info* axisflash_mtd;
45
43#endif 46#endif
diff --git a/include/asm-cris/bitops.h b/include/asm-cris/bitops.h
index d7861115d731..e3da57f97964 100644
--- a/include/asm-cris/bitops.h
+++ b/include/asm-cris/bitops.h
@@ -16,6 +16,7 @@
16 16
17#include <asm/arch/bitops.h> 17#include <asm/arch/bitops.h>
18#include <asm/system.h> 18#include <asm/system.h>
19#include <asm/atomic.h>
19#include <linux/compiler.h> 20#include <linux/compiler.h>
20 21
21/* 22/*
@@ -88,7 +89,7 @@ struct __dummy { unsigned long a[100]; };
88 * It also implies a memory barrier. 89 * It also implies a memory barrier.
89 */ 90 */
90 91
91extern inline int test_and_set_bit(int nr, void *addr) 92extern inline int test_and_set_bit(int nr, volatile unsigned long *addr)
92{ 93{
93 unsigned int mask, retval; 94 unsigned int mask, retval;
94 unsigned long flags; 95 unsigned long flags;
@@ -96,15 +97,15 @@ extern inline int test_and_set_bit(int nr, void *addr)
96 97
97 adr += nr >> 5; 98 adr += nr >> 5;
98 mask = 1 << (nr & 0x1f); 99 mask = 1 << (nr & 0x1f);
99 local_save_flags(flags); 100 cris_atomic_save(addr, flags);
100 local_irq_disable();
101 retval = (mask & *adr) != 0; 101 retval = (mask & *adr) != 0;
102 *adr |= mask; 102 *adr |= mask;
103 cris_atomic_restore(addr, flags);
103 local_irq_restore(flags); 104 local_irq_restore(flags);
104 return retval; 105 return retval;
105} 106}
106 107
107extern inline int __test_and_set_bit(int nr, void *addr) 108extern inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
108{ 109{
109 unsigned int mask, retval; 110 unsigned int mask, retval;
110 unsigned int *adr = (unsigned int *)addr; 111 unsigned int *adr = (unsigned int *)addr;
@@ -131,7 +132,7 @@ extern inline int __test_and_set_bit(int nr, void *addr)
131 * It also implies a memory barrier. 132 * It also implies a memory barrier.
132 */ 133 */
133 134
134extern inline int test_and_clear_bit(int nr, void *addr) 135extern inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
135{ 136{
136 unsigned int mask, retval; 137 unsigned int mask, retval;
137 unsigned long flags; 138 unsigned long flags;
@@ -139,11 +140,10 @@ extern inline int test_and_clear_bit(int nr, void *addr)
139 140
140 adr += nr >> 5; 141 adr += nr >> 5;
141 mask = 1 << (nr & 0x1f); 142 mask = 1 << (nr & 0x1f);
142 local_save_flags(flags); 143 cris_atomic_save(addr, flags);
143 local_irq_disable();
144 retval = (mask & *adr) != 0; 144 retval = (mask & *adr) != 0;
145 *adr &= ~mask; 145 *adr &= ~mask;
146 local_irq_restore(flags); 146 cris_atomic_restore(addr, flags);
147 return retval; 147 return retval;
148} 148}
149 149
@@ -157,7 +157,7 @@ extern inline int test_and_clear_bit(int nr, void *addr)
157 * but actually fail. You must protect multiple accesses with a lock. 157 * but actually fail. You must protect multiple accesses with a lock.
158 */ 158 */
159 159
160extern inline int __test_and_clear_bit(int nr, void *addr) 160extern inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
161{ 161{
162 unsigned int mask, retval; 162 unsigned int mask, retval;
163 unsigned int *adr = (unsigned int *)addr; 163 unsigned int *adr = (unsigned int *)addr;
@@ -177,24 +177,23 @@ extern inline int __test_and_clear_bit(int nr, void *addr)
177 * It also implies a memory barrier. 177 * It also implies a memory barrier.
178 */ 178 */
179 179
180extern inline int test_and_change_bit(int nr, void *addr) 180extern inline int test_and_change_bit(int nr, volatile unsigned long *addr)
181{ 181{
182 unsigned int mask, retval; 182 unsigned int mask, retval;
183 unsigned long flags; 183 unsigned long flags;
184 unsigned int *adr = (unsigned int *)addr; 184 unsigned int *adr = (unsigned int *)addr;
185 adr += nr >> 5; 185 adr += nr >> 5;
186 mask = 1 << (nr & 0x1f); 186 mask = 1 << (nr & 0x1f);
187 local_save_flags(flags); 187 cris_atomic_save(addr, flags);
188 local_irq_disable();
189 retval = (mask & *adr) != 0; 188 retval = (mask & *adr) != 0;
190 *adr ^= mask; 189 *adr ^= mask;
191 local_irq_restore(flags); 190 cris_atomic_restore(addr, flags);
192 return retval; 191 return retval;
193} 192}
194 193
195/* WARNING: non atomic and it can be reordered! */ 194/* WARNING: non atomic and it can be reordered! */
196 195
197extern inline int __test_and_change_bit(int nr, void *addr) 196extern inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
198{ 197{
199 unsigned int mask, retval; 198 unsigned int mask, retval;
200 unsigned int *adr = (unsigned int *)addr; 199 unsigned int *adr = (unsigned int *)addr;
@@ -215,7 +214,7 @@ extern inline int __test_and_change_bit(int nr, void *addr)
215 * This routine doesn't need to be atomic. 214 * This routine doesn't need to be atomic.
216 */ 215 */
217 216
218extern inline int test_bit(int nr, const void *addr) 217extern inline int test_bit(int nr, const volatile unsigned long *addr)
219{ 218{
220 unsigned int mask; 219 unsigned int mask;
221 unsigned int *adr = (unsigned int *)addr; 220 unsigned int *adr = (unsigned int *)addr;
@@ -259,7 +258,7 @@ extern inline int test_bit(int nr, const void *addr)
259 * @offset: The bitnumber to start searching at 258 * @offset: The bitnumber to start searching at
260 * @size: The maximum size to search 259 * @size: The maximum size to search
261 */ 260 */
262extern inline int find_next_zero_bit (void * addr, int size, int offset) 261extern inline int find_next_zero_bit (const unsigned long * addr, int size, int offset)
263{ 262{
264 unsigned long *p = ((unsigned long *) addr) + (offset >> 5); 263 unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
265 unsigned long result = offset & ~31UL; 264 unsigned long result = offset & ~31UL;
@@ -301,7 +300,7 @@ extern inline int find_next_zero_bit (void * addr, int size, int offset)
301 * @offset: The bitnumber to start searching at 300 * @offset: The bitnumber to start searching at
302 * @size: The maximum size to search 301 * @size: The maximum size to search
303 */ 302 */
304static __inline__ int find_next_bit(void *addr, int size, int offset) 303static __inline__ int find_next_bit(const unsigned long *addr, int size, int offset)
305{ 304{
306 unsigned long *p = ((unsigned long *) addr) + (offset >> 5); 305 unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
307 unsigned long result = offset & ~31UL; 306 unsigned long result = offset & ~31UL;
@@ -367,7 +366,7 @@ found_middle:
367#define minix_test_bit(nr,addr) test_bit(nr,addr) 366#define minix_test_bit(nr,addr) test_bit(nr,addr)
368#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) 367#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
369 368
370extern inline int sched_find_first_bit(unsigned long *b) 369extern inline int sched_find_first_bit(const unsigned long *b)
371{ 370{
372 if (unlikely(b[0])) 371 if (unlikely(b[0]))
373 return __ffs(b[0]); 372 return __ffs(b[0]);
diff --git a/include/asm-cris/dma-mapping.h b/include/asm-cris/dma-mapping.h
index 0d770f60127a..0b5c3fdaefe1 100644
--- a/include/asm-cris/dma-mapping.h
+++ b/include/asm-cris/dma-mapping.h
@@ -1,125 +1,179 @@
1/* DMA mapping. Nothing tricky here, just virt_to_phys */
2
1#ifndef _ASM_CRIS_DMA_MAPPING_H 3#ifndef _ASM_CRIS_DMA_MAPPING_H
2#define _ASM_CRIS_DMA_MAPPING_H 4#define _ASM_CRIS_DMA_MAPPING_H
3 5
4#include "scatterlist.h" 6#include <linux/mm.h>
7#include <linux/kernel.h>
5 8
6static inline int 9#include <asm/cache.h>
7dma_supported(struct device *dev, u64 mask) 10#include <asm/io.h>
8{ 11#include <asm/scatterlist.h>
9 BUG();
10 return 0;
11}
12 12
13static inline int 13#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
14dma_set_mask(struct device *dev, u64 dma_mask) 14#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
15{ 15
16 BUG(); 16#ifdef CONFIG_PCI
17 return 1; 17void *dma_alloc_coherent(struct device *dev, size_t size,
18} 18 dma_addr_t *dma_handle, int flag);
19 19
20void dma_free_coherent(struct device *dev, size_t size,
21 void *vaddr, dma_addr_t dma_handle);
22#else
20static inline void * 23static inline void *
21dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, 24dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
22 int flag) 25 int flag)
23{ 26{
24 BUG(); 27 BUG();
25 return NULL; 28 return NULL;
26} 29}
27 30
28static inline void 31static inline void
29dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, 32dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
30 dma_addr_t dma_handle) 33 dma_addr_t dma_handle)
31{ 34{
32 BUG(); 35 BUG();
33} 36}
34 37#endif
35static inline dma_addr_t 38static inline dma_addr_t
36dma_map_single(struct device *dev, void *cpu_addr, size_t size, 39dma_map_single(struct device *dev, void *ptr, size_t size,
37 enum dma_data_direction direction) 40 enum dma_data_direction direction)
38{ 41{
39 BUG(); 42 BUG_ON(direction == DMA_NONE);
40 return 0; 43 return virt_to_phys(ptr);
41} 44}
42 45
43static inline void 46static inline void
44dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, 47dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
45 enum dma_data_direction direction) 48 enum dma_data_direction direction)
46{ 49{
47 BUG(); 50 BUG_ON(direction == DMA_NONE);
51}
52
53static inline int
54dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
55 enum dma_data_direction direction)
56{
57 printk("Map sg\n");
58 return nents;
48} 59}
49 60
50static inline dma_addr_t 61static inline dma_addr_t
51dma_map_page(struct device *dev, struct page *page, 62dma_map_page(struct device *dev, struct page *page, unsigned long offset,
52 unsigned long offset, size_t size, 63 size_t size, enum dma_data_direction direction)
53 enum dma_data_direction direction)
54{ 64{
55 BUG(); 65 BUG_ON(direction == DMA_NONE);
56 return 0; 66 return page_to_phys(page) + offset;
57} 67}
58 68
59static inline void 69static inline void
60dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, 70dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
61 enum dma_data_direction direction) 71 enum dma_data_direction direction)
62{ 72{
63 BUG(); 73 BUG_ON(direction == DMA_NONE);
64} 74}
65 75
66static inline int
67dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
68 enum dma_data_direction direction)
69{
70 BUG();
71 return 1;
72}
73 76
74static inline void 77static inline void
75dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, 78dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
76 enum dma_data_direction direction) 79 enum dma_data_direction direction)
77{ 80{
78 BUG(); 81 BUG_ON(direction == DMA_NONE);
79} 82}
80 83
81static inline void 84static inline void
82dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size, 85dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
83 enum dma_data_direction direction) 86 enum dma_data_direction direction)
84{ 87{
85 BUG();
86} 88}
87 89
88static inline void 90static inline void
89dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems, 91dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size,
90 enum dma_data_direction direction) 92 enum dma_data_direction direction)
91{ 93{
92 BUG();
93} 94}
94 95
95/* Now for the API extensions over the pci_ one */ 96static inline void
97dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
98 unsigned long offset, size_t size,
99 enum dma_data_direction direction)
100{
101}
96 102
97#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) 103static inline void
98#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) 104dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
99#define dma_is_consistent(d) (1) 105 unsigned long offset, size_t size,
106 enum dma_data_direction direction)
107{
108}
100 109
101static inline int 110static inline void
102dma_get_cache_alignment(void) 111dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
112 enum dma_data_direction direction)
103{ 113{
104 /* no easy way to get cache size on all processors, so return
105 * the maximum possible, to be safe */
106 return (1 << L1_CACHE_SHIFT_MAX);
107} 114}
108 115
109static inline void 116static inline void
110dma_sync_single_range(struct device *dev, dma_addr_t dma_handle, 117dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
111 unsigned long offset, size_t size, 118 enum dma_data_direction direction)
112 enum dma_data_direction direction)
113{ 119{
114 BUG();
115} 120}
116 121
122static inline int
123dma_mapping_error(dma_addr_t dma_addr)
124{
125 return 0;
126}
127
128static inline int
129dma_supported(struct device *dev, u64 mask)
130{
131 /*
132 * we fall back to GFP_DMA when the mask isn't all 1s,
133 * so we can't guarantee allocations that must be
134 * within a tighter range than GFP_DMA..
135 */
136 if(mask < 0x00ffffff)
137 return 0;
138
139 return 1;
140}
141
142static inline int
143dma_set_mask(struct device *dev, u64 mask)
144{
145 if(!dev->dma_mask || !dma_supported(dev, mask))
146 return -EIO;
147
148 *dev->dma_mask = mask;
149
150 return 0;
151}
152
153static inline int
154dma_get_cache_alignment(void)
155{
156 return (1 << L1_CACHE_SHIFT_MAX);
157}
158
159#define dma_is_consistent(d) (1)
160
117static inline void 161static inline void
118dma_cache_sync(void *vaddr, size_t size, 162dma_cache_sync(void *vaddr, size_t size,
119 enum dma_data_direction direction) 163 enum dma_data_direction direction)
120{ 164{
121 BUG();
122} 165}
123 166
124#endif 167#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
168extern int
169dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
170 dma_addr_t device_addr, size_t size, int flags);
171
172extern void
173dma_release_declared_memory(struct device *dev);
125 174
175extern void *
176dma_mark_declared_memory_occupied(struct device *dev,
177 dma_addr_t device_addr, size_t size);
178
179#endif
diff --git a/include/asm-cris/dma.h b/include/asm-cris/dma.h
index c229fac35cdc..6f188dc56138 100644
--- a/include/asm-cris/dma.h
+++ b/include/asm-cris/dma.h
@@ -10,4 +10,12 @@
10 10
11#define MAX_DMA_ADDRESS PAGE_OFFSET 11#define MAX_DMA_ADDRESS PAGE_OFFSET
12 12
13/* From PCI */
14
15#ifdef CONFIG_PCI
16extern int isa_dma_bridge_buggy;
17#else
18#define isa_dma_bridge_buggy (0)
19#endif
20
13#endif /* _ASM_DMA_H */ 21#endif /* _ASM_DMA_H */
diff --git a/include/asm-cris/elf.h b/include/asm-cris/elf.h
index d37fd5c4a567..87a60bd8e667 100644
--- a/include/asm-cris/elf.h
+++ b/include/asm-cris/elf.h
@@ -8,6 +8,27 @@
8#include <asm/arch/elf.h> 8#include <asm/arch/elf.h>
9#include <asm/user.h> 9#include <asm/user.h>
10 10
11#define R_CRIS_NONE 0
12#define R_CRIS_8 1
13#define R_CRIS_16 2
14#define R_CRIS_32 3
15#define R_CRIS_8_PCREL 4
16#define R_CRIS_16_PCREL 5
17#define R_CRIS_32_PCREL 6
18#define R_CRIS_GNU_VTINHERIT 7
19#define R_CRIS_GNU_VTENTRY 8
20#define R_CRIS_COPY 9
21#define R_CRIS_GLOB_DAT 10
22#define R_CRIS_JUMP_SLOT 11
23#define R_CRIS_RELATIVE 12
24#define R_CRIS_16_GOT 13
25#define R_CRIS_32_GOT 14
26#define R_CRIS_16_GOTPLT 15
27#define R_CRIS_32_GOTPLT 16
28#define R_CRIS_32_GOTREL 17
29#define R_CRIS_32_PLT_GOTREL 18
30#define R_CRIS_32_PLT_PCREL 19
31
11typedef unsigned long elf_greg_t; 32typedef unsigned long elf_greg_t;
12 33
13/* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is 34/* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is
@@ -19,17 +40,29 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG];
19typedef unsigned long elf_fpregset_t; 40typedef unsigned long elf_fpregset_t;
20 41
21/* 42/*
22 * This is used to ensure we don't load something for the wrong architecture.
23 */
24#define elf_check_arch(x) ( (x)->e_machine == EM_CRIS )
25
26/*
27 * These are used to set parameters in the core dumps. 43 * These are used to set parameters in the core dumps.
28 */ 44 */
29#define ELF_CLASS ELFCLASS32 45#define ELF_CLASS ELFCLASS32
30#define ELF_DATA ELFDATA2LSB; 46#define ELF_DATA ELFDATA2LSB
31#define ELF_ARCH EM_CRIS 47#define ELF_ARCH EM_CRIS
32 48
49/* The master for these definitions is {binutils}/include/elf/cris.h: */
50/* User symbols in this file have a leading underscore. */
51#define EF_CRIS_UNDERSCORE 0x00000001
52
53/* This is a mask for different incompatible machine variants. */
54#define EF_CRIS_VARIANT_MASK 0x0000000e
55
56/* Variant 0; may contain v0..10 object. */
57#define EF_CRIS_VARIANT_ANY_V0_V10 0x00000000
58
59/* Variant 1; contains v32 object. */
60#define EF_CRIS_VARIANT_V32 0x00000002
61
62/* Variant 2; contains object compatible with v32 and v10. */
63#define EF_CRIS_VARIANT_COMMON_V10_V32 0x00000004
64/* End of excerpt from {binutils}/include/elf/cris.h. */
65
33#define USE_ELF_CORE_DUMP 66#define USE_ELF_CORE_DUMP
34 67
35#define ELF_EXEC_PAGESIZE 8192 68#define ELF_EXEC_PAGESIZE 8192
diff --git a/include/asm-cris/etraxgpio.h b/include/asm-cris/etraxgpio.h
index cf04af9635cc..80ee10f70d43 100644
--- a/include/asm-cris/etraxgpio.h
+++ b/include/asm-cris/etraxgpio.h
@@ -13,7 +13,7 @@
13 are enabled. 13 are enabled.
14 * 14 *
15 * 15 *
16 * For ETRAX 200 (ARCH_V32): 16 * For ETRAX FS (ARCH_V32):
17 * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction 17 * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
18 * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction 18 * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction
19 * /dev/gpioc minor 2, 18 bit GPIO, each bit can change direction 19 * /dev/gpioc minor 2, 18 bit GPIO, each bit can change direction
@@ -39,10 +39,10 @@
39#define ETRAXGPIO_IOCTYPE 43 39#define ETRAXGPIO_IOCTYPE 43
40#define GPIO_MINOR_A 0 40#define GPIO_MINOR_A 0
41#define GPIO_MINOR_B 1 41#define GPIO_MINOR_B 1
42#define GPIO_MINOR_C 2 42#define GPIO_MINOR_LEDS 2
43#define GPIO_MINOR_D 3 43#define GPIO_MINOR_C 3
44#define GPIO_MINOR_E 4 44#define GPIO_MINOR_D 4
45#define GPIO_MINOR_LEDS 5 45#define GPIO_MINOR_E 5
46#define GPIO_MINOR_LAST 5 46#define GPIO_MINOR_LAST 5
47#endif 47#endif
48 48
diff --git a/include/asm-cris/hardirq.h b/include/asm-cris/hardirq.h
index f4d136228ee1..1c13dd3faac3 100644
--- a/include/asm-cris/hardirq.h
+++ b/include/asm-cris/hardirq.h
@@ -1,18 +1,17 @@
1#ifndef __ASM_HARDIRQ_H 1#ifndef __ASM_HARDIRQ_H
2#define __ASM_HARDIRQ_H 2#define __ASM_HARDIRQ_H
3 3
4/* only non-SMP supported */
5
6#include <linux/threads.h> 4#include <linux/threads.h>
7#include <linux/cache.h> 5#include <linux/cache.h>
8 6
9/* entry.S is sensitive to the offsets of these fields */
10typedef struct { 7typedef struct {
11 unsigned int __softirq_pending; 8 unsigned int __softirq_pending;
12} ____cacheline_aligned irq_cpustat_t; 9} ____cacheline_aligned irq_cpustat_t;
13 10
14#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ 11#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
15 12
13void ack_bad_irq(unsigned int irq);
14
16#define HARDIRQ_BITS 8 15#define HARDIRQ_BITS 8
17 16
18/* 17/*
diff --git a/include/asm-cris/hw_irq.h b/include/asm-cris/hw_irq.h
new file mode 100644
index 000000000000..341536a234e9
--- /dev/null
+++ b/include/asm-cris/hw_irq.h
@@ -0,0 +1,7 @@
1#ifndef _ASM_HW_IRQ_H
2#define _ASM_HW_IRQ_H
3
4static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {}
5
6#endif
7
diff --git a/include/asm-cris/ide.h b/include/asm-cris/ide.h
new file mode 100644
index 000000000000..a894f66665f8
--- /dev/null
+++ b/include/asm-cris/ide.h
@@ -0,0 +1 @@
#include <asm/arch/ide.h>
diff --git a/include/asm-cris/io.h b/include/asm-cris/io.h
index 1d2b51701e8d..16e791b3c721 100644
--- a/include/asm-cris/io.h
+++ b/include/asm-cris/io.h
@@ -3,6 +3,21 @@
3 3
4#include <asm/page.h> /* for __va, __pa */ 4#include <asm/page.h> /* for __va, __pa */
5#include <asm/arch/io.h> 5#include <asm/arch/io.h>
6#include <linux/kernel.h>
7
8struct cris_io_operations
9{
10 u32 (*read_mem)(void *addr, int size);
11 void (*write_mem)(u32 val, int size, void *addr);
12 u32 (*read_io)(u32 port, void *addr, int size, int count);
13 void (*write_io)(u32 port, void *addr, int size, int count);
14};
15
16#ifdef CONFIG_PCI
17extern struct cris_io_operations *cris_iops;
18#else
19#define cris_iops ((struct cris_io_operations*)NULL)
20#endif
6 21
7/* 22/*
8 * Change virtual addresses to physical addresses and vv. 23 * Change virtual addresses to physical addresses and vv.
@@ -18,14 +33,17 @@ extern inline void * phys_to_virt(unsigned long address)
18 return __va(address); 33 return __va(address);
19} 34}
20 35
21extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); 36extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
37extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot);
22 38
23extern inline void * ioremap (unsigned long offset, unsigned long size) 39extern inline void __iomem * ioremap (unsigned long offset, unsigned long size)
24{ 40{
25 return __ioremap(offset, size, 0); 41 return __ioremap(offset, size, 0);
26} 42}
27 43
28extern void iounmap(void *addr); 44extern void iounmap(volatile void * __iomem addr);
45
46extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size);
29 47
30/* 48/*
31 * IO bus memory addresses are also 1:1 with the physical address 49 * IO bus memory addresses are also 1:1 with the physical address
@@ -39,9 +57,32 @@ extern void iounmap(void *addr);
39 * differently. On the CRIS architecture, we just read/write the 57 * differently. On the CRIS architecture, we just read/write the
40 * memory location directly. 58 * memory location directly.
41 */ 59 */
42#define readb(addr) (*(volatile unsigned char *) (addr)) 60#ifdef CONFIG_PCI
43#define readw(addr) (*(volatile unsigned short *) (addr)) 61#define PCI_SPACE(x) ((((unsigned)(x)) & 0x10000000) == 0x10000000)
44#define readl(addr) (*(volatile unsigned int *) (addr)) 62#else
63#define PCI_SPACE(x) 0
64#endif
65static inline unsigned char readb(const volatile void __iomem *addr)
66{
67 if (PCI_SPACE(addr) && cris_iops)
68 return cris_iops->read_mem((void*)addr, 1);
69 else
70 return *(volatile unsigned char __force *) addr;
71}
72static inline unsigned short readw(const volatile void __iomem *addr)
73{
74 if (PCI_SPACE(addr) && cris_iops)
75 return cris_iops->read_mem((void*)addr, 2);
76 else
77 return *(volatile unsigned short __force *) addr;
78}
79static inline unsigned int readl(const volatile void __iomem *addr)
80{
81 if (PCI_SPACE(addr) && cris_iops)
82 return cris_iops->read_mem((void*)addr, 4);
83 else
84 return *(volatile unsigned int __force *) addr;
85}
45#define readb_relaxed(addr) readb(addr) 86#define readb_relaxed(addr) readb(addr)
46#define readw_relaxed(addr) readw(addr) 87#define readw_relaxed(addr) readw(addr)
47#define readl_relaxed(addr) readl(addr) 88#define readl_relaxed(addr) readl(addr)
@@ -49,9 +90,27 @@ extern void iounmap(void *addr);
49#define __raw_readw readw 90#define __raw_readw readw
50#define __raw_readl readl 91#define __raw_readl readl
51 92
52#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b)) 93static inline void writeb(unsigned char b, volatile void __iomem *addr)
53#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b)) 94{
54#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) 95 if (PCI_SPACE(addr) && cris_iops)
96 cris_iops->write_mem(b, 1, (void*)addr);
97 else
98 *(volatile unsigned char __force *) addr = b;
99}
100static inline void writew(unsigned short b, volatile void __iomem *addr)
101{
102 if (PCI_SPACE(addr) && cris_iops)
103 cris_iops->write_mem(b, 2, (void*)addr);
104 else
105 *(volatile unsigned short __force *) addr = b;
106}
107static inline void writel(unsigned int b, volatile void __iomem *addr)
108{
109 if (PCI_SPACE(addr) && cris_iops)
110 cris_iops->write_mem(b, 4, (void*)addr);
111 else
112 *(volatile unsigned int __force *) addr = b;
113}
55#define __raw_writeb writeb 114#define __raw_writeb writeb
56#define __raw_writew writew 115#define __raw_writew writew
57#define __raw_writel writel 116#define __raw_writel writel
@@ -66,25 +125,25 @@ extern void iounmap(void *addr);
66 * Again, CRIS does not require mem IO specific function. 125 * Again, CRIS does not require mem IO specific function.
67 */ 126 */
68 127
69#define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void *)(b),(c),(d)) 128#define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void __force *)(b),(c),(d))
70 129
71/* The following is junk needed for the arch-independent code but which 130/* The following is junk needed for the arch-independent code but which
72 * we never use in the CRIS port 131 * we never use in the CRIS port
73 */ 132 */
74 133
75#define IO_SPACE_LIMIT 0xffff 134#define IO_SPACE_LIMIT 0xffff
76#define inb(x) (0) 135#define inb(port) (cris_iops ? cris_iops->read_io(port,NULL,1,1) : 0)
77#define inw(x) (0) 136#define inw(port) (cris_iops ? cris_iops->read_io(port,NULL,2,1) : 0)
78#define inl(x) (0) 137#define inl(port) (cris_iops ? cris_iops->read_io(port,NULL,4,1) : 0)
79#define outb(x,y) 138#define insb(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,1,count) : 0)
80#define outw(x,y) 139#define insw(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,2,count) : 0)
81#define outl(x,y) 140#define insl(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,4,count) : 0)
82#define insb(x,y,z) 141#define outb(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,1,1)
83#define insw(x,y,z) 142#define outw(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,2,1)
84#define insl(x,y,z) 143#define outl(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,4,1)
85#define outsb(x,y,z) 144#define outsb(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,1,count)
86#define outsw(x,y,z) 145#define outsw(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,2,count)
87#define outsl(x,y,z) 146#define outsl(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,3,count)
88 147
89/* 148/*
90 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 149 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
diff --git a/include/asm-cris/irq.h b/include/asm-cris/irq.h
index 87f342517bb1..8e787fdaedd4 100644
--- a/include/asm-cris/irq.h
+++ b/include/asm-cris/irq.h
@@ -8,16 +8,6 @@ extern __inline__ int irq_canonicalize(int irq)
8 return irq; 8 return irq;
9} 9}
10 10
11extern void disable_irq(unsigned int);
12extern void enable_irq(unsigned int);
13
14#define disable_irq_nosync disable_irq
15#define enable_irq_nosync enable_irq
16
17struct irqaction;
18struct pt_regs;
19int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
20
21#endif /* _ASM_IRQ_H */ 11#endif /* _ASM_IRQ_H */
22 12
23 13
diff --git a/include/asm-cris/kmap_types.h b/include/asm-cris/kmap_types.h
index eec0974c2417..492988cb9077 100644
--- a/include/asm-cris/kmap_types.h
+++ b/include/asm-cris/kmap_types.h
@@ -17,8 +17,8 @@ enum km_type {
17 KM_PTE1, 17 KM_PTE1,
18 KM_IRQ0, 18 KM_IRQ0,
19 KM_IRQ1, 19 KM_IRQ1,
20 KM_CRYPTO_USER, 20 KM_SOFTIRQ0,
21 KM_CRYPTO_SOFTIRQ, 21 KM_SOFTIRQ1,
22 KM_TYPE_NR 22 KM_TYPE_NR
23}; 23};
24 24
diff --git a/include/asm-cris/mmu_context.h b/include/asm-cris/mmu_context.h
index f9308c5bbd99..e6e659dc757b 100644
--- a/include/asm-cris/mmu_context.h
+++ b/include/asm-cris/mmu_context.h
@@ -15,7 +15,7 @@ extern void switch_mm(struct mm_struct *prev, struct mm_struct *next,
15 * registers like cr3 on the i386 15 * registers like cr3 on the i386
16 */ 16 */
17 17
18extern volatile pgd_t *current_pgd; /* defined in arch/cris/mm/fault.c */ 18extern volatile DEFINE_PER_CPU(pgd_t *,current_pgd); /* defined in arch/cris/mm/fault.c */
19 19
20static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 20static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
21{ 21{
diff --git a/include/asm-cris/page.h b/include/asm-cris/page.h
index c767da1ef8f5..bbf17bd39385 100644
--- a/include/asm-cris/page.h
+++ b/include/asm-cris/page.h
@@ -29,18 +29,15 @@
29 */ 29 */
30#ifndef __ASSEMBLY__ 30#ifndef __ASSEMBLY__
31typedef struct { unsigned long pte; } pte_t; 31typedef struct { unsigned long pte; } pte_t;
32typedef struct { unsigned long pmd; } pmd_t;
33typedef struct { unsigned long pgd; } pgd_t; 32typedef struct { unsigned long pgd; } pgd_t;
34typedef struct { unsigned long pgprot; } pgprot_t; 33typedef struct { unsigned long pgprot; } pgprot_t;
35#endif 34#endif
36 35
37#define pte_val(x) ((x).pte) 36#define pte_val(x) ((x).pte)
38#define pmd_val(x) ((x).pmd)
39#define pgd_val(x) ((x).pgd) 37#define pgd_val(x) ((x).pgd)
40#define pgprot_val(x) ((x).pgprot) 38#define pgprot_val(x) ((x).pgprot)
41 39
42#define __pte(x) ((pte_t) { (x) } ) 40#define __pte(x) ((pte_t) { (x) } )
43#define __pmd(x) ((pmd_t) { (x) } )
44#define __pgd(x) ((pgd_t) { (x) } ) 41#define __pgd(x) ((pgd_t) { (x) } )
45#define __pgprot(x) ((pgprot_t) { (x) } ) 42#define __pgprot(x) ((pgprot_t) { (x) } )
46 43
@@ -73,10 +70,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
73 70
74#ifndef __ASSEMBLY__ 71#ifndef __ASSEMBLY__
75 72
76#define BUG() do { \
77 printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
78} while (0)
79
80/* Pure 2^n version of get_order */ 73/* Pure 2^n version of get_order */
81static inline int get_order(unsigned long size) 74static inline int get_order(unsigned long size)
82{ 75{
diff --git a/include/asm-cris/pci.h b/include/asm-cris/pci.h
index c61041531889..2064bc1de074 100644
--- a/include/asm-cris/pci.h
+++ b/include/asm-cris/pci.h
@@ -1,13 +1,105 @@
1#ifndef __ASM_CRIS_PCI_H 1#ifndef __ASM_CRIS_PCI_H
2#define __ASM_CRIS_PCI_H 2#define __ASM_CRIS_PCI_H
3 3
4#include <linux/config.h>
5
6#ifdef __KERNEL__
7#include <linux/mm.h> /* for struct page */
8
9/* Can be used to override the logic in pci_scan_bus for skipping
10 already-configured bus numbers - to be used for buggy BIOSes
11 or architectures with incomplete PCI setup by the loader */
12
13#define pcibios_assign_all_busses(void) 1
14
15extern unsigned long pci_mem_start;
16#define PCIBIOS_MIN_IO 0x1000
17#define PCIBIOS_MIN_MEM 0x10000000
18
19#define PCIBIOS_MIN_CARDBUS_IO 0x4000
20
21void pcibios_config_init(void);
22struct pci_bus * pcibios_scan_root(int bus);
23int pcibios_assign_resources(void);
24
25void pcibios_set_master(struct pci_dev *dev);
26void pcibios_penalize_isa_irq(int irq);
27struct irq_routing_table *pcibios_get_irq_routing_table(void);
28int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
29
30/* Dynamic DMA mapping stuff.
31 * i386 has everything mapped statically.
32 */
33
34#include <linux/types.h>
35#include <linux/slab.h>
4#include <asm/scatterlist.h> 36#include <asm/scatterlist.h>
5#include <asm-generic/pci-dma-compat.h> 37#include <linux/string.h>
38#include <asm/io.h>
6 39
7/* ETRAX chips don't have a PCI bus. This file is just here because some stupid .c code 40struct pci_dev;
8 * includes it even if CONFIG_PCI is not set. 41
42/* The PCI address space does equal the physical memory
43 * address space. The networking and block device layers use
44 * this boolean for bounce buffer decisions.
9 */ 45 */
10#define PCI_DMA_BUS_IS_PHYS (1) 46#define PCI_DMA_BUS_IS_PHYS (1)
11 47
12#endif /* __ASM_CRIS_PCI_H */ 48/* pci_unmap_{page,single} is a nop so... */
49#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
50#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
51#define pci_unmap_addr(PTR, ADDR_NAME) (0)
52#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
53#define pci_unmap_len(PTR, LEN_NAME) (0)
54#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
55
56/* This is always fine. */
57#define pci_dac_dma_supported(pci_dev, mask) (1)
13 58
59static inline dma64_addr_t
60pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction)
61{
62 return ((dma64_addr_t) page_to_phys(page) +
63 (dma64_addr_t) offset);
64}
65
66static inline struct page *
67pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr)
68{
69 return pfn_to_page(dma_addr >> PAGE_SHIFT);
70}
71
72static inline unsigned long
73pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr)
74{
75 return (dma_addr & ~PAGE_MASK);
76}
77
78static inline void
79pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction)
80{
81}
82
83static inline void
84pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction)
85{
86}
87
88#define HAVE_PCI_MMAP
89extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
90 enum pci_mmap_state mmap_state, int write_combine);
91
92
93static inline void pcibios_add_platform_entries(struct pci_dev *dev)
94{
95}
96
97#endif /* __KERNEL__ */
98
99/* implement the pci_ DMA API in terms of the generic device dma_ one */
100#include <asm-generic/pci-dma-compat.h>
101
102/* generic pci stuff */
103#include <asm-generic/pci.h>
104
105#endif /* __ASM_CRIS_PCI_H */
diff --git a/include/asm-cris/pgalloc.h b/include/asm-cris/pgalloc.h
index b202e62ed6e0..a131776edf41 100644
--- a/include/asm-cris/pgalloc.h
+++ b/include/asm-cris/pgalloc.h
@@ -47,16 +47,6 @@ extern inline void pte_free(struct page *pte)
47 47
48#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) 48#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte))
49 49
50/*
51 * We don't have any real pmd's, and this code never triggers because
52 * the pgd will always be present..
53 */
54
55#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); })
56#define pmd_free(x) do { } while (0)
57#define __pmd_free_tlb(tlb,x) do { } while (0)
58#define pgd_populate(mm, pmd, pte) BUG()
59
60#define check_pgt_cache() do { } while (0) 50#define check_pgt_cache() do { } while (0)
61 51
62#endif 52#endif
diff --git a/include/asm-cris/pgtable.h b/include/asm-cris/pgtable.h
index f7042944b073..a9143bed99db 100644
--- a/include/asm-cris/pgtable.h
+++ b/include/asm-cris/pgtable.h
@@ -5,7 +5,8 @@
5#ifndef _CRIS_PGTABLE_H 5#ifndef _CRIS_PGTABLE_H
6#define _CRIS_PGTABLE_H 6#define _CRIS_PGTABLE_H
7 7
8#include <asm-generic/4level-fixup.h> 8#include <asm/page.h>
9#include <asm-generic/pgtable-nopmd.h>
9 10
10#ifndef __ASSEMBLY__ 11#ifndef __ASSEMBLY__
11#include <linux/config.h> 12#include <linux/config.h>
@@ -41,22 +42,14 @@ extern void paging_init(void);
41 * but the define is needed for a generic inline function.) 42 * but the define is needed for a generic inline function.)
42 */ 43 */
43#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) 44#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
44#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval) 45#define set_pgu(pudptr, pudval) (*(pudptr) = pudval)
45 46
46/* PMD_SHIFT determines the size of the area a second-level page table can 47/* PGDIR_SHIFT determines the size of the area a second-level page table can
47 * map. It is equal to the page size times the number of PTE's that fit in 48 * map. It is equal to the page size times the number of PTE's that fit in
48 * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number. 49 * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number.
49 */ 50 */
50 51
51#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2)) 52#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2))
52#define PMD_SIZE (1UL << PMD_SHIFT)
53#define PMD_MASK (~(PMD_SIZE-1))
54
55/* PGDIR_SHIFT determines what a third-level page table entry can map.
56 * Since we fold into a two-level structure, this is the same as PMD_SHIFT.
57 */
58
59#define PGDIR_SHIFT PMD_SHIFT
60#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 53#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
61#define PGDIR_MASK (~(PGDIR_SIZE-1)) 54#define PGDIR_MASK (~(PGDIR_SIZE-1))
62 55
@@ -67,7 +60,6 @@ extern void paging_init(void);
67 * divide it by 4 (shift by 2). 60 * divide it by 4 (shift by 2).
68 */ 61 */
69#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2)) 62#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2))
70#define PTRS_PER_PMD 1
71#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2)) 63#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2))
72 64
73/* calculate how many PGD entries a user-level program can use 65/* calculate how many PGD entries a user-level program can use
@@ -105,7 +97,7 @@ extern unsigned long empty_zero_page;
105#define pte_present(x) (pte_val(x) & _PAGE_PRESENT) 97#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
106#define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0) 98#define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0)
107 99
108#define pmd_none(x) (!pmd_val(x)) 100#define pmd_none(x) (!pmd_val(x))
109/* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad 101/* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad
110 * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries. 102 * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries.
111 */ 103 */
@@ -116,16 +108,6 @@ extern unsigned long empty_zero_page;
116#ifndef __ASSEMBLY__ 108#ifndef __ASSEMBLY__
117 109
118/* 110/*
119 * The "pgd_xxx()" functions here are trivial for a folded two-level
120 * setup: the pgd is never bad, and a pmd always exists (as it's folded
121 * into the pgd entry)
122 */
123extern inline int pgd_none(pgd_t pgd) { return 0; }
124extern inline int pgd_bad(pgd_t pgd) { return 0; }
125extern inline int pgd_present(pgd_t pgd) { return 1; }
126extern inline void pgd_clear(pgd_t * pgdp) { }
127
128/*
129 * The following only work if pte_present() is true. 111 * The following only work if pte_present() is true.
130 * Undefined behaviour if not.. 112 * Undefined behaviour if not..
131 */ 113 */
@@ -275,7 +257,7 @@ extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
275#define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) 257#define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
276 258
277/* to find an entry in a page-table-directory. */ 259/* to find an entry in a page-table-directory. */
278#define pgd_index(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 260#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
279 261
280/* to find an entry in a page-table-directory */ 262/* to find an entry in a page-table-directory */
281extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address) 263extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address)
@@ -286,12 +268,6 @@ extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address)
286/* to find an entry in a kernel page-table-directory */ 268/* to find an entry in a kernel page-table-directory */
287#define pgd_offset_k(address) pgd_offset(&init_mm, address) 269#define pgd_offset_k(address) pgd_offset(&init_mm, address)
288 270
289/* Find an entry in the second-level page table.. */
290extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
291{
292 return (pmd_t *) dir;
293}
294
295/* Find an entry in the third-level page table.. */ 271/* Find an entry in the third-level page table.. */
296#define __pte_offset(address) \ 272#define __pte_offset(address) \
297 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 273 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
@@ -308,8 +284,6 @@ extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
308 284
309#define pte_ERROR(e) \ 285#define pte_ERROR(e) \
310 printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e)) 286 printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
311#define pmd_ERROR(e) \
312 printk("%s:%d: bad pmd %p(%08lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
313#define pgd_ERROR(e) \ 287#define pgd_ERROR(e) \
314 printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e)) 288 printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
315 289
@@ -348,5 +322,7 @@ extern inline void update_mmu_cache(struct vm_area_struct * vma,
348#define pte_to_pgoff(x) (pte_val(x) >> 6) 322#define pte_to_pgoff(x) (pte_val(x) >> 6)
349#define pgoff_to_pte(x) __pte(((x) << 6) | _PAGE_FILE) 323#define pgoff_to_pte(x) __pte(((x) << 6) | _PAGE_FILE)
350 324
325typedef pte_t *pte_addr_t;
326
351#endif /* __ASSEMBLY__ */ 327#endif /* __ASSEMBLY__ */
352#endif /* _CRIS_PGTABLE_H */ 328#endif /* _CRIS_PGTABLE_H */
diff --git a/include/asm-cris/processor.h b/include/asm-cris/processor.h
index 623bdf06d911..0dc218117bd8 100644
--- a/include/asm-cris/processor.h
+++ b/include/asm-cris/processor.h
@@ -55,15 +55,6 @@ unsigned long get_wchan(struct task_struct *p);
55 55
56#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) 56#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp)
57 57
58/*
59 * Free current thread data structures etc..
60 */
61
62extern inline void exit_thread(void)
63{
64 /* Nothing needs to be done. */
65}
66
67extern unsigned long thread_saved_pc(struct task_struct *tsk); 58extern unsigned long thread_saved_pc(struct task_struct *tsk);
68 59
69/* Free all resources held by a thread. */ 60/* Free all resources held by a thread. */
diff --git a/include/asm-cris/ptrace.h b/include/asm-cris/ptrace.h
index 7a8c2880e487..1ec69a7ea836 100644
--- a/include/asm-cris/ptrace.h
+++ b/include/asm-cris/ptrace.h
@@ -9,4 +9,6 @@
9#define PTRACE_SETREGS 13 9#define PTRACE_SETREGS 13
10#endif 10#endif
11 11
12#define profile_pc(regs) instruction_pointer(regs)
13
12#endif /* _CRIS_PTRACE_H */ 14#endif /* _CRIS_PTRACE_H */
diff --git a/include/asm-cris/semaphore.h b/include/asm-cris/semaphore.h
index 605aa7eaaaf8..8ed7636ab311 100644
--- a/include/asm-cris/semaphore.h
+++ b/include/asm-cris/semaphore.h
@@ -72,10 +72,9 @@ extern inline void down(struct semaphore * sem)
72 might_sleep(); 72 might_sleep();
73 73
74 /* atomically decrement the semaphores count, and if its negative, we wait */ 74 /* atomically decrement the semaphores count, and if its negative, we wait */
75 local_save_flags(flags); 75 cris_atomic_save(sem, flags);
76 local_irq_disable();
77 failed = --(sem->count.counter) < 0; 76 failed = --(sem->count.counter) < 0;
78 local_irq_restore(flags); 77 cris_atomic_restore(sem, flags);
79 if(failed) { 78 if(failed) {
80 __down(sem); 79 __down(sem);
81 } 80 }
@@ -95,10 +94,9 @@ extern inline int down_interruptible(struct semaphore * sem)
95 might_sleep(); 94 might_sleep();
96 95
97 /* atomically decrement the semaphores count, and if its negative, we wait */ 96 /* atomically decrement the semaphores count, and if its negative, we wait */
98 local_save_flags(flags); 97 cris_atomic_save(sem, flags);
99 local_irq_disable();
100 failed = --(sem->count.counter) < 0; 98 failed = --(sem->count.counter) < 0;
101 local_irq_restore(flags); 99 cris_atomic_restore(sem, flags);
102 if(failed) 100 if(failed)
103 failed = __down_interruptible(sem); 101 failed = __down_interruptible(sem);
104 return(failed); 102 return(failed);
@@ -109,13 +107,13 @@ extern inline int down_trylock(struct semaphore * sem)
109 unsigned long flags; 107 unsigned long flags;
110 int failed; 108 int failed;
111 109
112 local_save_flags(flags); 110 cris_atomic_save(sem, flags);
113 local_irq_disable();
114 failed = --(sem->count.counter) < 0; 111 failed = --(sem->count.counter) < 0;
115 local_irq_restore(flags); 112 cris_atomic_restore(sem, flags);
116 if(failed) 113 if(failed)
117 failed = __down_trylock(sem); 114 failed = __down_trylock(sem);
118 return(failed); 115 return(failed);
116
119} 117}
120 118
121/* 119/*
@@ -130,10 +128,9 @@ extern inline void up(struct semaphore * sem)
130 int wakeup; 128 int wakeup;
131 129
132 /* atomically increment the semaphores count, and if it was negative, we wake people */ 130 /* atomically increment the semaphores count, and if it was negative, we wake people */
133 local_save_flags(flags); 131 cris_atomic_save(sem, flags);
134 local_irq_disable();
135 wakeup = ++(sem->count.counter) <= 0; 132 wakeup = ++(sem->count.counter) <= 0;
136 local_irq_restore(flags); 133 cris_atomic_restore(sem, flags);
137 if(wakeup) { 134 if(wakeup) {
138 __up(sem); 135 __up(sem);
139 } 136 }
diff --git a/include/asm-cris/smp.h b/include/asm-cris/smp.h
index c2f4feaa041d..dca5ef1d8c97 100644
--- a/include/asm-cris/smp.h
+++ b/include/asm-cris/smp.h
@@ -1,4 +1,11 @@
1#ifndef __ASM_SMP_H 1#ifndef __ASM_SMP_H
2#define __ASM_SMP_H 2#define __ASM_SMP_H
3 3
4#include <linux/cpumask.h>
5
6extern cpumask_t phys_cpu_present_map;
7#define cpu_possible_map phys_cpu_present_map
8
9#define __smp_processor_id() (current_thread_info()->cpu)
10
4#endif 11#endif
diff --git a/include/asm-cris/spinlock.h b/include/asm-cris/spinlock.h
new file mode 100644
index 000000000000..2e8ba8afc7af
--- /dev/null
+++ b/include/asm-cris/spinlock.h
@@ -0,0 +1 @@
#include <asm/arch/spinlock.h>
diff --git a/include/asm-cris/sync_serial.h b/include/asm-cris/sync_serial.h
new file mode 100644
index 000000000000..f930b6e00663
--- /dev/null
+++ b/include/asm-cris/sync_serial.h
@@ -0,0 +1,106 @@
1/*
2 * ioctl defines for synchronous serial port driver
3 *
4 * Copyright (c) 2001-2003 Axis Communications AB
5 *
6 * Author: Mikael Starvik
7 *
8 */
9
10#ifndef SYNC_SERIAL_H
11#define SYNC_SERIAL_H
12
13#include <linux/ioctl.h>
14
15#define SSP_SPEED _IOR('S', 0, unsigned int)
16#define SSP_MODE _IOR('S', 1, unsigned int)
17#define SSP_FRAME_SYNC _IOR('S', 2, unsigned int)
18#define SSP_IPOLARITY _IOR('S', 3, unsigned int)
19#define SSP_OPOLARITY _IOR('S', 4, unsigned int)
20#define SSP_SPI _IOR('S', 5, unsigned int)
21#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int)
22
23/* Values for SSP_SPEED */
24#define SSP150 0
25#define SSP300 1
26#define SSP600 2
27#define SSP1200 3
28#define SSP2400 4
29#define SSP4800 5
30#define SSP9600 6
31#define SSP19200 7
32#define SSP28800 8
33#define SSP57600 9
34#define SSP115200 10
35#define SSP230400 11
36#define SSP460800 12
37#define SSP921600 13
38#define SSP3125000 14
39#define CODEC 15
40
41#define FREQ_4MHz 0
42#define FREQ_2MHz 1
43#define FREQ_1MHz 2
44#define FREQ_512kHz 3
45#define FREQ_256kHz 4
46#define FREQ_128kHz 5
47#define FREQ_64kHz 6
48#define FREQ_32kHz 7
49
50/* Used by application to set CODEC divider, word rate and frame rate */
51#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) (CODEC | (freq << 8) | (clk_per_sync << 16) | (sync_per_frame << 28))
52
53/* Used by driver to extract speed */
54#define GET_SPEED(x) (x & 0xff)
55#define GET_FREQ(x) ((x & 0xff00) >> 8)
56#define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1)
57#define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1)
58
59/* Values for SSP_MODE */
60#define MASTER_OUTPUT 0
61#define SLAVE_OUTPUT 1
62#define MASTER_INPUT 2
63#define SLAVE_INPUT 3
64#define MASTER_BIDIR 4
65#define SLAVE_BIDIR 5
66
67/* Values for SSP_FRAME_SYNC */
68#define NORMAL_SYNC 1
69#define EARLY_SYNC 2
70
71#define BIT_SYNC 4
72#define WORD_SYNC 8
73#define EXTENDED_SYNC 0x10
74
75#define SYNC_OFF 0x20
76#define SYNC_ON 0x40
77#define WORD_SIZE_8 0x80
78#define WORD_SIZE_12 0x100
79#define WORD_SIZE_16 0x200
80#define WORD_SIZE_24 0x400
81#define WORD_SIZE_32 0x800
82#define BIT_ORDER_LSB 0x1000
83#define BIT_ORDER_MSB 0x2000
84#define FLOW_CONTROL_ENABLE 0x4000
85#define FLOW_CONTROL_DISABLE 0x8000
86#define CLOCK_GATED 0x10000
87#define CLOCK_NOT_GATED 0x20000
88
89/* Values for SSP_IPOLARITY and SSP_OPOLARITY */
90#define CLOCK_NORMAL 1
91#define CLOCK_INVERT 2
92#define CLOCK_INEGEDGE CLOCK_NORMAL
93#define CLOCK_IPOSEDGE CLOCK_INVERT
94#define FRAME_NORMAL 4
95#define FRAME_INVERT 8
96#define STATUS_NORMAL 0x10
97#define STATUS_INVERT 0x20
98
99/* Values for SSP_SPI */
100#define SPI_MASTER 0
101#define SPI_SLAVE 1
102
103/* Values for SSP_INBUFCHUNK */
104/* plain integer with the size of DMA chunks */
105
106#endif
diff --git a/include/asm-cris/termbits.h b/include/asm-cris/termbits.h
index 16d9a491fdb3..be0836d2f282 100644
--- a/include/asm-cris/termbits.h
+++ b/include/asm-cris/termbits.h
@@ -152,7 +152,7 @@ struct termios {
152#define B921600 0010005 152#define B921600 0010005
153#define B1843200 0010006 153#define B1843200 0010006
154#define B6250000 0010007 154#define B6250000 0010007
155/* etrax 200 supports this as well */ 155/* ETRAX FS supports this as well */
156#define B12500000 0010010 156#define B12500000 0010010
157#define CIBAUD 002003600000 /* input baud rate (used in v32) */ 157#define CIBAUD 002003600000 /* input baud rate (used in v32) */
158/* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX 158/* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX
diff --git a/include/asm-cris/thread_info.h b/include/asm-cris/thread_info.h
index 5ba4b7865cc5..cef0140fc104 100644
--- a/include/asm-cris/thread_info.h
+++ b/include/asm-cris/thread_info.h
@@ -43,7 +43,7 @@ struct thread_info {
43 43
44#endif 44#endif
45 45
46#define PREEMPT_ACTIVE 0x4000000 46#define PREEMPT_ACTIVE 0x10000000
47 47
48/* 48/*
49 * macros/functions for gaining access to the thread information structure 49 * macros/functions for gaining access to the thread information structure
diff --git a/include/asm-cris/timex.h b/include/asm-cris/timex.h
index 375c41af47de..3fb069a37717 100644
--- a/include/asm-cris/timex.h
+++ b/include/asm-cris/timex.h
@@ -14,7 +14,7 @@
14 * used so it does not matter. 14 * used so it does not matter.
15 */ 15 */
16 16
17typedef unsigned int cycles_t; 17typedef unsigned long long cycles_t;
18 18
19extern inline cycles_t get_cycles(void) 19extern inline cycles_t get_cycles(void)
20{ 20{
diff --git a/include/asm-cris/tlbflush.h b/include/asm-cris/tlbflush.h
index 1781fe1a32f6..6ed7d9ae90db 100644
--- a/include/asm-cris/tlbflush.h
+++ b/include/asm-cris/tlbflush.h
@@ -18,13 +18,26 @@
18 * 18 *
19 */ 19 */
20 20
21extern void __flush_tlb_all(void);
22extern void __flush_tlb_mm(struct mm_struct *mm);
23extern void __flush_tlb_page(struct vm_area_struct *vma,
24 unsigned long addr);
25
26#ifdef CONFIG_SMP
21extern void flush_tlb_all(void); 27extern void flush_tlb_all(void);
22extern void flush_tlb_mm(struct mm_struct *mm); 28extern void flush_tlb_mm(struct mm_struct *mm);
23extern void flush_tlb_page(struct vm_area_struct *vma, 29extern void flush_tlb_page(struct vm_area_struct *vma,
24 unsigned long addr); 30 unsigned long addr);
25extern void flush_tlb_range(struct vm_area_struct *vma, 31#else
26 unsigned long start, 32#define flush_tlb_all __flush_tlb_all
27 unsigned long end); 33#define flush_tlb_mm __flush_tlb_mm
34#define flush_tlb_page __flush_tlb_page
35#endif
36
37static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
38{
39 flush_tlb_mm(vma->vm_mm);
40}
28 41
29extern inline void flush_tlb_pgtables(struct mm_struct *mm, 42extern inline void flush_tlb_pgtables(struct mm_struct *mm,
30 unsigned long start, unsigned long end) 43 unsigned long start, unsigned long end)
diff --git a/include/asm-cris/types.h b/include/asm-cris/types.h
index 41a0d450ba1d..8fa6d6c7afce 100644
--- a/include/asm-cris/types.h
+++ b/include/asm-cris/types.h
@@ -52,7 +52,7 @@ typedef unsigned long long u64;
52typedef u32 dma_addr_t; 52typedef u32 dma_addr_t;
53typedef u32 dma64_addr_t; 53typedef u32 dma64_addr_t;
54 54
55typedef unsigned int kmem_bufctl_t; 55typedef unsigned short kmem_bufctl_t;
56 56
57#endif /* __ASSEMBLY__ */ 57#endif /* __ASSEMBLY__ */
58 58
diff --git a/include/asm-cris/unistd.h b/include/asm-cris/unistd.h
index e80bf276b101..28232ad2ff34 100644
--- a/include/asm-cris/unistd.h
+++ b/include/asm-cris/unistd.h
@@ -288,8 +288,15 @@
288#define __NR_mq_timedreceive (__NR_mq_open+3) 288#define __NR_mq_timedreceive (__NR_mq_open+3)
289#define __NR_mq_notify (__NR_mq_open+4) 289#define __NR_mq_notify (__NR_mq_open+4)
290#define __NR_mq_getsetattr (__NR_mq_open+5) 290#define __NR_mq_getsetattr (__NR_mq_open+5)
291 291#define __NR_sys_kexec_load 283
292#define NR_syscalls 283 292#define __NR_waitid 284
293/* #define __NR_sys_setaltroot 285 */
294#define __NR_add_key 286
295#define __NR_request_key 287
296#define __NR_keyctl 288
297
298#define NR_syscalls 289
299
293 300
294 301
295#ifdef __KERNEL__ 302#ifdef __KERNEL__
diff --git a/include/asm-generic/pci.h b/include/asm-generic/pci.h
index 9d4cc47bde39..ee1d8b5d8168 100644
--- a/include/asm-generic/pci.h
+++ b/include/asm-generic/pci.h
@@ -22,6 +22,14 @@ pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
22 region->end = res->end; 22 region->end = res->end;
23} 23}
24 24
25static inline void
26pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
27 struct pci_bus_region *region)
28{
29 res->start = region->start;
30 res->end = region->end;
31}
32
25#define pcibios_scan_all_fns(a, b) 0 33#define pcibios_scan_all_fns(a, b) 0
26 34
27#ifndef HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ 35#ifndef HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 195ccdc069e6..450eae22c39a 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -11,5 +11,6 @@ extern char _sinittext[], _einittext[];
11extern char _sextratext[] __attribute__((weak)); 11extern char _sextratext[] __attribute__((weak));
12extern char _eextratext[] __attribute__((weak)); 12extern char _eextratext[] __attribute__((weak));
13extern char _end[]; 13extern char _end[];
14extern char __per_cpu_start[], __per_cpu_end[];
14 15
15#endif /* _ASM_GENERIC_SECTIONS_H_ */ 16#endif /* _ASM_GENERIC_SECTIONS_H_ */
diff --git a/include/asm-i386/bitops.h b/include/asm-i386/bitops.h
index 9db0b712d57a..ddf1739dc7fd 100644
--- a/include/asm-i386/bitops.h
+++ b/include/asm-i386/bitops.h
@@ -311,6 +311,20 @@ static inline int find_first_zero_bit(const unsigned long *addr, unsigned size)
311int find_next_zero_bit(const unsigned long *addr, int size, int offset); 311int find_next_zero_bit(const unsigned long *addr, int size, int offset);
312 312
313/** 313/**
314 * __ffs - find first bit in word.
315 * @word: The word to search
316 *
317 * Undefined if no bit exists, so code should check against 0 first.
318 */
319static inline unsigned long __ffs(unsigned long word)
320{
321 __asm__("bsfl %1,%0"
322 :"=r" (word)
323 :"rm" (word));
324 return word;
325}
326
327/**
314 * find_first_bit - find the first set bit in a memory region 328 * find_first_bit - find the first set bit in a memory region
315 * @addr: The address to start the search at 329 * @addr: The address to start the search at
316 * @size: The maximum size to search 330 * @size: The maximum size to search
@@ -320,22 +334,15 @@ int find_next_zero_bit(const unsigned long *addr, int size, int offset);
320 */ 334 */
321static inline int find_first_bit(const unsigned long *addr, unsigned size) 335static inline int find_first_bit(const unsigned long *addr, unsigned size)
322{ 336{
323 int d0, d1; 337 int x = 0;
324 int res; 338
325 339 while (x < size) {
326 /* This looks at memory. Mark it volatile to tell gcc not to move it around */ 340 unsigned long val = *addr++;
327 __asm__ __volatile__( 341 if (val)
328 "xorl %%eax,%%eax\n\t" 342 return __ffs(val) + x;
329 "repe; scasl\n\t" 343 x += (sizeof(*addr)<<3);
330 "jz 1f\n\t" 344 }
331 "leal -4(%%edi),%%edi\n\t" 345 return x;
332 "bsfl (%%edi),%%eax\n"
333 "1:\tsubl %%ebx,%%edi\n\t"
334 "shll $3,%%edi\n\t"
335 "addl %%edi,%%eax"
336 :"=a" (res), "=&c" (d0), "=&D" (d1)
337 :"1" ((size + 31) >> 5), "2" (addr), "b" (addr) : "memory");
338 return res;
339} 346}
340 347
341/** 348/**
@@ -360,20 +367,6 @@ static inline unsigned long ffz(unsigned long word)
360 return word; 367 return word;
361} 368}
362 369
363/**
364 * __ffs - find first bit in word.
365 * @word: The word to search
366 *
367 * Undefined if no bit exists, so code should check against 0 first.
368 */
369static inline unsigned long __ffs(unsigned long word)
370{
371 __asm__("bsfl %1,%0"
372 :"=r" (word)
373 :"rm" (word));
374 return word;
375}
376
377/* 370/*
378 * fls: find last bit set. 371 * fls: find last bit set.
379 */ 372 */
diff --git a/include/asm-i386/mach-visws/do_timer.h b/include/asm-i386/mach-visws/do_timer.h
index 33acd50fd9a8..92d638fc8b11 100644
--- a/include/asm-i386/mach-visws/do_timer.h
+++ b/include/asm-i386/mach-visws/do_timer.h
@@ -1,6 +1,7 @@
1/* defines for inline arch setup functions */ 1/* defines for inline arch setup functions */
2 2
3#include <asm/fixmap.h> 3#include <asm/fixmap.h>
4#include <asm/i8259.h>
4#include "cobalt.h" 5#include "cobalt.h"
5 6
6static inline void do_timer_interrupt_hook(struct pt_regs *regs) 7static inline void do_timer_interrupt_hook(struct pt_regs *regs)
diff --git a/include/asm-i386/pci.h b/include/asm-i386/pci.h
index 78c85985aee3..2cbab30734d6 100644
--- a/include/asm-i386/pci.h
+++ b/include/asm-i386/pci.h
@@ -18,11 +18,9 @@ extern unsigned int pcibios_assign_all_busses(void);
18#define pcibios_scan_all_fns(a, b) 0 18#define pcibios_scan_all_fns(a, b) 0
19 19
20extern unsigned long pci_mem_start; 20extern unsigned long pci_mem_start;
21#define PCIBIOS_MIN_IO 0x1000 21#define PCIBIOS_MIN_IO 0x4000
22#define PCIBIOS_MIN_MEM (pci_mem_start) 22#define PCIBIOS_MIN_MEM (pci_mem_start)
23 23
24#define PCIBIOS_MIN_CARDBUS_IO 0x4000
25
26void pcibios_config_init(void); 24void pcibios_config_init(void);
27struct pci_bus * pcibios_scan_root(int bus); 25struct pci_bus * pcibios_scan_root(int bus);
28 26
diff --git a/include/asm-i386/ptrace.h b/include/asm-i386/ptrace.h
index b926cb4f4cfd..05532875e39e 100644
--- a/include/asm-i386/ptrace.h
+++ b/include/asm-i386/ptrace.h
@@ -55,6 +55,9 @@ struct pt_regs {
55#define PTRACE_SET_THREAD_AREA 26 55#define PTRACE_SET_THREAD_AREA 26
56 56
57#ifdef __KERNEL__ 57#ifdef __KERNEL__
58
59#include <asm/vm86.h>
60
58struct task_struct; 61struct task_struct;
59extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs, int error_code); 62extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs, int error_code);
60 63
diff --git a/include/asm-i386/smp.h b/include/asm-i386/smp.h
index edad9b4712fa..a283738b80b3 100644
--- a/include/asm-i386/smp.h
+++ b/include/asm-i386/smp.h
@@ -37,9 +37,6 @@ extern int smp_num_siblings;
37extern cpumask_t cpu_sibling_map[]; 37extern cpumask_t cpu_sibling_map[];
38extern cpumask_t cpu_core_map[]; 38extern cpumask_t cpu_core_map[];
39 39
40extern void smp_flush_tlb(void);
41extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs);
42extern void smp_invalidate_rcv(void); /* Process an NMI */
43extern void (*mtrr_hook) (void); 40extern void (*mtrr_hook) (void);
44extern void zap_low_mappings (void); 41extern void zap_low_mappings (void);
45extern void lock_ipi_call_lock(void); 42extern void lock_ipi_call_lock(void);
diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h
index 517f1649ee64..3a0c69524656 100644
--- a/include/asm-ia64/unistd.h
+++ b/include/asm-ia64/unistd.h
@@ -266,6 +266,9 @@
266#define __NR_ioprio_set 1274 266#define __NR_ioprio_set 1274
267#define __NR_ioprio_get 1275 267#define __NR_ioprio_get 1275
268#define __NR_set_zone_reclaim 1276 268#define __NR_set_zone_reclaim 1276
269#define __NR_inotify_init 1277
270#define __NR_inotify_add_watch 1278
271#define __NR_inotify_rm_watch 1279
269 272
270#ifdef __KERNEL__ 273#ifdef __KERNEL__
271 274
diff --git a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h
index ee741c150176..98d79a3d54fa 100644
--- a/include/asm-parisc/pci.h
+++ b/include/asm-parisc/pci.h
@@ -253,6 +253,10 @@ extern void
253pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 253pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
254 struct resource *res); 254 struct resource *res);
255 255
256extern void
257pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
258 struct pci_bus_region *region);
259
256static inline void pcibios_add_platform_entries(struct pci_dev *dev) 260static inline void pcibios_add_platform_entries(struct pci_dev *dev)
257{ 261{
258} 262}
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
index c5883dbed63f..9483d4bfacf7 100644
--- a/include/asm-ppc/cpm2.h
+++ b/include/asm-ppc/cpm2.h
@@ -109,6 +109,7 @@ static inline long IS_DPERR(const uint offset)
109 * and dual port ram. 109 * and dual port ram.
110 */ 110 */
111extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */ 111extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */
112
112extern uint cpm_dpalloc(uint size, uint align); 113extern uint cpm_dpalloc(uint size, uint align);
113extern int cpm_dpfree(uint offset); 114extern int cpm_dpfree(uint offset);
114extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align); 115extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align);
@@ -116,6 +117,8 @@ extern void cpm_dpdump(void);
116extern void *cpm_dpram_addr(uint offset); 117extern void *cpm_dpram_addr(uint offset);
117extern void cpm_setbrg(uint brg, uint rate); 118extern void cpm_setbrg(uint brg, uint rate);
118extern void cpm2_fastbrg(uint brg, uint rate, int div16); 119extern void cpm2_fastbrg(uint brg, uint rate, int div16);
120extern void cpm2_reset(void);
121
119 122
120/* Buffer descriptors used by many of the CPM protocols. 123/* Buffer descriptors used by many of the CPM protocols.
121*/ 124*/
@@ -1087,5 +1090,3 @@ typedef struct im_idma {
1087 1090
1088#endif /* __CPM2__ */ 1091#endif /* __CPM2__ */
1089#endif /* __KERNEL__ */ 1092#endif /* __KERNEL__ */
1090
1091
diff --git a/include/asm-ppc/dma-mapping.h b/include/asm-ppc/dma-mapping.h
index 7f0487afebbe..6f74f59938d4 100644
--- a/include/asm-ppc/dma-mapping.h
+++ b/include/asm-ppc/dma-mapping.h
@@ -117,7 +117,7 @@ dma_map_page(struct device *dev, struct page *page,
117 117
118 __dma_sync_page(page, offset, size, direction); 118 __dma_sync_page(page, offset, size, direction);
119 119
120 return (page - mem_map) * PAGE_SIZE + PCI_DRAM_OFFSET + offset; 120 return page_to_bus(page) + offset;
121} 121}
122 122
123/* We do nothing. */ 123/* We do nothing. */
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
index 87f051138b9d..21e41c9b7267 100644
--- a/include/asm-ppc/ibm44x.h
+++ b/include/asm-ppc/ibm44x.h
@@ -35,8 +35,10 @@
35#define PPC44x_LOW_SLOT 63 35#define PPC44x_LOW_SLOT 63
36 36
37/* LS 32-bits of UART0 physical address location for early serial text debug */ 37/* LS 32-bits of UART0 physical address location for early serial text debug */
38#ifdef CONFIG_440SP 38#if defined(CONFIG_440SP)
39#define UART0_PHYS_IO_BASE 0xf0000200 39#define UART0_PHYS_IO_BASE 0xf0000200
40#elif defined(CONFIG_440EP)
41#define UART0_PHYS_IO_BASE 0xe0000000
40#else 42#else
41#define UART0_PHYS_IO_BASE 0x40000200 43#define UART0_PHYS_IO_BASE 0x40000200
42#endif 44#endif
@@ -49,11 +51,16 @@
49/* 51/*
50 * Standard 4GB "page" definitions 52 * Standard 4GB "page" definitions
51 */ 53 */
52#ifdef CONFIG_440SP 54#if defined(CONFIG_440SP)
53#define PPC44x_IO_PAGE 0x0000000100000000ULL 55#define PPC44x_IO_PAGE 0x0000000100000000ULL
54#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL 56#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
55#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE 57#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
56#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL 58#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
59#elif defined(CONFIG_440EP)
60#define PPC44x_IO_PAGE 0x0000000000000000ULL
61#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL
62#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
63#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL
57#else 64#else
58#define PPC44x_IO_PAGE 0x0000000100000000ULL 65#define PPC44x_IO_PAGE 0x0000000100000000ULL
59#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL 66#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
@@ -64,7 +71,7 @@
64/* 71/*
65 * 36-bit trap ranges 72 * 36-bit trap ranges
66 */ 73 */
67#ifdef CONFIG_440SP 74#if defined(CONFIG_440SP)
68#define PPC44x_IO_LO 0xf0000000UL 75#define PPC44x_IO_LO 0xf0000000UL
69#define PPC44x_IO_HI 0xf0000fffUL 76#define PPC44x_IO_HI 0xf0000fffUL
70#define PPC44x_PCI0CFG_LO 0x0ec00000UL 77#define PPC44x_PCI0CFG_LO 0x0ec00000UL
@@ -75,6 +82,13 @@
75#define PPC44x_PCI2CFG_HI 0x2ec00007UL 82#define PPC44x_PCI2CFG_HI 0x2ec00007UL
76#define PPC44x_PCIMEM_LO 0x80000000UL 83#define PPC44x_PCIMEM_LO 0x80000000UL
77#define PPC44x_PCIMEM_HI 0xdfffffffUL 84#define PPC44x_PCIMEM_HI 0xdfffffffUL
85#elif defined(CONFIG_440EP)
86#define PPC44x_IO_LO 0xef500000UL
87#define PPC44x_IO_HI 0xefffffffUL
88#define PPC44x_PCI0CFG_LO 0xeec00000UL
89#define PPC44x_PCI0CFG_HI 0xeecfffffUL
90#define PPC44x_PCIMEM_LO 0xa0000000UL
91#define PPC44x_PCIMEM_HI 0xdfffffffUL
78#else 92#else
79#define PPC44x_IO_LO 0x40000000UL 93#define PPC44x_IO_LO 0x40000000UL
80#define PPC44x_IO_HI 0x40000fffUL 94#define PPC44x_IO_HI 0x40000fffUL
@@ -152,6 +166,12 @@
152#define DCRN_SDR_UART0 0x0120 166#define DCRN_SDR_UART0 0x0120
153#define DCRN_SDR_UART1 0x0121 167#define DCRN_SDR_UART1 0x0121
154 168
169#ifdef CONFIG_440EP
170#define DCRN_SDR_UART2 0x0122
171#define DCRN_SDR_UART3 0x0123
172#define DCRN_SDR_CUST0 0x4000
173#endif
174
155/* SDR read/write helper macros */ 175/* SDR read/write helper macros */
156#define SDR_READ(offset) ({\ 176#define SDR_READ(offset) ({\
157 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ 177 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
@@ -169,6 +189,14 @@
169#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ 189#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
170#define DCRN_MAL_BASE 0x180 190#define DCRN_MAL_BASE 0x180
171 191
192#ifdef CONFIG_440EP
193#define DCRN_DMA2P40_BASE 0x300
194#define DCRN_DMA2P41_BASE 0x308
195#define DCRN_DMA2P42_BASE 0x310
196#define DCRN_DMA2P43_BASE 0x318
197#define DCRN_DMA2P4SR_BASE 0x320
198#endif
199
172/* UIC */ 200/* UIC */
173#define DCRN_UIC0_BASE 0xc0 201#define DCRN_UIC0_BASE 0xc0
174#define DCRN_UIC1_BASE 0xd0 202#define DCRN_UIC1_BASE 0xd0
diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h
index 35260afa33a9..e807be96e981 100644
--- a/include/asm-ppc/ibm4xx.h
+++ b/include/asm-ppc/ibm4xx.h
@@ -97,6 +97,10 @@ void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
97 97
98#elif CONFIG_44x 98#elif CONFIG_44x
99 99
100#if defined(CONFIG_BAMBOO)
101#include <platforms/4xx/bamboo.h>
102#endif
103
100#if defined(CONFIG_EBONY) 104#if defined(CONFIG_EBONY)
101#include <platforms/4xx/ebony.h> 105#include <platforms/4xx/ebony.h>
102#endif 106#endif
diff --git a/include/asm-ppc/ibm_ocp.h b/include/asm-ppc/ibm_ocp.h
index 8c61d93043af..3f7b5669e6d5 100644
--- a/include/asm-ppc/ibm_ocp.h
+++ b/include/asm-ppc/ibm_ocp.h
@@ -71,6 +71,8 @@ struct ocp_func_emac_data {
71 71
72/* Sysfs support */ 72/* Sysfs support */
73#define OCP_SYSFS_EMAC_DATA() \ 73#define OCP_SYSFS_EMAC_DATA() \
74OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_idx) \
75OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_mux) \
74OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx) \ 76OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx) \
75OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux) \ 77OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux) \
76OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx) \ 78OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx) \
@@ -78,9 +80,14 @@ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan) \
78OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan) \ 80OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan) \
79OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq) \ 81OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq) \
80OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx) \ 82OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx) \
83OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, tah_idx) \
84OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, phy_mode) \
85OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_map) \
81 \ 86 \
82void ocp_show_emac_data(struct device *dev) \ 87void ocp_show_emac_data(struct device *dev) \
83{ \ 88{ \
89 device_create_file(dev, &dev_attr_emac_rgmii_idx); \
90 device_create_file(dev, &dev_attr_emac_rgmii_mux); \
84 device_create_file(dev, &dev_attr_emac_zmii_idx); \ 91 device_create_file(dev, &dev_attr_emac_zmii_idx); \
85 device_create_file(dev, &dev_attr_emac_zmii_mux); \ 92 device_create_file(dev, &dev_attr_emac_zmii_mux); \
86 device_create_file(dev, &dev_attr_emac_mal_idx); \ 93 device_create_file(dev, &dev_attr_emac_mal_idx); \
@@ -88,6 +95,9 @@ void ocp_show_emac_data(struct device *dev) \
88 device_create_file(dev, &dev_attr_emac_mal_tx_chan); \ 95 device_create_file(dev, &dev_attr_emac_mal_tx_chan); \
89 device_create_file(dev, &dev_attr_emac_wol_irq); \ 96 device_create_file(dev, &dev_attr_emac_wol_irq); \
90 device_create_file(dev, &dev_attr_emac_mdio_idx); \ 97 device_create_file(dev, &dev_attr_emac_mdio_idx); \
98 device_create_file(dev, &dev_attr_emac_tah_idx); \
99 device_create_file(dev, &dev_attr_emac_phy_mode); \
100 device_create_file(dev, &dev_attr_emac_phy_map); \
91} 101}
92 102
93#ifdef CONFIG_40x 103#ifdef CONFIG_40x
@@ -157,7 +167,7 @@ OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode) \
157 \ 167 \
158void ocp_show_iic_data(struct device *dev) \ 168void ocp_show_iic_data(struct device *dev) \
159{ \ 169{ \
160 device_create_file(dev, &dev_attr_iic_fast_mode); \ 170 device_create_file(dev, &dev_attr_iic_fast_mode); \
161} 171}
162#endif /* __IBM_OCP_H__ */ 172#endif /* __IBM_OCP_H__ */
163#endif /* __KERNEL__ */ 173#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mpc10x.h b/include/asm-ppc/mpc10x.h
index f5196a4efbe0..77b1e092c206 100644
--- a/include/asm-ppc/mpc10x.h
+++ b/include/asm-ppc/mpc10x.h
@@ -163,7 +163,8 @@ enum ppc_sys_devices {
163 MPC10X_IIC1, 163 MPC10X_IIC1,
164 MPC10X_DMA0, 164 MPC10X_DMA0,
165 MPC10X_DMA1, 165 MPC10X_DMA1,
166 MPC10X_DUART, 166 MPC10X_UART0,
167 MPC10X_UART1,
167}; 168};
168 169
169int mpc10x_bridge_init(struct pci_controller *hose, 170int mpc10x_bridge_init(struct pci_controller *hose,
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h
index a13d55870e62..a811e440c978 100644
--- a/include/asm-ppc/pci.h
+++ b/include/asm-ppc/pci.h
@@ -105,6 +105,10 @@ extern void
105pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 105pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
106 struct resource *res); 106 struct resource *res);
107 107
108extern void
109pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
110 struct pci_bus_region *region);
111
108extern void pcibios_add_platform_entries(struct pci_dev *dev); 112extern void pcibios_add_platform_entries(struct pci_dev *dev);
109 113
110struct file; 114struct file;
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index 4d4b20c9de78..92f30b28b252 100644
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -202,18 +202,64 @@ extern unsigned long ioremap_bot, ioremap_base;
202 * 202 *
203 * Note that these bits preclude future use of a page size 203 * Note that these bits preclude future use of a page size
204 * less than 4KB. 204 * less than 4KB.
205 *
206 *
207 * PPC 440 core has following TLB attribute fields;
208 *
209 * TLB1:
210 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
211 * RPN................................. - - - - - - ERPN.......
212 *
213 * TLB2:
214 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
215 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
216 *
217 * There are some constrains and options, to decide mapping software bits
218 * into TLB entry.
219 *
220 * - PRESENT *must* be in the bottom three bits because swap cache
221 * entries use the top 29 bits for TLB2.
222 *
223 * - FILE *must* be in the bottom three bits because swap cache
224 * entries use the top 29 bits for TLB2.
225 *
226 * - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
227 * doesn't support SMP. So we can use this as software bit, like
228 * DIRTY.
229 *
230 * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
231 * for memory protection related functions (see PTE structure in
232 * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the
233 * above bits. Note that the bit values are CPU specific, not architecture
234 * specific.
235 *
236 * The kernel PTE entry holds an arch-dependent swp_entry structure under
237 * certain situations. In other words, in such situations some portion of
238 * the PTE bits are used as a swp_entry. In the PPC implementation, the
239 * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
240 * hold protection values. That means the three protection bits are
241 * reserved for both PTE and SWAP entry at the most significant three
242 * LSBs.
243 *
244 * There are three protection bits available for SWAP entry:
245 * _PAGE_PRESENT
246 * _PAGE_FILE
247 * _PAGE_HASHPTE (if HW has)
248 *
249 * So those three bits have to be inside of 0-2nd LSB of PTE.
250 *
205 */ 251 */
252
206#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */ 253#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */
207#define _PAGE_RW 0x00000002 /* S: Write permission */ 254#define _PAGE_RW 0x00000002 /* S: Write permission */
208#define _PAGE_DIRTY 0x00000004 /* S: Page dirty */ 255#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */
209#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */ 256#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */
210#define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */ 257#define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */
211#define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */ 258#define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */
212#define _PAGE_USER 0x00000040 /* S: User page */ 259#define _PAGE_USER 0x00000040 /* S: User page */
213#define _PAGE_ENDIAN 0x00000080 /* H: E bit */ 260#define _PAGE_ENDIAN 0x00000080 /* H: E bit */
214#define _PAGE_GUARDED 0x00000100 /* H: G bit */ 261#define _PAGE_GUARDED 0x00000100 /* H: G bit */
215#define _PAGE_COHERENT 0x00000200 /* H: M bit */ 262#define _PAGE_DIRTY 0x00000200 /* S: Page dirty */
216#define _PAGE_FILE 0x00000400 /* S: nonlinear file mapping */
217#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ 263#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
218#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ 264#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
219 265
diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h
index f76221def484..bb53e2def363 100644
--- a/include/asm-ppc/ppc_asm.h
+++ b/include/asm-ppc/ppc_asm.h
@@ -186,6 +186,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
186#define PPC405_ERR77_SYNC 186#define PPC405_ERR77_SYNC
187#endif 187#endif
188 188
189#ifdef CONFIG_IBM440EP_ERR42
190#define PPC440EP_ERR42 isync
191#else
192#define PPC440EP_ERR42
193#endif
194
189/* The boring bits... */ 195/* The boring bits... */
190 196
191/* Condition Register Bit Fields */ 197/* Condition Register Bit Fields */
diff --git a/include/asm-ppc/unistd.h b/include/asm-ppc/unistd.h
index a7894e0fbbb1..3173ab3d2eb9 100644
--- a/include/asm-ppc/unistd.h
+++ b/include/asm-ppc/unistd.h
@@ -279,8 +279,11 @@
279#define __NR_waitid 272 279#define __NR_waitid 272
280#define __NR_ioprio_set 273 280#define __NR_ioprio_set 273
281#define __NR_ioprio_get 274 281#define __NR_ioprio_get 274
282#define __NR_inotify_init 275
283#define __NR_inotify_add_watch 276
284#define __NR_inotify_rm_watch 277
282 285
283#define __NR_syscalls 275 286#define __NR_syscalls 278
284 287
285#define __NR(n) #n 288#define __NR(n) #n
286 289
diff --git a/include/asm-ppc64/iSeries/HvReleaseData.h b/include/asm-ppc64/iSeries/HvReleaseData.h
index 01a1f13ea4a0..c8162e5ccb21 100644
--- a/include/asm-ppc64/iSeries/HvReleaseData.h
+++ b/include/asm-ppc64/iSeries/HvReleaseData.h
@@ -39,6 +39,11 @@
39 * know that this PLIC does not support running an OS "that old". 39 * know that this PLIC does not support running an OS "that old".
40 */ 40 */
41 41
42#define HVREL_TAGSINACTIVE 0x8000
43#define HVREL_32BIT 0x4000
44#define HVREL_NOSHAREDPROCS 0x2000
45#define HVREL_NOHMT 0x1000
46
42struct HvReleaseData { 47struct HvReleaseData {
43 u32 xDesc; /* Descriptor "HvRD" ebcdic x00-x03 */ 48 u32 xDesc; /* Descriptor "HvRD" ebcdic x00-x03 */
44 u16 xSize; /* Size of this control block x04-x05 */ 49 u16 xSize; /* Size of this control block x04-x05 */
@@ -46,11 +51,7 @@ struct HvReleaseData {
46 struct naca_struct *xSlicNacaAddr; /* Virt addr of SLIC NACA x08-x0F */ 51 struct naca_struct *xSlicNacaAddr; /* Virt addr of SLIC NACA x08-x0F */
47 u32 xMsNucDataOffset; /* Offset of Linux Mapping Data x10-x13 */ 52 u32 xMsNucDataOffset; /* Offset of Linux Mapping Data x10-x13 */
48 u32 xRsvd1; /* Reserved x14-x17 */ 53 u32 xRsvd1; /* Reserved x14-x17 */
49 u16 xTagsMode:1; /* 0 == tags active, 1 == tags inactive */ 54 u16 xFlags;
50 u16 xAddressSize:1; /* 0 == 64-bit, 1 == 32-bit */
51 u16 xNoSharedProcs:1; /* 0 == shared procs, 1 == no shared */
52 u16 xNoHMT:1; /* 0 == allow HMT, 1 == no HMT */
53 u16 xRsvd2:12; /* Reserved x18-x19 */
54 u16 xVrmIndex; /* VRM Index of OS image x1A-x1B */ 55 u16 xVrmIndex; /* VRM Index of OS image x1A-x1B */
55 u16 xMinSupportedPlicVrmIndex; /* Min PLIC level (soft) x1C-x1D */ 56 u16 xMinSupportedPlicVrmIndex; /* Min PLIC level (soft) x1C-x1D */
56 u16 xMinCompatablePlicVrmIndex; /* Min PLIC levelP (hard) x1E-x1F */ 57 u16 xMinCompatablePlicVrmIndex; /* Min PLIC levelP (hard) x1E-x1F */
diff --git a/include/asm-ppc64/iSeries/LparMap.h b/include/asm-ppc64/iSeries/LparMap.h
index 038e5df7e9f8..5c32e38c1c01 100644
--- a/include/asm-ppc64/iSeries/LparMap.h
+++ b/include/asm-ppc64/iSeries/LparMap.h
@@ -49,19 +49,26 @@
49 * entry to map the Esid to the Vsid. 49 * entry to map the Esid to the Vsid.
50*/ 50*/
51 51
52#define HvEsidsToMap 2
53#define HvRangesToMap 1
54
52/* Hypervisor initially maps 32MB of the load area */ 55/* Hypervisor initially maps 32MB of the load area */
53#define HvPagesToMap 8192 56#define HvPagesToMap 8192
54 57
55struct LparMap { 58struct LparMap {
56 u64 xNumberEsids; // Number of ESID/VSID pairs (1) 59 u64 xNumberEsids; // Number of ESID/VSID pairs
57 u64 xNumberRanges; // Number of VA ranges to map (1) 60 u64 xNumberRanges; // Number of VA ranges to map
58 u64 xSegmentTableOffs; // Page number within load area of seg table (0) 61 u64 xSegmentTableOffs; // Page number within load area of seg table
59 u64 xRsvd[5]; 62 u64 xRsvd[5];
60 u64 xKernelEsid; // Esid used to map kernel load (0x0C00000000) 63 struct {
61 u64 xKernelVsid; // Vsid used to map kernel load (0x0C00000000) 64 u64 xKernelEsid; // Esid used to map kernel load
62 u64 xPages; // Number of pages to be mapped (8192) 65 u64 xKernelVsid; // Vsid used to map kernel load
63 u64 xOffset; // Offset from start of load area (0) 66 } xEsids[HvEsidsToMap];
64 u64 xVPN; // Virtual Page Number (0x000C000000000000) 67 struct {
68 u64 xPages; // Number of pages to be mapped
69 u64 xOffset; // Offset from start of load area
70 u64 xVPN; // Virtual Page Number
71 } xRanges[HvRangesToMap];
65}; 72};
66 73
67extern struct LparMap xLparMap; 74extern struct LparMap xLparMap;
diff --git a/include/asm-ppc64/machdep.h b/include/asm-ppc64/machdep.h
index f0c1d2d92672..f0ef06375947 100644
--- a/include/asm-ppc64/machdep.h
+++ b/include/asm-ppc64/machdep.h
@@ -84,7 +84,7 @@ struct machdep_calls {
84 84
85 void (*init_IRQ)(void); 85 void (*init_IRQ)(void);
86 int (*get_irq)(struct pt_regs *); 86 int (*get_irq)(struct pt_regs *);
87 void (*cpu_irq_down)(void); 87 void (*cpu_irq_down)(int secondary);
88 88
89 /* PCI stuff */ 89 /* PCI stuff */
90 void (*pcibios_fixup)(void); 90 void (*pcibios_fixup)(void);
diff --git a/include/asm-ppc64/mmu.h b/include/asm-ppc64/mmu.h
index 3d07ddd11e3b..70348a851313 100644
--- a/include/asm-ppc64/mmu.h
+++ b/include/asm-ppc64/mmu.h
@@ -200,6 +200,8 @@ extern long native_hpte_insert(unsigned long hpte_group, unsigned long va,
200 unsigned long prpn, 200 unsigned long prpn,
201 unsigned long vflags, unsigned long rflags); 201 unsigned long vflags, unsigned long rflags);
202 202
203extern void stabs_alloc(void);
204
203#endif /* __ASSEMBLY__ */ 205#endif /* __ASSEMBLY__ */
204 206
205/* 207/*
@@ -336,6 +338,9 @@ static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
336 | (ea >> SID_SHIFT)); 338 | (ea >> SID_SHIFT));
337} 339}
338 340
341#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS)
342#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
343
339#endif /* __ASSEMBLY */ 344#endif /* __ASSEMBLY */
340 345
341#endif /* _PPC64_MMU_H_ */ 346#endif /* _PPC64_MMU_H_ */
diff --git a/include/asm-ppc64/pci.h b/include/asm-ppc64/pci.h
index faa772223075..4d057452f59b 100644
--- a/include/asm-ppc64/pci.h
+++ b/include/asm-ppc64/pci.h
@@ -134,6 +134,10 @@ extern void
134pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 134pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
135 struct resource *res); 135 struct resource *res);
136 136
137extern void
138pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
139 struct pci_bus_region *region);
140
137extern int 141extern int
138unmap_bus_range(struct pci_bus *bus); 142unmap_bus_range(struct pci_bus *bus);
139 143
diff --git a/include/asm-ppc64/topology.h b/include/asm-ppc64/topology.h
index fcdcfd26a26b..1e9b19073230 100644
--- a/include/asm-ppc64/topology.h
+++ b/include/asm-ppc64/topology.h
@@ -33,6 +33,7 @@ static inline int node_to_first_cpu(int node)
33 return first_cpu(tmp); 33 return first_cpu(tmp);
34} 34}
35 35
36#define pcibus_to_node(node) (-1)
36#define pcibus_to_cpumask(bus) (cpu_online_map) 37#define pcibus_to_cpumask(bus) (cpu_online_map)
37 38
38#define nr_cpus_node(node) (nr_cpus_in_node[node]) 39#define nr_cpus_node(node) (nr_cpus_in_node[node])
@@ -59,8 +60,10 @@ static inline int node_to_first_cpu(int node)
59 .nr_balance_failed = 0, \ 60 .nr_balance_failed = 0, \
60} 61}
61 62
62#endif /* CONFIG_NUMA */ 63#else
63 64
64#include <asm-generic/topology.h> 65#include <asm-generic/topology.h>
65 66
67#endif /* CONFIG_NUMA */
68
66#endif /* _ASM_PPC64_TOPOLOGY_H */ 69#endif /* _ASM_PPC64_TOPOLOGY_H */
diff --git a/include/asm-ppc64/unistd.h b/include/asm-ppc64/unistd.h
index 4a94acf6bfed..977bc980c1af 100644
--- a/include/asm-ppc64/unistd.h
+++ b/include/asm-ppc64/unistd.h
@@ -285,8 +285,11 @@
285#define __NR_waitid 272 285#define __NR_waitid 272
286#define __NR_ioprio_set 273 286#define __NR_ioprio_set 273
287#define __NR_ioprio_get 274 287#define __NR_ioprio_get 274
288#define __NR_inotify_init 275
289#define __NR_inotify_add_watch 276
290#define __NR_inotify_rm_watch 277
288 291
289#define __NR_syscalls 275 292#define __NR_syscalls 278
290#ifdef __KERNEL__ 293#ifdef __KERNEL__
291#define NR_syscalls __NR_syscalls 294#define NR_syscalls __NR_syscalls
292#endif 295#endif
diff --git a/include/asm-ppc64/xics.h b/include/asm-ppc64/xics.h
index 0c45e14e26ca..1092af55d707 100644
--- a/include/asm-ppc64/xics.h
+++ b/include/asm-ppc64/xics.h
@@ -17,7 +17,7 @@
17void xics_init_IRQ(void); 17void xics_init_IRQ(void);
18int xics_get_irq(struct pt_regs *); 18int xics_get_irq(struct pt_regs *);
19void xics_setup_cpu(void); 19void xics_setup_cpu(void);
20void xics_teardown_cpu(void); 20void xics_teardown_cpu(int secondary);
21void xics_cause_IPI(int cpu); 21void xics_cause_IPI(int cpu);
22void xics_request_IPIs(void); 22void xics_request_IPIs(void);
23void xics_migrate_irqs_away(void); 23void xics_migrate_irqs_away(void);
diff --git a/include/asm-s390/atomic.h b/include/asm-s390/atomic.h
index d5a05cf47168..9d86ba6f12d0 100644
--- a/include/asm-s390/atomic.h
+++ b/include/asm-s390/atomic.h
@@ -123,19 +123,19 @@ typedef struct {
123#define atomic64_read(v) ((v)->counter) 123#define atomic64_read(v) ((v)->counter)
124#define atomic64_set(v,i) (((v)->counter) = (i)) 124#define atomic64_set(v,i) (((v)->counter) = (i))
125 125
126static __inline__ void atomic64_add(int i, atomic64_t * v) 126static __inline__ void atomic64_add(long long i, atomic64_t * v)
127{ 127{
128 __CSG_LOOP(v, i, "agr"); 128 __CSG_LOOP(v, i, "agr");
129} 129}
130static __inline__ long long atomic64_add_return(int i, atomic64_t * v) 130static __inline__ long long atomic64_add_return(long long i, atomic64_t * v)
131{ 131{
132 return __CSG_LOOP(v, i, "agr"); 132 return __CSG_LOOP(v, i, "agr");
133} 133}
134static __inline__ long long atomic64_add_negative(int i, atomic64_t * v) 134static __inline__ long long atomic64_add_negative(long long i, atomic64_t * v)
135{ 135{
136 return __CSG_LOOP(v, i, "agr") < 0; 136 return __CSG_LOOP(v, i, "agr") < 0;
137} 137}
138static __inline__ void atomic64_sub(int i, atomic64_t * v) 138static __inline__ void atomic64_sub(long long i, atomic64_t * v)
139{ 139{
140 __CSG_LOOP(v, i, "sgr"); 140 __CSG_LOOP(v, i, "sgr");
141} 141}
diff --git a/include/asm-s390/bitops.h b/include/asm-s390/bitops.h
index 16bb08499c7f..8651524217fd 100644
--- a/include/asm-s390/bitops.h
+++ b/include/asm-s390/bitops.h
@@ -527,13 +527,64 @@ __constant_test_bit(unsigned long nr, const volatile unsigned long *addr) {
527 __constant_test_bit((nr),(addr)) : \ 527 __constant_test_bit((nr),(addr)) : \
528 __test_bit((nr),(addr)) ) 528 __test_bit((nr),(addr)) )
529 529
530#ifndef __s390x__ 530/*
531 * ffz = Find First Zero in word. Undefined if no zero exists,
532 * so code should check against ~0UL first..
533 */
534static inline unsigned long ffz(unsigned long word)
535{
536 unsigned long bit = 0;
537
538#ifdef __s390x__
539 if (likely((word & 0xffffffff) == 0xffffffff)) {
540 word >>= 32;
541 bit += 32;
542 }
543#endif
544 if (likely((word & 0xffff) == 0xffff)) {
545 word >>= 16;
546 bit += 16;
547 }
548 if (likely((word & 0xff) == 0xff)) {
549 word >>= 8;
550 bit += 8;
551 }
552 return bit + _zb_findmap[word & 0xff];
553}
554
555/*
556 * __ffs = find first bit in word. Undefined if no bit exists,
557 * so code should check against 0UL first..
558 */
559static inline unsigned long __ffs (unsigned long word)
560{
561 unsigned long bit = 0;
562
563#ifdef __s390x__
564 if (likely((word & 0xffffffff) == 0)) {
565 word >>= 32;
566 bit += 32;
567 }
568#endif
569 if (likely((word & 0xffff) == 0)) {
570 word >>= 16;
571 bit += 16;
572 }
573 if (likely((word & 0xff) == 0)) {
574 word >>= 8;
575 bit += 8;
576 }
577 return bit + _sb_findmap[word & 0xff];
578}
531 579
532/* 580/*
533 * Find-bit routines.. 581 * Find-bit routines..
534 */ 582 */
583
584#ifndef __s390x__
585
535static inline int 586static inline int
536find_first_zero_bit(const unsigned long * addr, unsigned int size) 587find_first_zero_bit(const unsigned long * addr, unsigned long size)
537{ 588{
538 typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype; 589 typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
539 unsigned long cmp, count; 590 unsigned long cmp, count;
@@ -548,7 +599,7 @@ find_first_zero_bit(const unsigned long * addr, unsigned int size)
548 " srl %2,5\n" 599 " srl %2,5\n"
549 "0: c %1,0(%0,%4)\n" 600 "0: c %1,0(%0,%4)\n"
550 " jne 1f\n" 601 " jne 1f\n"
551 " ahi %0,4\n" 602 " la %0,4(%0)\n"
552 " brct %2,0b\n" 603 " brct %2,0b\n"
553 " lr %0,%3\n" 604 " lr %0,%3\n"
554 " j 4f\n" 605 " j 4f\n"
@@ -574,7 +625,7 @@ find_first_zero_bit(const unsigned long * addr, unsigned int size)
574} 625}
575 626
576static inline int 627static inline int
577find_first_bit(const unsigned long * addr, unsigned int size) 628find_first_bit(const unsigned long * addr, unsigned long size)
578{ 629{
579 typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype; 630 typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
580 unsigned long cmp, count; 631 unsigned long cmp, count;
@@ -589,7 +640,7 @@ find_first_bit(const unsigned long * addr, unsigned int size)
589 " srl %2,5\n" 640 " srl %2,5\n"
590 "0: c %1,0(%0,%4)\n" 641 "0: c %1,0(%0,%4)\n"
591 " jne 1f\n" 642 " jne 1f\n"
592 " ahi %0,4\n" 643 " la %0,4(%0)\n"
593 " brct %2,0b\n" 644 " brct %2,0b\n"
594 " lr %0,%3\n" 645 " lr %0,%3\n"
595 " j 4f\n" 646 " j 4f\n"
@@ -614,89 +665,8 @@ find_first_bit(const unsigned long * addr, unsigned int size)
614 return (res < size) ? res : size; 665 return (res < size) ? res : size;
615} 666}
616 667
617static inline int
618find_next_zero_bit (const unsigned long * addr, int size, int offset)
619{
620 unsigned long * p = ((unsigned long *) addr) + (offset >> 5);
621 unsigned long bitvec, reg;
622 int set, bit = offset & 31, res;
623
624 if (bit) {
625 /*
626 * Look for zero in first word
627 */
628 bitvec = (*p) >> bit;
629 __asm__(" slr %0,%0\n"
630 " lhi %2,0xff\n"
631 " tml %1,0xffff\n"
632 " jno 0f\n"
633 " ahi %0,16\n"
634 " srl %1,16\n"
635 "0: tml %1,0x00ff\n"
636 " jno 1f\n"
637 " ahi %0,8\n"
638 " srl %1,8\n"
639 "1: nr %1,%2\n"
640 " ic %1,0(%1,%3)\n"
641 " alr %0,%1"
642 : "=&d" (set), "+a" (bitvec), "=&d" (reg)
643 : "a" (&_zb_findmap) : "cc" );
644 if (set < (32 - bit))
645 return set + offset;
646 offset += 32 - bit;
647 p++;
648 }
649 /*
650 * No zero yet, search remaining full words for a zero
651 */
652 res = find_first_zero_bit (p, size - 32 * (p - (unsigned long *) addr));
653 return (offset + res);
654}
655
656static inline int
657find_next_bit (const unsigned long * addr, int size, int offset)
658{
659 unsigned long * p = ((unsigned long *) addr) + (offset >> 5);
660 unsigned long bitvec, reg;
661 int set, bit = offset & 31, res;
662
663 if (bit) {
664 /*
665 * Look for set bit in first word
666 */
667 bitvec = (*p) >> bit;
668 __asm__(" slr %0,%0\n"
669 " lhi %2,0xff\n"
670 " tml %1,0xffff\n"
671 " jnz 0f\n"
672 " ahi %0,16\n"
673 " srl %1,16\n"
674 "0: tml %1,0x00ff\n"
675 " jnz 1f\n"
676 " ahi %0,8\n"
677 " srl %1,8\n"
678 "1: nr %1,%2\n"
679 " ic %1,0(%1,%3)\n"
680 " alr %0,%1"
681 : "=&d" (set), "+a" (bitvec), "=&d" (reg)
682 : "a" (&_sb_findmap) : "cc" );
683 if (set < (32 - bit))
684 return set + offset;
685 offset += 32 - bit;
686 p++;
687 }
688 /*
689 * No set bit yet, search remaining full words for a bit
690 */
691 res = find_first_bit (p, size - 32 * (p - (unsigned long *) addr));
692 return (offset + res);
693}
694
695#else /* __s390x__ */ 668#else /* __s390x__ */
696 669
697/*
698 * Find-bit routines..
699 */
700static inline unsigned long 670static inline unsigned long
701find_first_zero_bit(const unsigned long * addr, unsigned long size) 671find_first_zero_bit(const unsigned long * addr, unsigned long size)
702{ 672{
@@ -712,7 +682,7 @@ find_first_zero_bit(const unsigned long * addr, unsigned long size)
712 " srlg %2,%2,6\n" 682 " srlg %2,%2,6\n"
713 "0: cg %1,0(%0,%4)\n" 683 "0: cg %1,0(%0,%4)\n"
714 " jne 1f\n" 684 " jne 1f\n"
715 " aghi %0,8\n" 685 " la %0,8(%0)\n"
716 " brct %2,0b\n" 686 " brct %2,0b\n"
717 " lgr %0,%3\n" 687 " lgr %0,%3\n"
718 " j 5f\n" 688 " j 5f\n"
@@ -785,143 +755,66 @@ find_first_bit(const unsigned long * addr, unsigned long size)
785 return (res < size) ? res : size; 755 return (res < size) ? res : size;
786} 756}
787 757
788static inline unsigned long
789find_next_zero_bit (const unsigned long * addr, unsigned long size, unsigned long offset)
790{
791 unsigned long * p = ((unsigned long *) addr) + (offset >> 6);
792 unsigned long bitvec, reg;
793 unsigned long set, bit = offset & 63, res;
794
795 if (bit) {
796 /*
797 * Look for zero in first word
798 */
799 bitvec = (*p) >> bit;
800 __asm__(" lhi %2,-1\n"
801 " slgr %0,%0\n"
802 " clr %1,%2\n"
803 " jne 0f\n"
804 " aghi %0,32\n"
805 " srlg %1,%1,32\n"
806 "0: lghi %2,0xff\n"
807 " tmll %1,0xffff\n"
808 " jno 1f\n"
809 " aghi %0,16\n"
810 " srlg %1,%1,16\n"
811 "1: tmll %1,0x00ff\n"
812 " jno 2f\n"
813 " aghi %0,8\n"
814 " srlg %1,%1,8\n"
815 "2: ngr %1,%2\n"
816 " ic %1,0(%1,%3)\n"
817 " algr %0,%1"
818 : "=&d" (set), "+a" (bitvec), "=&d" (reg)
819 : "a" (&_zb_findmap) : "cc" );
820 if (set < (64 - bit))
821 return set + offset;
822 offset += 64 - bit;
823 p++;
824 }
825 /*
826 * No zero yet, search remaining full words for a zero
827 */
828 res = find_first_zero_bit (p, size - 64 * (p - (unsigned long *) addr));
829 return (offset + res);
830}
831
832static inline unsigned long
833find_next_bit (const unsigned long * addr, unsigned long size, unsigned long offset)
834{
835 unsigned long * p = ((unsigned long *) addr) + (offset >> 6);
836 unsigned long bitvec, reg;
837 unsigned long set, bit = offset & 63, res;
838
839 if (bit) {
840 /*
841 * Look for zero in first word
842 */
843 bitvec = (*p) >> bit;
844 __asm__(" slgr %0,%0\n"
845 " ltr %1,%1\n"
846 " jnz 0f\n"
847 " aghi %0,32\n"
848 " srlg %1,%1,32\n"
849 "0: lghi %2,0xff\n"
850 " tmll %1,0xffff\n"
851 " jnz 1f\n"
852 " aghi %0,16\n"
853 " srlg %1,%1,16\n"
854 "1: tmll %1,0x00ff\n"
855 " jnz 2f\n"
856 " aghi %0,8\n"
857 " srlg %1,%1,8\n"
858 "2: ngr %1,%2\n"
859 " ic %1,0(%1,%3)\n"
860 " algr %0,%1"
861 : "=&d" (set), "+a" (bitvec), "=&d" (reg)
862 : "a" (&_sb_findmap) : "cc" );
863 if (set < (64 - bit))
864 return set + offset;
865 offset += 64 - bit;
866 p++;
867 }
868 /*
869 * No set bit yet, search remaining full words for a bit
870 */
871 res = find_first_bit (p, size - 64 * (p - (unsigned long *) addr));
872 return (offset + res);
873}
874
875#endif /* __s390x__ */ 758#endif /* __s390x__ */
876 759
877/* 760static inline int
878 * ffz = Find First Zero in word. Undefined if no zero exists, 761find_next_zero_bit (const unsigned long * addr, unsigned long size,
879 * so code should check against ~0UL first.. 762 unsigned long offset)
880 */
881static inline unsigned long ffz(unsigned long word)
882{ 763{
883 unsigned long bit = 0; 764 const unsigned long *p;
884 765 unsigned long bit, set;
885#ifdef __s390x__ 766
886 if (likely((word & 0xffffffff) == 0xffffffff)) { 767 if (offset >= size)
887 word >>= 32; 768 return size;
888 bit += 32; 769 bit = offset & (__BITOPS_WORDSIZE - 1);
889 } 770 offset -= bit;
890#endif 771 size -= offset;
891 if (likely((word & 0xffff) == 0xffff)) { 772 p = addr + offset / __BITOPS_WORDSIZE;
892 word >>= 16; 773 if (bit) {
893 bit += 16; 774 /*
775 * s390 version of ffz returns __BITOPS_WORDSIZE
776 * if no zero bit is present in the word.
777 */
778 set = ffz(*p >> bit) + bit;
779 if (set >= size)
780 return size + offset;
781 if (set < __BITOPS_WORDSIZE)
782 return set + offset;
783 offset += __BITOPS_WORDSIZE;
784 size -= __BITOPS_WORDSIZE;
785 p++;
894 } 786 }
895 if (likely((word & 0xff) == 0xff)) { 787 return offset + find_first_zero_bit(p, size);
896 word >>= 8;
897 bit += 8;
898 }
899 return bit + _zb_findmap[word & 0xff];
900} 788}
901 789
902/* 790static inline int
903 * __ffs = find first bit in word. Undefined if no bit exists, 791find_next_bit (const unsigned long * addr, unsigned long size,
904 * so code should check against 0UL first.. 792 unsigned long offset)
905 */
906static inline unsigned long __ffs (unsigned long word)
907{ 793{
908 unsigned long bit = 0; 794 const unsigned long *p;
909 795 unsigned long bit, set;
910#ifdef __s390x__ 796
911 if (likely((word & 0xffffffff) == 0)) { 797 if (offset >= size)
912 word >>= 32; 798 return size;
913 bit += 32; 799 bit = offset & (__BITOPS_WORDSIZE - 1);
800 offset -= bit;
801 size -= offset;
802 p = addr + offset / __BITOPS_WORDSIZE;
803 if (bit) {
804 /*
805 * s390 version of __ffs returns __BITOPS_WORDSIZE
806 * if no one bit is present in the word.
807 */
808 set = __ffs(*p & (~0UL << bit));
809 if (set >= size)
810 return size + offset;
811 if (set < __BITOPS_WORDSIZE)
812 return set + offset;
813 offset += __BITOPS_WORDSIZE;
814 size -= __BITOPS_WORDSIZE;
815 p++;
914 } 816 }
915#endif 817 return offset + find_first_bit(p, size);
916 if (likely((word & 0xffff) == 0)) {
917 word >>= 16;
918 bit += 16;
919 }
920 if (likely((word & 0xff) == 0)) {
921 word >>= 8;
922 bit += 8;
923 }
924 return bit + _sb_findmap[word & 0xff];
925} 818}
926 819
927/* 820/*
@@ -1031,49 +924,6 @@ ext2_find_first_zero_bit(void *vaddr, unsigned int size)
1031 return (res < size) ? res : size; 924 return (res < size) ? res : size;
1032} 925}
1033 926
1034static inline int
1035ext2_find_next_zero_bit(void *vaddr, unsigned int size, unsigned offset)
1036{
1037 unsigned long *addr = vaddr;
1038 unsigned long *p = addr + (offset >> 5);
1039 unsigned long word, reg;
1040 unsigned int bit = offset & 31UL, res;
1041
1042 if (offset >= size)
1043 return size;
1044
1045 if (bit) {
1046 __asm__(" ic %0,0(%1)\n"
1047 " icm %0,2,1(%1)\n"
1048 " icm %0,4,2(%1)\n"
1049 " icm %0,8,3(%1)"
1050 : "=&a" (word) : "a" (p) : "cc" );
1051 word >>= bit;
1052 res = bit;
1053 /* Look for zero in first longword */
1054 __asm__(" lhi %2,0xff\n"
1055 " tml %1,0xffff\n"
1056 " jno 0f\n"
1057 " ahi %0,16\n"
1058 " srl %1,16\n"
1059 "0: tml %1,0x00ff\n"
1060 " jno 1f\n"
1061 " ahi %0,8\n"
1062 " srl %1,8\n"
1063 "1: nr %1,%2\n"
1064 " ic %1,0(%1,%3)\n"
1065 " alr %0,%1"
1066 : "+&d" (res), "+&a" (word), "=&d" (reg)
1067 : "a" (&_zb_findmap) : "cc" );
1068 if (res < 32)
1069 return (p - addr)*32 + res;
1070 p++;
1071 }
1072 /* No zero yet, search remaining full bytes for a zero */
1073 res = ext2_find_first_zero_bit (p, size - 32 * (p - addr));
1074 return (p - addr) * 32 + res;
1075}
1076
1077#else /* __s390x__ */ 927#else /* __s390x__ */
1078 928
1079static inline unsigned long 929static inline unsigned long
@@ -1120,56 +970,46 @@ ext2_find_first_zero_bit(void *vaddr, unsigned long size)
1120 return (res < size) ? res : size; 970 return (res < size) ? res : size;
1121} 971}
1122 972
1123static inline unsigned long 973#endif /* __s390x__ */
974
975static inline int
1124ext2_find_next_zero_bit(void *vaddr, unsigned long size, unsigned long offset) 976ext2_find_next_zero_bit(void *vaddr, unsigned long size, unsigned long offset)
1125{ 977{
1126 unsigned long *addr = vaddr; 978 unsigned long *addr = vaddr, *p;
1127 unsigned long *p = addr + (offset >> 6); 979 unsigned long word, bit, set;
1128 unsigned long word, reg;
1129 unsigned long bit = offset & 63UL, res;
1130 980
1131 if (offset >= size) 981 if (offset >= size)
1132 return size; 982 return size;
1133 983 bit = offset & (__BITOPS_WORDSIZE - 1);
984 offset -= bit;
985 size -= offset;
986 p = addr + offset / __BITOPS_WORDSIZE;
1134 if (bit) { 987 if (bit) {
1135 __asm__(" lrvg %0,%1" /* load reversed, neat instruction */ 988#ifndef __s390x__
1136 : "=a" (word) : "m" (*p) ); 989 asm(" ic %0,0(%1)\n"
1137 word >>= bit; 990 " icm %0,2,1(%1)\n"
1138 res = bit; 991 " icm %0,4,2(%1)\n"
1139 /* Look for zero in first 8 byte word */ 992 " icm %0,8,3(%1)"
1140 __asm__(" lghi %2,0xff\n" 993 : "=&a" (word) : "a" (p), "m" (*p) : "cc" );
1141 " tmll %1,0xffff\n" 994#else
1142 " jno 2f\n" 995 asm(" lrvg %0,%1" : "=a" (word) : "m" (*p) );
1143 " ahi %0,16\n" 996#endif
1144 " srlg %1,%1,16\n" 997 /*
1145 "0: tmll %1,0xffff\n" 998 * s390 version of ffz returns __BITOPS_WORDSIZE
1146 " jno 2f\n" 999 * if no zero bit is present in the word.
1147 " ahi %0,16\n" 1000 */
1148 " srlg %1,%1,16\n" 1001 set = ffz(word >> bit) + bit;
1149 "1: tmll %1,0xffff\n" 1002 if (set >= size)
1150 " jno 2f\n" 1003 return size + offset;
1151 " ahi %0,16\n" 1004 if (set < __BITOPS_WORDSIZE)
1152 " srl %1,16\n" 1005 return set + offset;
1153 "2: tmll %1,0x00ff\n" 1006 offset += __BITOPS_WORDSIZE;
1154 " jno 3f\n" 1007 size -= __BITOPS_WORDSIZE;
1155 " ahi %0,8\n" 1008 p++;
1156 " srl %1,8\n"
1157 "3: ngr %1,%2\n"
1158 " ic %1,0(%1,%3)\n"
1159 " alr %0,%1"
1160 : "+&d" (res), "+a" (word), "=&d" (reg)
1161 : "a" (&_zb_findmap) : "cc" );
1162 if (res < 64)
1163 return (p - addr)*64 + res;
1164 p++;
1165 } 1009 }
1166 /* No zero yet, search remaining full bytes for a zero */ 1010 return offset + ext2_find_first_zero_bit(p, size);
1167 res = ext2_find_first_zero_bit (p, size - 64 * (p - addr));
1168 return (p - addr) * 64 + res;
1169} 1011}
1170 1012
1171#endif /* __s390x__ */
1172
1173/* Bitmap functions for the minix filesystem. */ 1013/* Bitmap functions for the minix filesystem. */
1174/* FIXME !!! */ 1014/* FIXME !!! */
1175#define minix_test_and_set_bit(nr,addr) \ 1015#define minix_test_and_set_bit(nr,addr) \
diff --git a/include/asm-s390/lowcore.h b/include/asm-s390/lowcore.h
index 76b5b19c0ae2..afe6a9f9b0ae 100644
--- a/include/asm-s390/lowcore.h
+++ b/include/asm-s390/lowcore.h
@@ -90,7 +90,6 @@
90#define __LC_SYSTEM_TIMER 0x278 90#define __LC_SYSTEM_TIMER 0x278
91#define __LC_LAST_UPDATE_CLOCK 0x280 91#define __LC_LAST_UPDATE_CLOCK 0x280
92#define __LC_STEAL_CLOCK 0x288 92#define __LC_STEAL_CLOCK 0x288
93#define __LC_DIAG44_OPCODE 0x290
94#define __LC_KERNEL_STACK 0xD40 93#define __LC_KERNEL_STACK 0xD40
95#define __LC_THREAD_INFO 0xD48 94#define __LC_THREAD_INFO 0xD48
96#define __LC_ASYNC_STACK 0xD50 95#define __LC_ASYNC_STACK 0xD50
@@ -286,8 +285,7 @@ struct _lowcore
286 __u64 system_timer; /* 0x278 */ 285 __u64 system_timer; /* 0x278 */
287 __u64 last_update_clock; /* 0x280 */ 286 __u64 last_update_clock; /* 0x280 */
288 __u64 steal_clock; /* 0x288 */ 287 __u64 steal_clock; /* 0x288 */
289 __u32 diag44_opcode; /* 0x290 */ 288 __u8 pad8[0xc00-0x290]; /* 0x290 */
290 __u8 pad8[0xc00-0x294]; /* 0x294 */
291 /* System info area */ 289 /* System info area */
292 __u64 save_area[16]; /* 0xc00 */ 290 __u64 save_area[16]; /* 0xc00 */
293 __u8 pad9[0xd40-0xc80]; /* 0xc80 */ 291 __u8 pad9[0xd40-0xc80]; /* 0xc80 */
diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h
index 8bd14de69e35..4ec652ebb3b1 100644
--- a/include/asm-s390/processor.h
+++ b/include/asm-s390/processor.h
@@ -203,7 +203,10 @@ unsigned long get_wchan(struct task_struct *p);
203# define cpu_relax() asm volatile ("diag 0,0,68" : : : "memory") 203# define cpu_relax() asm volatile ("diag 0,0,68" : : : "memory")
204#else /* __s390x__ */ 204#else /* __s390x__ */
205# define cpu_relax() \ 205# define cpu_relax() \
206 asm volatile ("ex 0,%0" : : "i" (__LC_DIAG44_OPCODE) : "memory") 206 do { \
207 if (MACHINE_HAS_DIAG44) \
208 asm volatile ("diag 0,0,68" : : : "memory"); \
209 } while (0)
207#endif /* __s390x__ */ 210#endif /* __s390x__ */
208 211
209/* 212/*
diff --git a/include/asm-s390/spinlock.h b/include/asm-s390/spinlock.h
index 53cc736b9820..8ff10300f7ee 100644
--- a/include/asm-s390/spinlock.h
+++ b/include/asm-s390/spinlock.h
@@ -11,21 +11,16 @@
11#ifndef __ASM_SPINLOCK_H 11#ifndef __ASM_SPINLOCK_H
12#define __ASM_SPINLOCK_H 12#define __ASM_SPINLOCK_H
13 13
14#ifdef __s390x__ 14static inline int
15/* 15_raw_compare_and_swap(volatile unsigned int *lock,
16 * Grmph, take care of %&#! user space programs that include 16 unsigned int old, unsigned int new)
17 * asm/spinlock.h. The diagnose is only available in kernel 17{
18 * context. 18 asm volatile ("cs %0,%3,0(%4)"
19 */ 19 : "=d" (old), "=m" (*lock)
20#ifdef __KERNEL__ 20 : "0" (old), "d" (new), "a" (lock), "m" (*lock)
21#include <asm/lowcore.h> 21 : "cc", "memory" );
22#define __DIAG44_INSN "ex" 22 return old;
23#define __DIAG44_OPERAND __LC_DIAG44_OPCODE 23}
24#else
25#define __DIAG44_INSN "#"
26#define __DIAG44_OPERAND 0
27#endif
28#endif /* __s390x__ */
29 24
30/* 25/*
31 * Simple spin lock operations. There are two variants, one clears IRQ's 26 * Simple spin lock operations. There are two variants, one clears IRQ's
@@ -41,58 +36,35 @@ typedef struct {
41#endif 36#endif
42} __attribute__ ((aligned (4))) spinlock_t; 37} __attribute__ ((aligned (4))) spinlock_t;
43 38
44#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 } 39#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
45#define spin_lock_init(lp) do { (lp)->lock = 0; } while(0) 40#define spin_lock_init(lp) do { (lp)->lock = 0; } while(0)
46#define spin_unlock_wait(lp) do { barrier(); } while(((volatile spinlock_t *)(lp))->lock) 41#define spin_unlock_wait(lp) do { barrier(); } while(((volatile spinlock_t *)(lp))->lock)
47#define spin_is_locked(x) ((x)->lock != 0) 42#define spin_is_locked(x) ((x)->lock != 0)
48#define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock) 43#define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
49 44
50extern inline void _raw_spin_lock(spinlock_t *lp) 45extern void _raw_spin_lock_wait(spinlock_t *lp, unsigned int pc);
46extern int _raw_spin_trylock_retry(spinlock_t *lp, unsigned int pc);
47
48static inline void _raw_spin_lock(spinlock_t *lp)
51{ 49{
52#ifndef __s390x__ 50 unsigned long pc = (unsigned long) __builtin_return_address(0);
53 unsigned int reg1, reg2; 51
54 __asm__ __volatile__(" bras %0,1f\n" 52 if (unlikely(_raw_compare_and_swap(&lp->lock, 0, pc) != 0))
55 "0: diag 0,0,68\n" 53 _raw_spin_lock_wait(lp, pc);
56 "1: slr %1,%1\n"
57 " cs %1,%0,0(%3)\n"
58 " jl 0b\n"
59 : "=&d" (reg1), "=&d" (reg2), "=m" (lp->lock)
60 : "a" (&lp->lock), "m" (lp->lock)
61 : "cc", "memory" );
62#else /* __s390x__ */
63 unsigned long reg1, reg2;
64 __asm__ __volatile__(" bras %1,1f\n"
65 "0: " __DIAG44_INSN " 0,%4\n"
66 "1: slr %0,%0\n"
67 " cs %0,%1,0(%3)\n"
68 " jl 0b\n"
69 : "=&d" (reg1), "=&d" (reg2), "=m" (lp->lock)
70 : "a" (&lp->lock), "i" (__DIAG44_OPERAND),
71 "m" (lp->lock) : "cc", "memory" );
72#endif /* __s390x__ */
73} 54}
74 55
75extern inline int _raw_spin_trylock(spinlock_t *lp) 56static inline int _raw_spin_trylock(spinlock_t *lp)
76{ 57{
77 unsigned long reg; 58 unsigned long pc = (unsigned long) __builtin_return_address(0);
78 unsigned int result; 59
79 60 if (likely(_raw_compare_and_swap(&lp->lock, 0, pc) == 0))
80 __asm__ __volatile__(" basr %1,0\n" 61 return 1;
81 "0: cs %0,%1,0(%3)" 62 return _raw_spin_trylock_retry(lp, pc);
82 : "=d" (result), "=&d" (reg), "=m" (lp->lock)
83 : "a" (&lp->lock), "m" (lp->lock), "0" (0)
84 : "cc", "memory" );
85 return !result;
86} 63}
87 64
88extern inline void _raw_spin_unlock(spinlock_t *lp) 65static inline void _raw_spin_unlock(spinlock_t *lp)
89{ 66{
90 unsigned int old; 67 _raw_compare_and_swap(&lp->lock, lp->lock, 0);
91
92 __asm__ __volatile__("cs %0,%3,0(%4)"
93 : "=d" (old), "=m" (lp->lock)
94 : "0" (lp->lock), "d" (0), "a" (lp)
95 : "cc", "memory" );
96} 68}
97 69
98/* 70/*
@@ -106,7 +78,7 @@ extern inline void _raw_spin_unlock(spinlock_t *lp)
106 * read-locks. 78 * read-locks.
107 */ 79 */
108typedef struct { 80typedef struct {
109 volatile unsigned long lock; 81 volatile unsigned int lock;
110 volatile unsigned long owner_pc; 82 volatile unsigned long owner_pc;
111#ifdef CONFIG_PREEMPT 83#ifdef CONFIG_PREEMPT
112 unsigned int break_lock; 84 unsigned int break_lock;
@@ -129,123 +101,55 @@ typedef struct {
129 */ 101 */
130#define write_can_lock(x) ((x)->lock == 0) 102#define write_can_lock(x) ((x)->lock == 0)
131 103
132#ifndef __s390x__ 104extern void _raw_read_lock_wait(rwlock_t *lp);
133#define _raw_read_lock(rw) \ 105extern int _raw_read_trylock_retry(rwlock_t *lp);
134 asm volatile(" l 2,0(%1)\n" \ 106extern void _raw_write_lock_wait(rwlock_t *lp);
135 " j 1f\n" \ 107extern int _raw_write_trylock_retry(rwlock_t *lp);
136 "0: diag 0,0,68\n" \ 108
137 "1: la 2,0(2)\n" /* clear high (=write) bit */ \ 109static inline void _raw_read_lock(rwlock_t *rw)
138 " la 3,1(2)\n" /* one more reader */ \ 110{
139 " cs 2,3,0(%1)\n" /* try to write new value */ \ 111 unsigned int old;
140 " jl 0b" \ 112 old = rw->lock & 0x7fffffffU;
141 : "=m" ((rw)->lock) : "a" (&(rw)->lock), \ 113 if (_raw_compare_and_swap(&rw->lock, old, old + 1) != old)
142 "m" ((rw)->lock) : "2", "3", "cc", "memory" ) 114 _raw_read_lock_wait(rw);
143#else /* __s390x__ */ 115}
144#define _raw_read_lock(rw) \ 116
145 asm volatile(" lg 2,0(%1)\n" \ 117static inline void _raw_read_unlock(rwlock_t *rw)
146 " j 1f\n" \ 118{
147 "0: " __DIAG44_INSN " 0,%2\n" \ 119 unsigned int old, cmp;
148 "1: nihh 2,0x7fff\n" /* clear high (=write) bit */ \ 120
149 " la 3,1(2)\n" /* one more reader */ \ 121 old = rw->lock;
150 " csg 2,3,0(%1)\n" /* try to write new value */ \ 122 do {
151 " jl 0b" \ 123 cmp = old;
152 : "=m" ((rw)->lock) \ 124 old = _raw_compare_and_swap(&rw->lock, old, old - 1);
153 : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \ 125 } while (cmp != old);
154 "m" ((rw)->lock) : "2", "3", "cc", "memory" ) 126}
155#endif /* __s390x__ */ 127
156 128static inline void _raw_write_lock(rwlock_t *rw)
157#ifndef __s390x__ 129{
158#define _raw_read_unlock(rw) \ 130 if (unlikely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) != 0))
159 asm volatile(" l 2,0(%1)\n" \ 131 _raw_write_lock_wait(rw);
160 " j 1f\n" \ 132}
161 "0: diag 0,0,68\n" \ 133
162 "1: lr 3,2\n" \ 134static inline void _raw_write_unlock(rwlock_t *rw)
163 " ahi 3,-1\n" /* one less reader */ \ 135{
164 " cs 2,3,0(%1)\n" \ 136 _raw_compare_and_swap(&rw->lock, 0x80000000, 0);
165 " jl 0b" \ 137}
166 : "=m" ((rw)->lock) : "a" (&(rw)->lock), \ 138
167 "m" ((rw)->lock) : "2", "3", "cc", "memory" ) 139static inline int _raw_read_trylock(rwlock_t *rw)
168#else /* __s390x__ */ 140{
169#define _raw_read_unlock(rw) \ 141 unsigned int old;
170 asm volatile(" lg 2,0(%1)\n" \ 142 old = rw->lock & 0x7fffffffU;
171 " j 1f\n" \ 143 if (likely(_raw_compare_and_swap(&rw->lock, old, old + 1) == old))
172 "0: " __DIAG44_INSN " 0,%2\n" \ 144 return 1;
173 "1: lgr 3,2\n" \ 145 return _raw_read_trylock_retry(rw);
174 " bctgr 3,0\n" /* one less reader */ \ 146}
175 " csg 2,3,0(%1)\n" \ 147
176 " jl 0b" \ 148static inline int _raw_write_trylock(rwlock_t *rw)
177 : "=m" ((rw)->lock) \
178 : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
179 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
180#endif /* __s390x__ */
181
182#ifndef __s390x__
183#define _raw_write_lock(rw) \
184 asm volatile(" lhi 3,1\n" \
185 " sll 3,31\n" /* new lock value = 0x80000000 */ \
186 " j 1f\n" \
187 "0: diag 0,0,68\n" \
188 "1: slr 2,2\n" /* old lock value must be 0 */ \
189 " cs 2,3,0(%1)\n" \
190 " jl 0b" \
191 : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
192 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
193#else /* __s390x__ */
194#define _raw_write_lock(rw) \
195 asm volatile(" llihh 3,0x8000\n" /* new lock value = 0x80...0 */ \
196 " j 1f\n" \
197 "0: " __DIAG44_INSN " 0,%2\n" \
198 "1: slgr 2,2\n" /* old lock value must be 0 */ \
199 " csg 2,3,0(%1)\n" \
200 " jl 0b" \
201 : "=m" ((rw)->lock) \
202 : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
203 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
204#endif /* __s390x__ */
205
206#ifndef __s390x__
207#define _raw_write_unlock(rw) \
208 asm volatile(" slr 3,3\n" /* new lock value = 0 */ \
209 " j 1f\n" \
210 "0: diag 0,0,68\n" \
211 "1: lhi 2,1\n" \
212 " sll 2,31\n" /* old lock value must be 0x80000000 */ \
213 " cs 2,3,0(%1)\n" \
214 " jl 0b" \
215 : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
216 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
217#else /* __s390x__ */
218#define _raw_write_unlock(rw) \
219 asm volatile(" slgr 3,3\n" /* new lock value = 0 */ \
220 " j 1f\n" \
221 "0: " __DIAG44_INSN " 0,%2\n" \
222 "1: llihh 2,0x8000\n" /* old lock value must be 0x8..0 */\
223 " csg 2,3,0(%1)\n" \
224 " jl 0b" \
225 : "=m" ((rw)->lock) \
226 : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
227 "m" ((rw)->lock) : "2", "3", "cc", "memory" )
228#endif /* __s390x__ */
229
230#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
231
232extern inline int _raw_write_trylock(rwlock_t *rw)
233{ 149{
234 unsigned long result, reg; 150 if (likely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0))
235 151 return 1;
236 __asm__ __volatile__( 152 return _raw_write_trylock_retry(rw);
237#ifndef __s390x__
238 " lhi %1,1\n"
239 " sll %1,31\n"
240 " cs %0,%1,0(%3)"
241#else /* __s390x__ */
242 " llihh %1,0x8000\n"
243 "0: csg %0,%1,0(%3)\n"
244#endif /* __s390x__ */
245 : "=d" (result), "=&d" (reg), "=m" (rw->lock)
246 : "a" (&rw->lock), "m" (rw->lock), "0" (0UL)
247 : "cc", "memory" );
248 return result == 0;
249} 153}
250 154
251#endif /* __ASM_SPINLOCK_H */ 155#endif /* __ASM_SPINLOCK_H */
diff --git a/include/asm-s390/unistd.h b/include/asm-s390/unistd.h
index 363db45f8d07..221e965da924 100644
--- a/include/asm-s390/unistd.h
+++ b/include/asm-s390/unistd.h
@@ -274,8 +274,13 @@
274#define __NR_request_key 279 274#define __NR_request_key 279
275#define __NR_keyctl 280 275#define __NR_keyctl 280
276#define __NR_waitid 281 276#define __NR_waitid 281
277#define __NR_ioprio_set 282
278#define __NR_ioprio_get 283
279#define __NR_inotify_init 284
280#define __NR_inotify_add_watch 285
281#define __NR_inotify_rm_watch 286
277 282
278#define NR_syscalls 282 283#define NR_syscalls 287
279 284
280/* 285/*
281 * There are some system calls that are not present on 64 bit, some 286 * There are some system calls that are not present on 64 bit, some
diff --git a/include/asm-sparc/unistd.h b/include/asm-sparc/unistd.h
index aee17d7e2e44..58dba518239e 100644
--- a/include/asm-sparc/unistd.h
+++ b/include/asm-sparc/unistd.h
@@ -167,12 +167,12 @@
167#define __NR_pciconfig_read 148 /* ENOSYS under SunOS */ 167#define __NR_pciconfig_read 148 /* ENOSYS under SunOS */
168#define __NR_pciconfig_write 149 /* ENOSYS under SunOS */ 168#define __NR_pciconfig_write 149 /* ENOSYS under SunOS */
169#define __NR_getsockname 150 /* Common */ 169#define __NR_getsockname 150 /* Common */
170/* #define __NR_getmsg 151 SunOS Specific */ 170#define __NR_inotify_init 151 /* Linux specific */
171/* #define __NR_putmsg 152 SunOS Specific */ 171#define __NR_inotify_add_watch 152 /* Linux specific */
172#define __NR_poll 153 /* Common */ 172#define __NR_poll 153 /* Common */
173#define __NR_getdents64 154 /* Linux specific */ 173#define __NR_getdents64 154 /* Linux specific */
174#define __NR_fcntl64 155 /* Linux sparc32 Specific */ 174#define __NR_fcntl64 155 /* Linux sparc32 Specific */
175/* #define __NR_getdirentires 156 SunOS Specific */ 175#define __NR_inotify_rm_watch 156 /* Linux specific */
176#define __NR_statfs 157 /* Common */ 176#define __NR_statfs 157 /* Common */
177#define __NR_fstatfs 158 /* Common */ 177#define __NR_fstatfs 158 /* Common */
178#define __NR_umount 159 /* Common */ 178#define __NR_umount 159 /* Common */
diff --git a/include/asm-sparc64/unistd.h b/include/asm-sparc64/unistd.h
index f59144c6b76a..51ec2879b881 100644
--- a/include/asm-sparc64/unistd.h
+++ b/include/asm-sparc64/unistd.h
@@ -167,12 +167,12 @@
167#define __NR_pciconfig_read 148 /* ENOSYS under SunOS */ 167#define __NR_pciconfig_read 148 /* ENOSYS under SunOS */
168#define __NR_pciconfig_write 149 /* ENOSYS under SunOS */ 168#define __NR_pciconfig_write 149 /* ENOSYS under SunOS */
169#define __NR_getsockname 150 /* Common */ 169#define __NR_getsockname 150 /* Common */
170/* #define __NR_getmsg 151 SunOS Specific */ 170#define __NR_inotify_init 151 /* Linux specific */
171/* #define __NR_putmsg 152 SunOS Specific */ 171#define __NR_inotify_add_watch 152 /* Linux specific */
172#define __NR_poll 153 /* Common */ 172#define __NR_poll 153 /* Common */
173#define __NR_getdents64 154 /* Linux specific */ 173#define __NR_getdents64 154 /* Linux specific */
174/* #define __NR_fcntl64 155 Linux sparc32 Specific */ 174/* #define __NR_fcntl64 155 Linux sparc32 Specific */
175/* #define __NR_getdirentries 156 SunOS Specific */ 175#define __NR_inotify_rm_watch 156 /* Linux specific */
176#define __NR_statfs 157 /* Common */ 176#define __NR_statfs 157 /* Common */
177#define __NR_fstatfs 158 /* Common */ 177#define __NR_fstatfs 158 /* Common */
178#define __NR_umount 159 /* Common */ 178#define __NR_umount 159 /* Common */
diff --git a/include/asm-um/vm86.h b/include/asm-um/vm86.h
new file mode 100644
index 000000000000..7801f82de1f4
--- /dev/null
+++ b/include/asm-um/vm86.h
@@ -0,0 +1,6 @@
1#ifndef __UM_VM86_H
2#define __UM_VM86_H
3
4#include "asm/arch/vm86.h"
5
6#endif
diff --git a/include/asm-v850/bitops.h b/include/asm-v850/bitops.h
index 7c4ecaf5151c..0e5c2f210872 100644
--- a/include/asm-v850/bitops.h
+++ b/include/asm-v850/bitops.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * include/asm-v850/bitops.h -- Bit operations 2 * include/asm-v850/bitops.h -- Bit operations
3 * 3 *
4 * Copyright (C) 2001,02,03,04 NEC Electronics Corporation 4 * Copyright (C) 2001,02,03,04,05 NEC Electronics Corporation
5 * Copyright (C) 2001,02,03,04 Miles Bader <miles@gnu.org> 5 * Copyright (C) 2001,02,03,04,05 Miles Bader <miles@gnu.org>
6 * Copyright (C) 1992 Linus Torvalds. 6 * Copyright (C) 1992 Linus Torvalds.
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General 8 * This file is subject to the terms and conditions of the GNU General
@@ -157,7 +157,7 @@ extern __inline__ int __test_bit (int nr, const void *addr)
157#define find_first_zero_bit(addr, size) \ 157#define find_first_zero_bit(addr, size) \
158 find_next_zero_bit ((addr), (size), 0) 158 find_next_zero_bit ((addr), (size), 0)
159 159
160extern __inline__ int find_next_zero_bit (void *addr, int size, int offset) 160extern __inline__ int find_next_zero_bit(const void *addr, int size, int offset)
161{ 161{
162 unsigned long *p = ((unsigned long *) addr) + (offset >> 5); 162 unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
163 unsigned long result = offset & ~31UL; 163 unsigned long result = offset & ~31UL;
diff --git a/include/asm-v850/cache.h b/include/asm-v850/cache.h
index 027f8c9090cd..cbf9096e8517 100644
--- a/include/asm-v850/cache.h
+++ b/include/asm-v850/cache.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * include/asm-v850/cache.h -- Cache operations 2 * include/asm-v850/cache.h -- Cache operations
3 * 3 *
4 * Copyright (C) 2001 NEC Corporation 4 * Copyright (C) 2001,05 NEC Corporation
5 * Copyright (C) 2001 Miles Bader <miles@gnu.org> 5 * Copyright (C) 2001,05 Miles Bader <miles@gnu.org>
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General 7 * This file is subject to the terms and conditions of the GNU General
8 * Public License. See the file COPYING in the main directory of this 8 * Public License. See the file COPYING in the main directory of this
@@ -20,6 +20,9 @@
20#ifndef L1_CACHE_BYTES 20#ifndef L1_CACHE_BYTES
21/* This processor has no cache, so just choose an arbitrary value. */ 21/* This processor has no cache, so just choose an arbitrary value. */
22#define L1_CACHE_BYTES 16 22#define L1_CACHE_BYTES 16
23#define L1_CACHE_SHIFT 4
23#endif 24#endif
24 25
26#define L1_CACHE_SHIFT_MAX L1_CACHE_SHIFT
27
25#endif /* __V850_CACHE_H__ */ 28#endif /* __V850_CACHE_H__ */
diff --git a/include/asm-v850/io.h b/include/asm-v850/io.h
index bb5efd1b4b7d..cc364fcbec10 100644
--- a/include/asm-v850/io.h
+++ b/include/asm-v850/io.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * include/asm-v850/io.h -- Misc I/O operations 2 * include/asm-v850/io.h -- Misc I/O operations
3 * 3 *
4 * Copyright (C) 2001,02,03,04 NEC Electronics Corporation 4 * Copyright (C) 2001,02,03,04,05 NEC Electronics Corporation
5 * Copyright (C) 2001,02,03,04 Miles Bader <miles@gnu.org> 5 * Copyright (C) 2001,02,03,04,05 Miles Bader <miles@gnu.org>
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General 7 * This file is subject to the terms and conditions of the GNU General
8 * Public License. See the file COPYING in the main directory of this 8 * Public License. See the file COPYING in the main directory of this
@@ -27,12 +27,12 @@
27#define readw_relaxed(a) readw(a) 27#define readw_relaxed(a) readw(a)
28#define readl_relaxed(a) readl(a) 28#define readl_relaxed(a) readl(a)
29 29
30#define writeb(b, addr) \ 30#define writeb(val, addr) \
31 (void)((*(volatile unsigned char *) (addr)) = (b)) 31 (void)((*(volatile unsigned char *) (addr)) = (val))
32#define writew(b, addr) \ 32#define writew(val, addr) \
33 (void)((*(volatile unsigned short *) (addr)) = (b)) 33 (void)((*(volatile unsigned short *) (addr)) = (val))
34#define writel(b, addr) \ 34#define writel(val, addr) \
35 (void)((*(volatile unsigned int *) (addr)) = (b)) 35 (void)((*(volatile unsigned int *) (addr)) = (val))
36 36
37#define __raw_readb readb 37#define __raw_readb readb
38#define __raw_readw readw 38#define __raw_readw readw
@@ -96,11 +96,22 @@ outsl (unsigned long port, const void *src, unsigned long count)
96 outl (*p++, port); 96 outl (*p++, port);
97} 97}
98 98
99#define iounmap(addr) ((void)0) 99
100#define ioremap(physaddr, size) (physaddr) 100/* Some places try to pass in an loff_t for PHYSADDR (?!), so we cast it to
101#define ioremap_nocache(physaddr, size) (physaddr) 101 long before casting it to a pointer to avoid compiler warnings. */
102#define ioremap_writethrough(physaddr, size) (physaddr) 102#define ioremap(physaddr, size) ((void __iomem *)(unsigned long)(physaddr))
103#define ioremap_fullcache(physaddr, size) (physaddr) 103#define iounmap(addr) ((void)0)
104
105#define ioremap_nocache(physaddr, size) ioremap (physaddr, size)
106#define ioremap_writethrough(physaddr, size) ioremap (physaddr, size)
107#define ioremap_fullcache(physaddr, size) ioremap (physaddr, size)
108
109#define ioread8(addr) readb (addr)
110#define ioread16(addr) readw (addr)
111#define ioread32(addr) readl (addr)
112#define iowrite8(val, addr) writeb (val, addr)
113#define iowrite16(val, addr) writew (val, addr)
114#define iowrite32(val, addr) writel (val, addr)
104 115
105#define mmiowb() 116#define mmiowb()
106 117
diff --git a/include/asm-v850/page.h b/include/asm-v850/page.h
index 06085b0c043e..d6091622935d 100644
--- a/include/asm-v850/page.h
+++ b/include/asm-v850/page.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * include/asm-v850/page.h -- VM ops 2 * include/asm-v850/page.h -- VM ops
3 * 3 *
4 * Copyright (C) 2001,02,03 NEC Electronics Corporation 4 * Copyright (C) 2001,02,03,05 NEC Electronics Corporation
5 * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org> 5 * Copyright (C) 2001,02,03,05 Miles Bader <miles@gnu.org>
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General 7 * This file is subject to the terms and conditions of the GNU General
8 * Public License. See the file COPYING in the main directory of this 8 * Public License. See the file COPYING in the main directory of this
@@ -132,6 +132,7 @@ extern __inline__ int get_order (unsigned long size)
132 132
133#define pfn_to_page(pfn) virt_to_page (pfn_to_virt (pfn)) 133#define pfn_to_page(pfn) virt_to_page (pfn_to_virt (pfn))
134#define page_to_pfn(page) virt_to_pfn (page_to_virt (page)) 134#define page_to_pfn(page) virt_to_pfn (page_to_virt (page))
135#define pfn_valid(pfn) ((pfn) < max_mapnr)
135 136
136#define virt_addr_valid(kaddr) \ 137#define virt_addr_valid(kaddr) \
137 (((void *)(kaddr) >= (void *)PAGE_OFFSET) && MAP_NR (kaddr) < max_mapnr) 138 (((void *)(kaddr) >= (void *)PAGE_OFFSET) && MAP_NR (kaddr) < max_mapnr)
diff --git a/include/asm-v850/pci.h b/include/asm-v850/pci.h
index 8e79be0fe99d..4581826e1cac 100644
--- a/include/asm-v850/pci.h
+++ b/include/asm-v850/pci.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * include/asm-v850/pci.h -- PCI support 2 * include/asm-v850/pci.h -- PCI support
3 * 3 *
4 * Copyright (C) 2001,02 NEC Corporation 4 * Copyright (C) 2001,02,05 NEC Corporation
5 * Copyright (C) 2001,02 Miles Bader <miles@gnu.org> 5 * Copyright (C) 2001,02,05 Miles Bader <miles@gnu.org>
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General 7 * This file is subject to the terms and conditions of the GNU General
8 * Public License. See the file COPYING in the main directory of this 8 * Public License. See the file COPYING in the main directory of this
@@ -48,12 +48,12 @@ pci_unmap_single (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size,
48 perform a pci_dma_sync_for_device, and then the device again owns 48 perform a pci_dma_sync_for_device, and then the device again owns
49 the buffer. */ 49 the buffer. */
50extern void 50extern void
51pci_dma_sync_single_for_cpu (struct pci_dev *dev, dma_addr_t dma_addr, size_t size, 51pci_dma_sync_single_for_cpu (struct pci_dev *dev, dma_addr_t dma_addr,
52 int dir); 52 size_t size, int dir);
53 53
54extern void 54extern void
55pci_dma_sync_single_for_device (struct pci_dev *dev, dma_addr_t dma_addr, size_t size, 55pci_dma_sync_single_for_device (struct pci_dev *dev, dma_addr_t dma_addr,
56 int dir); 56 size_t size, int dir);
57 57
58 58
59/* Do multiple DMA mappings at once. */ 59/* Do multiple DMA mappings at once. */
@@ -65,6 +65,28 @@ extern void
65pci_unmap_sg (struct pci_dev *pdev, struct scatterlist *sg, int sg_len, 65pci_unmap_sg (struct pci_dev *pdev, struct scatterlist *sg, int sg_len,
66 int dir); 66 int dir);
67 67
68/* SG-list versions of pci_dma_sync functions. */
69extern void
70pci_dma_sync_sg_for_cpu (struct pci_dev *dev,
71 struct scatterlist *sg, int sg_len,
72 int dir);
73extern void
74pci_dma_sync_sg_for_device (struct pci_dev *dev,
75 struct scatterlist *sg, int sg_len,
76 int dir);
77
78#define pci_map_page(dev, page, offs, size, dir) \
79 pci_map_single(dev, (page_address(page) + (offs)), size, dir)
80#define pci_unmap_page(dev,addr,sz,dir) \
81 pci_unmap_single(dev, addr, sz, dir)
82
83/* Test for pci_map_single or pci_map_page having generated an error. */
84static inline int
85pci_dma_mapping_error (dma_addr_t dma_addr)
86{
87 return dma_addr == 0;
88}
89
68/* Allocate and map kernel buffer using consistent mode DMA for PCI 90/* Allocate and map kernel buffer using consistent mode DMA for PCI
69 device. Returns non-NULL cpu-view pointer to the buffer if 91 device. Returns non-NULL cpu-view pointer to the buffer if
70 successful and sets *DMA_ADDR to the pci side dma address as well, 92 successful and sets *DMA_ADDR to the pci side dma address as well,
@@ -91,6 +113,9 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
91} 113}
92#endif 114#endif
93 115
116extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
117extern void pci_iounmap (struct pci_dev *dev, void __iomem *addr);
118
94static inline void pcibios_add_platform_entries(struct pci_dev *dev) 119static inline void pcibios_add_platform_entries(struct pci_dev *dev)
95{ 120{
96} 121}
diff --git a/include/asm-v850/pgtable.h b/include/asm-v850/pgtable.h
index 76e380e481e9..3cf8775ce85f 100644
--- a/include/asm-v850/pgtable.h
+++ b/include/asm-v850/pgtable.h
@@ -23,6 +23,8 @@
23#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 23#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
24#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 24#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
25 25
26static inline int pte_file (pte_t pte) { return 0; }
27
26 28
27/* These mean nothing to !CONFIG_MMU. */ 29/* These mean nothing to !CONFIG_MMU. */
28#define PAGE_NONE __pgprot(0) 30#define PAGE_NONE __pgprot(0)
diff --git a/include/asm-v850/v850e2_cache.h b/include/asm-v850/v850e2_cache.h
index 61acda1023e8..87edf0d311d5 100644
--- a/include/asm-v850/v850e2_cache.h
+++ b/include/asm-v850/v850e2_cache.h
@@ -2,8 +2,8 @@
2 * include/asm-v850/v850e2_cache_cache.h -- Cache control for V850E2 2 * include/asm-v850/v850e2_cache_cache.h -- Cache control for V850E2
3 * cache memories 3 * cache memories
4 * 4 *
5 * Copyright (C) 2003 NEC Electronics Corporation 5 * Copyright (C) 2003,05 NEC Electronics Corporation
6 * Copyright (C) 2003 Miles Bader <miles@gnu.org> 6 * Copyright (C) 2003,05 Miles Bader <miles@gnu.org>
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General 8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file COPYING in the main directory of this 9 * Public License. See the file COPYING in the main directory of this
@@ -69,6 +69,7 @@
69 69
70/* For <asm/cache.h> */ 70/* For <asm/cache.h> */
71#define L1_CACHE_BYTES V850E2_CACHE_LINE_SIZE 71#define L1_CACHE_BYTES V850E2_CACHE_LINE_SIZE
72#define L1_CACHE_SHIFT V850E2_CACHE_LINE_SIZE_BITS
72 73
73 74
74#endif /* __V850_V850E2_CACHE_H__ */ 75#endif /* __V850_V850E2_CACHE_H__ */
diff --git a/include/asm-x86_64/bitops.h b/include/asm-x86_64/bitops.h
index a31bb99be53f..05a0d374404b 100644
--- a/include/asm-x86_64/bitops.h
+++ b/include/asm-x86_64/bitops.h
@@ -348,8 +348,7 @@ static inline int sched_find_first_bit(const unsigned long *b)
348 return __ffs(b[0]); 348 return __ffs(b[0]);
349 if (b[1]) 349 if (b[1])
350 return __ffs(b[1]) + 64; 350 return __ffs(b[1]) + 64;
351 if (b[2]) 351 return __ffs(b[2]) + 128;
352 return __ffs(b[2]) + 128;
353} 352}
354 353
355/** 354/**
diff --git a/include/asm-x86_64/bug.h b/include/asm-x86_64/bug.h
index 3d2a666a5dd5..eed785667289 100644
--- a/include/asm-x86_64/bug.h
+++ b/include/asm-x86_64/bug.h
@@ -8,17 +8,24 @@
8 * this frame. 8 * this frame.
9 */ 9 */
10struct bug_frame { 10struct bug_frame {
11 unsigned char ud2[2]; 11 unsigned char ud2[2];
12 unsigned char mov;
12 /* should use 32bit offset instead, but the assembler doesn't 13 /* should use 32bit offset instead, but the assembler doesn't
13 like it */ 14 like it */
14 char *filename; 15 char *filename;
16 unsigned char ret;
15 unsigned short line; 17 unsigned short line;
16} __attribute__((packed)); 18} __attribute__((packed));
17 19
18#ifdef CONFIG_BUG 20#ifdef CONFIG_BUG
19#define HAVE_ARCH_BUG 21#define HAVE_ARCH_BUG
20#define BUG() \ 22/* We turn the bug frame into valid instructions to not confuse
21 asm volatile("ud2 ; .quad %c1 ; .short %c0" :: \ 23 the disassembler. Thanks to Jan Beulich & Suresh Siddha
24 for nice instruction selection.
25 The magic numbers generate mov $64bitimm,%eax ; ret $offset. */
26#define BUG() \
27 asm volatile( \
28 "ud2 ; .byte 0xa3 ; .quad %c1 ; .byte 0xc2 ; .short %c0" :: \
22 "i"(__LINE__), "i" (__stringify(__FILE__))) 29 "i"(__LINE__), "i" (__stringify(__FILE__)))
23void out_of_line_bug(void); 30void out_of_line_bug(void);
24#else 31#else
diff --git a/include/asm-x86_64/desc.h b/include/asm-x86_64/desc.h
index 6aefb9c0280d..c89b58bebee2 100644
--- a/include/asm-x86_64/desc.h
+++ b/include/asm-x86_64/desc.h
@@ -75,6 +75,7 @@ struct desc_ptr {
75 */ 75 */
76extern struct desc_struct default_ldt[]; 76extern struct desc_struct default_ldt[];
77extern struct gate_struct idt_table[]; 77extern struct gate_struct idt_table[];
78extern struct desc_ptr cpu_gdt_descr[];
78 79
79static inline void _set_gate(void *adr, unsigned type, unsigned long func, unsigned dpl, unsigned ist) 80static inline void _set_gate(void *adr, unsigned type, unsigned long func, unsigned dpl, unsigned ist)
80{ 81{
diff --git a/include/asm-x86_64/ipi.h b/include/asm-x86_64/ipi.h
index d1841847ed89..5e166b9d3bde 100644
--- a/include/asm-x86_64/ipi.h
+++ b/include/asm-x86_64/ipi.h
@@ -82,30 +82,27 @@ static inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
82 */ 82 */
83 local_irq_save(flags); 83 local_irq_save(flags);
84 84
85 for (query_cpu = 0; query_cpu < NR_CPUS; ++query_cpu) { 85 for_each_cpu_mask(query_cpu, mask) {
86 if (cpu_isset(query_cpu, mask)) { 86 /*
87 87 * Wait for idle.
88 /* 88 */
89 * Wait for idle. 89 apic_wait_icr_idle();
90 */ 90
91 apic_wait_icr_idle(); 91 /*
92 92 * prepare target chip field
93 /* 93 */
94 * prepare target chip field 94 cfg = __prepare_ICR2(x86_cpu_to_apicid[query_cpu]);
95 */ 95 apic_write_around(APIC_ICR2, cfg);
96 cfg = __prepare_ICR2(x86_cpu_to_apicid[query_cpu]); 96
97 apic_write_around(APIC_ICR2, cfg); 97 /*
98 98 * program the ICR
99 /* 99 */
100 * program the ICR 100 cfg = __prepare_ICR(0, vector, APIC_DEST_PHYSICAL);
101 */ 101
102 cfg = __prepare_ICR(0, vector, APIC_DEST_PHYSICAL); 102 /*
103 103 * Send the IPI. The write to APIC_ICR fires this off.
104 /* 104 */
105 * Send the IPI. The write to APIC_ICR fires this off. 105 apic_write_around(APIC_ICR, cfg);
106 */
107 apic_write_around(APIC_ICR, cfg);
108 }
109 } 106 }
110 local_irq_restore(flags); 107 local_irq_restore(flags);
111} 108}
diff --git a/include/asm-x86_64/irq.h b/include/asm-x86_64/irq.h
index eb3b7aa9eb9f..4482657777bb 100644
--- a/include/asm-x86_64/irq.h
+++ b/include/asm-x86_64/irq.h
@@ -57,4 +57,6 @@ int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
57extern void fixup_irqs(cpumask_t map); 57extern void fixup_irqs(cpumask_t map);
58#endif 58#endif
59 59
60#define __ARCH_HAS_DO_SOFTIRQ 1
61
60#endif /* _ASM_IRQ_H */ 62#endif /* _ASM_IRQ_H */
diff --git a/include/asm-x86_64/msr.h b/include/asm-x86_64/msr.h
index bc700232728d..ba15279a79d0 100644
--- a/include/asm-x86_64/msr.h
+++ b/include/asm-x86_64/msr.h
@@ -218,7 +218,7 @@ extern inline unsigned int cpuid_edx(unsigned int op)
218#define MSR_K7_PERFCTR3 0xC0010007 218#define MSR_K7_PERFCTR3 0xC0010007
219#define MSR_K8_TOP_MEM1 0xC001001A 219#define MSR_K8_TOP_MEM1 0xC001001A
220#define MSR_K8_TOP_MEM2 0xC001001D 220#define MSR_K8_TOP_MEM2 0xC001001D
221#define MSR_K8_SYSCFG 0xC0000010 221#define MSR_K8_SYSCFG 0xC0010010
222 222
223/* K6 MSRs */ 223/* K6 MSRs */
224#define MSR_K6_EFER 0xC0000080 224#define MSR_K6_EFER 0xC0000080
diff --git a/include/asm-x86_64/pci.h b/include/asm-x86_64/pci.h
index eeb3088a1c9e..9c4527eb55e2 100644
--- a/include/asm-x86_64/pci.h
+++ b/include/asm-x86_64/pci.h
@@ -22,11 +22,9 @@ extern unsigned int pcibios_assign_all_busses(void);
22extern int no_iommu, force_iommu; 22extern int no_iommu, force_iommu;
23 23
24extern unsigned long pci_mem_start; 24extern unsigned long pci_mem_start;
25#define PCIBIOS_MIN_IO 0x1000 25#define PCIBIOS_MIN_IO 0x4000
26#define PCIBIOS_MIN_MEM (pci_mem_start) 26#define PCIBIOS_MIN_MEM (pci_mem_start)
27 27
28#define PCIBIOS_MIN_CARDBUS_IO 0x4000
29
30void pcibios_config_init(void); 28void pcibios_config_init(void);
31struct pci_bus * pcibios_scan_root(int bus); 29struct pci_bus * pcibios_scan_root(int bus);
32extern int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value); 30extern int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value);
diff --git a/include/asm-x86_64/pgtable.h b/include/asm-x86_64/pgtable.h
index 4eec176c3c39..4e167b5ea8f3 100644
--- a/include/asm-x86_64/pgtable.h
+++ b/include/asm-x86_64/pgtable.h
@@ -176,6 +176,8 @@ extern inline void pgd_clear (pgd_t * pgd)
176 (_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_PCD) 176 (_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_PCD)
177#define __PAGE_KERNEL_LARGE \ 177#define __PAGE_KERNEL_LARGE \
178 (__PAGE_KERNEL | _PAGE_PSE) 178 (__PAGE_KERNEL | _PAGE_PSE)
179#define __PAGE_KERNEL_LARGE_EXEC \
180 (__PAGE_KERNEL_EXEC | _PAGE_PSE)
179 181
180#define MAKE_GLOBAL(x) __pgprot((x) | _PAGE_GLOBAL) 182#define MAKE_GLOBAL(x) __pgprot((x) | _PAGE_GLOBAL)
181 183
diff --git a/include/asm-x86_64/smp.h b/include/asm-x86_64/smp.h
index aeb1b73e21e1..de8b57b2b62b 100644
--- a/include/asm-x86_64/smp.h
+++ b/include/asm-x86_64/smp.h
@@ -46,12 +46,12 @@ extern int pic_mode;
46extern void lock_ipi_call_lock(void); 46extern void lock_ipi_call_lock(void);
47extern void unlock_ipi_call_lock(void); 47extern void unlock_ipi_call_lock(void);
48extern int smp_num_siblings; 48extern int smp_num_siblings;
49extern void smp_flush_tlb(void);
50extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs);
51extern void smp_send_reschedule(int cpu); 49extern void smp_send_reschedule(int cpu);
52extern void smp_invalidate_rcv(void); /* Process an NMI */
53extern void zap_low_mappings(void); 50extern void zap_low_mappings(void);
54void smp_stop_cpu(void); 51void smp_stop_cpu(void);
52extern int smp_call_function_single(int cpuid, void (*func) (void *info),
53 void *info, int retry, int wait);
54
55extern cpumask_t cpu_sibling_map[NR_CPUS]; 55extern cpumask_t cpu_sibling_map[NR_CPUS];
56extern cpumask_t cpu_core_map[NR_CPUS]; 56extern cpumask_t cpu_core_map[NR_CPUS];
57extern u8 phys_proc_id[NR_CPUS]; 57extern u8 phys_proc_id[NR_CPUS];
diff --git a/include/asm-x86_64/system.h b/include/asm-x86_64/system.h
index 76165736e43a..8606e170a7dc 100644
--- a/include/asm-x86_64/system.h
+++ b/include/asm-x86_64/system.h
@@ -116,12 +116,12 @@ struct alt_instr {
116/* 116/*
117 * Alternative inline assembly with input. 117 * Alternative inline assembly with input.
118 * 118 *
119 * Pecularities: 119 * Peculiarities:
120 * No memory clobber here. 120 * No memory clobber here.
121 * Argument numbers start with 1. 121 * Argument numbers start with 1.
122 * Best is to use constraints that are fixed size (like (%1) ... "r") 122 * Best is to use constraints that are fixed size (like (%1) ... "r")
123 * If you use variable sized constraints like "m" or "g" in the 123 * If you use variable sized constraints like "m" or "g" in the
124 * replacement maake sure to pad to the worst case length. 124 * replacement make sure to pad to the worst case length.
125 */ 125 */
126#define alternative_input(oldinstr, newinstr, feature, input...) \ 126#define alternative_input(oldinstr, newinstr, feature, input...) \
127 asm volatile ("661:\n\t" oldinstr "\n662:\n" \ 127 asm volatile ("661:\n\t" oldinstr "\n662:\n" \
@@ -335,9 +335,6 @@ void cpu_idle_wait(void);
335void disable_hlt(void); 335void disable_hlt(void);
336void enable_hlt(void); 336void enable_hlt(void);
337 337
338#define HAVE_EAT_KEY
339void eat_key(void);
340
341extern unsigned long arch_align_stack(unsigned long sp); 338extern unsigned long arch_align_stack(unsigned long sp);
342 339
343#endif 340#endif
diff --git a/include/asm-x86_64/tlbflush.h b/include/asm-x86_64/tlbflush.h
index 061742382520..505b0cf906de 100644
--- a/include/asm-x86_64/tlbflush.h
+++ b/include/asm-x86_64/tlbflush.h
@@ -56,8 +56,9 @@ extern unsigned long pgkern_mask;
56 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages 56 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
57 * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables 57 * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
58 * 58 *
59 * ..but the x86_64 has somewhat limited tlb flushing capabilities, 59 * x86-64 can only flush individual pages or full VMs. For a range flush
60 * and page-granular flushes are available only on i486 and up. 60 * we always do the full VM. Might be worth trying if for a small
61 * range a few INVLPGs in a row are a win.
61 */ 62 */
62 63
63#ifndef CONFIG_SMP 64#ifndef CONFIG_SMP
@@ -115,7 +116,9 @@ static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long st
115static inline void flush_tlb_pgtables(struct mm_struct *mm, 116static inline void flush_tlb_pgtables(struct mm_struct *mm,
116 unsigned long start, unsigned long end) 117 unsigned long start, unsigned long end)
117{ 118{
118 /* x86_64 does not keep any page table caches in TLB */ 119 /* x86_64 does not keep any page table caches in a software TLB.
120 The CPUs do in their hardware TLBs, but they are handled
121 by the normal TLB flushing algorithms. */
119} 122}
120 123
121#endif /* _X8664_TLBFLUSH_H */ 124#endif /* _X8664_TLBFLUSH_H */
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index f85cbe919e13..b46a5205ee7b 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -453,9 +453,7 @@ int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
453 * If this matches the last registration, any IRQ resources for gsi 453 * If this matches the last registration, any IRQ resources for gsi
454 * are freed. 454 * are freed.
455 */ 455 */
456#ifdef CONFIG_ACPI_DEALLOCATE_IRQ
457void acpi_unregister_gsi (u32 gsi); 456void acpi_unregister_gsi (u32 gsi);
458#endif
459 457
460#ifdef CONFIG_ACPI_PCI 458#ifdef CONFIG_ACPI_PCI
461 459
@@ -480,9 +478,7 @@ struct pci_dev;
480int acpi_pci_irq_enable (struct pci_dev *dev); 478int acpi_pci_irq_enable (struct pci_dev *dev);
481void acpi_penalize_isa_irq(int irq, int active); 479void acpi_penalize_isa_irq(int irq, int active);
482 480
483#ifdef CONFIG_ACPI_DEALLOCATE_IRQ
484void acpi_pci_irq_disable (struct pci_dev *dev); 481void acpi_pci_irq_disable (struct pci_dev *dev);
485#endif
486 482
487struct acpi_pci_driver { 483struct acpi_pci_driver {
488 struct acpi_pci_driver *next; 484 struct acpi_pci_driver *next;
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index 0881b5cdee3d..19bd8e7e11bf 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -301,6 +301,7 @@ struct blk_queue_tag {
301 struct list_head busy_list; /* fifo list of busy tags */ 301 struct list_head busy_list; /* fifo list of busy tags */
302 int busy; /* current depth */ 302 int busy; /* current depth */
303 int max_depth; /* what we will send to device */ 303 int max_depth; /* what we will send to device */
304 int real_max_depth; /* what the array can hold */
304 atomic_t refcnt; /* map can be shared */ 305 atomic_t refcnt; /* map can be shared */
305}; 306};
306 307
diff --git a/include/linux/dcookies.h b/include/linux/dcookies.h
index c28050136164..1d68428c925d 100644
--- a/include/linux/dcookies.h
+++ b/include/linux/dcookies.h
@@ -48,12 +48,12 @@ int get_dcookie(struct dentry * dentry, struct vfsmount * vfsmnt,
48 48
49#else 49#else
50 50
51struct dcookie_user * dcookie_register(void) 51static inline struct dcookie_user * dcookie_register(void)
52{ 52{
53 return NULL; 53 return NULL;
54} 54}
55 55
56void dcookie_unregister(struct dcookie_user * user) 56static inline void dcookie_unregister(struct dcookie_user * user)
57{ 57{
58 return; 58 return;
59} 59}
diff --git a/include/linux/fs.h b/include/linux/fs.h
index 0f53e0124941..f9adf75fd9b4 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -697,11 +697,13 @@ extern struct list_head file_lock_list;
697#include <linux/fcntl.h> 697#include <linux/fcntl.h>
698 698
699extern int fcntl_getlk(struct file *, struct flock __user *); 699extern int fcntl_getlk(struct file *, struct flock __user *);
700extern int fcntl_setlk(struct file *, unsigned int, struct flock __user *); 700extern int fcntl_setlk(unsigned int, struct file *, unsigned int,
701 struct flock __user *);
701 702
702#if BITS_PER_LONG == 32 703#if BITS_PER_LONG == 32
703extern int fcntl_getlk64(struct file *, struct flock64 __user *); 704extern int fcntl_getlk64(struct file *, struct flock64 __user *);
704extern int fcntl_setlk64(struct file *, unsigned int, struct flock64 __user *); 705extern int fcntl_setlk64(unsigned int, struct file *, unsigned int,
706 struct flock64 __user *);
705#endif 707#endif
706 708
707extern void send_sigio(struct fown_struct *fown, int fd, int band); 709extern void send_sigio(struct fown_struct *fown, int fd, int band);
diff --git a/include/linux/fsnotify.h b/include/linux/fsnotify.h
index d07a92c94776..602c305c8585 100644
--- a/include/linux/fsnotify.h
+++ b/include/linux/fsnotify.h
@@ -21,7 +21,7 @@
21 */ 21 */
22static inline void fsnotify_move(struct inode *old_dir, struct inode *new_dir, 22static inline void fsnotify_move(struct inode *old_dir, struct inode *new_dir,
23 const char *old_name, const char *new_name, 23 const char *old_name, const char *new_name,
24 int isdir) 24 int isdir, struct inode *target)
25{ 25{
26 u32 cookie = inotify_get_cookie(); 26 u32 cookie = inotify_get_cookie();
27 27
@@ -36,31 +36,30 @@ static inline void fsnotify_move(struct inode *old_dir, struct inode *new_dir,
36 isdir = IN_ISDIR; 36 isdir = IN_ISDIR;
37 inotify_inode_queue_event(old_dir, IN_MOVED_FROM|isdir,cookie,old_name); 37 inotify_inode_queue_event(old_dir, IN_MOVED_FROM|isdir,cookie,old_name);
38 inotify_inode_queue_event(new_dir, IN_MOVED_TO|isdir, cookie, new_name); 38 inotify_inode_queue_event(new_dir, IN_MOVED_TO|isdir, cookie, new_name);
39
40 if (target) {
41 inotify_inode_queue_event(target, IN_DELETE_SELF, 0, NULL);
42 inotify_inode_is_dead(target);
43 }
39} 44}
40 45
41/* 46/*
42 * fsnotify_unlink - file was unlinked 47 * fsnotify_nameremove - a filename was removed from a directory
43 */ 48 */
44static inline void fsnotify_unlink(struct dentry *dentry, struct inode *dir) 49static inline void fsnotify_nameremove(struct dentry *dentry, int isdir)
45{ 50{
46 struct inode *inode = dentry->d_inode; 51 if (isdir)
47 52 isdir = IN_ISDIR;
48 inode_dir_notify(dir, DN_DELETE); 53 dnotify_parent(dentry, DN_DELETE);
49 inotify_inode_queue_event(dir, IN_DELETE, 0, dentry->d_name.name); 54 inotify_dentry_parent_queue_event(dentry, IN_DELETE|isdir, 0, dentry->d_name.name);
50 inotify_inode_queue_event(inode, IN_DELETE_SELF, 0, NULL);
51
52 inotify_inode_is_dead(inode);
53} 55}
54 56
55/* 57/*
56 * fsnotify_rmdir - directory was removed 58 * fsnotify_inoderemove - an inode is going away
57 */ 59 */
58static inline void fsnotify_rmdir(struct dentry *dentry, struct inode *inode, 60static inline void fsnotify_inoderemove(struct inode *inode)
59 struct inode *dir)
60{ 61{
61 inode_dir_notify(dir, DN_DELETE); 62 inotify_inode_queue_event(inode, IN_DELETE_SELF, 0, NULL);
62 inotify_inode_queue_event(dir,IN_DELETE|IN_ISDIR,0,dentry->d_name.name);
63 inotify_inode_queue_event(inode, IN_DELETE_SELF | IN_ISDIR, 0, NULL);
64 inotify_inode_is_dead(inode); 63 inotify_inode_is_dead(inode);
65} 64}
66 65
diff --git a/include/linux/ftape.h b/include/linux/ftape.h
index c6b38d5b9186..72faeec9f6e1 100644
--- a/include/linux/ftape.h
+++ b/include/linux/ftape.h
@@ -165,7 +165,7 @@ typedef union {
165# undef CONFIG_FT_FDC_DMA 165# undef CONFIG_FT_FDC_DMA
166# define CONFIG_FT_FDC_DMA 2 166# define CONFIG_FT_FDC_DMA 2
167# endif 167# endif
168#elif CONFIG_FT_ALT_FDC == 1 /* CONFIG_FT_MACH2 */ 168#elif defined(CONFIG_FT_ALT_FDC) /* CONFIG_FT_MACH2 */
169# if CONFIG_FT_FDC_BASE == 0 169# if CONFIG_FT_FDC_BASE == 0
170# undef CONFIG_FT_FDC_BASE 170# undef CONFIG_FT_FDC_BASE
171# define CONFIG_FT_FDC_BASE 0x370 171# define CONFIG_FT_FDC_BASE 0x370
diff --git a/include/linux/input.h b/include/linux/input.h
index b9cc0ac71f44..bdc53c6cc962 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -811,9 +811,9 @@ struct input_dev {
811 811
812 void *private; 812 void *private;
813 813
814 char *name; 814 const char *name;
815 char *phys; 815 const char *phys;
816 char *uniq; 816 const char *uniq;
817 struct input_id id; 817 struct input_id id;
818 818
819 unsigned long evbit[NBITS(EV_MAX)]; 819 unsigned long evbit[NBITS(EV_MAX)];
diff --git a/include/linux/mbcache.h b/include/linux/mbcache.h
index 8e5a10410a30..9263d2db2d67 100644
--- a/include/linux/mbcache.h
+++ b/include/linux/mbcache.h
@@ -29,7 +29,7 @@ struct mb_cache_op {
29 29
30struct mb_cache * mb_cache_create(const char *, struct mb_cache_op *, size_t, 30struct mb_cache * mb_cache_create(const char *, struct mb_cache_op *, size_t,
31 int, int); 31 int, int);
32void mb_cache_shrink(struct mb_cache *, struct block_device *); 32void mb_cache_shrink(struct block_device *);
33void mb_cache_destroy(struct mb_cache *); 33void mb_cache_destroy(struct mb_cache *);
34 34
35/* Functions on cache entries */ 35/* Functions on cache entries */
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 6eb7f48317f8..82d7024f0765 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -625,10 +625,16 @@ static inline int page_mapped(struct page *page)
625 * Used to decide whether a process gets delivered SIGBUS or 625 * Used to decide whether a process gets delivered SIGBUS or
626 * just gets major/minor fault counters bumped up. 626 * just gets major/minor fault counters bumped up.
627 */ 627 */
628#define VM_FAULT_OOM (-1) 628#define VM_FAULT_OOM 0x00
629#define VM_FAULT_SIGBUS 0 629#define VM_FAULT_SIGBUS 0x01
630#define VM_FAULT_MINOR 1 630#define VM_FAULT_MINOR 0x02
631#define VM_FAULT_MAJOR 2 631#define VM_FAULT_MAJOR 0x03
632
633/*
634 * Special case for get_user_pages.
635 * Must be in a distinct bit from the above VM_FAULT_ flags.
636 */
637#define VM_FAULT_WRITE 0x10
632 638
633#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) 639#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK)
634 640
@@ -704,7 +710,13 @@ extern pte_t *FASTCALL(pte_alloc_kernel(struct mm_struct *mm, pmd_t *pmd, unsign
704extern pte_t *FASTCALL(pte_alloc_map(struct mm_struct *mm, pmd_t *pmd, unsigned long address)); 710extern pte_t *FASTCALL(pte_alloc_map(struct mm_struct *mm, pmd_t *pmd, unsigned long address));
705extern int install_page(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, struct page *page, pgprot_t prot); 711extern int install_page(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, struct page *page, pgprot_t prot);
706extern int install_file_pte(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, unsigned long pgoff, pgprot_t prot); 712extern int install_file_pte(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, unsigned long pgoff, pgprot_t prot);
707extern int handle_mm_fault(struct mm_struct *mm,struct vm_area_struct *vma, unsigned long address, int write_access); 713extern int __handle_mm_fault(struct mm_struct *mm,struct vm_area_struct *vma, unsigned long address, int write_access);
714
715static inline int handle_mm_fault(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long address, int write_access)
716{
717 return __handle_mm_fault(mm, vma, address, write_access) & (~VM_FAULT_WRITE);
718}
719
708extern int make_pages_present(unsigned long addr, unsigned long end); 720extern int make_pages_present(unsigned long addr, unsigned long end);
709extern int access_process_vm(struct task_struct *tsk, unsigned long addr, void *buf, int len, int write); 721extern int access_process_vm(struct task_struct *tsk, unsigned long addr, void *buf, int len, int write);
710void install_arg_page(struct vm_area_struct *, struct page *, unsigned long); 722void install_arg_page(struct vm_area_struct *, struct page *, unsigned long);
diff --git a/include/linux/netlink.h b/include/linux/netlink.h
index 70c2a9dc4b2b..6552b71bfa73 100644
--- a/include/linux/netlink.h
+++ b/include/linux/netlink.h
@@ -12,15 +12,13 @@
12#define NETLINK_NFLOG 5 /* netfilter/iptables ULOG */ 12#define NETLINK_NFLOG 5 /* netfilter/iptables ULOG */
13#define NETLINK_XFRM 6 /* ipsec */ 13#define NETLINK_XFRM 6 /* ipsec */
14#define NETLINK_SELINUX 7 /* SELinux event notifications */ 14#define NETLINK_SELINUX 7 /* SELinux event notifications */
15#define NETLINK_ARPD 8 15#define NETLINK_ISCSI 8 /* Open-iSCSI */
16#define NETLINK_AUDIT 9 /* auditing */ 16#define NETLINK_AUDIT 9 /* auditing */
17#define NETLINK_FIB_LOOKUP 10 17#define NETLINK_FIB_LOOKUP 10
18#define NETLINK_ROUTE6 11 /* af_inet6 route comm channel */
19#define NETLINK_NETFILTER 12 /* netfilter subsystem */ 18#define NETLINK_NETFILTER 12 /* netfilter subsystem */
20#define NETLINK_IP6_FW 13 19#define NETLINK_IP6_FW 13
21#define NETLINK_DNRTMSG 14 /* DECnet routing messages */ 20#define NETLINK_DNRTMSG 14 /* DECnet routing messages */
22#define NETLINK_KOBJECT_UEVENT 15 /* Kernel messages to userspace */ 21#define NETLINK_KOBJECT_UEVENT 15 /* Kernel messages to userspace */
23#define NETLINK_TAPBASE 16 /* 16 to 31 are ethertap */
24 22
25#define MAX_LINKS 32 23#define MAX_LINKS 32
26 24
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 7ac14961ba22..8621cf42b46f 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -971,6 +971,8 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int en
971 971
972#define isa_bridge ((struct pci_dev *)NULL) 972#define isa_bridge ((struct pci_dev *)NULL)
973 973
974#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
975
974#else 976#else
975 977
976/* 978/*
@@ -985,9 +987,6 @@ static inline int pci_proc_domain(struct pci_bus *bus)
985 return 0; 987 return 0;
986} 988}
987#endif 989#endif
988
989#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
990
991#endif /* !CONFIG_PCI */ 990#endif /* !CONFIG_PCI */
992 991
993/* these helpers provide future and backwards compatibility 992/* these helpers provide future and backwards compatibility
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index d2ad2c4f835a..bc4cc10fabe9 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1020,6 +1020,7 @@
1020#define PCI_DEVICE_ID_PLX_SPCOM200 0x1103 1020#define PCI_DEVICE_ID_PLX_SPCOM200 0x1103
1021#define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151 1021#define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151
1022#define PCI_DEVICE_ID_PLX_R753 0x1152 1022#define PCI_DEVICE_ID_PLX_R753 0x1152
1023#define PCI_DEVICE_ID_PLX_OLITEC 0x1187
1023#define PCI_DEVICE_ID_PLX_9030 0x9030 1024#define PCI_DEVICE_ID_PLX_9030 0x9030
1024#define PCI_DEVICE_ID_PLX_9050 0x9050 1025#define PCI_DEVICE_ID_PLX_9050 0x9050
1025#define PCI_DEVICE_ID_PLX_9060 0x9060 1026#define PCI_DEVICE_ID_PLX_9060 0x9060
diff --git a/include/linux/raid/bitmap.h b/include/linux/raid/bitmap.h
index 6213e976eade..4bf1659f8aa8 100644
--- a/include/linux/raid/bitmap.h
+++ b/include/linux/raid/bitmap.h
@@ -248,6 +248,7 @@ struct bitmap {
248 248
249/* these are used only by md/bitmap */ 249/* these are used only by md/bitmap */
250int bitmap_create(mddev_t *mddev); 250int bitmap_create(mddev_t *mddev);
251void bitmap_flush(mddev_t *mddev);
251void bitmap_destroy(mddev_t *mddev); 252void bitmap_destroy(mddev_t *mddev);
252int bitmap_active(struct bitmap *bitmap); 253int bitmap_active(struct bitmap *bitmap);
253 254
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 30b64f3534f4..f6fca8f2f3ca 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -104,7 +104,7 @@
104#define PORT_MPSC 63 104#define PORT_MPSC 63
105 105
106/* TXX9 type number */ 106/* TXX9 type number */
107#define PORT_TXX9 64 107#define PORT_TXX9 64
108 108
109/* NEC VR4100 series SIU/DSIU */ 109/* NEC VR4100 series SIU/DSIU */
110#define PORT_VR41XX_SIU 65 110#define PORT_VR41XX_SIU 65
diff --git a/include/linux/slab.h b/include/linux/slab.h
index 4c8e552471b0..80b2dfde2e80 100644
--- a/include/linux/slab.h
+++ b/include/linux/slab.h
@@ -111,7 +111,7 @@ static inline void *kmem_cache_alloc_node(kmem_cache_t *cachep, int flags, int n
111{ 111{
112 return kmem_cache_alloc(cachep, flags); 112 return kmem_cache_alloc(cachep, flags);
113} 113}
114static inline void *kmalloc_node(size_t size, int flags, int node) 114static inline void *kmalloc_node(size_t size, unsigned int __nocast flags, int node)
115{ 115{
116 return kmalloc(size, flags); 116 return kmalloc(size, flags);
117} 117}
diff --git a/include/linux/swap.h b/include/linux/swap.h
index 239f520cc49e..bfe3e763ccf2 100644
--- a/include/linux/swap.h
+++ b/include/linux/swap.h
@@ -7,7 +7,6 @@
7#include <linux/mmzone.h> 7#include <linux/mmzone.h>
8#include <linux/list.h> 8#include <linux/list.h>
9#include <linux/sched.h> 9#include <linux/sched.h>
10#include <linux/pagemap.h>
11 10
12#include <asm/atomic.h> 11#include <asm/atomic.h>
13#include <asm/page.h> 12#include <asm/page.h>
@@ -255,6 +254,8 @@ static inline void put_swap_token(struct mm_struct *mm)
255 254
256#define si_swapinfo(val) \ 255#define si_swapinfo(val) \
257 do { (val)->freeswap = (val)->totalswap = 0; } while (0) 256 do { (val)->freeswap = (val)->totalswap = 0; } while (0)
257/* only sparc can not include linux/pagemap.h in this file
258 * so leave page_cache_release and release_pages undeclared... */
258#define free_page_and_swap_cache(page) \ 259#define free_page_and_swap_cache(page) \
259 page_cache_release(page) 260 page_cache_release(page)
260#define free_pages_and_swap_cache(pages, nr) \ 261#define free_pages_and_swap_cache(pages, nr) \
diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h
index bfbbe94b297d..e82be96d4906 100644
--- a/include/linux/sysctl.h
+++ b/include/linux/sysctl.h
@@ -145,6 +145,7 @@ enum
145 KERN_BOOTLOADER_TYPE=67, /* int: boot loader type */ 145 KERN_BOOTLOADER_TYPE=67, /* int: boot loader type */
146 KERN_RANDOMIZE=68, /* int: randomize virtual address space */ 146 KERN_RANDOMIZE=68, /* int: randomize virtual address space */
147 KERN_SETUID_DUMPABLE=69, /* int: behaviour of dumps for setuid core */ 147 KERN_SETUID_DUMPABLE=69, /* int: behaviour of dumps for setuid core */
148 KERN_SPIN_RETRY=70, /* int: number of spinlock retries */
148}; 149};
149 150
150 151
diff --git a/include/linux/uinput.h b/include/linux/uinput.h
index 4c2c82336d10..84876077027f 100644
--- a/include/linux/uinput.h
+++ b/include/linux/uinput.h
@@ -42,8 +42,7 @@ struct uinput_request {
42 int code; /* UI_FF_UPLOAD, UI_FF_ERASE */ 42 int code; /* UI_FF_UPLOAD, UI_FF_ERASE */
43 43
44 int retval; 44 int retval;
45 wait_queue_head_t waitq; 45 struct completion done;
46 int completed;
47 46
48 union { 47 union {
49 int effect_id; 48 int effect_id;
@@ -62,7 +61,7 @@ struct uinput_device {
62 61
63 struct uinput_request *requests[UINPUT_NUM_REQUESTS]; 62 struct uinput_request *requests[UINPUT_NUM_REQUESTS];
64 wait_queue_head_t requests_waitq; 63 wait_queue_head_t requests_waitq;
65 struct semaphore requests_sem; 64 spinlock_t requests_lock;
66}; 65};
67#endif /* __KERNEL__ */ 66#endif /* __KERNEL__ */
68 67
diff --git a/include/linux/usb_input.h b/include/linux/usb_input.h
new file mode 100644
index 000000000000..716e0cc16043
--- /dev/null
+++ b/include/linux/usb_input.h
@@ -0,0 +1,25 @@
1#ifndef __USB_INPUT_H
2#define __USB_INPUT_H
3
4/*
5 * Copyright (C) 2005 Dmitry Torokhov
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11
12#include <linux/usb.h>
13#include <linux/input.h>
14#include <asm/byteorder.h>
15
16static inline void
17usb_to_input_id(const struct usb_device *dev, struct input_id *id)
18{
19 id->bustype = BUS_USB;
20 id->vendor = le16_to_cpu(dev->descriptor.idVendor);
21 id->product = le16_to_cpu(dev->descriptor.idProduct);
22 id->version = le16_to_cpu(dev->descriptor.bcdDevice);
23}
24
25#endif
diff --git a/include/linux/watchdog.h b/include/linux/watchdog.h
index 88ba0d29f8c8..1192ed8f4fe8 100644
--- a/include/linux/watchdog.h
+++ b/include/linux/watchdog.h
@@ -47,4 +47,14 @@ struct watchdog_info {
47#define WDIOS_ENABLECARD 0x0002 /* Turn on the watchdog timer */ 47#define WDIOS_ENABLECARD 0x0002 /* Turn on the watchdog timer */
48#define WDIOS_TEMPPANIC 0x0004 /* Kernel panic on temperature trip */ 48#define WDIOS_TEMPPANIC 0x0004 /* Kernel panic on temperature trip */
49 49
50#ifdef __KERNEL__
51
52#ifdef CONFIG_WATCHDOG_NOWAYOUT
53#define WATCHDOG_NOWAYOUT 1
54#else
55#define WATCHDOG_NOWAYOUT 0
56#endif
57
58#endif /* __KERNEL__ */
59
50#endif /* ifndef _LINUX_WATCHDOG_H */ 60#endif /* ifndef _LINUX_WATCHDOG_H */
diff --git a/include/linux/zlib.h b/include/linux/zlib.h
index 850076ea14d3..74f7b78c22d2 100644
--- a/include/linux/zlib.h
+++ b/include/linux/zlib.h
@@ -506,6 +506,11 @@ extern int zlib_deflateReset (z_streamp strm);
506 stream state was inconsistent (such as zalloc or state being NULL). 506 stream state was inconsistent (such as zalloc or state being NULL).
507*/ 507*/
508 508
509static inline unsigned long deflateBound(unsigned long s)
510{
511 return s + ((s + 7) >> 3) + ((s + 63) >> 6) + 11;
512}
513
509extern int zlib_deflateParams (z_streamp strm, int level, int strategy); 514extern int zlib_deflateParams (z_streamp strm, int level, int strategy);
510/* 515/*
511 Dynamically update the compression level and compression strategy. The 516 Dynamically update the compression level and compression strategy. The
diff --git a/include/media/tuner.h b/include/media/tuner.h
index d8c0a5563289..eeaa15ddee85 100644
--- a/include/media/tuner.h
+++ b/include/media/tuner.h
@@ -1,5 +1,5 @@
1 1
2/* $Id: tuner.h,v 1.42 2005/07/06 09:42:19 mchehab Exp $ 2/* $Id: tuner.h,v 1.45 2005/07/28 18:41:21 mchehab Exp $
3 * 3 *
4 tuner.h - definition for different tuners 4 tuner.h - definition for different tuners
5 5
@@ -108,6 +108,8 @@
108 108
109#define TUNER_TEA5767 62 /* Only FM Radio Tuner */ 109#define TUNER_TEA5767 62 /* Only FM Radio Tuner */
110#define TUNER_PHILIPS_FMD1216ME_MK3 63 110#define TUNER_PHILIPS_FMD1216ME_MK3 63
111#define TUNER_LG_TDVS_H062F 64 /* DViCO FusionHDTV 5 */
112#define TUNER_YMEC_TVF66T5_B_DFF 65 /* Acorp Y878F */
111 113
112#define NOTUNER 0 114#define NOTUNER 0
113#define PAL 1 /* PAL_BG */ 115#define PAL 1 /* PAL_BG */
diff --git a/include/media/tveeprom.h b/include/media/tveeprom.h
index 5c4fe30e8d1d..854a2c2f105b 100644
--- a/include/media/tveeprom.h
+++ b/include/media/tveeprom.h
@@ -24,4 +24,3 @@ void tveeprom_hauppauge_analog(struct tveeprom *tvee,
24 unsigned char *eeprom_data); 24 unsigned char *eeprom_data);
25 25
26int tveeprom_read(struct i2c_client *c, unsigned char *eedata, int len); 26int tveeprom_read(struct i2c_client *c, unsigned char *eedata, int len);
27int tveeprom_dump(unsigned char *eedata, int len);
diff --git a/include/net/bluetooth/bluetooth.h b/include/net/bluetooth/bluetooth.h
index 42a84c53678b..06b24f637026 100644
--- a/include/net/bluetooth/bluetooth.h
+++ b/include/net/bluetooth/bluetooth.h
@@ -57,12 +57,6 @@
57#define BT_DBG(fmt, arg...) printk(KERN_INFO "%s: " fmt "\n" , __FUNCTION__ , ## arg) 57#define BT_DBG(fmt, arg...) printk(KERN_INFO "%s: " fmt "\n" , __FUNCTION__ , ## arg)
58#define BT_ERR(fmt, arg...) printk(KERN_ERR "%s: " fmt "\n" , __FUNCTION__ , ## arg) 58#define BT_ERR(fmt, arg...) printk(KERN_ERR "%s: " fmt "\n" , __FUNCTION__ , ## arg)
59 59
60#ifdef HCI_DATA_DUMP
61#define BT_DMP(buf, len) bt_dump(__FUNCTION__, buf, len)
62#else
63#define BT_DMP(D...)
64#endif
65
66extern struct proc_dir_entry *proc_bt; 60extern struct proc_dir_entry *proc_bt;
67 61
68/* Connection and socket states */ 62/* Connection and socket states */
@@ -174,8 +168,6 @@ static inline int skb_frags_no(struct sk_buff *skb)
174 return n; 168 return n;
175} 169}
176 170
177void bt_dump(char *pref, __u8 *buf, int count);
178
179int bt_err(__u16 code); 171int bt_err(__u16 code);
180 172
181#endif /* __BLUETOOTH_H */ 173#endif /* __BLUETOOTH_H */
diff --git a/include/net/tcp.h b/include/net/tcp.h
index f4f9aba07ac2..5010f0c5a56e 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -1236,7 +1236,7 @@ static inline void tcp_sync_left_out(struct tcp_sock *tp)
1236 tp->left_out = tp->sacked_out + tp->lost_out; 1236 tp->left_out = tp->sacked_out + tp->lost_out;
1237} 1237}
1238 1238
1239/* Set slow start threshould and cwnd not falling to slow start */ 1239/* Set slow start threshold and cwnd not falling to slow start */
1240static inline void __tcp_enter_cwr(struct tcp_sock *tp) 1240static inline void __tcp_enter_cwr(struct tcp_sock *tp)
1241{ 1241{
1242 tp->undo_marker = 0; 1242 tp->undo_marker = 0;
diff --git a/include/sound/core.h b/include/sound/core.h
index f8c4ef0aa352..38b357fc8958 100644
--- a/include/sound/core.h
+++ b/include/sound/core.h
@@ -126,25 +126,26 @@ struct snd_monitor_file {
126 struct snd_monitor_file *next; 126 struct snd_monitor_file *next;
127}; 127};
128 128
129struct snd_shutdown_f_ops; /* define it later */ 129struct snd_shutdown_f_ops; /* define it later in init.c */
130 130
131/* main structure for soundcard */ 131/* main structure for soundcard */
132 132
133struct _snd_card { 133struct _snd_card {
134 int number; /* number of soundcard (index to snd_cards) */ 134 int number; /* number of soundcard (index to
135 snd_cards) */
135 136
136 char id[16]; /* id string of this card */ 137 char id[16]; /* id string of this card */
137 char driver[16]; /* driver name */ 138 char driver[16]; /* driver name */
138 char shortname[32]; /* short name of this soundcard */ 139 char shortname[32]; /* short name of this soundcard */
139 char longname[80]; /* name of this soundcard */ 140 char longname[80]; /* name of this soundcard */
140 char mixername[80]; /* mixer name */ 141 char mixername[80]; /* mixer name */
141 char components[80]; /* card components delimited with space */ 142 char components[80]; /* card components delimited with
142 143 space */
143 struct module *module; /* top-level module */ 144 struct module *module; /* top-level module */
144 145
145 void *private_data; /* private data for soundcard */ 146 void *private_data; /* private data for soundcard */
146 void (*private_free) (snd_card_t *card); /* callback for freeing of private data */ 147 void (*private_free) (snd_card_t *card); /* callback for freeing of
147 148 private data */
148 struct list_head devices; /* devices */ 149 struct list_head devices; /* devices */
149 150
150 unsigned int last_numid; /* last used numeric ID */ 151 unsigned int last_numid; /* last used numeric ID */
@@ -160,7 +161,8 @@ struct _snd_card {
160 struct proc_dir_entry *proc_root_link; /* number link to real id */ 161 struct proc_dir_entry *proc_root_link; /* number link to real id */
161 162
162 struct snd_monitor_file *files; /* all files associated to this card */ 163 struct snd_monitor_file *files; /* all files associated to this card */
163 struct snd_shutdown_f_ops *s_f_ops; /* file operations in the shutdown state */ 164 struct snd_shutdown_f_ops *s_f_ops; /* file operations in the shutdown
165 state */
164 spinlock_t files_lock; /* lock the files for this card */ 166 spinlock_t files_lock; /* lock the files for this card */
165 int shutdown; /* this card is going down */ 167 int shutdown; /* this card is going down */
166 wait_queue_head_t shutdown_sleep; 168 wait_queue_head_t shutdown_sleep;
@@ -196,8 +198,6 @@ static inline void snd_power_unlock(snd_card_t *card)
196 up(&card->power_lock); 198 up(&card->power_lock);
197} 199}
198 200
199int snd_power_wait(snd_card_t *card, unsigned int power_state, struct file *file);
200
201static inline unsigned int snd_power_get_state(snd_card_t *card) 201static inline unsigned int snd_power_get_state(snd_card_t *card)
202{ 202{
203 return card->power_state; 203 return card->power_state;
@@ -208,6 +208,10 @@ static inline void snd_power_change_state(snd_card_t *card, unsigned int state)
208 card->power_state = state; 208 card->power_state = state;
209 wake_up(&card->power_sleep); 209 wake_up(&card->power_sleep);
210} 210}
211
212/* init.c */
213int snd_power_wait(snd_card_t *card, unsigned int power_state, struct file *file);
214
211int snd_card_set_pm_callback(snd_card_t *card, 215int snd_card_set_pm_callback(snd_card_t *card,
212 int (*suspend)(snd_card_t *, pm_message_t), 216 int (*suspend)(snd_card_t *, pm_message_t),
213 int (*resume)(snd_card_t *), 217 int (*resume)(snd_card_t *),
@@ -238,15 +242,14 @@ static inline int snd_power_wait(snd_card_t *card, unsigned int state, struct fi
238 242
239#endif /* CONFIG_PM */ 243#endif /* CONFIG_PM */
240 244
241/* device.c */
242
243struct _snd_minor { 245struct _snd_minor {
244 struct list_head list; /* list of all minors per card */ 246 struct list_head list; /* list of all minors per card */
245 int number; /* minor number */ 247 int number; /* minor number */
246 int device; /* device number */ 248 int device; /* device number */
247 const char *comment; /* for /proc/asound/devices */ 249 const char *comment; /* for /proc/asound/devices */
248 struct file_operations *f_ops; /* file operations */ 250 struct file_operations *f_ops; /* file operations */
249 char name[0]; /* device name (keep at the end of structure) */ 251 char name[0]; /* device name (keep at the end of
252 structure) */
250}; 253};
251 254
252typedef struct _snd_minor snd_minor_t; 255typedef struct _snd_minor snd_minor_t;
@@ -287,12 +290,12 @@ void snd_memory_init(void);
287void snd_memory_done(void); 290void snd_memory_done(void);
288int snd_memory_info_init(void); 291int snd_memory_info_init(void);
289int snd_memory_info_done(void); 292int snd_memory_info_done(void);
290void *snd_hidden_kmalloc(size_t size, int flags); 293void *snd_hidden_kmalloc(size_t size, unsigned int __nocast flags);
291void *snd_hidden_kcalloc(size_t n, size_t size, int flags); 294void *snd_hidden_kcalloc(size_t n, size_t size, unsigned int __nocast flags);
292void snd_hidden_kfree(const void *obj); 295void snd_hidden_kfree(const void *obj);
293void *snd_hidden_vmalloc(unsigned long size); 296void *snd_hidden_vmalloc(unsigned long size);
294void snd_hidden_vfree(void *obj); 297void snd_hidden_vfree(void *obj);
295char *snd_hidden_kstrdup(const char *s, int flags); 298char *snd_hidden_kstrdup(const char *s, unsigned int __nocast flags);
296#define kmalloc(size, flags) snd_hidden_kmalloc(size, flags) 299#define kmalloc(size, flags) snd_hidden_kmalloc(size, flags)
297#define kcalloc(n, size, flags) snd_hidden_kcalloc(n, size, flags) 300#define kcalloc(n, size, flags) snd_hidden_kcalloc(n, size, flags)
298#define kfree(obj) snd_hidden_kfree(obj) 301#define kfree(obj) snd_hidden_kfree(obj)
@@ -411,7 +414,7 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...)
411 printk(fmt ,##args) 414 printk(fmt ,##args)
412#endif 415#endif
413/** 416/**
414 * snd_assert - run-time assersion macro 417 * snd_assert - run-time assertion macro
415 * @expr: expression 418 * @expr: expression
416 * @args...: the action 419 * @args...: the action
417 * 420 *
@@ -427,7 +430,7 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...)
427 }\ 430 }\
428} while (0) 431} while (0)
429/** 432/**
430 * snd_runtime_check - run-time assersion macro 433 * snd_runtime_check - run-time assertion macro
431 * @expr: expression 434 * @expr: expression
432 * @args...: the action 435 * @args...: the action
433 * 436 *
diff --git a/include/sound/driver.h b/include/sound/driver.h
index 948e9a1aebef..0d12456ec3ae 100644
--- a/include/sound/driver.h
+++ b/include/sound/driver.h
@@ -51,7 +51,7 @@
51#ifdef CONFIG_SND_DEBUG_MEMORY 51#ifdef CONFIG_SND_DEBUG_MEMORY
52#include <linux/slab.h> 52#include <linux/slab.h>
53#include <linux/vmalloc.h> 53#include <linux/vmalloc.h>
54void *snd_wrapper_kmalloc(size_t, int); 54void *snd_wrapper_kmalloc(size_t, unsigned int __nocast);
55#undef kmalloc 55#undef kmalloc
56void snd_wrapper_kfree(const void *); 56void snd_wrapper_kfree(const void *);
57#undef kfree 57#undef kfree
diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h
index c50b91958ff9..c2ef3f023687 100644
--- a/include/sound/emu10k1.h
+++ b/include/sound/emu10k1.h
@@ -1167,6 +1167,7 @@ int snd_emu10k1_create(snd_card_t * card,
1167 unsigned short extout_mask, 1167 unsigned short extout_mask,
1168 long max_cache_bytes, 1168 long max_cache_bytes,
1169 int enable_ir, 1169 int enable_ir,
1170 uint subsystem,
1170 emu10k1_t ** remu); 1171 emu10k1_t ** remu);
1171 1172
1172int snd_emu10k1_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm); 1173int snd_emu10k1_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
diff --git a/include/sound/version.h b/include/sound/version.h
index 46acfa8c9988..c085136f391f 100644
--- a/include/sound/version.h
+++ b/include/sound/version.h
@@ -1,3 +1,3 @@
1/* include/version.h. Generated by configure. */ 1/* include/version.h. Generated by configure. */
2#define CONFIG_SND_VERSION "1.0.9" 2#define CONFIG_SND_VERSION "1.0.9b"
3#define CONFIG_SND_DATE " (Sun May 29 07:31:02 2005 UTC)" 3#define CONFIG_SND_DATE " (Thu Jul 28 12:20:13 2005 UTC)"
diff --git a/include/sound/vx_core.h b/include/sound/vx_core.h
index a7e29933f2d0..7a60a3888667 100644
--- a/include/sound/vx_core.h
+++ b/include/sound/vx_core.h
@@ -233,37 +233,37 @@ irqreturn_t snd_vx_irq_handler(int irq, void *dev, struct pt_regs *regs);
233/* 233/*
234 * lowlevel functions 234 * lowlevel functions
235 */ 235 */
236inline static int vx_test_and_ack(vx_core_t *chip) 236static inline int vx_test_and_ack(vx_core_t *chip)
237{ 237{
238 snd_assert(chip->ops->test_and_ack, return -ENXIO); 238 snd_assert(chip->ops->test_and_ack, return -ENXIO);
239 return chip->ops->test_and_ack(chip); 239 return chip->ops->test_and_ack(chip);
240} 240}
241 241
242inline static void vx_validate_irq(vx_core_t *chip, int enable) 242static inline void vx_validate_irq(vx_core_t *chip, int enable)
243{ 243{
244 snd_assert(chip->ops->validate_irq, return); 244 snd_assert(chip->ops->validate_irq, return);
245 chip->ops->validate_irq(chip, enable); 245 chip->ops->validate_irq(chip, enable);
246} 246}
247 247
248inline static unsigned char snd_vx_inb(vx_core_t *chip, int reg) 248static inline unsigned char snd_vx_inb(vx_core_t *chip, int reg)
249{ 249{
250 snd_assert(chip->ops->in8, return 0); 250 snd_assert(chip->ops->in8, return 0);
251 return chip->ops->in8(chip, reg); 251 return chip->ops->in8(chip, reg);
252} 252}
253 253
254inline static unsigned int snd_vx_inl(vx_core_t *chip, int reg) 254static inline unsigned int snd_vx_inl(vx_core_t *chip, int reg)
255{ 255{
256 snd_assert(chip->ops->in32, return 0); 256 snd_assert(chip->ops->in32, return 0);
257 return chip->ops->in32(chip, reg); 257 return chip->ops->in32(chip, reg);
258} 258}
259 259
260inline static void snd_vx_outb(vx_core_t *chip, int reg, unsigned char val) 260static inline void snd_vx_outb(vx_core_t *chip, int reg, unsigned char val)
261{ 261{
262 snd_assert(chip->ops->out8, return); 262 snd_assert(chip->ops->out8, return);
263 chip->ops->out8(chip, reg, val); 263 chip->ops->out8(chip, reg, val);
264} 264}
265 265
266inline static void snd_vx_outl(vx_core_t *chip, int reg, unsigned int val) 266static inline void snd_vx_outl(vx_core_t *chip, int reg, unsigned int val)
267{ 267{
268 snd_assert(chip->ops->out32, return); 268 snd_assert(chip->ops->out32, return);
269 chip->ops->out32(chip, reg, val); 269 chip->ops->out32(chip, reg, val);
@@ -303,14 +303,14 @@ int snd_vx_check_reg_bit(vx_core_t *chip, int reg, int mask, int bit, int time);
303/* 303/*
304 * pseudo-DMA transfer 304 * pseudo-DMA transfer
305 */ 305 */
306inline static void vx_pseudo_dma_write(vx_core_t *chip, snd_pcm_runtime_t *runtime, 306static inline void vx_pseudo_dma_write(vx_core_t *chip, snd_pcm_runtime_t *runtime,
307 vx_pipe_t *pipe, int count) 307 vx_pipe_t *pipe, int count)
308{ 308{
309 snd_assert(chip->ops->dma_write, return); 309 snd_assert(chip->ops->dma_write, return);
310 chip->ops->dma_write(chip, runtime, pipe, count); 310 chip->ops->dma_write(chip, runtime, pipe, count);
311} 311}
312 312
313inline static void vx_pseudo_dma_read(vx_core_t *chip, snd_pcm_runtime_t *runtime, 313static inline void vx_pseudo_dma_read(vx_core_t *chip, snd_pcm_runtime_t *runtime,
314 vx_pipe_t *pipe, int count) 314 vx_pipe_t *pipe, int count)
315{ 315{
316 snd_assert(chip->ops->dma_read, return); 316 snd_assert(chip->ops->dma_read, return);