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authorKumar Gala <galak@kernel.crashing.org>2008-01-27 15:06:14 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-01-28 09:33:10 -0500
commitc42f3ad7f1bf17f31c3febdc71034ed6d793d40f (patch)
tree5a56c44717cf8fe4a5f402370506e5fbb78368e4 /include
parent3155f7f23f7865e64f7eb14e226a2dff8197e51f (diff)
[PPC] Remove 85xx from arch/ppc
85xx exists in arch/powerpc as well as cuImage support to boot from a u-boot that doesn't support device trees. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-powerpc/irq.h121
-rw-r--r--include/asm-ppc/cpm2.h2
-rw-r--r--include/asm-ppc/immap_85xx.h126
-rw-r--r--include/asm-ppc/mmu_context.h5
-rw-r--r--include/asm-ppc/mpc85xx.h192
-rw-r--r--include/asm-ppc/pgtable.h46
-rw-r--r--include/asm-ppc/ppc_sys.h2
-rw-r--r--include/asm-ppc/ppcboot.h7
-rw-r--r--include/asm-ppc/reg_booke.h26
-rw-r--r--include/asm-ppc/serial.h2
10 files changed, 4 insertions, 525 deletions
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
index 4a015da9fb1e..0efe7b24b633 100644
--- a/include/asm-powerpc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -483,127 +483,6 @@ static __inline__ int irq_canonicalize(int irq)
483 */ 483 */
484#define mk_int_int_mask(IL) (1 << (7 - (IL/2))) 484#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
485 485
486#elif defined(CONFIG_85xx)
487/* Now include the board configuration specific associations.
488*/
489#include <asm/mpc85xx.h>
490
491/* The MPC8548 openpic has 48 internal interrupts and 12 external
492 * interrupts.
493 *
494 * We are "flattening" the interrupt vectors of the cascaded CPM
495 * so that we can uniquely identify any interrupt source with a
496 * single integer.
497 */
498#define NR_CPM_INTS 64
499#define NR_EPIC_INTS 60
500#ifndef NR_8259_INTS
501#define NR_8259_INTS 0
502#endif
503#define NUM_8259_INTERRUPTS NR_8259_INTS
504
505#ifndef CPM_IRQ_OFFSET
506#define CPM_IRQ_OFFSET 0
507#endif
508
509#define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS)
510
511/* Internal IRQs on MPC85xx OpenPIC */
512
513#ifndef MPC85xx_OPENPIC_IRQ_OFFSET
514#ifdef CONFIG_CPM2
515#define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
516#else
517#define MPC85xx_OPENPIC_IRQ_OFFSET 0
518#endif
519#endif
520
521/* Not all of these exist on all MPC85xx implementations */
522#define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET)
523#define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET)
524#define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET)
525#define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET)
526#define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET)
527#define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET)
528#define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET)
529#define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET)
530#define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET)
531#define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
532#define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
533#define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET)
534#define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET)
535#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
536#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
537#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
538#define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET)
539#define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET)
540#define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET)
541#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
542#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
543#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
544#define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET)
545#define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET)
546#define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET)
547#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
548#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
549#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
550#define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET)
551#define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET)
552#define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET)
553#define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
554
555/* The 12 external interrupt lines */
556#define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET)
557#define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET)
558#define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET)
559#define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET)
560#define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET)
561#define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET)
562#define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET)
563#define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET)
564#define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET)
565#define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET)
566#define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET)
567#define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET)
568
569/* CPM related interrupts */
570#define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET)
571#define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET)
572#define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET)
573#define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET)
574#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
575#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
576#define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET)
577#define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET)
578#define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET)
579#define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET)
580#define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET)
581#define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET)
582#define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET)
583#define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET)
584#define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET)
585#define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET)
586#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
587#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
588#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
589#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
590#define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET)
591#define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET)
592#define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET)
593#define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET)
594#define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET)
595#define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET)
596#define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET)
597#define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET)
598#define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET)
599#define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET)
600#define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET)
601#define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET)
602#define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET)
603#define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET)
604#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
605#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
606
607#elif defined(CONFIG_PPC_86xx) 486#elif defined(CONFIG_PPC_86xx)
608#include <asm/mpc86xx.h> 487#include <asm/mpc86xx.h>
609 488
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
index 12a2860f9a9c..4c538228e42f 100644
--- a/include/asm-ppc/cpm2.h
+++ b/include/asm-ppc/cpm2.h
@@ -90,7 +90,7 @@
90 */ 90 */
91#define CPM_DATAONLY_BASE ((uint)128) 91#define CPM_DATAONLY_BASE ((uint)128)
92#define CPM_DP_NOSPACE ((uint)0x7fffffff) 92#define CPM_DP_NOSPACE ((uint)0x7fffffff)
93#if defined(CONFIG_8272) || defined(CONFIG_MPC8555) 93#if defined(CONFIG_8272)
94#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) 94#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
95#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) 95#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
96#else 96#else
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
deleted file mode 100644
index 9383d0c13ff8..000000000000
--- a/include/asm-ppc/immap_85xx.h
+++ /dev/null
@@ -1,126 +0,0 @@
1/*
2 * include/asm-ppc/immap_85xx.h
3 *
4 * MPC85xx Internal Memory Map
5 *
6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 *
8 * Copyright 2004 Freescale Semiconductor, Inc
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#ifdef __KERNEL__
18#ifndef __ASM_IMMAP_85XX_H__
19#define __ASM_IMMAP_85XX_H__
20
21/* Eventually this should define all the IO block registers in 85xx */
22
23/* PCI Registers */
24typedef struct ccsr_pci {
25 uint cfg_addr; /* 0x.000 - PCI Configuration Address Register */
26 uint cfg_data; /* 0x.004 - PCI Configuration Data Register */
27 uint int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
28 char res1[3060];
29 uint potar0; /* 0x.c00 - PCI Outbound Transaction Address Register 0 */
30 uint potear0; /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */
31 uint powbar0; /* 0x.c08 - PCI Outbound Window Base Address Register 0 */
32 char res2[4];
33 uint powar0; /* 0x.c10 - PCI Outbound Window Attributes Register 0 */
34 char res3[12];
35 uint potar1; /* 0x.c20 - PCI Outbound Transaction Address Register 1 */
36 uint potear1; /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */
37 uint powbar1; /* 0x.c28 - PCI Outbound Window Base Address Register 1 */
38 char res4[4];
39 uint powar1; /* 0x.c30 - PCI Outbound Window Attributes Register 1 */
40 char res5[12];
41 uint potar2; /* 0x.c40 - PCI Outbound Transaction Address Register 2 */
42 uint potear2; /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */
43 uint powbar2; /* 0x.c48 - PCI Outbound Window Base Address Register 2 */
44 char res6[4];
45 uint powar2; /* 0x.c50 - PCI Outbound Window Attributes Register 2 */
46 char res7[12];
47 uint potar3; /* 0x.c60 - PCI Outbound Transaction Address Register 3 */
48 uint potear3; /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */
49 uint powbar3; /* 0x.c68 - PCI Outbound Window Base Address Register 3 */
50 char res8[4];
51 uint powar3; /* 0x.c70 - PCI Outbound Window Attributes Register 3 */
52 char res9[12];
53 uint potar4; /* 0x.c80 - PCI Outbound Transaction Address Register 4 */
54 uint potear4; /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */
55 uint powbar4; /* 0x.c88 - PCI Outbound Window Base Address Register 4 */
56 char res10[4];
57 uint powar4; /* 0x.c90 - PCI Outbound Window Attributes Register 4 */
58 char res11[268];
59 uint pitar3; /* 0x.da0 - PCI Inbound Translation Address Register 3 */
60 char res12[4];
61 uint piwbar3; /* 0x.da8 - PCI Inbound Window Base Address Register 3 */
62 uint piwbear3; /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */
63 uint piwar3; /* 0x.db0 - PCI Inbound Window Attributes Register 3 */
64 char res13[12];
65 uint pitar2; /* 0x.dc0 - PCI Inbound Translation Address Register 2 */
66 char res14[4];
67 uint piwbar2; /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */
68 uint piwbear2; /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */
69 uint piwar2; /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */
70 char res15[12];
71 uint pitar1; /* 0x.de0 - PCI Inbound Translation Address Register 1 */
72 char res16[4];
73 uint piwbar1; /* 0x.de8 - PCI Inbound Window Base Address Register 1 */
74 char res17[4];
75 uint piwar1; /* 0x.df0 - PCI Inbound Window Attributes Register 1 */
76 char res18[12];
77 uint err_dr; /* 0x.e00 - PCI Error Detect Register */
78 uint err_cap_dr; /* 0x.e04 - PCI Error Capture Disable Register */
79 uint err_en; /* 0x.e08 - PCI Error Enable Register */
80 uint err_attrib; /* 0x.e0c - PCI Error Attributes Capture Register */
81 uint err_addr; /* 0x.e10 - PCI Error Address Capture Register */
82 uint err_ext_addr; /* 0x.e14 - PCI Error Extended Address Capture Register */
83 uint err_dl; /* 0x.e18 - PCI Error Data Low Capture Register */
84 uint err_dh; /* 0x.e1c - PCI Error Data High Capture Register */
85 uint gas_timr; /* 0x.e20 - PCI Gasket Timer Register */
86 uint pci_timr; /* 0x.e24 - PCI Timer Register */
87 char res19[472];
88} ccsr_pci_t;
89
90/* Global Utility Registers */
91typedef struct ccsr_guts {
92 uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
93 uint porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
94 uint porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
95 uint pordevsr; /* 0x.000c - POR I/O Device Status Register */
96 uint pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
97 char res1[12];
98 uint gpporcr; /* 0x.0020 - General-Purpose POR Configuration Register */
99 char res2[12];
100 uint gpiocr; /* 0x.0030 - GPIO Control Register */
101 char res3[12];
102 uint gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
103 char res4[12];
104 uint gpindr; /* 0x.0050 - General-Purpose Input Data Register */
105 char res5[12];
106 uint pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
107 char res6[12];
108 uint devdisr; /* 0x.0070 - Device Disable Control */
109 char res7[12];
110 uint powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
111 char res8[12];
112 uint mcpsumr; /* 0x.0090 - Machine Check Summary Register */
113 char res9[12];
114 uint pvr; /* 0x.00a0 - Processor Version Register */
115 uint svr; /* 0x.00a4 - System Version Register */
116 char res10[3416];
117 uint clkocr; /* 0x.0e00 - Clock Out Select Register */
118 char res11[12];
119 uint ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
120 char res12[12];
121 uint lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
122 char res13[61916];
123} ccsr_guts_t;
124
125#endif /* __ASM_IMMAP_85XX_H__ */
126#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h
index b2e25d8997bf..9f097e25b169 100644
--- a/include/asm-ppc/mmu_context.h
+++ b/include/asm-ppc/mmu_context.h
@@ -64,11 +64,6 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
64#define LAST_CONTEXT 255 64#define LAST_CONTEXT 255
65#define FIRST_CONTEXT 1 65#define FIRST_CONTEXT 1
66 66
67#elif defined(CONFIG_E200) || defined(CONFIG_E500)
68#define NO_CONTEXT 256
69#define LAST_CONTEXT 255
70#define FIRST_CONTEXT 1
71
72#else 67#else
73 68
74/* PPC 6xx, 7xx CPUs */ 69/* PPC 6xx, 7xx CPUs */
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
deleted file mode 100644
index d7e4a79d77fb..000000000000
--- a/include/asm-ppc/mpc85xx.h
+++ /dev/null
@@ -1,192 +0,0 @@
1/*
2 * include/asm-ppc/mpc85xx.h
3 *
4 * MPC85xx definitions
5 *
6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 *
8 * Copyright 2004 Freescale Semiconductor, Inc
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifdef __KERNEL__
17#ifndef __ASM_MPC85xx_H__
18#define __ASM_MPC85xx_H__
19
20#include <asm/mmu.h>
21
22#ifdef CONFIG_85xx
23
24#ifdef CONFIG_MPC8540_ADS
25#include <platforms/85xx/mpc8540_ads.h>
26#endif
27#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
28#include <platforms/85xx/mpc8555_cds.h>
29#endif
30#ifdef CONFIG_MPC85xx_CDS
31#include <platforms/85xx/mpc85xx_cds.h>
32#endif
33#ifdef CONFIG_MPC8560_ADS
34#include <platforms/85xx/mpc8560_ads.h>
35#endif
36#ifdef CONFIG_SBC8560
37#include <platforms/85xx/sbc8560.h>
38#endif
39#ifdef CONFIG_STX_GP3
40#include <platforms/85xx/stx_gp3.h>
41#endif
42#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8541) || \
43 defined(CONFIG_TQM8555) || defined(CONFIG_TQM8560)
44#include <platforms/85xx/tqm85xx.h>
45#endif
46
47/*
48 * The "residual" board information structure the boot loader passes
49 * into the kernel.
50 */
51extern unsigned char __res[];
52
53/* Offset from CCSRBAR */
54#define MPC85xx_CPM_OFFSET (0x80000)
55#define MPC85xx_CPM_SIZE (0x40000)
56#define MPC85xx_DMA_OFFSET (0x21000)
57#define MPC85xx_DMA_SIZE (0x01000)
58#define MPC85xx_DMA0_OFFSET (0x21100)
59#define MPC85xx_DMA0_SIZE (0x00080)
60#define MPC85xx_DMA1_OFFSET (0x21180)
61#define MPC85xx_DMA1_SIZE (0x00080)
62#define MPC85xx_DMA2_OFFSET (0x21200)
63#define MPC85xx_DMA2_SIZE (0x00080)
64#define MPC85xx_DMA3_OFFSET (0x21280)
65#define MPC85xx_DMA3_SIZE (0x00080)
66#define MPC85xx_ENET1_OFFSET (0x24000)
67#define MPC85xx_ENET1_SIZE (0x01000)
68#define MPC85xx_MIIM_OFFSET (0x24520)
69#define MPC85xx_MIIM_SIZE (0x00018)
70#define MPC85xx_ENET2_OFFSET (0x25000)
71#define MPC85xx_ENET2_SIZE (0x01000)
72#define MPC85xx_ENET3_OFFSET (0x26000)
73#define MPC85xx_ENET3_SIZE (0x01000)
74#define MPC85xx_GUTS_OFFSET (0xe0000)
75#define MPC85xx_GUTS_SIZE (0x01000)
76#define MPC85xx_IIC1_OFFSET (0x03000)
77#define MPC85xx_IIC1_SIZE (0x00100)
78#define MPC85xx_OPENPIC_OFFSET (0x40000)
79#define MPC85xx_OPENPIC_SIZE (0x40000)
80#define MPC85xx_PCI1_OFFSET (0x08000)
81#define MPC85xx_PCI1_SIZE (0x01000)
82#define MPC85xx_PCI2_OFFSET (0x09000)
83#define MPC85xx_PCI2_SIZE (0x01000)
84#define MPC85xx_PERFMON_OFFSET (0xe1000)
85#define MPC85xx_PERFMON_SIZE (0x01000)
86#define MPC85xx_SEC2_OFFSET (0x30000)
87#define MPC85xx_SEC2_SIZE (0x10000)
88#define MPC85xx_UART0_OFFSET (0x04500)
89#define MPC85xx_UART0_SIZE (0x00100)
90#define MPC85xx_UART1_OFFSET (0x04600)
91#define MPC85xx_UART1_SIZE (0x00100)
92
93#define MPC85xx_CCSRBAR_SIZE (1024*1024)
94
95/* Let modules/drivers get at CCSRBAR */
96extern phys_addr_t get_ccsrbar(void);
97
98#ifdef MODULE
99#define CCSRBAR get_ccsrbar()
100#else
101#define CCSRBAR BOARD_CCSRBAR
102#endif
103
104enum ppc_sys_devices {
105 MPC85xx_TSEC1,
106 MPC85xx_TSEC2,
107 MPC85xx_FEC,
108 MPC85xx_IIC1,
109 MPC85xx_DMA0,
110 MPC85xx_DMA1,
111 MPC85xx_DMA2,
112 MPC85xx_DMA3,
113 MPC85xx_DUART,
114 MPC85xx_PERFMON,
115 MPC85xx_SEC2,
116 MPC85xx_CPM_SPI,
117 MPC85xx_CPM_I2C,
118 MPC85xx_CPM_USB,
119 MPC85xx_CPM_SCC1,
120 MPC85xx_CPM_SCC2,
121 MPC85xx_CPM_SCC3,
122 MPC85xx_CPM_SCC4,
123 MPC85xx_CPM_FCC1,
124 MPC85xx_CPM_FCC2,
125 MPC85xx_CPM_FCC3,
126 MPC85xx_CPM_MCC1,
127 MPC85xx_CPM_MCC2,
128 MPC85xx_CPM_SMC1,
129 MPC85xx_CPM_SMC2,
130 MPC85xx_eTSEC1,
131 MPC85xx_eTSEC2,
132 MPC85xx_eTSEC3,
133 MPC85xx_eTSEC4,
134 MPC85xx_IIC2,
135 MPC85xx_MDIO,
136 NUM_PPC_SYS_DEVS,
137};
138
139/* Internal interrupts are all Level Sensitive, and Positive Polarity */
140#define MPC85XX_INTERNAL_IRQ_SENSES \
141 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0 */ \
142 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1 */ \
143 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2 */ \
144 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3 */ \
145 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4 */ \
146 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5 */ \
147 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6 */ \
148 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7 */ \
149 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8 */ \
150 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9 */ \
151 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10 */ \
152 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11 */ \
153 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12 */ \
154 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13 */ \
155 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14 */ \
156 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15 */ \
157 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16 */ \
158 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17 */ \
159 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18 */ \
160 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19 */ \
161 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20 */ \
162 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21 */ \
163 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22 */ \
164 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23 */ \
165 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24 */ \
166 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25 */ \
167 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26 */ \
168 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27 */ \
169 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28 */ \
170 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29 */ \
171 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30 */ \
172 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31 */ \
173 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32 */ \
174 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33 */ \
175 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34 */ \
176 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35 */ \
177 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36 */ \
178 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37 */ \
179 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38 */ \
180 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39 */ \
181 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40 */ \
182 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41 */ \
183 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42 */ \
184 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43 */ \
185 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44 */ \
186 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45 */ \
187 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46 */ \
188 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE) /* Internal 47 */
189
190#endif /* CONFIG_85xx */
191#endif /* __ASM_MPC85xx_H__ */
192#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index 063ad91cbbcc..69347bdbb401 100644
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -271,48 +271,6 @@ extern unsigned long ioremap_bot, ioremap_base;
271/* ERPN in a PTE never gets cleared, ignore it */ 271/* ERPN in a PTE never gets cleared, ignore it */
272#define _PTE_NONE_MASK 0xffffffff00000000ULL 272#define _PTE_NONE_MASK 0xffffffff00000000ULL
273 273
274#elif defined(CONFIG_FSL_BOOKE)
275/*
276 MMU Assist Register 3:
277
278 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
279 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
280
281 - PRESENT *must* be in the bottom three bits because swap cache
282 entries use the top 29 bits.
283
284 - FILE *must* be in the bottom three bits because swap cache
285 entries use the top 29 bits.
286*/
287
288/* Definitions for FSL Book-E Cores */
289#define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
290#define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
291#define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */
292#define _PAGE_ACCESSED 0x00004 /* S: Page referenced */
293#define _PAGE_HWWRITE 0x00008 /* H: Dirty & RW, set in exception */
294#define _PAGE_RW 0x00010 /* S: Write permission */
295#define _PAGE_HWEXEC 0x00020 /* H: UX permission */
296
297#define _PAGE_ENDIAN 0x00040 /* H: E bit */
298#define _PAGE_GUARDED 0x00080 /* H: G bit */
299#define _PAGE_COHERENT 0x00100 /* H: M bit */
300#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
301#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
302
303#ifdef CONFIG_PTE_64BIT
304#define _PAGE_DIRTY 0x08000 /* S: Page dirty */
305
306/* ERPN in a PTE never gets cleared, ignore it */
307#define _PTE_NONE_MASK 0xffffffffffff0000ULL
308#else
309#define _PAGE_DIRTY 0x00800 /* S: Page dirty */
310#endif
311
312#define _PMD_PRESENT 0
313#define _PMD_PRESENT_MASK (PAGE_MASK)
314#define _PMD_BAD (~PAGE_MASK)
315
316#elif defined(CONFIG_8xx) 274#elif defined(CONFIG_8xx)
317/* Definitions for 8xx embedded chips. */ 275/* Definitions for 8xx embedded chips. */
318#define _PAGE_PRESENT 0x0001 /* Page is valid */ 276#define _PAGE_PRESENT 0x0001 /* Page is valid */
@@ -484,11 +442,7 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
484 442
485/* in some case we want to additionaly adjust where the pfn is in the pte to 443/* in some case we want to additionaly adjust where the pfn is in the pte to
486 * allow room for more flags */ 444 * allow room for more flags */
487#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
488#define PFN_SHIFT_OFFSET (PAGE_SHIFT + 8)
489#else
490#define PFN_SHIFT_OFFSET (PAGE_SHIFT) 445#define PFN_SHIFT_OFFSET (PAGE_SHIFT)
491#endif
492 446
493#define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET) 447#define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET)
494#define pte_page(x) pfn_to_page(pte_pfn(x)) 448#define pte_page(x) pfn_to_page(pte_pfn(x))
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h
index 80c5851972f5..d2fee41d600b 100644
--- a/include/asm-ppc/ppc_sys.h
+++ b/include/asm-ppc/ppc_sys.h
@@ -23,8 +23,6 @@
23 23
24#if defined(CONFIG_8260) 24#if defined(CONFIG_8260)
25#include <asm/mpc8260.h> 25#include <asm/mpc8260.h>
26#elif defined(CONFIG_85xx)
27#include <asm/mpc85xx.h>
28#elif defined(CONFIG_8xx) 26#elif defined(CONFIG_8xx)
29#include <asm/mpc8xx.h> 27#include <asm/mpc8xx.h>
30#elif defined(CONFIG_PPC_MPC52xx) 28#elif defined(CONFIG_PPC_MPC52xx)
diff --git a/include/asm-ppc/ppcboot.h b/include/asm-ppc/ppcboot.h
index 18d04e8164ca..3819e17cd7b0 100644
--- a/include/asm-ppc/ppcboot.h
+++ b/include/asm-ppc/ppcboot.h
@@ -38,7 +38,7 @@ typedef struct bd_info {
38 unsigned long bi_flashoffset; /* reserved area for startup monitor */ 38 unsigned long bi_flashoffset; /* reserved area for startup monitor */
39 unsigned long bi_sramstart; /* start of SRAM memory */ 39 unsigned long bi_sramstart; /* start of SRAM memory */
40 unsigned long bi_sramsize; /* size of SRAM memory */ 40 unsigned long bi_sramsize; /* size of SRAM memory */
41#if defined(CONFIG_8xx) || defined(CONFIG_CPM2) || defined(CONFIG_85xx) 41#if defined(CONFIG_8xx) || defined(CONFIG_CPM2)
42 unsigned long bi_immr_base; /* base of IMMR register */ 42 unsigned long bi_immr_base; /* base of IMMR register */
43#endif 43#endif
44#if defined(CONFIG_PPC_MPC52xx) 44#if defined(CONFIG_PPC_MPC52xx)
@@ -72,12 +72,11 @@ typedef struct bd_info {
72#if defined(CONFIG_HYMOD) 72#if defined(CONFIG_HYMOD)
73 hymod_conf_t bi_hymod_conf; /* hymod configuration information */ 73 hymod_conf_t bi_hymod_conf; /* hymod configuration information */
74#endif 74#endif
75#if defined(CONFIG_EVB64260) || defined(CONFIG_405EP) || defined(CONFIG_44x) || \ 75#if defined(CONFIG_EVB64260) || defined(CONFIG_405EP) || defined(CONFIG_44x)
76 defined(CONFIG_85xx)
77 /* second onboard ethernet port */ 76 /* second onboard ethernet port */
78 unsigned char bi_enet1addr[6]; 77 unsigned char bi_enet1addr[6];
79#endif 78#endif
80#if defined(CONFIG_EVB64260) || defined(CONFIG_440GX) || defined(CONFIG_85xx) 79#if defined(CONFIG_EVB64260) || defined(CONFIG_440GX)
81 /* third onboard ethernet ports */ 80 /* third onboard ethernet ports */
82 unsigned char bi_enet2addr[6]; 81 unsigned char bi_enet2addr[6];
83#endif 82#endif
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
index 2f1a2afcfc28..91e96af88bd8 100644
--- a/include/asm-ppc/reg_booke.h
+++ b/include/asm-ppc/reg_booke.h
@@ -218,32 +218,6 @@
218#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ 218#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
219#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ 219#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
220#endif 220#endif
221#ifdef CONFIG_E500
222#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
223#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
224#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
225#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
226#define MCSR_GL_CI 0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */
227#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */
228#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */
229#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */
230#define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */
231#define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */
232#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */
233#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
234#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
235#endif
236#ifdef CONFIG_E200
237#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
238#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */
239#define MCSR_CPERR 0x10000000UL /* Cache Parity Error */
240#define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
241 fetch for an exception handler */
242#define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/
243#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */
244#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered
245 store or cache line push */
246#endif
247 221
248/* Bit definitions for the DBSR. */ 222/* Bit definitions for the DBSR. */
249/* 223/*
diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h
index 6220ef9ab8bc..d35ed10315b1 100644
--- a/include/asm-ppc/serial.h
+++ b/include/asm-ppc/serial.h
@@ -29,8 +29,6 @@
29#include <platforms/spruce.h> 29#include <platforms/spruce.h>
30#elif defined(CONFIG_4xx) 30#elif defined(CONFIG_4xx)
31#include <asm/ibm4xx.h> 31#include <asm/ibm4xx.h>
32#elif defined(CONFIG_85xx)
33#include <asm/mpc85xx.h>
34#elif defined(CONFIG_RADSTONE_PPC7D) 32#elif defined(CONFIG_RADSTONE_PPC7D)
35#include <platforms/radstone_ppc7d.h> 33#include <platforms/radstone_ppc7d.h>
36#else 34#else
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 19:13:24 -0500