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authorBecky Bruce <becky.bruce@freescale.com>2007-11-09 17:17:49 -0500
committerPaul Mackerras <paulus@samba.org>2007-11-13 00:22:43 -0500
commitb64f87c16f3c00fe593f632e1ee5798ba3f4f3f4 (patch)
tree1e0c63707b73c4b2f316a01b2e3c6ebd82c6356a /include
parent64c911a3f7c9864a4bbddbb77b722d5553ddcd32 (diff)
[POWERPC] Avoid unpaired stwcx. on some processors
The context switch code in the kernel issues a dummy stwcx. to clear the reservation, as recommended by the architecture. However, some processors can have issues if this stwcx to address A occurs while the reservation is already held to a different address B. To avoid this problem, the dummy stwcx. needs to be paired with a dummy lwarx to the same address. This adds the dummy lwarx, and creates a cpu feature bit to indicate which cpus are affected. Tested on mpc8641_hpcn_defconfig in arch/powerpc; build tested in arch/ppc. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-powerpc/cputable.h22
1 files changed, 12 insertions, 10 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 9d74338e3dec..4525c784dfd0 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -138,6 +138,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
138#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000) 138#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
139#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000) 139#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
140#define CPU_FTR_SPE ASM_CONST(0x0000000002000000) 140#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
141#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
141 142
142/* 143/*
143 * Add the 64-bit processor unique features in the top half of the word; 144 * Add the 64-bit processor unique features in the top half of the word;
@@ -261,25 +262,25 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
261#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ 262#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
262 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 263 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
263 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 264 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
264 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 265 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
265#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ 266#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
266 CPU_FTR_USE_TB | \ 267 CPU_FTR_USE_TB | \
267 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 268 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
268 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 269 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
269 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 270 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
270 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 271 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
271#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ 272#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
272 CPU_FTR_USE_TB | \ 273 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
273 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 274 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
274 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 275 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
275 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 276 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
276#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ 277#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
277 CPU_FTR_USE_TB | \ 278 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
278 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ 279 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
279 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \ 280 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
280 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 281 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
281#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ 282#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
282 CPU_FTR_USE_TB | \ 283 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
283 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 284 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
284 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 285 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
285 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 286 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
@@ -289,31 +290,32 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
289 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 290 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
290 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 291 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
291 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ 292 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
292 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 293 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
293#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ 294#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
294 CPU_FTR_USE_TB | \ 295 CPU_FTR_USE_TB | \
295 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 296 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
296 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 297 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
297 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ 298 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
298 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE) 299 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
300 CPU_FTR_NEED_PAIRED_STWCX)
299#define CPU_FTRS_7447 (CPU_FTR_COMMON | \ 301#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
300 CPU_FTR_USE_TB | \ 302 CPU_FTR_USE_TB | \
301 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 303 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
302 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 304 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
303 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ 305 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
304 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 306 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
305#define CPU_FTRS_7447A (CPU_FTR_COMMON | \ 307#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
306 CPU_FTR_USE_TB | \ 308 CPU_FTR_USE_TB | \
307 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 309 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
308 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 310 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
309 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ 311 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
310 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 312 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
311#define CPU_FTRS_7448 (CPU_FTR_COMMON | \ 313#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
312 CPU_FTR_USE_TB | \ 314 CPU_FTR_USE_TB | \
313 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 315 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
314 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 316 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
315 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ 317 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
316 CPU_FTR_PPC_LE) 318 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
317#define CPU_FTRS_82XX (CPU_FTR_COMMON | \ 319#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
318 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) 320 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
319#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ 321#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \