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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2008-02-19 18:53:02 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2008-02-19 18:53:02 -0500
commit989b0b930218661b504bbb056b309e2c7bcdfb86 (patch)
treedea722310d814fff27b02c0e00d8243252d74be4 /include
parente03f1a842287480aa03732612148c0d333baca61 (diff)
parent42086cec3263b8c015ca3faa01e8190f0e3ff445 (diff)
Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/czankel/xtensa-2.6
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/czankel/xtensa-2.6: (29 commits) [XTENSA] Allow debugger to modify the WINDOWBASE register. [XTENSA] Fix makefile to work with binutils-2.18. [XTENSA] Fix register corruption for certain processor configurations [XTENSA] Fix cache flush macro for D$/I$ aliasing/non-aliasing [XTENSA] Exclude thread-global registers from the xtregs structures. [XTENSA] Add support for the sa_restorer function [XTENSA] Add support for configurable registers and coprocessors [XTENSA] Clean up stat structs. [XTENSA] Use preprocessor to generate the linker script for the ELF boot image [XTENSA] Add missing RELOCATE_ENTRY for debug vector [XTENSA] Add volatile keyword to asm statements accessing counter registers [XTENSA] Remove unused code [XTENSA] Fix modules for non-exec processor configurations [XTENSA] Add missing cast in elf.h ELF_CORE_COPY_REGS() [XTENSA] Fix comments regarding the number of frames to save [XTENSA] Add missing a2 register restore in register spill routine [XTENSA] adjust boot linker script start addresses [XTENSA] Remove oldmask from sigcontext and fix register flush [XTENSA] Clean up elf-gregset. [XTENSA] Fix icache flush for cache aliasing ...
Diffstat (limited to 'include')
-rw-r--r--include/asm-xtensa/cacheflush.h2
-rw-r--r--include/asm-xtensa/coprocessor.h214
-rw-r--r--include/asm-xtensa/elf.h110
-rw-r--r--include/asm-xtensa/module.h4
-rw-r--r--include/asm-xtensa/pgalloc.h2
-rw-r--r--include/asm-xtensa/pgtable.h8
-rw-r--r--include/asm-xtensa/processor.h13
-rw-r--r--include/asm-xtensa/ptrace.h44
-rw-r--r--include/asm-xtensa/regs.h9
-rw-r--r--include/asm-xtensa/sigcontext.h4
-rw-r--r--include/asm-xtensa/stat.h36
-rw-r--r--include/asm-xtensa/system.h39
-rw-r--r--include/asm-xtensa/thread_info.h21
-rw-r--r--include/asm-xtensa/timex.h8
-rw-r--r--include/asm-xtensa/uaccess.h99
-rw-r--r--include/asm-xtensa/variant-fsf/tie-asm.h70
-rw-r--r--include/asm-xtensa/variant-fsf/tie.h75
17 files changed, 440 insertions, 318 deletions
diff --git a/include/asm-xtensa/cacheflush.h b/include/asm-xtensa/cacheflush.h
index b773c57e75a5..94c4c53a099e 100644
--- a/include/asm-xtensa/cacheflush.h
+++ b/include/asm-xtensa/cacheflush.h
@@ -70,6 +70,8 @@ extern void __flush_invalidate_dcache_page_alias(unsigned long, unsigned long);
70#endif 70#endif
71#if (ICACHE_WAY_SIZE > PAGE_SIZE) 71#if (ICACHE_WAY_SIZE > PAGE_SIZE)
72extern void __invalidate_icache_page_alias(unsigned long, unsigned long); 72extern void __invalidate_icache_page_alias(unsigned long, unsigned long);
73#else
74# define __invalidate_icache_page_alias(v,p) do { } while(0)
73#endif 75#endif
74 76
75/* 77/*
diff --git a/include/asm-xtensa/coprocessor.h b/include/asm-xtensa/coprocessor.h
index aa2121034558..1cbcf9001a41 100644
--- a/include/asm-xtensa/coprocessor.h
+++ b/include/asm-xtensa/coprocessor.h
@@ -5,81 +5,173 @@
5 * License. See the file "COPYING" in the main directory of this archive 5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details. 6 * for more details.
7 * 7 *
8 * Copyright (C) 2003 - 2005 Tensilica Inc. 8 * Copyright (C) 2003 - 2007 Tensilica Inc.
9 */ 9 */
10 10
11
11#ifndef _XTENSA_COPROCESSOR_H 12#ifndef _XTENSA_COPROCESSOR_H
12#define _XTENSA_COPROCESSOR_H 13#define _XTENSA_COPROCESSOR_H
13 14
14#include <asm/variant/core.h> 15#include <linux/stringify.h>
15#include <asm/variant/tie.h> 16#include <asm/variant/tie.h>
17#include <asm/types.h>
18
19#ifdef __ASSEMBLY__
20# include <asm/variant/tie-asm.h>
21
22.macro xchal_sa_start a b
23 .set .Lxchal_pofs_, 0
24 .set .Lxchal_ofs_, 0
25.endm
26
27.macro xchal_sa_align ptr minofs maxofs ofsalign totalign
28 .set .Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ + \totalign - 1
29 .set .Lxchal_ofs_, (.Lxchal_ofs_ & -\totalign) - .Lxchal_pofs_
30.endm
31
32#define _SELECT ( XTHAL_SAS_TIE | XTHAL_SAS_OPT \
33 | XTHAL_SAS_CC \
34 | XTHAL_SAS_CALR | XTHAL_SAS_CALE )
35
36.macro save_xtregs_opt ptr clb at1 at2 at3 at4 offset
37 .if XTREGS_OPT_SIZE > 0
38 addi \clb, \ptr, \offset
39 xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
40 .endif
41.endm
42
43.macro load_xtregs_opt ptr clb at1 at2 at3 at4 offset
44 .if XTREGS_OPT_SIZE > 0
45 addi \clb, \ptr, \offset
46 xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
47 .endif
48.endm
49#undef _SELECT
50
51#define _SELECT ( XTHAL_SAS_TIE | XTHAL_SAS_OPT \
52 | XTHAL_SAS_NOCC \
53 | XTHAL_SAS_CALR | XTHAL_SAS_CALE | XTHAL_SAS_GLOB )
54
55.macro save_xtregs_user ptr clb at1 at2 at3 at4 offset
56 .if XTREGS_USER_SIZE > 0
57 addi \clb, \ptr, \offset
58 xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
59 .endif
60.endm
61
62.macro load_xtregs_user ptr clb at1 at2 at3 at4 offset
63 .if XTREGS_USER_SIZE > 0
64 addi \clb, \ptr, \offset
65 xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
66 .endif
67.endm
68#undef _SELECT
69
70
71
72#endif /* __ASSEMBLY__ */
16 73
17#if !XCHAL_HAVE_CP
18
19#define XTENSA_CP_EXTRA_OFFSET 0
20#define XTENSA_CP_EXTRA_ALIGN 1 /* must be a power of 2 */
21#define XTENSA_CP_EXTRA_SIZE 0
22
23#else
24
25#define XTOFS(last_start,last_size,align) \
26 ((last_start+last_size+align-1) & -align)
27
28#define XTENSA_CP_EXTRA_OFFSET 0
29#define XTENSA_CP_EXTRA_ALIGN XCHAL_EXTRA_SA_ALIGN
30
31#define XTENSA_CPE_CP0_OFFSET \
32 XTOFS(XTENSA_CP_EXTRA_OFFSET, XCHAL_EXTRA_SA_SIZE, XCHAL_CP0_SA_ALIGN)
33#define XTENSA_CPE_CP1_OFFSET \
34 XTOFS(XTENSA_CPE_CP0_OFFSET, XCHAL_CP0_SA_SIZE, XCHAL_CP1_SA_ALIGN)
35#define XTENSA_CPE_CP2_OFFSET \
36 XTOFS(XTENSA_CPE_CP1_OFFSET, XCHAL_CP1_SA_SIZE, XCHAL_CP2_SA_ALIGN)
37#define XTENSA_CPE_CP3_OFFSET \
38 XTOFS(XTENSA_CPE_CP2_OFFSET, XCHAL_CP2_SA_SIZE, XCHAL_CP3_SA_ALIGN)
39#define XTENSA_CPE_CP4_OFFSET \
40 XTOFS(XTENSA_CPE_CP3_OFFSET, XCHAL_CP3_SA_SIZE, XCHAL_CP4_SA_ALIGN)
41#define XTENSA_CPE_CP5_OFFSET \
42 XTOFS(XTENSA_CPE_CP4_OFFSET, XCHAL_CP4_SA_SIZE, XCHAL_CP5_SA_ALIGN)
43#define XTENSA_CPE_CP6_OFFSET \
44 XTOFS(XTENSA_CPE_CP5_OFFSET, XCHAL_CP5_SA_SIZE, XCHAL_CP6_SA_ALIGN)
45#define XTENSA_CPE_CP7_OFFSET \
46 XTOFS(XTENSA_CPE_CP6_OFFSET, XCHAL_CP6_SA_SIZE, XCHAL_CP7_SA_ALIGN)
47#define XTENSA_CP_EXTRA_SIZE \
48 XTOFS(XTENSA_CPE_CP7_OFFSET, XCHAL_CP7_SA_SIZE, 16)
49
50#if XCHAL_CP_NUM > 0
51# ifndef __ASSEMBLY__
52/* 74/*
53 * Tasks that own contents of (last user) each coprocessor. 75 * XTENSA_HAVE_COPROCESSOR(x) returns 1 if coprocessor x is configured.
54 * Entries are 0 for not-owned or non-existent coprocessors. 76 *
55 * Note: The size of this structure is fixed to 8 bytes in entry.S 77 * XTENSA_HAVE_IO_PORT(x) returns 1 if io-port x is configured.
78 *
56 */ 79 */
57typedef struct {
58 struct task_struct *owner; /* owner */
59 int offset; /* offset in cpextra space. */
60} coprocessor_info_t;
61# else
62# define COPROCESSOR_INFO_OWNER 0
63# define COPROCESSOR_INFO_OFFSET 4
64# define COPROCESSOR_INFO_SIZE 8
65# endif
66#endif
67#endif /* XCHAL_HAVE_CP */
68 80
81#define XTENSA_HAVE_COPROCESSOR(x) \
82 ((XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK) & (1 << (x)))
83#define XTENSA_HAVE_COPROCESSORS \
84 (XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK)
85#define XTENSA_HAVE_IO_PORT(x) \
86 (XCHAL_CP_PORT_MASK & (1 << (x)))
87#define XTENSA_HAVE_IO_PORTS \
88 XCHAL_CP_PORT_MASK
69 89
70#ifndef __ASSEMBLY__ 90#ifndef __ASSEMBLY__
71# if XCHAL_CP_NUM > 0
72struct task_struct;
73extern void release_coprocessors (struct task_struct*);
74extern void save_coprocessor_registers(void*, int);
75# else
76# define release_coprocessors(task)
77# endif
78 91
79typedef unsigned char cp_state_t[XTENSA_CP_EXTRA_SIZE]
80 __attribute__ ((aligned (XTENSA_CP_EXTRA_ALIGN)));
81 92
82#endif /* !__ASSEMBLY__ */ 93#if XCHAL_HAVE_CP
94
95#define RSR_CPENABLE(x) do { \
96 __asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \
97 } while(0);
98#define WSR_CPENABLE(x) do { \
99 __asm__ __volatile__("wsr %0," __stringify(CPENABLE) "; rsync" \
100 :: "a" (x)); \
101 } while(0);
83 102
103#endif /* XCHAL_HAVE_CP */
84 104
105
106/*
107 * Additional registers.
108 * We define three types of additional registers:
109 * ext: extra registers that are used by the compiler
110 * cpn: optional registers that can be used by a user application
111 * cpX: coprocessor registers that can only be used if the corresponding
112 * CPENABLE bit is set.
113 */
114
115#define XCHAL_SA_REG(list,cc,abi,type,y,name,z,align,size,...) \
116 __REG ## list (cc, abi, type, name, size, align)
117
118#define __REG0(cc,abi,t,name,s,a) __REG0_ ## cc (abi,name)
119#define __REG1(cc,abi,t,name,s,a) __REG1_ ## cc (name)
120#define __REG2(cc,abi,type,...) __REG2_ ## type (__VA_ARGS__)
121
122#define __REG0_0(abi,name)
123#define __REG0_1(abi,name) __REG0_1 ## abi (name)
124#define __REG0_10(name) __u32 name;
125#define __REG0_11(name) __u32 name;
126#define __REG0_12(name)
127
128#define __REG1_0(name) __u32 name;
129#define __REG1_1(name)
130
131#define __REG2_0(n,s,a) __u32 name;
132#define __REG2_1(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));
133#define __REG2_2(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));
134
135typedef struct { XCHAL_NCP_SA_LIST(0) } xtregs_opt_t
136 __attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
137typedef struct { XCHAL_NCP_SA_LIST(1) } xtregs_user_t
138 __attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
139
140#if XTENSA_HAVE_COPROCESSORS
141
142typedef struct { XCHAL_CP0_SA_LIST(2) } xtregs_cp0_t
143 __attribute__ ((aligned (XCHAL_CP0_SA_ALIGN)));
144typedef struct { XCHAL_CP1_SA_LIST(2) } xtregs_cp1_t
145 __attribute__ ((aligned (XCHAL_CP1_SA_ALIGN)));
146typedef struct { XCHAL_CP2_SA_LIST(2) } xtregs_cp2_t
147 __attribute__ ((aligned (XCHAL_CP2_SA_ALIGN)));
148typedef struct { XCHAL_CP3_SA_LIST(2) } xtregs_cp3_t
149 __attribute__ ((aligned (XCHAL_CP3_SA_ALIGN)));
150typedef struct { XCHAL_CP4_SA_LIST(2) } xtregs_cp4_t
151 __attribute__ ((aligned (XCHAL_CP4_SA_ALIGN)));
152typedef struct { XCHAL_CP5_SA_LIST(2) } xtregs_cp5_t
153 __attribute__ ((aligned (XCHAL_CP5_SA_ALIGN)));
154typedef struct { XCHAL_CP6_SA_LIST(2) } xtregs_cp6_t
155 __attribute__ ((aligned (XCHAL_CP6_SA_ALIGN)));
156typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t
157 __attribute__ ((aligned (XCHAL_CP7_SA_ALIGN)));
158
159extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX];
160extern void coprocessor_save(void*, int);
161extern void coprocessor_load(void*, int);
162extern void coprocessor_flush(struct thread_info*, int);
163extern void coprocessor_restore(struct thread_info*, int);
164
165extern void coprocessor_release_all(struct thread_info*);
166extern void coprocessor_flush_all(struct thread_info*);
167
168static inline void coprocessor_clear_cpenable(void)
169{
170 unsigned long i = 0;
171 WSR_CPENABLE(i);
172}
173
174#endif /* XTENSA_HAVE_COPROCESSORS */
175
176#endif /* !__ASSEMBLY__ */
85#endif /* _XTENSA_COPROCESSOR_H */ 177#endif /* _XTENSA_COPROCESSOR_H */
diff --git a/include/asm-xtensa/elf.h b/include/asm-xtensa/elf.h
index 467384542502..ca6e5101a2cb 100644
--- a/include/asm-xtensa/elf.h
+++ b/include/asm-xtensa/elf.h
@@ -72,115 +72,32 @@
72 72
73/* ELF register definitions. This is needed for core dump support. */ 73/* ELF register definitions. This is needed for core dump support. */
74 74
75/*
76 * elf_gregset_t contains the application-level state in the following order:
77 * Processor info: config_version, cpuxy
78 * Processor state: pc, ps, exccause, excvaddr, wb, ws,
79 * lbeg, lend, lcount, sar
80 * GP regs: ar0 - arXX
81 */
82
83typedef unsigned long elf_greg_t; 75typedef unsigned long elf_greg_t;
84 76
85typedef struct { 77typedef struct {
86 elf_greg_t xchal_config_id0;
87 elf_greg_t xchal_config_id1;
88 elf_greg_t cpux;
89 elf_greg_t cpuy;
90 elf_greg_t pc; 78 elf_greg_t pc;
91 elf_greg_t ps; 79 elf_greg_t ps;
92 elf_greg_t exccause;
93 elf_greg_t excvaddr;
94 elf_greg_t windowbase;
95 elf_greg_t windowstart;
96 elf_greg_t lbeg; 80 elf_greg_t lbeg;
97 elf_greg_t lend; 81 elf_greg_t lend;
98 elf_greg_t lcount; 82 elf_greg_t lcount;
99 elf_greg_t sar; 83 elf_greg_t sar;
100 elf_greg_t syscall; 84 elf_greg_t windowstart;
101 elf_greg_t ar[64]; 85 elf_greg_t windowbase;
86 elf_greg_t reserved[8+48];
87 elf_greg_t a[64];
102} xtensa_gregset_t; 88} xtensa_gregset_t;
103 89
104#define ELF_NGREG (sizeof(xtensa_gregset_t) / sizeof(elf_greg_t)) 90#define ELF_NGREG (sizeof(xtensa_gregset_t) / sizeof(elf_greg_t))
105 91
106typedef elf_greg_t elf_gregset_t[ELF_NGREG]; 92typedef elf_greg_t elf_gregset_t[ELF_NGREG];
107 93
108/* 94#define ELF_NFPREG 18
109 * Compute the size of the coprocessor and extra state layout (register info)
110 * table (in bytes).
111 * This is actually the maximum size of the table, as opposed to the size,
112 * which is available from the _xtensa_reginfo_table_size global variable.
113 *
114 * (See also arch/xtensa/kernel/coprocessor.S)
115 *
116 */
117
118#ifndef XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM
119# define XTENSA_CPE_LTABLE_SIZE 0
120#else
121# define XTENSA_CPE_SEGMENT(num) (num ? (1+num) : 0)
122# define XTENSA_CPE_LTABLE_ENTRIES \
123 ( XTENSA_CPE_SEGMENT(XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM) \
124 + XTENSA_CPE_SEGMENT(XCHAL_CP0_SA_CONTENTS_LIBDB_NUM) \
125 + XTENSA_CPE_SEGMENT(XCHAL_CP1_SA_CONTENTS_LIBDB_NUM) \
126 + XTENSA_CPE_SEGMENT(XCHAL_CP2_SA_CONTENTS_LIBDB_NUM) \
127 + XTENSA_CPE_SEGMENT(XCHAL_CP3_SA_CONTENTS_LIBDB_NUM) \
128 + XTENSA_CPE_SEGMENT(XCHAL_CP4_SA_CONTENTS_LIBDB_NUM) \
129 + XTENSA_CPE_SEGMENT(XCHAL_CP5_SA_CONTENTS_LIBDB_NUM) \
130 + XTENSA_CPE_SEGMENT(XCHAL_CP6_SA_CONTENTS_LIBDB_NUM) \
131 + XTENSA_CPE_SEGMENT(XCHAL_CP7_SA_CONTENTS_LIBDB_NUM) \
132 + 1 /* final entry */ \
133 )
134# define XTENSA_CPE_LTABLE_SIZE (XTENSA_CPE_LTABLE_ENTRIES * 8)
135#endif
136
137
138/*
139 * Instantiations of the elf_fpregset_t type contain, in most
140 * architectures, the floating point (FPU) register set.
141 * For Xtensa, this type is extended to contain all custom state,
142 * ie. coprocessor and "extra" (non-coprocessor) state (including,
143 * for example, TIE-defined states and register files; as well
144 * as other optional processor state).
145 * This includes FPU state if a floating-point coprocessor happens
146 * to have been configured within the Xtensa processor.
147 *
148 * TOTAL_FPREGS_SIZE is the required size (without rounding)
149 * of elf_fpregset_t. It provides space for the following:
150 *
151 * a) 32-bit mask of active coprocessors for this task (similar
152 * to CPENABLE in single-threaded Xtensa processor systems)
153 *
154 * b) table describing the layout of custom states (ie. of
155 * individual registers, etc) within the save areas
156 *
157 * c) save areas for each coprocessor and for non-coprocessor
158 * ("extra") state
159 *
160 * Note that save areas may require up to 16-byte alignment when
161 * accessed by save/restore sequences. We do not need to ensure
162 * such alignment in an elf_fpregset_t structure because custom
163 * state is not directly loaded/stored into it; rather, save area
164 * contents are copied to elf_fpregset_t from the active save areas
165 * (see 'struct task_struct' definition in processor.h for that)
166 * using memcpy(). But we do allow space for such alignment,
167 * to allow optimizations of layout and copying.
168 */
169#if 0
170#define TOTAL_FPREGS_SIZE \
171 (4 + XTENSA_CPE_LTABLE_SIZE + XTENSA_CP_EXTRA_SIZE)
172#define ELF_NFPREG \
173 ((TOTAL_FPREGS_SIZE + sizeof(elf_fpreg_t) - 1) / sizeof(elf_fpreg_t))
174#else
175#define TOTAL_FPREGS_SIZE 0
176#define ELF_NFPREG 0
177#endif
178 95
179typedef unsigned int elf_fpreg_t; 96typedef unsigned int elf_fpreg_t;
180typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; 97typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
181 98
182#define ELF_CORE_COPY_REGS(_eregs, _pregs) \ 99#define ELF_CORE_COPY_REGS(_eregs, _pregs) \
183 xtensa_elf_core_copy_regs (&_eregs, _pregs); 100 xtensa_elf_core_copy_regs ((xtensa_gregset_t*)&(_eregs), _pregs);
184 101
185extern void xtensa_elf_core_copy_regs (xtensa_gregset_t *, struct pt_regs *); 102extern void xtensa_elf_core_copy_regs (xtensa_gregset_t *, struct pt_regs *);
186 103
@@ -257,6 +174,21 @@ extern void xtensa_elf_core_copy_regs (xtensa_gregset_t *, struct pt_regs *);
257 _r->areg[12]=0; _r->areg[13]=0; _r->areg[14]=0; _r->areg[15]=0; \ 174 _r->areg[12]=0; _r->areg[13]=0; _r->areg[14]=0; _r->areg[15]=0; \
258 } while (0) 175 } while (0)
259 176
177typedef struct {
178 xtregs_opt_t opt;
179 xtregs_user_t user;
180#if XTENSA_HAVE_COPROCESSORS
181 xtregs_cp0_t cp0;
182 xtregs_cp1_t cp1;
183 xtregs_cp2_t cp2;
184 xtregs_cp3_t cp3;
185 xtregs_cp4_t cp4;
186 xtregs_cp5_t cp5;
187 xtregs_cp6_t cp6;
188 xtregs_cp7_t cp7;
189#endif
190} elf_xtregs_t;
191
260#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT) 192#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT)
261 193
262struct task_struct; 194struct task_struct;
diff --git a/include/asm-xtensa/module.h b/include/asm-xtensa/module.h
index ffb25bfdf6a1..d9b34bee4d42 100644
--- a/include/asm-xtensa/module.h
+++ b/include/asm-xtensa/module.h
@@ -15,9 +15,11 @@
15 15
16struct mod_arch_specific 16struct mod_arch_specific
17{ 17{
18 /* Module support is not completely implemented. */ 18 /* No special elements, yet. */
19}; 19};
20 20
21#define MODULE_ARCH_VERMAGIC "xtensa-" __stringify(XCHAL_CORE_ID) " "
22
21#define Elf_Shdr Elf32_Shdr 23#define Elf_Shdr Elf32_Shdr
22#define Elf_Sym Elf32_Sym 24#define Elf_Sym Elf32_Sym
23#define Elf_Ehdr Elf32_Ehdr 25#define Elf_Ehdr Elf32_Ehdr
diff --git a/include/asm-xtensa/pgalloc.h b/include/asm-xtensa/pgalloc.h
index 8d1544eb461e..4f4a7987eded 100644
--- a/include/asm-xtensa/pgalloc.h
+++ b/include/asm-xtensa/pgalloc.h
@@ -47,7 +47,7 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
47 return kmem_cache_alloc(pgtable_cache, GFP_KERNEL|__GFP_REPEAT); 47 return kmem_cache_alloc(pgtable_cache, GFP_KERNEL|__GFP_REPEAT);
48} 48}
49 49
50static inline pte_token_t pte_alloc_one(struct mm_struct *mm, 50static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
51 unsigned long addr) 51 unsigned long addr)
52{ 52{
53 struct page *page; 53 struct page *page;
diff --git a/include/asm-xtensa/pgtable.h b/include/asm-xtensa/pgtable.h
index c0fcc1c9660c..c8b024a48b4d 100644
--- a/include/asm-xtensa/pgtable.h
+++ b/include/asm-xtensa/pgtable.h
@@ -66,11 +66,9 @@
66 */ 66 */
67 67
68#define VMALLOC_START 0xC0000000 68#define VMALLOC_START 0xC0000000
69#define VMALLOC_END 0xC6FEFFFF 69#define VMALLOC_END 0xC7FEFFFF
70#define TLBTEMP_BASE_1 0xC6FF0000 70#define TLBTEMP_BASE_1 0xC7FF0000
71#define TLBTEMP_BASE_2 0xC6FF8000 71#define TLBTEMP_BASE_2 0xC7FF8000
72#define MODULE_START 0xC7000000
73#define MODULE_END 0xC7FFFFFF
74 72
75/* 73/*
76 * Xtensa Linux config PTE layout (when present): 74 * Xtensa Linux config PTE layout (when present):
diff --git a/include/asm-xtensa/processor.h b/include/asm-xtensa/processor.h
index 96408f436624..4918a4e96d42 100644
--- a/include/asm-xtensa/processor.h
+++ b/include/asm-xtensa/processor.h
@@ -103,10 +103,6 @@ struct thread_struct {
103 unsigned long dbreaka[XCHAL_NUM_DBREAK]; 103 unsigned long dbreaka[XCHAL_NUM_DBREAK];
104 unsigned long dbreakc[XCHAL_NUM_DBREAK]; 104 unsigned long dbreakc[XCHAL_NUM_DBREAK];
105 105
106 /* Allocate storage for extra state and coprocessor state. */
107 unsigned char cp_save[XTENSA_CP_EXTRA_SIZE]
108 __attribute__ ((aligned(XTENSA_CP_EXTRA_ALIGN)));
109
110 /* Make structure 16 bytes aligned. */ 106 /* Make structure 16 bytes aligned. */
111 int align[0] __attribute__ ((aligned(16))); 107 int align[0] __attribute__ ((aligned(16)));
112}; 108};
@@ -162,21 +158,16 @@ struct thread_struct {
162struct task_struct; 158struct task_struct;
163struct mm_struct; 159struct mm_struct;
164 160
165// FIXME: do we need release_thread for CP??
166/* Free all resources held by a thread. */ 161/* Free all resources held by a thread. */
167#define release_thread(thread) do { } while(0) 162#define release_thread(thread) do { } while(0)
168 163
169// FIXME: do we need prepare_to_copy (lazy status) for CP??
170/* Prepare to copy thread state - unlazy all lazy status */ 164/* Prepare to copy thread state - unlazy all lazy status */
171#define prepare_to_copy(tsk) do { } while (0) 165extern void prepare_to_copy(struct task_struct*);
172 166
173/* 167/* Create a kernel thread without removing it from tasklists */
174 * create a kernel thread without removing it from tasklists
175 */
176extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); 168extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
177 169
178/* Copy and release all segment info associated with a VM */ 170/* Copy and release all segment info associated with a VM */
179
180#define copy_segments(p, mm) do { } while(0) 171#define copy_segments(p, mm) do { } while(0)
181#define release_segments(mm) do { } while(0) 172#define release_segments(mm) do { } while(0)
182#define forget_segments() do { } while (0) 173#define forget_segments() do { } while (0)
diff --git a/include/asm-xtensa/ptrace.h b/include/asm-xtensa/ptrace.h
index 77ff02d307bb..422c73e26937 100644
--- a/include/asm-xtensa/ptrace.h
+++ b/include/asm-xtensa/ptrace.h
@@ -53,33 +53,30 @@
53 53
54/* Registers used by strace */ 54/* Registers used by strace */
55 55
56#define REG_A_BASE 0xfc000000 56#define REG_A_BASE 0x0000
57#define REG_AR_BASE 0x04000000 57#define REG_AR_BASE 0x0100
58#define REG_PC 0x14000000 58#define REG_PC 0x0020
59#define REG_PS 0x080000e6 59#define REG_PS 0x02e6
60#define REG_WB 0x08000048 60#define REG_WB 0x0248
61#define REG_WS 0x08000049 61#define REG_WS 0x0249
62#define REG_LBEG 0x08000000 62#define REG_LBEG 0x0200
63#define REG_LEND 0x08000001 63#define REG_LEND 0x0201
64#define REG_LCOUNT 0x08000002 64#define REG_LCOUNT 0x0202
65#define REG_SAR 0x08000003 65#define REG_SAR 0x0203
66#define REG_DEPC 0x080000c0 66
67#define REG_EXCCAUSE 0x080000e8 67#define SYSCALL_NR 0x00ff
68#define REG_EXCVADDR 0x080000ee
69#define SYSCALL_NR 0x1
70
71#define AR_REGNO_TO_A_REGNO(ar, wb) (ar - wb*4) & ~(XCHAL_NUM_AREGS - 1)
72 68
73/* Other PTRACE_ values defined in <linux/ptrace.h> using values 0-9,16,17,24 */ 69/* Other PTRACE_ values defined in <linux/ptrace.h> using values 0-9,16,17,24 */
74 70
75#define PTRACE_GETREGS 12 71#define PTRACE_GETREGS 12
76#define PTRACE_SETREGS 13 72#define PTRACE_SETREGS 13
77#define PTRACE_GETFPREGS 14 73#define PTRACE_GETXTREGS 18
78#define PTRACE_SETFPREGS 15 74#define PTRACE_SETXTREGS 19
79#define PTRACE_GETFPREGSIZE 18
80 75
81#ifndef __ASSEMBLY__ 76#ifndef __ASSEMBLY__
82 77
78#ifdef __KERNEL__
79
83/* 80/*
84 * This struct defines the way the registers are stored on the 81 * This struct defines the way the registers are stored on the
85 * kernel stack during a system call or other kernel entry. 82 * kernel stack during a system call or other kernel entry.
@@ -102,6 +99,9 @@ struct pt_regs {
102 unsigned long icountlevel; /* 60 */ 99 unsigned long icountlevel; /* 60 */
103 int reserved[1]; /* 64 */ 100 int reserved[1]; /* 64 */
104 101
102 /* Additional configurable registers that are used by the compiler. */
103 xtregs_opt_t xtregs_opt;
104
105 /* Make sure the areg field is 16 bytes aligned. */ 105 /* Make sure the areg field is 16 bytes aligned. */
106 int align[0] __attribute__ ((aligned(16))); 106 int align[0] __attribute__ ((aligned(16)));
107 107
@@ -111,8 +111,6 @@ struct pt_regs {
111 unsigned long areg[16]; /* 128 (64) */ 111 unsigned long areg[16]; /* 128 (64) */
112}; 112};
113 113
114#ifdef __KERNEL__
115
116#include <asm/variant/core.h> 114#include <asm/variant/core.h>
117 115
118# define task_pt_regs(tsk) ((struct pt_regs*) \ 116# define task_pt_regs(tsk) ((struct pt_regs*) \
diff --git a/include/asm-xtensa/regs.h b/include/asm-xtensa/regs.h
index c913d259faaa..d4baed246928 100644
--- a/include/asm-xtensa/regs.h
+++ b/include/asm-xtensa/regs.h
@@ -100,7 +100,14 @@
100#define EXCCAUSE_DTLB_SIZE_RESTRICTION 27 100#define EXCCAUSE_DTLB_SIZE_RESTRICTION 27
101#define EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 101#define EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28
102#define EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 102#define EXCCAUSE_STORE_CACHE_ATTRIBUTE 29
103#define EXCCAUSE_FLOATING_POINT 40 103#define EXCCAUSE_COPROCESSOR0_DISABLED 32
104#define EXCCAUSE_COPROCESSOR1_DISABLED 33
105#define EXCCAUSE_COPROCESSOR2_DISABLED 34
106#define EXCCAUSE_COPROCESSOR3_DISABLED 35
107#define EXCCAUSE_COPROCESSOR4_DISABLED 36
108#define EXCCAUSE_COPROCESSOR5_DISABLED 37
109#define EXCCAUSE_COPROCESSOR6_DISABLED 38
110#define EXCCAUSE_COPROCESSOR7_DISABLED 39
104 111
105/* PS register fields. */ 112/* PS register fields. */
106 113
diff --git a/include/asm-xtensa/sigcontext.h b/include/asm-xtensa/sigcontext.h
index e3381cee5059..03383af8c3b7 100644
--- a/include/asm-xtensa/sigcontext.h
+++ b/include/asm-xtensa/sigcontext.h
@@ -13,9 +13,6 @@
13 13
14 14
15struct sigcontext { 15struct sigcontext {
16 unsigned long oldmask;
17
18 /* CPU registers */
19 unsigned long sc_pc; 16 unsigned long sc_pc;
20 unsigned long sc_ps; 17 unsigned long sc_ps;
21 unsigned long sc_lbeg; 18 unsigned long sc_lbeg;
@@ -25,6 +22,7 @@ struct sigcontext {
25 unsigned long sc_acclo; 22 unsigned long sc_acclo;
26 unsigned long sc_acchi; 23 unsigned long sc_acchi;
27 unsigned long sc_a[16]; 24 unsigned long sc_a[16];
25 void *sc_xtregs;
28}; 26};
29 27
30#endif /* _XTENSA_SIGCONTEXT_H */ 28#endif /* _XTENSA_SIGCONTEXT_H */
diff --git a/include/asm-xtensa/stat.h b/include/asm-xtensa/stat.h
index 149f4bce092f..c4992038cee0 100644
--- a/include/asm-xtensa/stat.h
+++ b/include/asm-xtensa/stat.h
@@ -5,25 +5,23 @@
5 * License. See the file "COPYING" in the main directory of this archive 5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details. 6 * for more details.
7 * 7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc. 8 * Copyright (C) 2001 - 2007 Tensilica Inc.
9 */ 9 */
10 10
11#ifndef _XTENSA_STAT_H 11#ifndef _XTENSA_STAT_H
12#define _XTENSA_STAT_H 12#define _XTENSA_STAT_H
13 13
14#include <linux/types.h>
15
16#define STAT_HAVE_NSEC 1 14#define STAT_HAVE_NSEC 1
17 15
18struct stat { 16struct stat {
19 unsigned long st_dev; 17 unsigned long st_dev;
20 ino_t st_ino; 18 unsigned long st_ino;
21 mode_t st_mode; 19 unsigned int st_mode;
22 nlink_t st_nlink; 20 unsigned int st_nlink;
23 uid_t st_uid; 21 unsigned int st_uid;
24 gid_t st_gid; 22 unsigned int st_gid;
25 unsigned int st_rdev; 23 unsigned long st_rdev;
26 off_t st_size; 24 long st_size;
27 unsigned long st_blksize; 25 unsigned long st_blksize;
28 unsigned long st_blocks; 26 unsigned long st_blocks;
29 unsigned long st_atime; 27 unsigned long st_atime;
@@ -36,8 +34,6 @@ struct stat {
36 unsigned long __unused5; 34 unsigned long __unused5;
37}; 35};
38 36
39/* This matches struct stat64 in glibc-2.3 */
40
41struct stat64 { 37struct stat64 {
42 unsigned long long st_dev; /* Device */ 38 unsigned long long st_dev; /* Device */
43 unsigned long long st_ino; /* File serial number */ 39 unsigned long long st_ino; /* File serial number */
@@ -47,20 +43,14 @@ struct stat64 {
47 unsigned int st_gid; /* Group ID of the file's group. */ 43 unsigned int st_gid; /* Group ID of the file's group. */
48 unsigned long long st_rdev; /* Device number, if device. */ 44 unsigned long long st_rdev; /* Device number, if device. */
49 long long st_size; /* Size of file, in bytes. */ 45 long long st_size; /* Size of file, in bytes. */
50 long st_blksize; /* Optimal block size for I/O. */ 46 unsigned long st_blksize; /* Optimal block size for I/O. */
51 unsigned long __unused2; 47 unsigned long __unused2;
52#ifdef __XTENSA_EB__ 48 unsigned long long st_blocks; /* Number 512-byte blocks allocated. */
53 unsigned long __unused3; 49 unsigned long st_atime; /* Time of last access. */
54 long st_blocks; /* Number 512-byte blocks allocated. */
55#else
56 long st_blocks; /* Number 512-byte blocks allocated. */
57 unsigned long __unused3;
58#endif
59 long st_atime; /* Time of last access. */
60 unsigned long st_atime_nsec; 50 unsigned long st_atime_nsec;
61 long st_mtime; /* Time of last modification. */ 51 unsigned long st_mtime; /* Time of last modification. */
62 unsigned long st_mtime_nsec; 52 unsigned long st_mtime_nsec;
63 long st_ctime; /* Time of last status change. */ 53 unsigned long st_ctime; /* Time of last status change. */
64 unsigned long st_ctime_nsec; 54 unsigned long st_ctime_nsec;
65 unsigned long __unused4; 55 unsigned long __unused4;
66 unsigned long __unused5; 56 unsigned long __unused5;
diff --git a/include/asm-xtensa/system.h b/include/asm-xtensa/system.h
index e0cb9116d8ab..62b1e8f3c13c 100644
--- a/include/asm-xtensa/system.h
+++ b/include/asm-xtensa/system.h
@@ -46,42 +46,6 @@ static inline int irqs_disabled(void)
46 return flags & 0xf; 46 return flags & 0xf;
47} 47}
48 48
49#define RSR_CPENABLE(x) do { \
50 __asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \
51 } while(0);
52#define WSR_CPENABLE(x) do { \
53 __asm__ __volatile__("wsr %0," __stringify(CPENABLE)";rsync" \
54 :: "a" (x));} while(0);
55
56#define clear_cpenable() __clear_cpenable()
57
58static inline void __clear_cpenable(void)
59{
60#if XCHAL_HAVE_CP
61 unsigned long i = 0;
62 WSR_CPENABLE(i);
63#endif
64}
65
66static inline void enable_coprocessor(int i)
67{
68#if XCHAL_HAVE_CP
69 int cp;
70 RSR_CPENABLE(cp);
71 cp |= 1 << i;
72 WSR_CPENABLE(cp);
73#endif
74}
75
76static inline void disable_coprocessor(int i)
77{
78#if XCHAL_HAVE_CP
79 int cp;
80 RSR_CPENABLE(cp);
81 cp &= ~(1 << i);
82 WSR_CPENABLE(cp);
83#endif
84}
85 49
86#define smp_read_barrier_depends() do { } while(0) 50#define smp_read_barrier_depends() do { } while(0)
87#define read_barrier_depends() do { } while(0) 51#define read_barrier_depends() do { } while(0)
@@ -111,7 +75,6 @@ extern void *_switch_to(void *last, void *next);
111 75
112#define switch_to(prev,next,last) \ 76#define switch_to(prev,next,last) \
113do { \ 77do { \
114 clear_cpenable(); \
115 (last) = _switch_to(prev, next); \ 78 (last) = _switch_to(prev, next); \
116} while(0) 79} while(0)
117 80
@@ -244,7 +207,7 @@ static inline void spill_registers(void)
244 "wsr a13," __stringify(SAR) "\n\t" 207 "wsr a13," __stringify(SAR) "\n\t"
245 "wsr a14," __stringify(PS) "\n\t" 208 "wsr a14," __stringify(PS) "\n\t"
246 :: "a" (&a0), "a" (&ps) 209 :: "a" (&a0), "a" (&ps)
247 : "a2", "a3", "a12", "a13", "a14", "a15", "memory"); 210 : "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15", "memory");
248} 211}
249 212
250#define arch_align_stack(x) (x) 213#define arch_align_stack(x) (x)
diff --git a/include/asm-xtensa/thread_info.h b/include/asm-xtensa/thread_info.h
index 52c958285bcb..a2c640682ed9 100644
--- a/include/asm-xtensa/thread_info.h
+++ b/include/asm-xtensa/thread_info.h
@@ -27,6 +27,21 @@
27 27
28#ifndef __ASSEMBLY__ 28#ifndef __ASSEMBLY__
29 29
30#if XTENSA_HAVE_COPROCESSORS
31
32typedef struct xtregs_coprocessor {
33 xtregs_cp0_t cp0;
34 xtregs_cp1_t cp1;
35 xtregs_cp2_t cp2;
36 xtregs_cp3_t cp3;
37 xtregs_cp4_t cp4;
38 xtregs_cp5_t cp5;
39 xtregs_cp6_t cp6;
40 xtregs_cp7_t cp7;
41} xtregs_coprocessor_t;
42
43#endif
44
30struct thread_info { 45struct thread_info {
31 struct task_struct *task; /* main task structure */ 46 struct task_struct *task; /* main task structure */
32 struct exec_domain *exec_domain; /* execution domain */ 47 struct exec_domain *exec_domain; /* execution domain */
@@ -38,7 +53,13 @@ struct thread_info {
38 mm_segment_t addr_limit; /* thread address space */ 53 mm_segment_t addr_limit; /* thread address space */
39 struct restart_block restart_block; 54 struct restart_block restart_block;
40 55
56 unsigned long cpenable;
41 57
58 /* Allocate storage for extra user states and coprocessor states. */
59#if XTENSA_HAVE_COPROCESSORS
60 xtregs_coprocessor_t xtregs_cp;
61#endif
62 xtregs_user_t xtregs_user;
42}; 63};
43 64
44#else /* !__ASSEMBLY__ */ 65#else /* !__ASSEMBLY__ */
diff --git a/include/asm-xtensa/timex.h b/include/asm-xtensa/timex.h
index a5fca59fba9e..b83a8181d448 100644
--- a/include/asm-xtensa/timex.h
+++ b/include/asm-xtensa/timex.h
@@ -63,10 +63,10 @@ extern cycles_t cacheflush_time;
63 * Register access. 63 * Register access.
64 */ 64 */
65 65
66#define WSR_CCOUNT(r) __asm__("wsr %0,"__stringify(CCOUNT) :: "a" (r)) 66#define WSR_CCOUNT(r) asm volatile ("wsr %0,"__stringify(CCOUNT) :: "a" (r))
67#define RSR_CCOUNT(r) __asm__("rsr %0,"__stringify(CCOUNT) : "=a" (r)) 67#define RSR_CCOUNT(r) asm volatile ("rsr %0,"__stringify(CCOUNT) : "=a" (r))
68#define WSR_CCOMPARE(x,r) __asm__("wsr %0,"__stringify(CCOMPARE)"+"__stringify(x) :: "a"(r)) 68#define WSR_CCOMPARE(x,r) asm volatile ("wsr %0,"__stringify(CCOMPARE)"+"__stringify(x) :: "a"(r))
69#define RSR_CCOMPARE(x,r) __asm__("rsr %0,"__stringify(CCOMPARE)"+"__stringify(x) : "=a"(r)) 69#define RSR_CCOMPARE(x,r) asm volatile ("rsr %0,"__stringify(CCOMPARE)"+"__stringify(x) : "=a"(r))
70 70
71static inline unsigned long get_ccount (void) 71static inline unsigned long get_ccount (void)
72{ 72{
diff --git a/include/asm-xtensa/uaccess.h b/include/asm-xtensa/uaccess.h
index d6352da05b10..b8528426ab1f 100644
--- a/include/asm-xtensa/uaccess.h
+++ b/include/asm-xtensa/uaccess.h
@@ -26,6 +26,7 @@
26#include <asm/current.h> 26#include <asm/current.h>
27#include <asm/asm-offsets.h> 27#include <asm/asm-offsets.h>
28#include <asm/processor.h> 28#include <asm/processor.h>
29#include <asm/types.h>
29 30
30/* 31/*
31 * These assembly macros mirror the C macros that follow below. They 32 * These assembly macros mirror the C macros that follow below. They
@@ -118,7 +119,7 @@
118 * <at> destroyed (actually, (TASK_SIZE + 1 - size)) 119 * <at> destroyed (actually, (TASK_SIZE + 1 - size))
119 */ 120 */
120 .macro user_ok aa, as, at, error 121 .macro user_ok aa, as, at, error
121 movi \at, (TASK_SIZE+1) 122 movi \at, __XTENSA_UL_CONST(TASK_SIZE)
122 bgeu \as, \at, \error 123 bgeu \as, \at, \error
123 sub \at, \at, \as 124 sub \at, \at, \as
124 bgeu \aa, \at, \error 125 bgeu \aa, \at, \error
@@ -226,20 +227,21 @@ extern long __put_user_bad(void);
226 __pu_err; \ 227 __pu_err; \
227}) 228})
228 229
229#define __put_user_size(x,ptr,size,retval) \ 230#define __put_user_size(x,ptr,size,retval) \
230do { \ 231do { \
231 retval = 0; \ 232 int __cb; \
232 switch (size) { \ 233 retval = 0; \
233 case 1: __put_user_asm(x,ptr,retval,1,"s8i"); break; \ 234 switch (size) { \
234 case 2: __put_user_asm(x,ptr,retval,2,"s16i"); break; \ 235 case 1: __put_user_asm(x,ptr,retval,1,"s8i",__cb); break; \
235 case 4: __put_user_asm(x,ptr,retval,4,"s32i"); break; \ 236 case 2: __put_user_asm(x,ptr,retval,2,"s16i",__cb); break; \
236 case 8: { \ 237 case 4: __put_user_asm(x,ptr,retval,4,"s32i",__cb); break; \
237 __typeof__(*ptr) __v64 = x; \ 238 case 8: { \
238 retval = __copy_to_user(ptr,&__v64,8); \ 239 __typeof__(*ptr) __v64 = x; \
239 break; \ 240 retval = __copy_to_user(ptr,&__v64,8); \
240 } \ 241 break; \
241 default: __put_user_bad(); \ 242 } \
242 } \ 243 default: __put_user_bad(); \
244 } \
243} while (0) 245} while (0)
244 246
245 247
@@ -267,14 +269,14 @@ do { \
267#define __check_align_1 "" 269#define __check_align_1 ""
268 270
269#define __check_align_2 \ 271#define __check_align_2 \
270 " _bbci.l %2, 0, 1f \n" \ 272 " _bbci.l %3, 0, 1f \n" \
271 " movi %0, %3 \n" \ 273 " movi %0, %4 \n" \
272 " _j 2f \n" 274 " _j 2f \n"
273 275
274#define __check_align_4 \ 276#define __check_align_4 \
275 " _bbsi.l %2, 0, 0f \n" \ 277 " _bbsi.l %3, 0, 0f \n" \
276 " _bbci.l %2, 1, 1f \n" \ 278 " _bbci.l %3, 1, 1f \n" \
277 "0: movi %0, %3 \n" \ 279 "0: movi %0, %4 \n" \
278 " _j 2f \n" 280 " _j 2f \n"
279 281
280 282
@@ -286,24 +288,24 @@ do { \
286 * WARNING: If you modify this macro at all, verify that the 288 * WARNING: If you modify this macro at all, verify that the
287 * __check_align_* macros still work. 289 * __check_align_* macros still work.
288 */ 290 */
289#define __put_user_asm(x, addr, err, align, insn) \ 291#define __put_user_asm(x, addr, err, align, insn, cb) \
290 __asm__ __volatile__( \ 292 __asm__ __volatile__( \
291 __check_align_##align \ 293 __check_align_##align \
292 "1: "insn" %1, %2, 0 \n" \ 294 "1: "insn" %2, %3, 0 \n" \
293 "2: \n" \ 295 "2: \n" \
294 " .section .fixup,\"ax\" \n" \ 296 " .section .fixup,\"ax\" \n" \
295 " .align 4 \n" \ 297 " .align 4 \n" \
296 "4: \n" \ 298 "4: \n" \
297 " .long 2b \n" \ 299 " .long 2b \n" \
298 "5: \n" \ 300 "5: \n" \
299 " l32r %2, 4b \n" \ 301 " l32r %1, 4b \n" \
300 " movi %0, %3 \n" \ 302 " movi %0, %4 \n" \
301 " jx %2 \n" \ 303 " jx %1 \n" \
302 " .previous \n" \ 304 " .previous \n" \
303 " .section __ex_table,\"a\" \n" \ 305 " .section __ex_table,\"a\" \n" \
304 " .long 1b, 5b \n" \ 306 " .long 1b, 5b \n" \
305 " .previous" \ 307 " .previous" \
306 :"=r" (err) \ 308 :"=r" (err), "=r" (cb) \
307 :"r" ((int)(x)), "r" (addr), "i" (-EFAULT), "0" (err)) 309 :"r" ((int)(x)), "r" (addr), "i" (-EFAULT), "0" (err))
308 310
309#define __get_user_nocheck(x,ptr,size) \ 311#define __get_user_nocheck(x,ptr,size) \
@@ -328,11 +330,12 @@ extern long __get_user_bad(void);
328 330
329#define __get_user_size(x,ptr,size,retval) \ 331#define __get_user_size(x,ptr,size,retval) \
330do { \ 332do { \
333 int __cb; \
331 retval = 0; \ 334 retval = 0; \
332 switch (size) { \ 335 switch (size) { \
333 case 1: __get_user_asm(x,ptr,retval,1,"l8ui"); break; \ 336 case 1: __get_user_asm(x,ptr,retval,1,"l8ui",__cb); break; \
334 case 2: __get_user_asm(x,ptr,retval,2,"l16ui"); break; \ 337 case 2: __get_user_asm(x,ptr,retval,2,"l16ui",__cb); break; \
335 case 4: __get_user_asm(x,ptr,retval,4,"l32i"); break; \ 338 case 4: __get_user_asm(x,ptr,retval,4,"l32i",__cb); break; \
336 case 8: retval = __copy_from_user(&x,ptr,8); break; \ 339 case 8: retval = __copy_from_user(&x,ptr,8); break; \
337 default: (x) = __get_user_bad(); \ 340 default: (x) = __get_user_bad(); \
338 } \ 341 } \
@@ -343,25 +346,25 @@ do { \
343 * WARNING: If you modify this macro at all, verify that the 346 * WARNING: If you modify this macro at all, verify that the
344 * __check_align_* macros still work. 347 * __check_align_* macros still work.
345 */ 348 */
346#define __get_user_asm(x, addr, err, align, insn) \ 349#define __get_user_asm(x, addr, err, align, insn, cb) \
347 __asm__ __volatile__( \ 350 __asm__ __volatile__( \
348 __check_align_##align \ 351 __check_align_##align \
349 "1: "insn" %1, %2, 0 \n" \ 352 "1: "insn" %2, %3, 0 \n" \
350 "2: \n" \ 353 "2: \n" \
351 " .section .fixup,\"ax\" \n" \ 354 " .section .fixup,\"ax\" \n" \
352 " .align 4 \n" \ 355 " .align 4 \n" \
353 "4: \n" \ 356 "4: \n" \
354 " .long 2b \n" \ 357 " .long 2b \n" \
355 "5: \n" \ 358 "5: \n" \
356 " l32r %2, 4b \n" \ 359 " l32r %1, 4b \n" \
357 " movi %1, 0 \n" \ 360 " movi %2, 0 \n" \
358 " movi %0, %3 \n" \ 361 " movi %0, %4 \n" \
359 " jx %2 \n" \ 362 " jx %1 \n" \
360 " .previous \n" \ 363 " .previous \n" \
361 " .section __ex_table,\"a\" \n" \ 364 " .section __ex_table,\"a\" \n" \
362 " .long 1b, 5b \n" \ 365 " .long 1b, 5b \n" \
363 " .previous" \ 366 " .previous" \
364 :"=r" (err), "=r" (x) \ 367 :"=r" (err), "=r" (cb), "=r" (x) \
365 :"r" (addr), "i" (-EFAULT), "0" (err)) 368 :"r" (addr), "i" (-EFAULT), "0" (err))
366 369
367 370
diff --git a/include/asm-xtensa/variant-fsf/tie-asm.h b/include/asm-xtensa/variant-fsf/tie-asm.h
new file mode 100644
index 000000000000..68a73bf4ffc5
--- /dev/null
+++ b/include/asm-xtensa/variant-fsf/tie-asm.h
@@ -0,0 +1,70 @@
1/*
2 * This header file contains assembly-language definitions (assembly
3 * macros, etc.) for this specific Xtensa processor's TIE extensions
4 * and options. It is customized to this Xtensa processor configuration.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1999-2008 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_CORE_TIE_ASM_H
14#define _XTENSA_CORE_TIE_ASM_H
15
16/* Selection parameter values for save-area save/restore macros: */
17/* Option vs. TIE: */
18#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
19#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
20/* Whether used automatically by compiler: */
21#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
22#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
23/* ABI handling across function calls: */
24#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
25#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
26#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
27/* Misc */
28#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
29
30
31
32/* Macro to save all non-coprocessor (extra) custom TIE and optional state
33 * (not including zero-overhead loop registers).
34 * Save area ptr (clobbered): ptr (1 byte aligned)
35 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
36 */
37 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
38 xchal_sa_start \continue, \ofs
39 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
40 xchal_sa_align \ptr, 0, 1024-4, 4, 4
41 rur \at1, THREADPTR // threadptr option
42 s32i \at1, \ptr, .Lxchal_ofs_ + 0
43 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
44 .endif
45 .endm // xchal_ncp_store
46
47/* Macro to save all non-coprocessor (extra) custom TIE and optional state
48 * (not including zero-overhead loop registers).
49 * Save area ptr (clobbered): ptr (1 byte aligned)
50 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
51 */
52 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
53 xchal_sa_start \continue, \ofs
54 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
55 xchal_sa_align \ptr, 0, 1024-4, 4, 4
56 l32i \at1, \ptr, .Lxchal_ofs_ + 0
57 wur \at1, THREADPTR // threadptr option
58 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
59 .endif
60 .endm // xchal_ncp_load
61
62
63
64#define XCHAL_NCP_NUM_ATMPS 1
65
66
67#define XCHAL_SA_NUM_ATMPS 1
68
69#endif /*_XTENSA_CORE_TIE_ASM_H*/
70
diff --git a/include/asm-xtensa/variant-fsf/tie.h b/include/asm-xtensa/variant-fsf/tie.h
index a73c71664918..bf4020116df5 100644
--- a/include/asm-xtensa/variant-fsf/tie.h
+++ b/include/asm-xtensa/variant-fsf/tie.h
@@ -1,22 +1,77 @@
1/* 1/*
2 * Xtensa processor core configuration information. 2 * This header file describes this specific Xtensa processor's TIE extensions
3 * that extend basic Xtensa core functionality. It is customized to this
4 * Xtensa processor configuration.
3 * 5 *
4 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
6 * for more details. 8 * for more details.
7 * 9 *
8 * Copyright (C) 1999-2006 Tensilica Inc. 10 * Copyright (C) 1999-2007 Tensilica Inc.
9 */ 11 */
10 12
11#ifndef XTENSA_TIE_H 13#ifndef _XTENSA_CORE_TIE_H
12#define XTENSA_TIE_H 14#define _XTENSA_CORE_TIE_H
13
14/*----------------------------------------------------------------------
15 COPROCESSORS and EXTRA STATE
16 ----------------------------------------------------------------------*/
17 15
18#define XCHAL_CP_NUM 0 /* number of coprocessors */ 16#define XCHAL_CP_NUM 0 /* number of coprocessors */
19#define XCHAL_CP_MASK 0x00 17#define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */
18#define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
19#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
20
21/* Basic parameters of each coprocessor: */
22#define XCHAL_CP7_NAME "XTIOP"
23#define XCHAL_CP7_IDENT XTIOP
24#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
25#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
26#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
27
28/* Filler info for unassigned coprocessors, to simplify arrays etc: */
29#define XCHAL_NCP_SA_SIZE 0
30#define XCHAL_NCP_SA_ALIGN 1
31#define XCHAL_CP0_SA_SIZE 0
32#define XCHAL_CP0_SA_ALIGN 1
33#define XCHAL_CP1_SA_SIZE 0
34#define XCHAL_CP1_SA_ALIGN 1
35#define XCHAL_CP2_SA_SIZE 0
36#define XCHAL_CP2_SA_ALIGN 1
37#define XCHAL_CP3_SA_SIZE 0
38#define XCHAL_CP3_SA_ALIGN 1
39#define XCHAL_CP4_SA_SIZE 0
40#define XCHAL_CP4_SA_ALIGN 1
41#define XCHAL_CP5_SA_SIZE 0
42#define XCHAL_CP5_SA_ALIGN 1
43#define XCHAL_CP6_SA_SIZE 0
44#define XCHAL_CP6_SA_ALIGN 1
45
46/* Save area for non-coprocessor optional and custom (TIE) state: */
47#define XCHAL_NCP_SA_SIZE 0
48#define XCHAL_NCP_SA_ALIGN 1
49
50/* Total save area for optional and custom state (NCP + CPn): */
51#define XCHAL_TOTAL_SA_SIZE 0 /* with 16-byte align padding */
52#define XCHAL_TOTAL_SA_ALIGN 1 /* actual minimum alignment */
53
54#define XCHAL_NCP_SA_NUM 0
55#define XCHAL_NCP_SA_LIST(s)
56#define XCHAL_CP0_SA_NUM 0
57#define XCHAL_CP0_SA_LIST(s)
58#define XCHAL_CP1_SA_NUM 0
59#define XCHAL_CP1_SA_LIST(s)
60#define XCHAL_CP2_SA_NUM 0
61#define XCHAL_CP2_SA_LIST(s)
62#define XCHAL_CP3_SA_NUM 0
63#define XCHAL_CP3_SA_LIST(s)
64#define XCHAL_CP4_SA_NUM 0
65#define XCHAL_CP4_SA_LIST(s)
66#define XCHAL_CP5_SA_NUM 0
67#define XCHAL_CP5_SA_LIST(s)
68#define XCHAL_CP6_SA_NUM 0
69#define XCHAL_CP6_SA_LIST(s)
70#define XCHAL_CP7_SA_NUM 0
71#define XCHAL_CP7_SA_LIST(s)
72
73/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
74#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
20 75
21#endif /*XTENSA_CONFIG_TIE_H*/ 76#endif /*_XTENSA_CORE_TIE_H*/
22 77
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 17:08:54 -0500