aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
authorRobin Getz <robin.getz@analog.com>2007-10-10 11:55:26 -0400
committerBryan Wu <bryan.wu@analog.com>2007-10-10 11:55:26 -0400
commit3bebca2d20796dd3dc62c5d3e74148087c7ce5bd (patch)
treefdb5eb8eb774fa5e8df41ebbf0e0d2c82b9ff627 /include
parenta298049180d2c56fc8ac1796b24973bf4f019cc7 (diff)
Blackfin arch: to do some consolidation of common code and common name spaces
now all BLKFIN should be BFIN, should be no functional changes. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include')
-rw-r--r--include/asm-blackfin/cacheflush.h14
-rw-r--r--include/asm-blackfin/cplb.h89
-rw-r--r--include/asm-blackfin/mach-bf533/bf533.h16
-rw-r--r--include/asm-blackfin/mach-bf533/mem_map.h56
-rw-r--r--include/asm-blackfin/mach-bf537/anomaly.h1
-rw-r--r--include/asm-blackfin/mach-bf537/bf537.h67
-rw-r--r--include/asm-blackfin/mach-bf537/mem_map.h60
-rw-r--r--include/asm-blackfin/mach-bf548/bf548.h67
-rw-r--r--include/asm-blackfin/mach-bf548/mem_map.h24
-rw-r--r--include/asm-blackfin/mach-bf561/bf561.h91
-rw-r--r--include/asm-blackfin/mach-bf561/mem_map.h24
-rw-r--r--include/asm-blackfin/mach-common/clocks.h4
-rw-r--r--include/asm-blackfin/mach-common/def_LPBlackfin.h3
-rw-r--r--include/asm-blackfin/pgtable.h2
-rw-r--r--include/asm-blackfin/system.h2
15 files changed, 205 insertions, 315 deletions
diff --git a/include/asm-blackfin/cacheflush.h b/include/asm-blackfin/cacheflush.h
index e5e000de3c36..d81a77545a04 100644
--- a/include/asm-blackfin/cacheflush.h
+++ b/include/asm-blackfin/cacheflush.h
@@ -48,9 +48,9 @@ extern void blackfin_dflush_page(void *);
48 48
49static inline void flush_icache_range(unsigned start, unsigned end) 49static inline void flush_icache_range(unsigned start, unsigned end)
50{ 50{
51#if defined(CONFIG_BLKFIN_DCACHE) && defined(CONFIG_BLKFIN_CACHE) 51#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE)
52 52
53# if defined(CONFIG_BLKFIN_WT) 53# if defined(CONFIG_BFIN_WT)
54 blackfin_icache_flush_range((start), (end)); 54 blackfin_icache_flush_range((start), (end));
55# else 55# else
56 blackfin_icache_dcache_flush_range((start), (end)); 56 blackfin_icache_dcache_flush_range((start), (end));
@@ -58,10 +58,10 @@ static inline void flush_icache_range(unsigned start, unsigned end)
58 58
59#else 59#else
60 60
61# if defined(CONFIG_BLKFIN_CACHE) 61# if defined(CONFIG_BFIN_ICACHE)
62 blackfin_icache_flush_range((start), (end)); 62 blackfin_icache_flush_range((start), (end));
63# endif 63# endif
64# if defined(CONFIG_BLKFIN_DCACHE) 64# if defined(CONFIG_BFIN_DCACHE)
65 blackfin_dcache_flush_range((start), (end)); 65 blackfin_dcache_flush_range((start), (end));
66# endif 66# endif
67 67
@@ -74,12 +74,12 @@ do { memcpy(dst, src, len); \
74} while (0) 74} while (0)
75#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len) 75#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
76 76
77#if defined(CONFIG_BLKFIN_DCACHE) 77#if defined(CONFIG_BFIN_DCACHE)
78# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end)) 78# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end))
79#else 79#else
80# define invalidate_dcache_range(start,end) do { } while (0) 80# define invalidate_dcache_range(start,end) do { } while (0)
81#endif 81#endif
82#if defined(CONFIG_BLKFIN_DCACHE) && defined(CONFIG_BLKFIN_WB) 82#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB)
83# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) 83# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
84# define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) 84# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
85#else 85#else
@@ -87,4 +87,4 @@ do { memcpy(dst, src, len); \
87# define flush_dcache_page(page) do { } while (0) 87# define flush_dcache_page(page) do { } while (0)
88#endif 88#endif
89 89
90#endif /* _BLACKFIN_CACHEFLUSH_H */ 90#endif /* _BLACKFIN_ICACHEFLUSH_H */
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
index e0dd56bfa4c7..c9fc77684fb2 100644
--- a/include/asm-blackfin/cplb.h
+++ b/include/asm-blackfin/cplb.h
@@ -1,18 +1,93 @@
1/************************************************************************ 1/*
2 * File: include/asm-blackfin/cplb.h
3 * Based on: include/asm-blackfin/mach-bf537/bf537.h
4 * Author: Robin Getz <rgetz@blackfin.uclinux.org>
2 * 5 *
3 * cplb.h 6 * Created: 2000
7 * Description: Common CPLB definitions for CPLB init
4 * 8 *
5 * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved. 9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
6 * 11 *
7 ************************************************************************/ 12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
8 13 *
9/* Defines necessary for cplb initialisation routines. */ 14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
10 29
11#ifndef _CPLB_H 30#ifndef _CPLB_H
12#define _CPLB_H 31#define _CPLB_H
13 32
14# include <asm/blackfin.h> 33# include <asm/blackfin.h>
15 34
35#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
36#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
37#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
38#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
39
40/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
41
42#if ANOMALY_05000158
43#define ANOMALY_05000158_WORKAROUND 0x200
44#else
45#define ANOMALY_05000158_WORKAROUND 0x0
46#endif
47
48#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
49
50#ifdef CONFIG_BFIN_WB /*Write Back Policy */
51#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
52#else /*Write Through */
53#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
54#endif
55
56#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
57#define SDRAM_DNON_CHBL (CPLB_COMMON)
58#define SDRAM_EBIU (CPLB_COMMON)
59#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
60
61#define SIZE_1K 0x00000400 /* 1K */
62#define SIZE_4K 0x00001000 /* 4K */
63#define SIZE_1M 0x00100000 /* 1M */
64#define SIZE_4M 0x00400000 /* 4M */
65
66#define MAX_CPLBS (16 * 2)
67
68/*
69* Number of required data CPLB switchtable entries
70* MEMSIZE / 4 (we mostly install 4M page size CPLBs
71* approx 16 for smaller 1MB page size CPLBs for allignment purposes
72* 1 for L1 Data Memory
73* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
74* 1 for ASYNC Memory
75*/
76
77
78#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
79
80/*
81* Number of required instruction CPLB switchtable entries
82* MEMSIZE / 4 (we mostly install 4M page size CPLBs
83* approx 12 for smaller 1MB page size CPLBs for allignment purposes
84* 1 for L1 Instruction Memory
85* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
86*/
87
88#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
89
90
16#define CPLB_ENABLE_ICACHE_P 0 91#define CPLB_ENABLE_ICACHE_P 0
17#define CPLB_ENABLE_DCACHE_P 1 92#define CPLB_ENABLE_DCACHE_P 1
18#define CPLB_ENABLE_DCACHE2_P 2 93#define CPLB_ENABLE_DCACHE2_P 2
@@ -39,8 +114,6 @@
39#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT 114#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
40#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY 115#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
41 116
42#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
43
44#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID 117#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
45#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID 118#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
46#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID 119#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
diff --git a/include/asm-blackfin/mach-bf533/bf533.h b/include/asm-blackfin/mach-bf533/bf533.h
index cb210f6f7689..cb0785768b35 100644
--- a/include/asm-blackfin/mach-bf533/bf533.h
+++ b/include/asm-blackfin/mach-bf533/bf533.h
@@ -52,12 +52,12 @@
52/***************************/ 52/***************************/
53 53
54 54
55#define BLKFIN_DSUBBANKS 4 55#define BFIN_DSUBBANKS 4
56#define BLKFIN_DWAYS 2 56#define BFIN_DWAYS 2
57#define BLKFIN_DLINES 64 57#define BFIN_DLINES 64
58#define BLKFIN_ISUBBANKS 4 58#define BFIN_ISUBBANKS 4
59#define BLKFIN_IWAYS 4 59#define BFIN_IWAYS 4
60#define BLKFIN_ILINES 32 60#define BFIN_ILINES 32
61 61
62#define WAY0_L 0x1 62#define WAY0_L 0x1
63#define WAY1_L 0x2 63#define WAY1_L 0x2
@@ -167,10 +167,10 @@
167#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) 167#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
168#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) 168#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
169 169
170/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ 170/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
171 171
172#define ANOMALY_05000158_WORKAROUND 0x200 172#define ANOMALY_05000158_WORKAROUND 0x200
173#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ 173#ifdef CONFIG_BFIN_WB /*Write Back Policy */
174#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ 174#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
175 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) 175 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
176#else /*Write Through */ 176#else /*Write Through */
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h
index e84baa3e939d..94d8c4062eb7 100644
--- a/include/asm-blackfin/mach-bf533/mem_map.h
+++ b/include/asm-blackfin/mach-bf533/mem_map.h
@@ -51,10 +51,10 @@
51 51
52/* Level 1 Memory */ 52/* Level 1 Memory */
53 53
54#ifdef CONFIG_BLKFIN_CACHE 54#ifdef CONFIG_BFIN_ICACHE
55#define BLKFIN_ICACHESIZE (16*1024) 55#define BFIN_ICACHESIZE (16*1024)
56#else 56#else
57#define BLKFIN_ICACHESIZE (0*1024) 57#define BFIN_ICACHESIZE (0*1024)
58#endif 58#endif
59 59
60/* Memory Map for ADSP-BF533 processors */ 60/* Memory Map for ADSP-BF533 processors */
@@ -64,35 +64,35 @@
64#define L1_DATA_A_START 0xFF800000 64#define L1_DATA_A_START 0xFF800000
65#define L1_DATA_B_START 0xFF900000 65#define L1_DATA_B_START 0xFF900000
66 66
67#ifdef CONFIG_BLKFIN_CACHE 67#ifdef CONFIG_BFIN_ICACHE
68#define L1_CODE_LENGTH (0x14000 - 0x4000) 68#define L1_CODE_LENGTH (0x14000 - 0x4000)
69#else 69#else
70#define L1_CODE_LENGTH 0x14000 70#define L1_CODE_LENGTH 0x14000
71#endif 71#endif
72 72
73#ifdef CONFIG_BLKFIN_DCACHE 73#ifdef CONFIG_BFIN_DCACHE
74 74
75#ifdef CONFIG_BLKFIN_DCACHE_BANKA 75#ifdef CONFIG_BFIN_DCACHE_BANKA
76#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 76#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
77#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 77#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
78#define L1_DATA_B_LENGTH 0x8000 78#define L1_DATA_B_LENGTH 0x8000
79#define BLKFIN_DCACHESIZE (16*1024) 79#define BFIN_DCACHESIZE (16*1024)
80#define BLKFIN_DSUPBANKS 1 80#define BFIN_DSUPBANKS 1
81#else 81#else
82#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 82#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
83#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 83#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
84#define L1_DATA_B_LENGTH (0x8000 - 0x4000) 84#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
85#define BLKFIN_DCACHESIZE (32*1024) 85#define BFIN_DCACHESIZE (32*1024)
86#define BLKFIN_DSUPBANKS 2 86#define BFIN_DSUPBANKS 2
87#endif 87#endif
88 88
89#else 89#else
90#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 90#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
91#define L1_DATA_A_LENGTH 0x8000 91#define L1_DATA_A_LENGTH 0x8000
92#define L1_DATA_B_LENGTH 0x8000 92#define L1_DATA_B_LENGTH 0x8000
93#define BLKFIN_DCACHESIZE (0*1024) 93#define BFIN_DCACHESIZE (0*1024)
94#define BLKFIN_DSUPBANKS 0 94#define BFIN_DSUPBANKS 0
95#endif /*CONFIG_BLKFIN_DCACHE*/ 95#endif /*CONFIG_BFIN_DCACHE*/
96#endif 96#endif
97 97
98/* Memory Map for ADSP-BF532 processors */ 98/* Memory Map for ADSP-BF532 processors */
@@ -102,36 +102,36 @@
102#define L1_DATA_A_START 0xFF804000 102#define L1_DATA_A_START 0xFF804000
103#define L1_DATA_B_START 0xFF904000 103#define L1_DATA_B_START 0xFF904000
104 104
105#ifdef CONFIG_BLKFIN_CACHE 105#ifdef CONFIG_BFIN_ICACHE
106#define L1_CODE_LENGTH (0xC000 - 0x4000) 106#define L1_CODE_LENGTH (0xC000 - 0x4000)
107#else 107#else
108#define L1_CODE_LENGTH 0xC000 108#define L1_CODE_LENGTH 0xC000
109#endif 109#endif
110 110
111#ifdef CONFIG_BLKFIN_DCACHE 111#ifdef CONFIG_BFIN_DCACHE
112 112
113#ifdef CONFIG_BLKFIN_DCACHE_BANKA 113#ifdef CONFIG_BFIN_DCACHE_BANKA
114#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 114#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
115#define L1_DATA_A_LENGTH (0x4000 - 0x4000) 115#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
116#define L1_DATA_B_LENGTH 0x4000 116#define L1_DATA_B_LENGTH 0x4000
117#define BLKFIN_DCACHESIZE (16*1024) 117#define BFIN_DCACHESIZE (16*1024)
118#define BLKFIN_DSUPBANKS 1 118#define BFIN_DSUPBANKS 1
119 119
120#else 120#else
121#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 121#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
122#define L1_DATA_A_LENGTH (0x4000 - 0x4000) 122#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
123#define L1_DATA_B_LENGTH (0x4000 - 0x4000) 123#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
124#define BLKFIN_DCACHESIZE (32*1024) 124#define BFIN_DCACHESIZE (32*1024)
125#define BLKFIN_DSUPBANKS 2 125#define BFIN_DSUPBANKS 2
126#endif 126#endif
127 127
128#else 128#else
129#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 129#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
130#define L1_DATA_A_LENGTH 0x4000 130#define L1_DATA_A_LENGTH 0x4000
131#define L1_DATA_B_LENGTH 0x4000 131#define L1_DATA_B_LENGTH 0x4000
132#define BLKFIN_DCACHESIZE (0*1024) 132#define BFIN_DCACHESIZE (0*1024)
133#define BLKFIN_DSUPBANKS 0 133#define BFIN_DSUPBANKS 0
134#endif /*CONFIG_BLKFIN_DCACHE*/ 134#endif /*CONFIG_BFIN_DCACHE*/
135#endif 135#endif
136 136
137/* Memory Map for ADSP-BF531 processors */ 137/* Memory Map for ADSP-BF531 processors */
@@ -144,16 +144,16 @@
144#define L1_DATA_B_LENGTH 0x0000 144#define L1_DATA_B_LENGTH 0x0000
145 145
146 146
147#ifdef CONFIG_BLKFIN_DCACHE 147#ifdef CONFIG_BFIN_DCACHE
148#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 148#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
149#define L1_DATA_A_LENGTH (0x4000 - 0x4000) 149#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
150#define BLKFIN_DCACHESIZE (16*1024) 150#define BFIN_DCACHESIZE (16*1024)
151#define BLKFIN_DSUPBANKS 1 151#define BFIN_DSUPBANKS 1
152#else 152#else
153#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 153#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
154#define L1_DATA_A_LENGTH 0x4000 154#define L1_DATA_A_LENGTH 0x4000
155#define BLKFIN_DCACHESIZE (0*1024) 155#define BFIN_DCACHESIZE (0*1024)
156#define BLKFIN_DSUPBANKS 0 156#define BFIN_DSUPBANKS 0
157#endif 157#endif
158 158
159#endif 159#endif
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 3803f156bf1c..e377064b307c 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -133,6 +133,7 @@
133 133
134/* Anomalies that don't exist on this proc */ 134/* Anomalies that don't exist on this proc */
135#define ANOMALY_05000125 (0) 135#define ANOMALY_05000125 (0)
136#define ANOMALY_05000158 (0)
136#define ANOMALY_05000183 (0) 137#define ANOMALY_05000183 (0)
137#define ANOMALY_05000198 (0) 138#define ANOMALY_05000198 (0)
138#define ANOMALY_05000266 (0) 139#define ANOMALY_05000266 (0)
diff --git a/include/asm-blackfin/mach-bf537/bf537.h b/include/asm-blackfin/mach-bf537/bf537.h
index 603823f51ca0..cfe2a221112e 100644
--- a/include/asm-blackfin/mach-bf537/bf537.h
+++ b/include/asm-blackfin/mach-bf537/bf537.h
@@ -62,12 +62,12 @@
62/***************************/ 62/***************************/
63 63
64 64
65#define BLKFIN_DSUBBANKS 4 65#define BFIN_DSUBBANKS 4
66#define BLKFIN_DWAYS 2 66#define BFIN_DWAYS 2
67#define BLKFIN_DLINES 64 67#define BFIN_DLINES 64
68#define BLKFIN_ISUBBANKS 4 68#define BFIN_ISUBBANKS 4
69#define BLKFIN_IWAYS 4 69#define BFIN_IWAYS 4
70#define BLKFIN_ILINES 32 70#define BFIN_ILINES 32
71 71
72#define WAY0_L 0x1 72#define WAY0_L 0x1
73#define WAY1_L 0x2 73#define WAY1_L 0x2
@@ -138,59 +138,4 @@
138#define CPUID 0x0 138#define CPUID 0x0
139#endif 139#endif
140 140
141#if (CONFIG_MEM_SIZE % 4)
142#error "SDRAM mem size must be multible of 4MB"
143#endif
144
145#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
146#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
147#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
148#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
149
150/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
151
152#define ANOMALY_05000158_WORKAROUND 0x200
153#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
154#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
155 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
156#else /*Write Through */
157#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
158 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
159#endif
160
161
162#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
163#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
164#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
165#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
166
167#define SIZE_1K 0x00000400 /* 1K */
168#define SIZE_4K 0x00001000 /* 4K */
169#define SIZE_1M 0x00100000 /* 1M */
170#define SIZE_4M 0x00400000 /* 4M */
171
172#define MAX_CPLBS (16 * 2)
173
174/*
175* Number of required data CPLB switchtable entries
176* MEMSIZE / 4 (we mostly install 4M page size CPLBs
177* approx 16 for smaller 1MB page size CPLBs for allignment purposes
178* 1 for L1 Data Memory
179* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
180* 1 for ASYNC Memory
181*/
182
183
184#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
185
186/*
187* Number of required instruction CPLB switchtable entries
188* MEMSIZE / 4 (we mostly install 4M page size CPLBs
189* approx 12 for smaller 1MB page size CPLBs for allignment purposes
190* 1 for L1 Instruction Memory
191* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
192*/
193
194#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
195
196#endif /* __MACH_BF537_H__ */ 141#endif /* __MACH_BF537_H__ */
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h
index 2a808c1202bf..18759e38eaae 100644
--- a/include/asm-blackfin/mach-bf537/mem_map.h
+++ b/include/asm-blackfin/mach-bf537/mem_map.h
@@ -52,10 +52,10 @@
52 52
53/* Memory Map for ADSP-BF537 processors */ 53/* Memory Map for ADSP-BF537 processors */
54 54
55#ifdef CONFIG_BLKFIN_CACHE 55#ifdef CONFIG_BFIN_ICACHE
56#define BLKFIN_ICACHESIZE (16*1024) 56#define BFIN_ICACHESIZE (16*1024)
57#else 57#else
58#define BLKFIN_ICACHESIZE (0*1024) 58#define BFIN_ICACHESIZE (0*1024)
59#endif 59#endif
60 60
61 61
@@ -66,29 +66,29 @@
66 66
67#define L1_CODE_LENGTH 0xC000 67#define L1_CODE_LENGTH 0xC000
68 68
69#ifdef CONFIG_BLKFIN_DCACHE 69#ifdef CONFIG_BFIN_DCACHE
70 70
71#ifdef CONFIG_BLKFIN_DCACHE_BANKA 71#ifdef CONFIG_BFIN_DCACHE_BANKA
72#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 72#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
73#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 73#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
74#define L1_DATA_B_LENGTH 0x8000 74#define L1_DATA_B_LENGTH 0x8000
75#define BLKFIN_DCACHESIZE (16*1024) 75#define BFIN_DCACHESIZE (16*1024)
76#define BLKFIN_DSUPBANKS 1 76#define BFIN_DSUPBANKS 1
77#else 77#else
78#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 78#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
79#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 79#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
80#define L1_DATA_B_LENGTH (0x8000 - 0x4000) 80#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
81#define BLKFIN_DCACHESIZE (32*1024) 81#define BFIN_DCACHESIZE (32*1024)
82#define BLKFIN_DSUPBANKS 2 82#define BFIN_DSUPBANKS 2
83#endif 83#endif
84 84
85#else 85#else
86#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 86#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
87#define L1_DATA_A_LENGTH 0x8000 87#define L1_DATA_A_LENGTH 0x8000
88#define L1_DATA_B_LENGTH 0x8000 88#define L1_DATA_B_LENGTH 0x8000
89#define BLKFIN_DCACHESIZE (0*1024) 89#define BFIN_DCACHESIZE (0*1024)
90#define BLKFIN_DSUPBANKS 0 90#define BFIN_DSUPBANKS 0
91#endif /*CONFIG_BLKFIN_DCACHE*/ 91#endif /*CONFIG_BFIN_DCACHE*/
92 92
93#endif /*CONFIG_BF537*/ 93#endif /*CONFIG_BF537*/
94 94
@@ -102,30 +102,30 @@
102#define L1_CODE_LENGTH 0xC000 102#define L1_CODE_LENGTH 0xC000
103 103
104 104
105#ifdef CONFIG_BLKFIN_DCACHE 105#ifdef CONFIG_BFIN_DCACHE
106 106
107#ifdef CONFIG_BLKFIN_DCACHE_BANKA 107#ifdef CONFIG_BFIN_DCACHE_BANKA
108#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 108#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
109#define L1_DATA_A_LENGTH (0x4000 - 0x4000) 109#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
110#define L1_DATA_B_LENGTH 0x4000 110#define L1_DATA_B_LENGTH 0x4000
111#define BLKFIN_DCACHESIZE (16*1024) 111#define BFIN_DCACHESIZE (16*1024)
112#define BLKFIN_DSUPBANKS 1 112#define BFIN_DSUPBANKS 1
113 113
114#else 114#else
115#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 115#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
116#define L1_DATA_A_LENGTH (0x4000 - 0x4000) 116#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
117#define L1_DATA_B_LENGTH (0x4000 - 0x4000) 117#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
118#define BLKFIN_DCACHESIZE (32*1024) 118#define BFIN_DCACHESIZE (32*1024)
119#define BLKFIN_DSUPBANKS 2 119#define BFIN_DSUPBANKS 2
120#endif 120#endif
121 121
122#else 122#else
123#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 123#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
124#define L1_DATA_A_LENGTH 0x4000 124#define L1_DATA_A_LENGTH 0x4000
125#define L1_DATA_B_LENGTH 0x4000 125#define L1_DATA_B_LENGTH 0x4000
126#define BLKFIN_DCACHESIZE (0*1024) 126#define BFIN_DCACHESIZE (0*1024)
127#define BLKFIN_DSUPBANKS 0 127#define BFIN_DSUPBANKS 0
128#endif /*CONFIG_BLKFIN_DCACHE*/ 128#endif /*CONFIG_BFIN_DCACHE*/
129 129
130#endif 130#endif
131 131
@@ -138,30 +138,30 @@
138 138
139#define L1_CODE_LENGTH 0xC000 139#define L1_CODE_LENGTH 0xC000
140 140
141#ifdef CONFIG_BLKFIN_DCACHE 141#ifdef CONFIG_BFIN_DCACHE
142 142
143#ifdef CONFIG_BLKFIN_DCACHE_BANKA 143#ifdef CONFIG_BFIN_DCACHE_BANKA
144#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 144#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
145#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 145#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
146#define L1_DATA_B_LENGTH 0x8000 146#define L1_DATA_B_LENGTH 0x8000
147#define BLKFIN_DCACHESIZE (16*1024) 147#define BFIN_DCACHESIZE (16*1024)
148#define BLKFIN_DSUPBANKS 1 148#define BFIN_DSUPBANKS 1
149 149
150#else 150#else
151#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 151#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
152#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 152#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
153#define L1_DATA_B_LENGTH (0x8000 - 0x4000) 153#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
154#define BLKFIN_DCACHESIZE (32*1024) 154#define BFIN_DCACHESIZE (32*1024)
155#define BLKFIN_DSUPBANKS 2 155#define BFIN_DSUPBANKS 2
156#endif 156#endif
157 157
158#else 158#else
159#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 159#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
160#define L1_DATA_A_LENGTH 0x8000 160#define L1_DATA_A_LENGTH 0x8000
161#define L1_DATA_B_LENGTH 0x8000 161#define L1_DATA_B_LENGTH 0x8000
162#define BLKFIN_DCACHESIZE (0*1024) 162#define BFIN_DCACHESIZE (0*1024)
163#define BLKFIN_DSUPBANKS 0 163#define BFIN_DSUPBANKS 0
164#endif /*CONFIG_BLKFIN_DCACHE*/ 164#endif /*CONFIG_BFIN_DCACHE*/
165 165
166#endif 166#endif
167 167
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h
index 50306a846628..7e6d349beb08 100644
--- a/include/asm-blackfin/mach-bf548/bf548.h
+++ b/include/asm-blackfin/mach-bf548/bf548.h
@@ -52,12 +52,12 @@
52/***************************/ 52/***************************/
53 53
54 54
55#define BLKFIN_DSUBBANKS 4 55#define BFIN_DSUBBANKS 4
56#define BLKFIN_DWAYS 2 56#define BFIN_DWAYS 2
57#define BLKFIN_DLINES 64 57#define BFIN_DLINES 64
58#define BLKFIN_ISUBBANKS 4 58#define BFIN_ISUBBANKS 4
59#define BLKFIN_IWAYS 4 59#define BFIN_IWAYS 4
60#define BLKFIN_ILINES 32 60#define BFIN_ILINES 32
61 61
62#define WAY0_L 0x1 62#define WAY0_L 0x1
63#define WAY1_L 0x2 63#define WAY1_L 0x2
@@ -126,59 +126,4 @@
126#define CPUID 0x0 126#define CPUID 0x0
127#endif 127#endif
128 128
129#if (CONFIG_MEM_SIZE % 4)
130#error "SDRAM mem size must be multible of 4MB"
131#endif
132
133#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
134#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
135#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
136#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
137
138/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
139
140#define ANOMALY_05000158_WORKAROUND 0x200
141#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
142#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
143 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
144#else /*Write Through */
145#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
146 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
147#endif
148
149
150#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
151#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
152#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
153#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
154
155#define SIZE_1K 0x00000400 /* 1K */
156#define SIZE_4K 0x00001000 /* 4K */
157#define SIZE_1M 0x00100000 /* 1M */
158#define SIZE_4M 0x00400000 /* 4M */
159
160#define MAX_CPLBS (16 * 2)
161
162/*
163* Number of required data CPLB switchtable entries
164* MEMSIZE / 4 (we mostly install 4M page size CPLBs
165* approx 16 for smaller 1MB page size CPLBs for allignment purposes
166* 1 for L1 Data Memory
167* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
168* 1 for ASYNC Memory
169*/
170
171
172#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
173
174/*
175* Number of required instruction CPLB switchtable entries
176* MEMSIZE / 4 (we mostly install 4M page size CPLBs
177* approx 12 for smaller 1MB page size CPLBs for allignment purposes
178* 1 for L1 Instruction Memory
179* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
180*/
181
182#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
183
184#endif /* __MACH_BF48_H__ */ 129#endif /* __MACH_BF48_H__ */
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h
index 72d80e8a6e81..ec1597e31831 100644
--- a/include/asm-blackfin/mach-bf548/mem_map.h
+++ b/include/asm-blackfin/mach-bf548/mem_map.h
@@ -51,10 +51,10 @@
51/* Level 1 Memory */ 51/* Level 1 Memory */
52 52
53/* Memory Map for ADSP-BF548 processors */ 53/* Memory Map for ADSP-BF548 processors */
54#ifdef CONFIG_BLKFIN_ICACHE 54#ifdef CONFIG_BFIN_ICACHE
55#define BLKFIN_ICACHESIZE (16*1024) 55#define BFIN_ICACHESIZE (16*1024)
56#else 56#else
57#define BLKFIN_ICACHESIZE (0*1024) 57#define BFIN_ICACHESIZE (0*1024)
58#endif 58#endif
59 59
60#define L1_CODE_START 0xFFA00000 60#define L1_CODE_START 0xFFA00000
@@ -63,29 +63,29 @@
63 63
64#define L1_CODE_LENGTH 0xC000 64#define L1_CODE_LENGTH 0xC000
65 65
66#ifdef CONFIG_BLKFIN_DCACHE 66#ifdef CONFIG_BFIN_DCACHE
67 67
68#ifdef CONFIG_BLKFIN_DCACHE_BANKA 68#ifdef CONFIG_BFIN_DCACHE_BANKA
69#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 69#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
70#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 70#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
71#define L1_DATA_B_LENGTH 0x8000 71#define L1_DATA_B_LENGTH 0x8000
72#define BLKFIN_DCACHESIZE (16*1024) 72#define BFIN_DCACHESIZE (16*1024)
73#define BLKFIN_DSUPBANKS 1 73#define BFIN_DSUPBANKS 1
74#else 74#else
75#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 75#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
76#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 76#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
77#define L1_DATA_B_LENGTH (0x8000 - 0x4000) 77#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
78#define BLKFIN_DCACHESIZE (32*1024) 78#define BFIN_DCACHESIZE (32*1024)
79#define BLKFIN_DSUPBANKS 2 79#define BFIN_DSUPBANKS 2
80#endif 80#endif
81 81
82#else 82#else
83#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 83#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
84#define L1_DATA_A_LENGTH 0x8000 84#define L1_DATA_A_LENGTH 0x8000
85#define L1_DATA_B_LENGTH 0x8000 85#define L1_DATA_B_LENGTH 0x8000
86#define BLKFIN_DCACHESIZE (0*1024) 86#define BFIN_DCACHESIZE (0*1024)
87#define BLKFIN_DSUPBANKS 0 87#define BFIN_DSUPBANKS 0
88#endif /*CONFIG_BLKFIN_DCACHE*/ 88#endif /*CONFIG_BFIN_DCACHE*/
89 89
90/* Scratch Pad Memory */ 90/* Scratch Pad Memory */
91 91
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
index 53b650f31342..17e1d5dcef02 100644
--- a/include/asm-blackfin/mach-bf561/bf561.h
+++ b/include/asm-blackfin/mach-bf561/bf561.h
@@ -73,13 +73,13 @@
73 */ 73 */
74 74
75 75
76#define BLKFIN_ISUBBANKS 4 76#define BFIN_ISUBBANKS 4
77#define BLKFIN_IWAYS 4 77#define BFIN_IWAYS 4
78#define BLKFIN_ILINES 32 78#define BFIN_ILINES 32
79 79
80#define BLKFIN_DSUBBANKS 4 80#define BFIN_DSUBBANKS 4
81#define BLKFIN_DWAYS 2 81#define BFIN_DWAYS 2
82#define BLKFIN_DLINES 64 82#define BFIN_DLINES 64
83 83
84#define WAY0_L 0x1 84#define WAY0_L 0x1
85#define WAY1_L 0x2 85#define WAY1_L 0x2
@@ -239,83 +239,4 @@
239#define CPUID 0x0 239#define CPUID 0x0
240#endif 240#endif
241 241
242#if (CONFIG_MEM_SIZE % 4)
243#error "SDRAM memory size must be a multiple of 4MB!"
244#endif
245#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
246#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
247#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
248#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
249
250/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
251
252#define ANOMALY_05000158_WORKAROUND 0x200
253#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
254#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
255 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
256#else /*Write Through */
257#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \
258 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
259#endif
260
261
262#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
263#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
264#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
265#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
266
267#define L2_MEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
268
269#define SIZE_1K 0x00000400 /* 1K */
270#define SIZE_4K 0x00001000 /* 4K */
271#define SIZE_1M 0x00100000 /* 1M */
272#define SIZE_4M 0x00400000 /* 4M */
273
274#define MAX_CPLBS (16 * 2)
275
276/*
277* Number of required data CPLB switchtable entries
278* MEMSIZE / 4 (we mostly install 4M page size CPLBs
279* approx 16 for smaller 1MB page size CPLBs for allignment purposes
280* 1 for L1 Data Memory
281* 1 for L2 Data Memory
282* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
283* 64 for ASYNC Memory
284*/
285
286
287#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 + 64) * 2)
288
289/*
290* Number of required instruction CPLB switchtable entries
291* MEMSIZE / 4 (we mostly install 4M page size CPLBs
292* approx 12 for smaller 1MB page size CPLBs for allignment purposes
293* 1 for L1 Instruction Memory
294* 1 for L2 Instruction Memory
295* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
296*/
297
298#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
299
300#if 0 /* comment by mhfan */
301/* Event Vector Table Address */
302#define EVT_EMULATION_ADDR 0xffe02000
303#define EVT_RESET_ADDR 0xffe02004
304#define EVT_NMI_ADDR 0xffe02008
305#define EVT_EXCEPTION_ADDR 0xffe0200c
306#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
307#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
308#define EVT_TIMER_ADDR 0xffe02018
309#define EVT_IVG7_ADDR 0xffe0201c
310#define EVT_IVG8_ADDR 0xffe02020
311#define EVT_IVG9_ADDR 0xffe02024
312#define EVT_IVG10_ADDR 0xffe02028
313#define EVT_IVG11_ADDR 0xffe0202c
314#define EVT_IVG12_ADDR 0xffe02030
315#define EVT_IVG13_ADDR 0xffe02034
316#define EVT_IVG14_ADDR 0xffe02038
317#define EVT_IVG15_ADDR 0xffe0203c
318#define EVT_OVERRIDE_ADDR 0xffe02100
319#endif /* comment by mhfan */
320
321#endif /* __MACH_BF561_H__ */ 242#endif /* __MACH_BF561_H__ */
diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h
index ebac9a8d838d..f7ac09cf2c3d 100644
--- a/include/asm-blackfin/mach-bf561/mem_map.h
+++ b/include/asm-blackfin/mach-bf561/mem_map.h
@@ -21,10 +21,10 @@
21 21
22/* Level 1 Memory */ 22/* Level 1 Memory */
23 23
24#ifdef CONFIG_BLKFIN_CACHE 24#ifdef CONFIG_BFIN_ICACHE
25#define BLKFIN_ICACHESIZE (16*1024) 25#define BFIN_ICACHESIZE (16*1024)
26#else 26#else
27#define BLKFIN_ICACHESIZE (0*1024) 27#define BFIN_ICACHESIZE (0*1024)
28#endif 28#endif
29 29
30/* Memory Map for ADSP-BF561 processors */ 30/* Memory Map for ADSP-BF561 processors */
@@ -36,29 +36,29 @@
36 36
37#define L1_CODE_LENGTH 0x4000 37#define L1_CODE_LENGTH 0x4000
38 38
39#ifdef CONFIG_BLKFIN_DCACHE 39#ifdef CONFIG_BFIN_DCACHE
40 40
41#ifdef CONFIG_BLKFIN_DCACHE_BANKA 41#ifdef CONFIG_BFIN_DCACHE_BANKA
42#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 42#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
43#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 43#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
44#define L1_DATA_B_LENGTH 0x8000 44#define L1_DATA_B_LENGTH 0x8000
45#define BLKFIN_DCACHESIZE (16*1024) 45#define BFIN_DCACHESIZE (16*1024)
46#define BLKFIN_DSUPBANKS 1 46#define BFIN_DSUPBANKS 1
47#else 47#else
48#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 48#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
49#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 49#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
50#define L1_DATA_B_LENGTH (0x8000 - 0x4000) 50#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
51#define BLKFIN_DCACHESIZE (32*1024) 51#define BFIN_DCACHESIZE (32*1024)
52#define BLKFIN_DSUPBANKS 2 52#define BFIN_DSUPBANKS 2
53#endif 53#endif
54 54
55#else 55#else
56#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 56#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
57#define L1_DATA_A_LENGTH 0x8000 57#define L1_DATA_A_LENGTH 0x8000
58#define L1_DATA_B_LENGTH 0x8000 58#define L1_DATA_B_LENGTH 0x8000
59#define BLKFIN_DCACHESIZE (0*1024) 59#define BFIN_DCACHESIZE (0*1024)
60#define BLKFIN_DSUPBANKS 0 60#define BFIN_DSUPBANKS 0
61#endif /*CONFIG_BLKFIN_DCACHE*/ 61#endif /*CONFIG_BFIN_DCACHE*/
62#endif 62#endif
63 63
64/* Level 2 Memory */ 64/* Level 2 Memory */
diff --git a/include/asm-blackfin/mach-common/clocks.h b/include/asm-blackfin/mach-common/clocks.h
index 5e8113ee8939..033bba92d61c 100644
--- a/include/asm-blackfin/mach-common/clocks.h
+++ b/include/asm-blackfin/mach-common/clocks.h
@@ -27,7 +27,8 @@
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */ 28 */
29 29
30 30#ifndef _BFIN_CLOCKS_H
31#define _BFIN_CLOCKS_H
31 32
32#ifdef CONFIG_CCLK_DIV_1 33#ifdef CONFIG_CCLK_DIV_1
33# define CONFIG_CCLK_ACT_DIV CCLK_DIV1 34# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
@@ -66,3 +67,4 @@
66# define CONFIG_VCO_MULT 0 67# define CONFIG_VCO_MULT 0
67#endif 68#endif
68 69
70#endif
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
index 260515d15280..c1d8c4a78fcf 100644
--- a/include/asm-blackfin/mach-common/def_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h
@@ -639,6 +639,7 @@
639#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access 639#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
640 * allowed (user mode) 640 * allowed (user mode)
641 */ 641 */
642
642#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ 643#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
643#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ 644#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
644#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ 645#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
@@ -671,6 +672,8 @@
671 */ 672 */
672#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ 673#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
673 674
675#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
676
674/* TBUFCTL Masks */ 677/* TBUFCTL Masks */
675#define TBUFPWR 0x0001 678#define TBUFPWR 0x0001
676#define TBUFEN 0x0002 679#define TBUFEN 0x0002
diff --git a/include/asm-blackfin/pgtable.h b/include/asm-blackfin/pgtable.h
index 5a8f9e431c40..b11b114689c0 100644
--- a/include/asm-blackfin/pgtable.h
+++ b/include/asm-blackfin/pgtable.h
@@ -4,7 +4,7 @@
4#include <asm-generic/4level-fixup.h> 4#include <asm-generic/4level-fixup.h>
5 5
6#include <asm/page.h> 6#include <asm/page.h>
7#include <asm/cplb.h> 7#include <asm/mach-common/def_LPBlackfin.h>
8 8
9typedef pte_t *pte_addr_t; 9typedef pte_t *pte_addr_t;
10/* 10/*
diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h
index b03cf7d5b9a3..2b3d47d0bbb6 100644
--- a/include/asm-blackfin/system.h
+++ b/include/asm-blackfin/system.h
@@ -60,7 +60,7 @@ extern unsigned long irq_flags;
60 ); \ 60 ); \
61 } while (0) 61 } while (0)
62 62
63#if ANOMALY_05000244 && defined(CONFIG_BLKFIN_CACHE) 63#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
64# define NOP_PAD_ANOMALY_05000244 "nop; nop;" 64# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
65#else 65#else
66# define NOP_PAD_ANOMALY_05000244 66# define NOP_PAD_ANOMALY_05000244
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 19:20:11 -0500