diff options
| author | Dave Kleikamp <shaggy@linux.vnet.ibm.com> | 2008-07-07 10:28:53 -0400 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2008-07-09 02:30:45 -0400 |
| commit | 379070491e1e744a59e69e5bcf3765012d15ecb4 (patch) | |
| tree | 32524cdac93dce578438d14529f2a5c7caca5092 /include | |
| parent | aba46c5027cb59d98052231b36efcbbde9c77a1d (diff) | |
powerpc/mm: Add SAO Feature bit to the cputable
Add the CPU feature bit for the new Strong Access Ordering
facility of Power7
Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
Signed-off-by: Joel Schopp <jschopp@austin.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-powerpc/cputable.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 3171ac904b91..4fd76898975b 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h | |||
| @@ -186,6 +186,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, | |||
| 186 | #define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000) | 186 | #define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000) |
| 187 | #define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000) | 187 | #define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000) |
| 188 | #define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000) | 188 | #define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000) |
| 189 | #define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000) | ||
| 189 | 190 | ||
| 190 | #ifndef __ASSEMBLY__ | 191 | #ifndef __ASSEMBLY__ |
| 191 | 192 | ||
| @@ -401,7 +402,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, | |||
| 401 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 402 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
| 402 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | 403 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ |
| 403 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ | 404 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ |
| 404 | CPU_FTR_DSCR) | 405 | CPU_FTR_DSCR | CPU_FTR_SAO) |
| 405 | #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 406 | #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
| 406 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 407 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 407 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 408 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |