diff options
| author | Enrico Scholz <enrico.scholz@de.rmk.(none)> | 2006-11-03 07:47:39 -0500 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-11-03 14:52:52 -0500 |
| commit | 1f4a39319e9226c3b1d5b91a1e4d3559ef8740e4 (patch) | |
| tree | 7b5397114bbd7e8c3d592d876525b0667fcf162c /include | |
| parent | 984d115bbf2d731ed2264031fe49c1378d730db0 (diff) | |
[ARM] 3919/1: Fixed definition of some PXA270 CIF related registers
Fixed definition of some CIF registers; see PXA27x Developer\'s Manual.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-pxa/pxa-regs.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 68731e0923a4..cff752f35230 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h | |||
| @@ -2242,7 +2242,7 @@ | |||
| 2242 | 2242 | ||
| 2243 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | 2243 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ |
| 2244 | #define CICR1_RGBT_CONV (0x3 << 30) /* RGBT conversion mask */ | 2244 | #define CICR1_RGBT_CONV (0x3 << 30) /* RGBT conversion mask */ |
| 2245 | #define CICR1_PPL (0x3f << 15) /* Pixels per line mask */ | 2245 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ |
| 2246 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | 2246 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ |
| 2247 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | 2247 | #define CICR1_RGB_F (1 << 11) /* RGB format */ |
| 2248 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | 2248 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ |
| @@ -2268,7 +2268,7 @@ | |||
| 2268 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | 2268 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ |
| 2269 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | 2269 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock |
| 2270 | wait count mask */ | 2270 | wait count mask */ |
| 2271 | #define CICR3_LPF (0x3ff << 0) /* Lines per frame mask */ | 2271 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ |
| 2272 | 2272 | ||
| 2273 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | 2273 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ |
| 2274 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | 2274 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ |
| @@ -2289,8 +2289,8 @@ | |||
| 2289 | #define CISR_EOL (1 << 8) /* End of line */ | 2289 | #define CISR_EOL (1 << 8) /* End of line */ |
| 2290 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | 2290 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ |
| 2291 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | 2291 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ |
| 2292 | #define CISR_SOF (1 << 5) /* Start of frame */ | 2292 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ |
| 2293 | #define CISR_CDD (1 << 4) /* Camera interface disable done */ | 2293 | #define CISR_SOF (1 << 4) /* Start of frame */ |
| 2294 | #define CISR_EOF (1 << 3) /* End of frame */ | 2294 | #define CISR_EOF (1 << 3) /* End of frame */ |
| 2295 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | 2295 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ |
| 2296 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | 2296 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ |