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authorHao Wu <hao.wu@intel.com>2009-06-04 04:06:50 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2009-06-16 00:44:47 -0400
commit453f77558810ffa669ed5a510a7173ec49def396 (patch)
tree48b76bea4dc9bc0fadaa751be8349b4eb1678f5e /include
parent5be19a9daa2df2507adf5b4676a7db8d131cf56e (diff)
USB: Add Intel Langwell USB OTG Transceiver Drive
Description: This driver is used for Intel Langwell* USB OTG controller in Intel Moorestown* platform. It tries to implement host/device role switch according to OTG spec. The actual hsot and device functions are accomplished in modified EHCI driver and Intel Langwell USB OTG client controller driver. * Langwell and Moorestown are names used in development. They are not approved official name. Note: This patch is the first version Intel Langwell USB OTG Transceiver driver. The development is not finished, and the bug fixing is on going for some hardware and software issues. The main purpose of this submission is for code view. Supported features: - Data-line Pulsing SRP - Support HNP to switch roles - PCI D0/D3 power management support Known issues: - HNP is only tested with another Moorestown platform. - PCI D0/D3 power management support is not fully tested. - VBus Pulsing SRP is not support in current version. Signed-off-by: Hao Wu <hao.wu@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'include')
-rw-r--r--include/linux/usb/langwell_otg.h177
1 files changed, 177 insertions, 0 deletions
diff --git a/include/linux/usb/langwell_otg.h b/include/linux/usb/langwell_otg.h
new file mode 100644
index 000000000000..e115ae6df1da
--- /dev/null
+++ b/include/linux/usb/langwell_otg.h
@@ -0,0 +1,177 @@
1/*
2 * Intel Langwell USB OTG transceiver driver
3 * Copyright (C) 2008, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20#ifndef __LANGWELL_OTG_H__
21#define __LANGWELL_OTG_H__
22
23/* notify transceiver driver about OTG events */
24extern void langwell_update_transceiver(void);
25/* HCD register bus driver */
26extern int langwell_register_host(struct pci_driver *host_driver);
27/* HCD unregister bus driver */
28extern void langwell_unregister_host(struct pci_driver *host_driver);
29/* DCD register bus driver */
30extern int langwell_register_peripheral(struct pci_driver *client_driver);
31/* DCD unregister bus driver */
32extern void langwell_unregister_peripheral(struct pci_driver *client_driver);
33/* No silent failure, output warning message */
34extern void langwell_otg_nsf_msg(unsigned long message);
35
36#define CI_USBCMD 0x30
37# define USBCMD_RST BIT(1)
38# define USBCMD_RS BIT(0)
39#define CI_USBSTS 0x34
40# define USBSTS_SLI BIT(8)
41# define USBSTS_URI BIT(6)
42# define USBSTS_PCI BIT(2)
43#define CI_PORTSC1 0x74
44# define PORTSC_PP BIT(12)
45# define PORTSC_LS (BIT(11) | BIT(10))
46# define PORTSC_SUSP BIT(7)
47# define PORTSC_CCS BIT(0)
48#define CI_HOSTPC1 0xb4
49# define HOSTPC1_PHCD BIT(22)
50#define CI_OTGSC 0xf4
51# define OTGSC_DPIE BIT(30)
52# define OTGSC_1MSE BIT(29)
53# define OTGSC_BSEIE BIT(28)
54# define OTGSC_BSVIE BIT(27)
55# define OTGSC_ASVIE BIT(26)
56# define OTGSC_AVVIE BIT(25)
57# define OTGSC_IDIE BIT(24)
58# define OTGSC_DPIS BIT(22)
59# define OTGSC_1MSS BIT(21)
60# define OTGSC_BSEIS BIT(20)
61# define OTGSC_BSVIS BIT(19)
62# define OTGSC_ASVIS BIT(18)
63# define OTGSC_AVVIS BIT(17)
64# define OTGSC_IDIS BIT(16)
65# define OTGSC_DPS BIT(14)
66# define OTGSC_1MST BIT(13)
67# define OTGSC_BSE BIT(12)
68# define OTGSC_BSV BIT(11)
69# define OTGSC_ASV BIT(10)
70# define OTGSC_AVV BIT(9)
71# define OTGSC_ID BIT(8)
72# define OTGSC_HABA BIT(7)
73# define OTGSC_HADP BIT(6)
74# define OTGSC_IDPU BIT(5)
75# define OTGSC_DP BIT(4)
76# define OTGSC_OT BIT(3)
77# define OTGSC_HAAR BIT(2)
78# define OTGSC_VC BIT(1)
79# define OTGSC_VD BIT(0)
80# define OTGSC_INTEN_MASK (0x7f << 24)
81# define OTGSC_INTSTS_MASK (0x7f << 16)
82#define CI_USBMODE 0xf8
83# define USBMODE_CM (BIT(1) | BIT(0))
84# define USBMODE_IDLE 0
85# define USBMODE_DEVICE 0x2
86# define USBMODE_HOST 0x3
87
88#define INTR_DUMMY_MASK (USBSTS_SLI | USBSTS_URI | USBSTS_PCI)
89
90struct otg_hsm {
91 /* Input */
92 int a_bus_resume;
93 int a_bus_suspend;
94 int a_conn;
95 int a_sess_vld;
96 int a_srp_det;
97 int a_vbus_vld;
98 int b_bus_resume;
99 int b_bus_suspend;
100 int b_conn;
101 int b_se0_srp;
102 int b_sess_end;
103 int b_sess_vld;
104 int id;
105
106 /* Internal variables */
107 int a_set_b_hnp_en;
108 int b_srp_done;
109 int b_hnp_enable;
110
111 /* Timeout indicator for timers */
112 int a_wait_vrise_tmout;
113 int a_wait_bcon_tmout;
114 int a_aidl_bdis_tmout;
115 int b_ase0_brst_tmout;
116 int b_bus_suspend_tmout;
117 int b_srp_res_tmout;
118
119 /* Informative variables */
120 int a_bus_drop;
121 int a_bus_req;
122 int a_clr_err;
123 int a_suspend_req;
124 int b_bus_req;
125
126 /* Output */
127 int drv_vbus;
128 int loc_conn;
129 int loc_sof;
130
131 /* Others */
132 int b_bus_suspend_vld;
133};
134
135#define TA_WAIT_VRISE 100
136#define TA_WAIT_BCON 30000
137#define TA_AIDL_BDIS 15000
138#define TB_ASE0_BRST 5000
139#define TB_SE0_SRP 2
140#define TB_SRP_RES 100
141#define TB_BUS_SUSPEND 500
142
143struct langwell_otg_timer {
144 unsigned long expires; /* Number of count increase to timeout */
145 unsigned long count; /* Tick counter */
146 void (*function)(unsigned long); /* Timeout function */
147 unsigned long data; /* Data passed to function */
148 struct list_head list;
149};
150
151struct langwell_otg {
152 struct otg_transceiver otg;
153 struct otg_hsm hsm;
154 void __iomem *regs;
155 unsigned region;
156 struct pci_driver *host_ops;
157 struct pci_driver *client_ops;
158 struct pci_dev *pdev;
159 struct work_struct work;
160 struct workqueue_struct *qwork;
161 spinlock_t lock;
162 spinlock_t wq_lock;
163};
164
165static inline struct langwell_otg *otg_to_langwell(struct otg_transceiver *otg)
166{
167 return container_of(otg, struct langwell_otg, otg);
168}
169
170#ifdef DEBUG
171#define otg_dbg(fmt, args...) \
172 printk(KERN_DEBUG fmt , ## args)
173#else
174#define otg_dbg(fmt, args...) \
175 do { } while (0)
176#endif /* DEBUG */
177#endif /* __LANGWELL_OTG_H__ */
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