diff options
author | Paul Mackerras <paulus@samba.org> | 2006-02-10 00:51:29 -0500 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2006-02-10 00:51:29 -0500 |
commit | d6d93856cb90eeb07062ad938bd26f554bf1b9b9 (patch) | |
tree | eeec5011a42f38d3dfe7b61788b7ac1cc890edeb /include | |
parent | 8f75015f33c3005e0bbf83ffc0d5e0b4262cc03d (diff) | |
parent | ad71f123a9e9b809f6c829db1222ce0423a1153c (diff) |
Merge ../powerpc-merge
Diffstat (limited to 'include')
58 files changed, 542 insertions, 642 deletions
diff --git a/include/asm-alpha/system.h b/include/asm-alpha/system.h index cc9c7e8cced5..f3b7b1a59c56 100644 --- a/include/asm-alpha/system.h +++ b/include/asm-alpha/system.h | |||
@@ -572,7 +572,7 @@ __cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new) | |||
572 | if something tries to do an invalid cmpxchg(). */ | 572 | if something tries to do an invalid cmpxchg(). */ |
573 | extern void __cmpxchg_called_with_bad_pointer(void); | 573 | extern void __cmpxchg_called_with_bad_pointer(void); |
574 | 574 | ||
575 | static inline unsigned long | 575 | static __always_inline unsigned long |
576 | __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) | 576 | __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) |
577 | { | 577 | { |
578 | switch (size) { | 578 | switch (size) { |
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h index f5bcc9a1aed6..b726acfcab14 100644 --- a/include/asm-arm/arch-omap/io.h +++ b/include/asm-arm/arch-omap/io.h | |||
@@ -116,7 +116,11 @@ typedef struct { volatile u32 offset[4096]; } __regbase32; | |||
116 | ->offset[((vaddr)&4095)>>2] | 116 | ->offset[((vaddr)&4095)>>2] |
117 | #define __REG32(paddr) __REGV32(io_p2v(paddr)) | 117 | #define __REG32(paddr) __REGV32(io_p2v(paddr)) |
118 | 118 | ||
119 | extern void omap_map_common_io(void); | 119 | extern void omap1_map_common_io(void); |
120 | extern void omap1_init_common_hw(void); | ||
121 | |||
122 | extern void omap2_map_common_io(void); | ||
123 | extern void omap2_init_common_hw(void); | ||
120 | 124 | ||
121 | #else | 125 | #else |
122 | 126 | ||
diff --git a/include/asm-arm/mutex.h b/include/asm-arm/mutex.h index 6caa59f1f595..cb29d84e690d 100644 --- a/include/asm-arm/mutex.h +++ b/include/asm-arm/mutex.h | |||
@@ -23,72 +23,71 @@ | |||
23 | * simply bail out immediately through the slow path where the lock will be | 23 | * simply bail out immediately through the slow path where the lock will be |
24 | * reattempted until it succeeds. | 24 | * reattempted until it succeeds. |
25 | */ | 25 | */ |
26 | #define __mutex_fastpath_lock(count, fail_fn) \ | 26 | static inline void |
27 | do { \ | 27 | __mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) |
28 | int __ex_flag, __res; \ | 28 | { |
29 | \ | 29 | int __ex_flag, __res; |
30 | typecheck(atomic_t *, count); \ | 30 | |
31 | typecheck_fn(fastcall void (*)(atomic_t *), fail_fn); \ | 31 | __asm__ ( |
32 | \ | 32 | |
33 | __asm__ ( \ | 33 | "ldrex %0, [%2] \n\t" |
34 | "ldrex %0, [%2] \n" \ | 34 | "sub %0, %0, #1 \n\t" |
35 | "sub %0, %0, #1 \n" \ | 35 | "strex %1, %0, [%2] " |
36 | "strex %1, %0, [%2] \n" \ | 36 | |
37 | \ | 37 | : "=&r" (__res), "=&r" (__ex_flag) |
38 | : "=&r" (__res), "=&r" (__ex_flag) \ | 38 | : "r" (&(count)->counter) |
39 | : "r" (&(count)->counter) \ | 39 | : "cc","memory" ); |
40 | : "cc","memory" ); \ | 40 | |
41 | \ | 41 | __res |= __ex_flag; |
42 | if (unlikely(__res || __ex_flag)) \ | 42 | if (unlikely(__res != 0)) |
43 | fail_fn(count); \ | 43 | fail_fn(count); |
44 | } while (0) | 44 | } |
45 | 45 | ||
46 | #define __mutex_fastpath_lock_retval(count, fail_fn) \ | 46 | static inline int |
47 | ({ \ | 47 | __mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t *)) |
48 | int __ex_flag, __res; \ | 48 | { |
49 | \ | 49 | int __ex_flag, __res; |
50 | typecheck(atomic_t *, count); \ | 50 | |
51 | typecheck_fn(fastcall int (*)(atomic_t *), fail_fn); \ | 51 | __asm__ ( |
52 | \ | 52 | |
53 | __asm__ ( \ | 53 | "ldrex %0, [%2] \n\t" |
54 | "ldrex %0, [%2] \n" \ | 54 | "sub %0, %0, #1 \n\t" |
55 | "sub %0, %0, #1 \n" \ | 55 | "strex %1, %0, [%2] " |
56 | "strex %1, %0, [%2] \n" \ | 56 | |
57 | \ | 57 | : "=&r" (__res), "=&r" (__ex_flag) |
58 | : "=&r" (__res), "=&r" (__ex_flag) \ | 58 | : "r" (&(count)->counter) |
59 | : "r" (&(count)->counter) \ | 59 | : "cc","memory" ); |
60 | : "cc","memory" ); \ | 60 | |
61 | \ | 61 | __res |= __ex_flag; |
62 | __res |= __ex_flag; \ | 62 | if (unlikely(__res != 0)) |
63 | if (unlikely(__res != 0)) \ | 63 | __res = fail_fn(count); |
64 | __res = fail_fn(count); \ | 64 | return __res; |
65 | __res; \ | 65 | } |
66 | }) | ||
67 | 66 | ||
68 | /* | 67 | /* |
69 | * Same trick is used for the unlock fast path. However the original value, | 68 | * Same trick is used for the unlock fast path. However the original value, |
70 | * rather than the result, is used to test for success in order to have | 69 | * rather than the result, is used to test for success in order to have |
71 | * better generated assembly. | 70 | * better generated assembly. |
72 | */ | 71 | */ |
73 | #define __mutex_fastpath_unlock(count, fail_fn) \ | 72 | static inline void |
74 | do { \ | 73 | __mutex_fastpath_unlock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) |
75 | int __ex_flag, __res, __orig; \ | 74 | { |
76 | \ | 75 | int __ex_flag, __res, __orig; |
77 | typecheck(atomic_t *, count); \ | 76 | |
78 | typecheck_fn(fastcall void (*)(atomic_t *), fail_fn); \ | 77 | __asm__ ( |
79 | \ | 78 | |
80 | __asm__ ( \ | 79 | "ldrex %0, [%3] \n\t" |
81 | "ldrex %0, [%3] \n" \ | 80 | "add %1, %0, #1 \n\t" |
82 | "add %1, %0, #1 \n" \ | 81 | "strex %2, %1, [%3] " |
83 | "strex %2, %1, [%3] \n" \ | 82 | |
84 | \ | 83 | : "=&r" (__orig), "=&r" (__res), "=&r" (__ex_flag) |
85 | : "=&r" (__orig), "=&r" (__res), "=&r" (__ex_flag) \ | 84 | : "r" (&(count)->counter) |
86 | : "r" (&(count)->counter) \ | 85 | : "cc","memory" ); |
87 | : "cc","memory" ); \ | 86 | |
88 | \ | 87 | __orig |= __ex_flag; |
89 | if (unlikely(__orig || __ex_flag)) \ | 88 | if (unlikely(__orig != 0)) |
90 | fail_fn(count); \ | 89 | fail_fn(count); |
91 | } while (0) | 90 | } |
92 | 91 | ||
93 | /* | 92 | /* |
94 | * If the unlock was done on a contended lock, or if the unlock simply fails | 93 | * If the unlock was done on a contended lock, or if the unlock simply fails |
@@ -110,12 +109,12 @@ __mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *)) | |||
110 | 109 | ||
111 | __asm__ ( | 110 | __asm__ ( |
112 | 111 | ||
113 | "1: ldrex %0, [%3] \n" | 112 | "1: ldrex %0, [%3] \n\t" |
114 | "subs %1, %0, #1 \n" | 113 | "subs %1, %0, #1 \n\t" |
115 | "strexeq %2, %1, [%3] \n" | 114 | "strexeq %2, %1, [%3] \n\t" |
116 | "movlt %0, #0 \n" | 115 | "movlt %0, #0 \n\t" |
117 | "cmpeq %2, #0 \n" | 116 | "cmpeq %2, #0 \n\t" |
118 | "bgt 1b \n" | 117 | "bgt 1b " |
119 | 118 | ||
120 | : "=&r" (__orig), "=&r" (__res), "=&r" (__ex_flag) | 119 | : "=&r" (__orig), "=&r" (__res), "=&r" (__ex_flag) |
121 | : "r" (&count->counter) | 120 | : "r" (&count->counter) |
diff --git a/include/asm-i386/unistd.h b/include/asm-i386/unistd.h index 597496ed2aee..cf6f2cd9c514 100644 --- a/include/asm-i386/unistd.h +++ b/include/asm-i386/unistd.h | |||
@@ -315,8 +315,9 @@ | |||
315 | #define __NR_faccessat 307 | 315 | #define __NR_faccessat 307 |
316 | #define __NR_pselect6 308 | 316 | #define __NR_pselect6 308 |
317 | #define __NR_ppoll 309 | 317 | #define __NR_ppoll 309 |
318 | #define __NR_unshare 310 | ||
318 | 319 | ||
319 | #define NR_syscalls 310 | 320 | #define NR_syscalls 311 |
320 | 321 | ||
321 | /* | 322 | /* |
322 | * user-visible error numbers are in the range -1 - -128: see | 323 | * user-visible error numbers are in the range -1 - -128: see |
diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h index 09b99029ac1a..23c8e1be1911 100644 --- a/include/asm-ia64/processor.h +++ b/include/asm-ia64/processor.h | |||
@@ -559,6 +559,23 @@ ia64_eoi (void) | |||
559 | 559 | ||
560 | #define cpu_relax() ia64_hint(ia64_hint_pause) | 560 | #define cpu_relax() ia64_hint(ia64_hint_pause) |
561 | 561 | ||
562 | static inline int | ||
563 | ia64_get_irr(unsigned int vector) | ||
564 | { | ||
565 | unsigned int reg = vector / 64; | ||
566 | unsigned int bit = vector % 64; | ||
567 | u64 irr; | ||
568 | |||
569 | switch (reg) { | ||
570 | case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break; | ||
571 | case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break; | ||
572 | case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break; | ||
573 | case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break; | ||
574 | } | ||
575 | |||
576 | return test_bit(bit, &irr); | ||
577 | } | ||
578 | |||
562 | static inline void | 579 | static inline void |
563 | ia64_set_lrr0 (unsigned long val) | 580 | ia64_set_lrr0 (unsigned long val) |
564 | { | 581 | { |
diff --git a/include/asm-ia64/sal.h b/include/asm-ia64/sal.h index 313cad0628d0..0b210abbe003 100644 --- a/include/asm-ia64/sal.h +++ b/include/asm-ia64/sal.h | |||
@@ -658,15 +658,7 @@ ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second, | |||
658 | return isrv.status; | 658 | return isrv.status; |
659 | } | 659 | } |
660 | 660 | ||
661 | /* Flush all the processor and platform level instruction and/or data caches */ | 661 | extern s64 ia64_sal_cache_flush (u64 cache_type); |
662 | static inline s64 | ||
663 | ia64_sal_cache_flush (u64 cache_type) | ||
664 | { | ||
665 | struct ia64_sal_retval isrv; | ||
666 | SAL_CALL(isrv, SAL_CACHE_FLUSH, cache_type, 0, 0, 0, 0, 0, 0); | ||
667 | return isrv.status; | ||
668 | } | ||
669 | |||
670 | 662 | ||
671 | /* Initialize all the processor and platform level instruction and data caches */ | 663 | /* Initialize all the processor and platform level instruction and data caches */ |
672 | static inline s64 | 664 | static inline s64 |
diff --git a/include/asm-ia64/sn/bte.h b/include/asm-ia64/sn/bte.h index f50da3d91d07..01e5b4103235 100644 --- a/include/asm-ia64/sn/bte.h +++ b/include/asm-ia64/sn/bte.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (c) 2000-2005 Silicon Graphics, Inc. All Rights Reserved. | 6 | * Copyright (c) 2000-2006 Silicon Graphics, Inc. All Rights Reserved. |
7 | */ | 7 | */ |
8 | 8 | ||
9 | 9 | ||
@@ -100,13 +100,28 @@ | |||
100 | #define BTE_LNSTAT_STORE(_bte, _x) \ | 100 | #define BTE_LNSTAT_STORE(_bte, _x) \ |
101 | HUB_S(_bte->bte_base_addr, (_x)) | 101 | HUB_S(_bte->bte_base_addr, (_x)) |
102 | #define BTE_SRC_STORE(_bte, _x) \ | 102 | #define BTE_SRC_STORE(_bte, _x) \ |
103 | HUB_S(_bte->bte_source_addr, (_x)) | 103 | ({ \ |
104 | u64 __addr = ((_x) & ~AS_MASK); \ | ||
105 | if (is_shub2()) \ | ||
106 | __addr = SH2_TIO_PHYS_TO_DMA(__addr); \ | ||
107 | HUB_S(_bte->bte_source_addr, __addr); \ | ||
108 | }) | ||
104 | #define BTE_DEST_STORE(_bte, _x) \ | 109 | #define BTE_DEST_STORE(_bte, _x) \ |
105 | HUB_S(_bte->bte_destination_addr, (_x)) | 110 | ({ \ |
111 | u64 __addr = ((_x) & ~AS_MASK); \ | ||
112 | if (is_shub2()) \ | ||
113 | __addr = SH2_TIO_PHYS_TO_DMA(__addr); \ | ||
114 | HUB_S(_bte->bte_destination_addr, __addr); \ | ||
115 | }) | ||
106 | #define BTE_CTRL_STORE(_bte, _x) \ | 116 | #define BTE_CTRL_STORE(_bte, _x) \ |
107 | HUB_S(_bte->bte_control_addr, (_x)) | 117 | HUB_S(_bte->bte_control_addr, (_x)) |
108 | #define BTE_NOTIF_STORE(_bte, _x) \ | 118 | #define BTE_NOTIF_STORE(_bte, _x) \ |
109 | HUB_S(_bte->bte_notify_addr, (_x)) | 119 | ({ \ |
120 | u64 __addr = ia64_tpa((_x) & ~AS_MASK); \ | ||
121 | if (is_shub2()) \ | ||
122 | __addr = SH2_TIO_PHYS_TO_DMA(__addr); \ | ||
123 | HUB_S(_bte->bte_notify_addr, __addr); \ | ||
124 | }) | ||
110 | 125 | ||
111 | #define BTE_START_TRANSFER(_bte, _len, _mode) \ | 126 | #define BTE_START_TRANSFER(_bte, _len, _mode) \ |
112 | is_shub2() ? BTE_CTRL_STORE(_bte, IBLS_BUSY | (_mode << 24) | _len) \ | 127 | is_shub2() ? BTE_CTRL_STORE(_bte, IBLS_BUSY | (_mode << 24) | _len) \ |
diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h index a3431372c6e7..60a51a406eec 100644 --- a/include/asm-ia64/sn/intr.h +++ b/include/asm-ia64/sn/intr.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. | 6 | * Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved. |
7 | */ | 7 | */ |
8 | 8 | ||
9 | #ifndef _ASM_IA64_SN_INTR_H | 9 | #ifndef _ASM_IA64_SN_INTR_H |
@@ -11,26 +11,26 @@ | |||
11 | 11 | ||
12 | #include <linux/rcupdate.h> | 12 | #include <linux/rcupdate.h> |
13 | 13 | ||
14 | #define SGI_UART_VECTOR (0xe9) | 14 | #define SGI_UART_VECTOR 0xe9 |
15 | 15 | ||
16 | /* Reserved IRQs : Note, not to exceed IA64_SN2_FIRST_DEVICE_VECTOR */ | 16 | /* Reserved IRQs : Note, not to exceed IA64_SN2_FIRST_DEVICE_VECTOR */ |
17 | #define SGI_XPC_ACTIVATE (0x30) | 17 | #define SGI_XPC_ACTIVATE 0x30 |
18 | #define SGI_II_ERROR (0x31) | 18 | #define SGI_II_ERROR 0x31 |
19 | #define SGI_XBOW_ERROR (0x32) | 19 | #define SGI_XBOW_ERROR 0x32 |
20 | #define SGI_PCIASIC_ERROR (0x33) | 20 | #define SGI_PCIASIC_ERROR 0x33 |
21 | #define SGI_ACPI_SCI_INT (0x34) | 21 | #define SGI_ACPI_SCI_INT 0x34 |
22 | #define SGI_TIOCA_ERROR (0x35) | 22 | #define SGI_TIOCA_ERROR 0x35 |
23 | #define SGI_TIO_ERROR (0x36) | 23 | #define SGI_TIO_ERROR 0x36 |
24 | #define SGI_TIOCX_ERROR (0x37) | 24 | #define SGI_TIOCX_ERROR 0x37 |
25 | #define SGI_MMTIMER_VECTOR (0x38) | 25 | #define SGI_MMTIMER_VECTOR 0x38 |
26 | #define SGI_XPC_NOTIFY (0xe7) | 26 | #define SGI_XPC_NOTIFY 0xe7 |
27 | 27 | ||
28 | #define IA64_SN2_FIRST_DEVICE_VECTOR (0x3c) | 28 | #define IA64_SN2_FIRST_DEVICE_VECTOR 0x3c |
29 | #define IA64_SN2_LAST_DEVICE_VECTOR (0xe6) | 29 | #define IA64_SN2_LAST_DEVICE_VECTOR 0xe6 |
30 | 30 | ||
31 | #define SN2_IRQ_RESERVED (0x1) | 31 | #define SN2_IRQ_RESERVED 0x1 |
32 | #define SN2_IRQ_CONNECTED (0x2) | 32 | #define SN2_IRQ_CONNECTED 0x2 |
33 | #define SN2_IRQ_SHARED (0x4) | 33 | #define SN2_IRQ_SHARED 0x4 |
34 | 34 | ||
35 | // The SN PROM irq struct | 35 | // The SN PROM irq struct |
36 | struct sn_irq_info { | 36 | struct sn_irq_info { |
diff --git a/include/asm-ia64/system.h b/include/asm-ia64/system.h index 80c5a234e259..062538715623 100644 --- a/include/asm-ia64/system.h +++ b/include/asm-ia64/system.h | |||
@@ -249,32 +249,7 @@ extern void ia64_load_extra (struct task_struct *task); | |||
249 | # define switch_to(prev,next,last) __switch_to(prev, next, last) | 249 | # define switch_to(prev,next,last) __switch_to(prev, next, last) |
250 | #endif | 250 | #endif |
251 | 251 | ||
252 | /* | ||
253 | * On IA-64, we don't want to hold the runqueue's lock during the low-level context-switch, | ||
254 | * because that could cause a deadlock. Here is an example by Erich Focht: | ||
255 | * | ||
256 | * Example: | ||
257 | * CPU#0: | ||
258 | * schedule() | ||
259 | * -> spin_lock_irq(&rq->lock) | ||
260 | * -> context_switch() | ||
261 | * -> wrap_mmu_context() | ||
262 | * -> read_lock(&tasklist_lock) | ||
263 | * | ||
264 | * CPU#1: | ||
265 | * sys_wait4() or release_task() or forget_original_parent() | ||
266 | * -> write_lock(&tasklist_lock) | ||
267 | * -> do_notify_parent() | ||
268 | * -> wake_up_parent() | ||
269 | * -> try_to_wake_up() | ||
270 | * -> spin_lock_irq(&parent_rq->lock) | ||
271 | * | ||
272 | * If the parent's rq happens to be on CPU#0, we'll wait for the rq->lock | ||
273 | * of that CPU which will not be released, because there we wait for the | ||
274 | * tasklist_lock to become available. | ||
275 | */ | ||
276 | #define __ARCH_WANT_UNLOCKED_CTXSW | 252 | #define __ARCH_WANT_UNLOCKED_CTXSW |
277 | |||
278 | #define ARCH_HAS_PREFETCH_SWITCH_STACK | 253 | #define ARCH_HAS_PREFETCH_SWITCH_STACK |
279 | #define ia64_platform_is(x) (strcmp(x, platform_name) == 0) | 254 | #define ia64_platform_is(x) (strcmp(x, platform_name) == 0) |
280 | 255 | ||
diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h index 962f9bd1bdff..019956c613e4 100644 --- a/include/asm-ia64/unistd.h +++ b/include/asm-ia64/unistd.h | |||
@@ -270,12 +270,27 @@ | |||
270 | #define __NR_inotify_add_watch 1278 | 270 | #define __NR_inotify_add_watch 1278 |
271 | #define __NR_inotify_rm_watch 1279 | 271 | #define __NR_inotify_rm_watch 1279 |
272 | #define __NR_migrate_pages 1280 | 272 | #define __NR_migrate_pages 1280 |
273 | #define __NR_openat 1281 | ||
274 | #define __NR_mkdirat 1282 | ||
275 | #define __NR_mknodat 1283 | ||
276 | #define __NR_fchownat 1284 | ||
277 | #define __NR_futimesat 1285 | ||
278 | #define __NR_newfstatat 1286 | ||
279 | #define __NR_unlinkat 1287 | ||
280 | #define __NR_renameat 1288 | ||
281 | #define __NR_linkat 1289 | ||
282 | #define __NR_symlinkat 1290 | ||
283 | #define __NR_readlinkat 1291 | ||
284 | #define __NR_fchmodat 1292 | ||
285 | #define __NR_faccessat 1293 | ||
286 | /* 1294, 1295 reserved for pselect/ppoll */ | ||
287 | #define __NR_unshare 1296 | ||
273 | 288 | ||
274 | #ifdef __KERNEL__ | 289 | #ifdef __KERNEL__ |
275 | 290 | ||
276 | #include <linux/config.h> | 291 | #include <linux/config.h> |
277 | 292 | ||
278 | #define NR_syscalls 270 /* length of syscall table */ | 293 | #define NR_syscalls 273 /* length of syscall table */ |
279 | 294 | ||
280 | #define __ARCH_WANT_SYS_RT_SIGACTION | 295 | #define __ARCH_WANT_SYS_RT_SIGACTION |
281 | 296 | ||
diff --git a/include/asm-m68knommu/hardirq.h b/include/asm-m68knommu/hardirq.h index e8659e739a64..476180f4cba2 100644 --- a/include/asm-m68knommu/hardirq.h +++ b/include/asm-m68knommu/hardirq.h | |||
@@ -4,6 +4,7 @@ | |||
4 | #include <linux/config.h> | 4 | #include <linux/config.h> |
5 | #include <linux/cache.h> | 5 | #include <linux/cache.h> |
6 | #include <linux/threads.h> | 6 | #include <linux/threads.h> |
7 | #include <asm/irq.h> | ||
7 | 8 | ||
8 | typedef struct { | 9 | typedef struct { |
9 | unsigned int __softirq_pending; | 10 | unsigned int __softirq_pending; |
diff --git a/include/asm-mips/abi.h b/include/asm-mips/abi.h index 2e7e651c3e3f..1ce0518ace2e 100644 --- a/include/asm-mips/abi.h +++ b/include/asm-mips/abi.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 2005 by Ralf Baechle | 6 | * Copyright (C) 2005, 06 by Ralf Baechle (ralf@linux-mips.org) |
7 | * Copyright (C) 2005 MIPS Technologies, Inc. | 7 | * Copyright (C) 2005 MIPS Technologies, Inc. |
8 | */ | 8 | */ |
9 | #ifndef _ASM_ABI_H | 9 | #ifndef _ASM_ABI_H |
@@ -13,7 +13,7 @@ | |||
13 | #include <asm/siginfo.h> | 13 | #include <asm/siginfo.h> |
14 | 14 | ||
15 | struct mips_abi { | 15 | struct mips_abi { |
16 | int (* const do_signal)(sigset_t *oldset, struct pt_regs *regs); | 16 | void (* const do_signal)(struct pt_regs *regs); |
17 | int (* const setup_frame)(struct k_sigaction * ka, | 17 | int (* const setup_frame)(struct k_sigaction * ka, |
18 | struct pt_regs *regs, int signr, | 18 | struct pt_regs *regs, int signr, |
19 | sigset_t *set); | 19 | sigset_t *set); |
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 3b0c8aaf6e8b..8e802059fe67 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h | |||
@@ -644,20 +644,26 @@ static inline unsigned long ffz(unsigned long word) | |||
644 | } | 644 | } |
645 | 645 | ||
646 | /* | 646 | /* |
647 | * flz - find last zero in word. | 647 | * fls - find last bit set. |
648 | * @word: The word to search | 648 | * @word: The word to search |
649 | * | 649 | * |
650 | * Returns 0..SZLONG-1 | 650 | * Returns 1..SZLONG |
651 | * Undefined if no zero exists, so code should check against ~0UL first. | 651 | * Returns 0 if no bit exists |
652 | */ | 652 | */ |
653 | static inline unsigned long flz(unsigned long word) | 653 | static inline unsigned long fls(unsigned long word) |
654 | { | 654 | { |
655 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) | ||
656 | return __ilog2(~word); | ||
657 | #else | ||
658 | #ifdef CONFIG_32BIT | 655 | #ifdef CONFIG_32BIT |
659 | int r = 31, s; | 656 | #ifdef CONFIG_CPU_MIPS32 |
660 | word = ~word; | 657 | __asm__ ("clz %0, %1" : "=r" (word) : "r" (word)); |
658 | |||
659 | return 32 - word; | ||
660 | #else | ||
661 | { | ||
662 | int r = 32, s; | ||
663 | |||
664 | if (word == 0) | ||
665 | return 0; | ||
666 | |||
661 | s = 16; if ((word & 0xffff0000)) s = 0; r -= s; word <<= s; | 667 | s = 16; if ((word & 0xffff0000)) s = 0; r -= s; word <<= s; |
662 | s = 8; if ((word & 0xff000000)) s = 0; r -= s; word <<= s; | 668 | s = 8; if ((word & 0xff000000)) s = 0; r -= s; word <<= s; |
663 | s = 4; if ((word & 0xf0000000)) s = 0; r -= s; word <<= s; | 669 | s = 4; if ((word & 0xf0000000)) s = 0; r -= s; word <<= s; |
@@ -665,10 +671,23 @@ static inline unsigned long flz(unsigned long word) | |||
665 | s = 1; if ((word & 0x80000000)) s = 0; r -= s; | 671 | s = 1; if ((word & 0x80000000)) s = 0; r -= s; |
666 | 672 | ||
667 | return r; | 673 | return r; |
674 | } | ||
668 | #endif | 675 | #endif |
676 | #endif /* CONFIG_32BIT */ | ||
677 | |||
669 | #ifdef CONFIG_64BIT | 678 | #ifdef CONFIG_64BIT |
670 | int r = 63, s; | 679 | #ifdef CONFIG_CPU_MIPS64 |
671 | word = ~word; | 680 | |
681 | __asm__ ("dclz %0, %1" : "=r" (word) : "r" (word)); | ||
682 | |||
683 | return 64 - word; | ||
684 | #else | ||
685 | { | ||
686 | int r = 64, s; | ||
687 | |||
688 | if (word == 0) | ||
689 | return 0; | ||
690 | |||
672 | s = 32; if ((word & 0xffffffff00000000UL)) s = 0; r -= s; word <<= s; | 691 | s = 32; if ((word & 0xffffffff00000000UL)) s = 0; r -= s; word <<= s; |
673 | s = 16; if ((word & 0xffff000000000000UL)) s = 0; r -= s; word <<= s; | 692 | s = 16; if ((word & 0xffff000000000000UL)) s = 0; r -= s; word <<= s; |
674 | s = 8; if ((word & 0xff00000000000000UL)) s = 0; r -= s; word <<= s; | 693 | s = 8; if ((word & 0xff00000000000000UL)) s = 0; r -= s; word <<= s; |
@@ -677,24 +696,11 @@ static inline unsigned long flz(unsigned long word) | |||
677 | s = 1; if ((word & 0x8000000000000000UL)) s = 0; r -= s; | 696 | s = 1; if ((word & 0x8000000000000000UL)) s = 0; r -= s; |
678 | 697 | ||
679 | return r; | 698 | return r; |
699 | } | ||
680 | #endif | 700 | #endif |
681 | #endif | 701 | #endif /* CONFIG_64BIT */ |
682 | } | 702 | } |
683 | 703 | ||
684 | /* | ||
685 | * fls - find last bit set. | ||
686 | * @word: The word to search | ||
687 | * | ||
688 | * Returns 1..SZLONG | ||
689 | * Returns 0 if no bit exists | ||
690 | */ | ||
691 | static inline unsigned long fls(unsigned long word) | ||
692 | { | ||
693 | if (word == 0) | ||
694 | return 0; | ||
695 | |||
696 | return flz(~word) + 1; | ||
697 | } | ||
698 | #define fls64(x) generic_fls64(x) | 704 | #define fls64(x) generic_fls64(x) |
699 | 705 | ||
700 | /* | 706 | /* |
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h index d1fe9e5c62e4..584f8128fffd 100644 --- a/include/asm-mips/byteorder.h +++ b/include/asm-mips/byteorder.h | |||
@@ -8,10 +8,39 @@ | |||
8 | #ifndef _ASM_BYTEORDER_H | 8 | #ifndef _ASM_BYTEORDER_H |
9 | #define _ASM_BYTEORDER_H | 9 | #define _ASM_BYTEORDER_H |
10 | 10 | ||
11 | #include <linux/config.h> | ||
12 | #include <linux/compiler.h> | ||
11 | #include <asm/types.h> | 13 | #include <asm/types.h> |
12 | 14 | ||
13 | #ifdef __GNUC__ | 15 | #ifdef __GNUC__ |
14 | 16 | ||
17 | #ifdef CONFIG_CPU_MIPSR2 | ||
18 | |||
19 | static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) | ||
20 | { | ||
21 | __asm__( | ||
22 | " wsbh %0, %1 \n" | ||
23 | : "=r" (x) | ||
24 | : "r" (x)); | ||
25 | |||
26 | return x; | ||
27 | } | ||
28 | #define __arch__swab16(x) ___arch__swab16(x) | ||
29 | |||
30 | static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) | ||
31 | { | ||
32 | __asm__( | ||
33 | " wsbh %0, %1 \n" | ||
34 | " rotr %0, %0, 16 \n" | ||
35 | : "=r" (x) | ||
36 | : "r" (x)); | ||
37 | |||
38 | return x; | ||
39 | } | ||
40 | #define __arch__swab32(x) ___arch__swab32(x) | ||
41 | |||
42 | #endif /* CONFIG_CPU_MIPSR2 */ | ||
43 | |||
15 | #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) | 44 | #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) |
16 | # define __BYTEORDER_HAS_U64__ | 45 | # define __BYTEORDER_HAS_U64__ |
17 | # define __SWAB_64_THRU_32__ | 46 | # define __SWAB_64_THRU_32__ |
diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h index a18ba2edc0b6..aeae9fabf4a9 100644 --- a/include/asm-mips/cacheflush.h +++ b/include/asm-mips/cacheflush.h | |||
@@ -49,8 +49,7 @@ static inline void flush_dcache_page(struct page *page) | |||
49 | 49 | ||
50 | extern void (*flush_icache_page)(struct vm_area_struct *vma, | 50 | extern void (*flush_icache_page)(struct vm_area_struct *vma, |
51 | struct page *page); | 51 | struct page *page); |
52 | extern void (*flush_icache_range)(unsigned long __user start, | 52 | extern void (*flush_icache_range)(unsigned long start, unsigned long end); |
53 | unsigned long __user end); | ||
54 | #define flush_cache_vmap(start, end) flush_cache_all() | 53 | #define flush_cache_vmap(start, end) flush_cache_all() |
55 | #define flush_cache_vunmap(start, end) flush_cache_all() | 54 | #define flush_cache_vunmap(start, end) flush_cache_all() |
56 | 55 | ||
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index 2fc90632f88c..6111a0ce58c4 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h | |||
@@ -100,7 +100,7 @@ | |||
100 | 100 | ||
101 | __asm__( | 101 | __asm__( |
102 | " .macro _ssnop \n\t" | 102 | " .macro _ssnop \n\t" |
103 | " sll $0, $2, 1 \n\t" | 103 | " sll $0, $0, 1 \n\t" |
104 | " .endm \n\t" | 104 | " .endm \n\t" |
105 | " \n\t" | 105 | " \n\t" |
106 | " .macro _ehb \n\t" | 106 | " .macro _ehb \n\t" |
diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/interrupt.h index abdf54ee64cf..774348734fa0 100644 --- a/include/asm-mips/interrupt.h +++ b/include/asm-mips/interrupt.h | |||
@@ -47,6 +47,17 @@ static inline void local_irq_enable(void) | |||
47 | * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs | 47 | * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs |
48 | * no nops at all. | 48 | * no nops at all. |
49 | */ | 49 | */ |
50 | /* | ||
51 | * For TX49, operating only IE bit is not enough. | ||
52 | * | ||
53 | * If mfc0 $12 follows store and the mfc0 is last instruction of a | ||
54 | * page and fetching the next instruction causes TLB miss, the result | ||
55 | * of the mfc0 might wrongly contain EXL bit. | ||
56 | * | ||
57 | * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 | ||
58 | * | ||
59 | * Workaround: mask EXL bit of the result or place a nop before mfc0. | ||
60 | */ | ||
50 | __asm__ ( | 61 | __asm__ ( |
51 | " .macro local_irq_disable\n" | 62 | " .macro local_irq_disable\n" |
52 | " .set push \n" | 63 | " .set push \n" |
@@ -55,8 +66,8 @@ __asm__ ( | |||
55 | " di \n" | 66 | " di \n" |
56 | #else | 67 | #else |
57 | " mfc0 $1,$12 \n" | 68 | " mfc0 $1,$12 \n" |
58 | " ori $1,1 \n" | 69 | " ori $1,0x1f \n" |
59 | " xori $1,1 \n" | 70 | " xori $1,0x1f \n" |
60 | " .set noreorder \n" | 71 | " .set noreorder \n" |
61 | " mtc0 $1,$12 \n" | 72 | " mtc0 $1,$12 \n" |
62 | #endif | 73 | #endif |
@@ -96,8 +107,8 @@ __asm__ ( | |||
96 | " andi \\result, 1 \n" | 107 | " andi \\result, 1 \n" |
97 | #else | 108 | #else |
98 | " mfc0 \\result, $12 \n" | 109 | " mfc0 \\result, $12 \n" |
99 | " ori $1, \\result, 1 \n" | 110 | " ori $1, \\result, 0x1f \n" |
100 | " xori $1, 1 \n" | 111 | " xori $1, 0x1f \n" |
101 | " .set noreorder \n" | 112 | " .set noreorder \n" |
102 | " mtc0 $1, $12 \n" | 113 | " mtc0 $1, $12 \n" |
103 | #endif | 114 | #endif |
@@ -114,6 +125,7 @@ __asm__ __volatile__( \ | |||
114 | 125 | ||
115 | __asm__ ( | 126 | __asm__ ( |
116 | " .macro local_irq_restore flags \n" | 127 | " .macro local_irq_restore flags \n" |
128 | " .set push \n" | ||
117 | " .set noreorder \n" | 129 | " .set noreorder \n" |
118 | " .set noat \n" | 130 | " .set noat \n" |
119 | #if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) | 131 | #if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) |
@@ -135,14 +147,13 @@ __asm__ ( | |||
135 | #else | 147 | #else |
136 | " mfc0 $1, $12 \n" | 148 | " mfc0 $1, $12 \n" |
137 | " andi \\flags, 1 \n" | 149 | " andi \\flags, 1 \n" |
138 | " ori $1, 1 \n" | 150 | " ori $1, 0x1f \n" |
139 | " xori $1, 1 \n" | 151 | " xori $1, 0x1f \n" |
140 | " or \\flags, $1 \n" | 152 | " or \\flags, $1 \n" |
141 | " mtc0 \\flags, $12 \n" | 153 | " mtc0 \\flags, $12 \n" |
142 | #endif | 154 | #endif |
143 | " irq_disable_hazard \n" | 155 | " irq_disable_hazard \n" |
144 | " .set at \n" | 156 | " .set pop \n" |
145 | " .set reorder \n" | ||
146 | " .endm \n"); | 157 | " .endm \n"); |
147 | 158 | ||
148 | #define local_irq_restore(flags) \ | 159 | #define local_irq_restore(flags) \ |
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index d42685747e7d..5a4c8a54b8f4 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h | |||
@@ -18,7 +18,6 @@ | |||
18 | #include <linux/types.h> | 18 | #include <linux/types.h> |
19 | 19 | ||
20 | #include <asm/addrspace.h> | 20 | #include <asm/addrspace.h> |
21 | #include <asm/bug.h> | ||
22 | #include <asm/byteorder.h> | 21 | #include <asm/byteorder.h> |
23 | #include <asm/cpu.h> | 22 | #include <asm/cpu.h> |
24 | #include <asm/cpu-features.h> | 23 | #include <asm/cpu-features.h> |
@@ -57,38 +56,38 @@ | |||
57 | * variations of functions: non-prefixed ones that preserve the value | 56 | * variations of functions: non-prefixed ones that preserve the value |
58 | * and prefixed ones that preserve byte addresses. The latters are | 57 | * and prefixed ones that preserve byte addresses. The latters are |
59 | * typically used for moving raw data between a peripheral and memory (cf. | 58 | * typically used for moving raw data between a peripheral and memory (cf. |
60 | * string I/O functions), hence the "mem_" prefix. | 59 | * string I/O functions), hence the "__mem_" prefix. |
61 | */ | 60 | */ |
62 | #if defined(CONFIG_SWAP_IO_SPACE) | 61 | #if defined(CONFIG_SWAP_IO_SPACE) |
63 | 62 | ||
64 | # define ioswabb(x) (x) | 63 | # define ioswabb(x) (x) |
65 | # define mem_ioswabb(x) (x) | 64 | # define __mem_ioswabb(x) (x) |
66 | # ifdef CONFIG_SGI_IP22 | 65 | # ifdef CONFIG_SGI_IP22 |
67 | /* | 66 | /* |
68 | * IP22 seems braindead enough to swap 16bits values in hardware, but | 67 | * IP22 seems braindead enough to swap 16bits values in hardware, but |
69 | * not 32bits. Go figure... Can't tell without documentation. | 68 | * not 32bits. Go figure... Can't tell without documentation. |
70 | */ | 69 | */ |
71 | # define ioswabw(x) (x) | 70 | # define ioswabw(x) (x) |
72 | # define mem_ioswabw(x) le16_to_cpu(x) | 71 | # define __mem_ioswabw(x) le16_to_cpu(x) |
73 | # else | 72 | # else |
74 | # define ioswabw(x) le16_to_cpu(x) | 73 | # define ioswabw(x) le16_to_cpu(x) |
75 | # define mem_ioswabw(x) (x) | 74 | # define __mem_ioswabw(x) (x) |
76 | # endif | 75 | # endif |
77 | # define ioswabl(x) le32_to_cpu(x) | 76 | # define ioswabl(x) le32_to_cpu(x) |
78 | # define mem_ioswabl(x) (x) | 77 | # define __mem_ioswabl(x) (x) |
79 | # define ioswabq(x) le64_to_cpu(x) | 78 | # define ioswabq(x) le64_to_cpu(x) |
80 | # define mem_ioswabq(x) (x) | 79 | # define __mem_ioswabq(x) (x) |
81 | 80 | ||
82 | #else | 81 | #else |
83 | 82 | ||
84 | # define ioswabb(x) (x) | 83 | # define ioswabb(x) (x) |
85 | # define mem_ioswabb(x) (x) | 84 | # define __mem_ioswabb(x) (x) |
86 | # define ioswabw(x) (x) | 85 | # define ioswabw(x) (x) |
87 | # define mem_ioswabw(x) cpu_to_le16(x) | 86 | # define __mem_ioswabw(x) cpu_to_le16(x) |
88 | # define ioswabl(x) (x) | 87 | # define ioswabl(x) (x) |
89 | # define mem_ioswabl(x) cpu_to_le32(x) | 88 | # define __mem_ioswabl(x) cpu_to_le32(x) |
90 | # define ioswabq(x) (x) | 89 | # define ioswabq(x) (x) |
91 | # define mem_ioswabq(x) cpu_to_le32(x) | 90 | # define __mem_ioswabq(x) cpu_to_le32(x) |
92 | 91 | ||
93 | #endif | 92 | #endif |
94 | 93 | ||
@@ -343,7 +342,7 @@ static inline void pfx##write##bwlq(type val, \ | |||
343 | BUG(); \ | 342 | BUG(); \ |
344 | } \ | 343 | } \ |
345 | \ | 344 | \ |
346 | static inline type pfx##read##bwlq(volatile void __iomem *mem) \ | 345 | static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ |
347 | { \ | 346 | { \ |
348 | volatile type *__mem; \ | 347 | volatile type *__mem; \ |
349 | type __val; \ | 348 | type __val; \ |
@@ -418,7 +417,7 @@ __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1) | |||
418 | \ | 417 | \ |
419 | __BUILD_MEMORY_PFX(__raw_, bwlq, type) \ | 418 | __BUILD_MEMORY_PFX(__raw_, bwlq, type) \ |
420 | __BUILD_MEMORY_PFX(, bwlq, type) \ | 419 | __BUILD_MEMORY_PFX(, bwlq, type) \ |
421 | __BUILD_MEMORY_PFX(mem_, bwlq, type) \ | 420 | __BUILD_MEMORY_PFX(__mem_, bwlq, type) \ |
422 | 421 | ||
423 | BUILDIO_MEM(b, u8) | 422 | BUILDIO_MEM(b, u8) |
424 | BUILDIO_MEM(w, u16) | 423 | BUILDIO_MEM(w, u16) |
@@ -431,7 +430,7 @@ BUILDIO_MEM(q, u64) | |||
431 | 430 | ||
432 | #define BUILDIO_IOPORT(bwlq, type) \ | 431 | #define BUILDIO_IOPORT(bwlq, type) \ |
433 | __BUILD_IOPORT_PFX(, bwlq, type) \ | 432 | __BUILD_IOPORT_PFX(, bwlq, type) \ |
434 | __BUILD_IOPORT_PFX(mem_, bwlq, type) | 433 | __BUILD_IOPORT_PFX(__mem_, bwlq, type) |
435 | 434 | ||
436 | BUILDIO_IOPORT(b, u8) | 435 | BUILDIO_IOPORT(b, u8) |
437 | BUILDIO_IOPORT(w, u16) | 436 | BUILDIO_IOPORT(w, u16) |
@@ -465,7 +464,7 @@ static inline void writes##bwlq(volatile void __iomem *mem, \ | |||
465 | const volatile type *__addr = addr; \ | 464 | const volatile type *__addr = addr; \ |
466 | \ | 465 | \ |
467 | while (count--) { \ | 466 | while (count--) { \ |
468 | mem_write##bwlq(*__addr, mem); \ | 467 | __mem_write##bwlq(*__addr, mem); \ |
469 | __addr++; \ | 468 | __addr++; \ |
470 | } \ | 469 | } \ |
471 | } \ | 470 | } \ |
@@ -476,7 +475,7 @@ static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ | |||
476 | volatile type *__addr = addr; \ | 475 | volatile type *__addr = addr; \ |
477 | \ | 476 | \ |
478 | while (count--) { \ | 477 | while (count--) { \ |
479 | *__addr = mem_read##bwlq(mem); \ | 478 | *__addr = __mem_read##bwlq(mem); \ |
480 | __addr++; \ | 479 | __addr++; \ |
481 | } \ | 480 | } \ |
482 | } | 481 | } |
@@ -489,7 +488,7 @@ static inline void outs##bwlq(unsigned long port, const void *addr, \ | |||
489 | const volatile type *__addr = addr; \ | 488 | const volatile type *__addr = addr; \ |
490 | \ | 489 | \ |
491 | while (count--) { \ | 490 | while (count--) { \ |
492 | mem_out##bwlq(*__addr, port); \ | 491 | __mem_out##bwlq(*__addr, port); \ |
493 | __addr++; \ | 492 | __addr++; \ |
494 | } \ | 493 | } \ |
495 | } \ | 494 | } \ |
@@ -500,7 +499,7 @@ static inline void ins##bwlq(unsigned long port, void *addr, \ | |||
500 | volatile type *__addr = addr; \ | 499 | volatile type *__addr = addr; \ |
501 | \ | 500 | \ |
502 | while (count--) { \ | 501 | while (count--) { \ |
503 | *__addr = mem_in##bwlq(port); \ | 502 | *__addr = __mem_in##bwlq(port); \ |
504 | __addr++; \ | 503 | __addr++; \ |
505 | } \ | 504 | } \ |
506 | } | 505 | } |
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 8e1d7ed7d8e3..4686e17c206c 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h | |||
@@ -1198,7 +1198,11 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; | |||
1198 | 1198 | ||
1199 | /* UARTS 0-3 */ | 1199 | /* UARTS 0-3 */ |
1200 | #define UART_BASE UART0_ADDR | 1200 | #define UART_BASE UART0_ADDR |
1201 | #ifdef CONFIG_SOC_AU1200 | ||
1202 | #define UART_DEBUG_BASE UART1_ADDR | ||
1203 | #else | ||
1201 | #define UART_DEBUG_BASE UART3_ADDR | 1204 | #define UART_DEBUG_BASE UART3_ADDR |
1205 | #endif | ||
1202 | 1206 | ||
1203 | #define UART_RX 0 /* Receive buffer */ | 1207 | #define UART_RX 0 /* Receive buffer */ |
1204 | #define UART_TX 4 /* Transmit buffer */ | 1208 | #define UART_TX 4 /* Transmit buffer */ |
diff --git a/include/asm-mips/cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h index 78e1df2095fb..78e1df2095fb 100644 --- a/include/asm-mips/cobalt/cobalt.h +++ b/include/asm-mips/mach-cobalt/cobalt.h | |||
diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h new file mode 100644 index 000000000000..ace8c5ef9701 --- /dev/null +++ b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h | |||
@@ -0,0 +1,56 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) | ||
7 | */ | ||
8 | #ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H | ||
9 | #define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H | ||
10 | |||
11 | #include <linux/config.h> | ||
12 | |||
13 | #define cpu_has_tlb 1 | ||
14 | #define cpu_has_4kex 1 | ||
15 | #define cpu_has_3k_cache 0 | ||
16 | #define cpu_has_4k_cache 1 | ||
17 | #define cpu_has_tx39_cache 0 | ||
18 | #define cpu_has_sb1_cache 0 | ||
19 | #define cpu_has_fpu 1 | ||
20 | #define cpu_has_32fpr 1 | ||
21 | #define cpu_has_counter 1 | ||
22 | #define cpu_has_watch 0 | ||
23 | #define cpu_has_divec 1 | ||
24 | #define cpu_has_vce 0 | ||
25 | #define cpu_has_cache_cdex_p 0 | ||
26 | #define cpu_has_cache_cdex_s 0 | ||
27 | #define cpu_has_prefetch 0 | ||
28 | #define cpu_has_mcheck 0 | ||
29 | #define cpu_has_ejtag 0 | ||
30 | |||
31 | #define cpu_has_subset_pcaches 0 | ||
32 | #define cpu_dcache_line_size() 32 | ||
33 | #define cpu_icache_line_size() 32 | ||
34 | #define cpu_scache_line_size() 0 | ||
35 | |||
36 | #ifdef CONFIG_64BIT | ||
37 | #define cpu_has_llsc 0 | ||
38 | #else | ||
39 | #define cpu_has_llsc 1 | ||
40 | #endif | ||
41 | |||
42 | #define cpu_has_mips16 0 | ||
43 | #define cpu_has_mdmx 0 | ||
44 | #define cpu_has_mips3d 0 | ||
45 | #define cpu_has_smartmips 0 | ||
46 | #define cpu_has_vtag_icache 0 | ||
47 | #define cpu_has_ic_fills_f_dc 0 | ||
48 | #define cpu_icache_snoops_remote_store 0 | ||
49 | #define cpu_has_dsp 0 | ||
50 | |||
51 | #define cpu_has_mips32r1 0 | ||
52 | #define cpu_has_mips32r2 0 | ||
53 | #define cpu_has_mips64r1 0 | ||
54 | #define cpu_has_mips64r2 0 | ||
55 | |||
56 | #endif /* __ASM_COBALT_CPU_FEATURE_OVERRIDES_H */ | ||
diff --git a/include/asm-mips/cobalt/mach-gt64120.h b/include/asm-mips/mach-cobalt/mach-gt64120.h index 587fc4378f44..587fc4378f44 100644 --- a/include/asm-mips/cobalt/mach-gt64120.h +++ b/include/asm-mips/mach-cobalt/mach-gt64120.h | |||
diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h index b80c30725cf6..36070b5654ab 100644 --- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h | |||
@@ -18,7 +18,7 @@ | |||
18 | * so, for 64bit IP32 kernel we just don't use ll/sc. | 18 | * so, for 64bit IP32 kernel we just don't use ll/sc. |
19 | * This does not affect luserland. | 19 | * This does not affect luserland. |
20 | */ | 20 | */ |
21 | #if defined(CONFIG_CPU_R5000) && defined(CONFIG_64BIT) | 21 | #if (defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_NEVADA)) && defined(CONFIG_64BIT) |
22 | #define cpu_has_llsc 0 | 22 | #define cpu_has_llsc 0 |
23 | #else | 23 | #else |
24 | #define cpu_has_llsc 1 | 24 | #define cpu_has_llsc 1 |
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index a5ea9d828aee..cc53196efa40 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h | |||
@@ -166,123 +166,6 @@ static inline void invalidate_tcache_page(unsigned long addr) | |||
166 | : "r" (base), \ | 166 | : "r" (base), \ |
167 | "i" (op)); | 167 | "i" (op)); |
168 | 168 | ||
169 | static inline void blast_dcache16(void) | ||
170 | { | ||
171 | unsigned long start = INDEX_BASE; | ||
172 | unsigned long end = start + current_cpu_data.dcache.waysize; | ||
173 | unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; | ||
174 | unsigned long ws_end = current_cpu_data.dcache.ways << | ||
175 | current_cpu_data.dcache.waybit; | ||
176 | unsigned long ws, addr; | ||
177 | |||
178 | for (ws = 0; ws < ws_end; ws += ws_inc) | ||
179 | for (addr = start; addr < end; addr += 0x200) | ||
180 | cache16_unroll32(addr|ws,Index_Writeback_Inv_D); | ||
181 | } | ||
182 | |||
183 | static inline void blast_dcache16_page(unsigned long page) | ||
184 | { | ||
185 | unsigned long start = page; | ||
186 | unsigned long end = start + PAGE_SIZE; | ||
187 | |||
188 | do { | ||
189 | cache16_unroll32(start,Hit_Writeback_Inv_D); | ||
190 | start += 0x200; | ||
191 | } while (start < end); | ||
192 | } | ||
193 | |||
194 | static inline void blast_dcache16_page_indexed(unsigned long page) | ||
195 | { | ||
196 | unsigned long start = page; | ||
197 | unsigned long end = start + PAGE_SIZE; | ||
198 | unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; | ||
199 | unsigned long ws_end = current_cpu_data.dcache.ways << | ||
200 | current_cpu_data.dcache.waybit; | ||
201 | unsigned long ws, addr; | ||
202 | |||
203 | for (ws = 0; ws < ws_end; ws += ws_inc) | ||
204 | for (addr = start; addr < end; addr += 0x200) | ||
205 | cache16_unroll32(addr|ws,Index_Writeback_Inv_D); | ||
206 | } | ||
207 | |||
208 | static inline void blast_icache16(void) | ||
209 | { | ||
210 | unsigned long start = INDEX_BASE; | ||
211 | unsigned long end = start + current_cpu_data.icache.waysize; | ||
212 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | ||
213 | unsigned long ws_end = current_cpu_data.icache.ways << | ||
214 | current_cpu_data.icache.waybit; | ||
215 | unsigned long ws, addr; | ||
216 | |||
217 | for (ws = 0; ws < ws_end; ws += ws_inc) | ||
218 | for (addr = start; addr < end; addr += 0x200) | ||
219 | cache16_unroll32(addr|ws,Index_Invalidate_I); | ||
220 | } | ||
221 | |||
222 | static inline void blast_icache16_page(unsigned long page) | ||
223 | { | ||
224 | unsigned long start = page; | ||
225 | unsigned long end = start + PAGE_SIZE; | ||
226 | |||
227 | do { | ||
228 | cache16_unroll32(start,Hit_Invalidate_I); | ||
229 | start += 0x200; | ||
230 | } while (start < end); | ||
231 | } | ||
232 | |||
233 | static inline void blast_icache16_page_indexed(unsigned long page) | ||
234 | { | ||
235 | unsigned long start = page; | ||
236 | unsigned long end = start + PAGE_SIZE; | ||
237 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | ||
238 | unsigned long ws_end = current_cpu_data.icache.ways << | ||
239 | current_cpu_data.icache.waybit; | ||
240 | unsigned long ws, addr; | ||
241 | |||
242 | for (ws = 0; ws < ws_end; ws += ws_inc) | ||
243 | for (addr = start; addr < end; addr += 0x200) | ||
244 | cache16_unroll32(addr|ws,Index_Invalidate_I); | ||
245 | } | ||
246 | |||
247 | static inline void blast_scache16(void) | ||
248 | { | ||
249 | unsigned long start = INDEX_BASE; | ||
250 | unsigned long end = start + current_cpu_data.scache.waysize; | ||
251 | unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; | ||
252 | unsigned long ws_end = current_cpu_data.scache.ways << | ||
253 | current_cpu_data.scache.waybit; | ||
254 | unsigned long ws, addr; | ||
255 | |||
256 | for (ws = 0; ws < ws_end; ws += ws_inc) | ||
257 | for (addr = start; addr < end; addr += 0x200) | ||
258 | cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); | ||
259 | } | ||
260 | |||
261 | static inline void blast_scache16_page(unsigned long page) | ||
262 | { | ||
263 | unsigned long start = page; | ||
264 | unsigned long end = page + PAGE_SIZE; | ||
265 | |||
266 | do { | ||
267 | cache16_unroll32(start,Hit_Writeback_Inv_SD); | ||
268 | start += 0x200; | ||
269 | } while (start < end); | ||
270 | } | ||
271 | |||
272 | static inline void blast_scache16_page_indexed(unsigned long page) | ||
273 | { | ||
274 | unsigned long start = page; | ||
275 | unsigned long end = start + PAGE_SIZE; | ||
276 | unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; | ||
277 | unsigned long ws_end = current_cpu_data.scache.ways << | ||
278 | current_cpu_data.scache.waybit; | ||
279 | unsigned long ws, addr; | ||
280 | |||
281 | for (ws = 0; ws < ws_end; ws += ws_inc) | ||
282 | for (addr = start; addr < end; addr += 0x200) | ||
283 | cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); | ||
284 | } | ||
285 | |||
286 | #define cache32_unroll32(base,op) \ | 169 | #define cache32_unroll32(base,op) \ |
287 | __asm__ __volatile__( \ | 170 | __asm__ __volatile__( \ |
288 | " .set push \n" \ | 171 | " .set push \n" \ |
@@ -309,123 +192,6 @@ static inline void blast_scache16_page_indexed(unsigned long page) | |||
309 | : "r" (base), \ | 192 | : "r" (base), \ |
310 | "i" (op)); | 193 | "i" (op)); |
311 | 194 | ||
312 | static inline void blast_dcache32(void) | ||
313 | { | ||
314 | unsigned long start = INDEX_BASE; | ||
315 | unsigned long end = start + current_cpu_data.dcache.waysize; | ||
316 | unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; | ||
317 | unsigned long ws_end = current_cpu_data.dcache.ways << | ||
318 | current_cpu_data.dcache.waybit; | ||
319 | unsigned long ws, addr; | ||
320 | |||
321 | for (ws = 0; ws < ws_end; ws += ws_inc) | ||
322 | for (addr = start; addr < end; addr += 0x400) | ||
323 | cache32_unroll32(addr|ws,Index_Writeback_Inv_D); | ||
324 | } | ||
325 | |||
326 | static inline void blast_dcache32_page(unsigned long page) | ||
327 | { | ||
328 | unsigned long start = page; | ||
329 | unsigned long end = start + PAGE_SIZE; | ||
330 | |||
331 | do { | ||
332 | cache32_unroll32(start,Hit_Writeback_Inv_D); | ||
333 | start += 0x400; | ||
334 | } while (start < end); | ||
335 | } | ||
336 | |||
337 | static inline void blast_dcache32_page_indexed(unsigned long page) | ||
338 | { | ||
339 | unsigned long start = page; | ||
340 | unsigned long end = start + PAGE_SIZE; | ||
341 | unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; | ||
342 | unsigned long ws_end = current_cpu_data.dcache.ways << | ||
343 | current_cpu_data.dcache.waybit; | ||
344 | unsigned long ws, addr; | ||
345 | |||
346 | for (ws = 0; ws < ws_end; ws += ws_inc) | ||
347 | for (addr = start; addr < end; addr += 0x400) | ||
348 | cache32_unroll32(addr|ws,Index_Writeback_Inv_D); | ||
349 | } | ||
350 | |||
351 | static inline void blast_icache32(void) | ||
352 | { | ||
353 | unsigned long start = INDEX_BASE; | ||
354 | unsigned long end = start + current_cpu_data.icache.waysize; | ||
355 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | ||
356 | unsigned long ws_end = current_cpu_data.icache.ways << | ||
357 | current_cpu_data.icache.waybit; | ||
358 | unsigned long ws, addr; | ||
359 | |||
360 | for (ws = 0; ws < ws_end; ws += ws_inc) | ||
361 | for (addr = start; addr < end; addr += 0x400) | ||
362 | cache32_unroll32(addr|ws,Index_Invalidate_I); | ||
363 | } | ||
364 | |||
365 | static inline void blast_icache32_page(unsigned long page) | ||
366 | { | ||
367 | unsigned long start = page; | ||
368 | unsigned long end = start + PAGE_SIZE; | ||
369 | |||
370 | do { | ||
371 | cache32_unroll32(start,Hit_Invalidate_I); | ||
372 | start += 0x400; | ||
373 | } while (start < end); | ||
374 | } | ||
375 | |||
376 | static inline void blast_icache32_page_indexed(unsigned long page) | ||
377 | { | ||
378 | unsigned long start = page; | ||
379 | unsigned long end = start + PAGE_SIZE; | ||
380 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | ||
381 | unsigned long ws_end = current_cpu_data.icache.ways << | ||
382 | current_cpu_data.icache.waybit; | ||
383 | unsigned long ws, addr; | ||
384 | |||
385 | for (ws = 0; ws < ws_end; ws += ws_inc) | ||
386 | for (addr = start; addr < end; addr += 0x400) | ||
387 | cache32_unroll32(addr|ws,Index_Invalidate_I); | ||
388 | } | ||
389 | |||
390 | static inline void blast_scache32(void) | ||
391 | { | ||
392 | unsigned long start = INDEX_BASE; | ||
393 | unsigned long end = start + current_cpu_data.scache.waysize; | ||
394 | unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; | ||
395 | unsigned long ws_end = current_cpu_data.scache.ways << | ||
396 | current_cpu_data.scache.waybit; | ||
397 | unsigned long ws, addr; | ||
398 | |||
399 | for (ws = 0; ws < ws_end; ws += ws_inc) | ||
400 | for (addr = start; addr < end; addr += 0x400) | ||
401 | cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); | ||
402 | } | ||
403 | |||
404 | static inline void blast_scache32_page(unsigned long page) | ||
405 | { | ||
406 | unsigned long start = page; | ||
407 | unsigned long end = page + PAGE_SIZE; | ||
408 | |||
409 | do { | ||
410 | cache32_unroll32(start,Hit_Writeback_Inv_SD); | ||
411 | start += 0x400; | ||
412 | } while (start < end); | ||
413 | } | ||
414 | |||
415 | static inline void blast_scache32_page_indexed(unsigned long page) | ||
416 | { | ||
417 | unsigned long start = page; | ||
418 | unsigned long end = start + PAGE_SIZE; | ||
419 | unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; | ||
420 | unsigned long ws_end = current_cpu_data.scache.ways << | ||
421 | current_cpu_data.scache.waybit; | ||
422 | unsigned long ws, addr; | ||
423 | |||
424 | for (ws = 0; ws < ws_end; ws += ws_inc) | ||
425 | for (addr = start; addr < end; addr += 0x400) | ||
426 | cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); | ||
427 | } | ||
428 | |||
429 | #define cache64_unroll32(base,op) \ | 195 | #define cache64_unroll32(base,op) \ |
430 | __asm__ __volatile__( \ | 196 | __asm__ __volatile__( \ |
431 | " .set push \n" \ | 197 | " .set push \n" \ |
@@ -452,84 +218,6 @@ static inline void blast_scache32_page_indexed(unsigned long page) | |||
452 | : "r" (base), \ | 218 | : "r" (base), \ |
453 | "i" (op)); | 219 | "i" (op)); |
454 | 220 | ||
455 | static inline void blast_icache64(void) | ||
456 | { | ||
457 | unsigned long start = INDEX_BASE; | ||
458 | unsigned long end = start + current_cpu_data.icache.waysize; | ||
459 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | ||
460 | unsigned long ws_end = current_cpu_data.icache.ways << | ||
461 | current_cpu_data.icache.waybit; | ||
462 | unsigned long ws, addr; | ||
463 | |||
464 | for (ws = 0; ws < ws_end; ws += ws_inc) | ||
465 | for (addr = start; addr < end; addr += 0x800) | ||
466 | cache64_unroll32(addr|ws,Index_Invalidate_I); | ||
467 | } | ||
468 | |||
469 | static inline void blast_icache64_page(unsigned long page) | ||
470 | { | ||
471 | unsigned long start = page; | ||
472 | unsigned long end = start + PAGE_SIZE; | ||
473 | |||
474 | do { | ||
475 | cache64_unroll32(start,Hit_Invalidate_I); | ||
476 | start += 0x800; | ||
477 | } while (start < end); | ||
478 | } | ||
479 | |||
480 | static inline void blast_icache64_page_indexed(unsigned long page) | ||
481 | { | ||
482 | unsigned long start = page; | ||
483 | unsigned long end = start + PAGE_SIZE; | ||
484 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | ||
485 | unsigned long ws_end = current_cpu_data.icache.ways << | ||
486 | current_cpu_data.icache.waybit; | ||
487 | unsigned long ws, addr; | ||
488 | |||
489 | for (ws = 0; ws < ws_end; ws += ws_inc) | ||
490 | for (addr = start; addr < end; addr += 0x800) | ||
491 | cache64_unroll32(addr|ws,Index_Invalidate_I); | ||
492 | } | ||
493 | |||
494 | static inline void blast_scache64(void) | ||
495 | { | ||
496 | unsigned long start = INDEX_BASE; | ||
497 | unsigned long end = start + current_cpu_data.scache.waysize; | ||
498 | unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; | ||
499 | unsigned long ws_end = current_cpu_data.scache.ways << | ||
500 | current_cpu_data.scache.waybit; | ||
501 | unsigned long ws, addr; | ||
502 | |||
503 | for (ws = 0; ws < ws_end; ws += ws_inc) | ||
504 | for (addr = start; addr < end; addr += 0x800) | ||
505 | cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); | ||
506 | } | ||
507 | |||
508 | static inline void blast_scache64_page(unsigned long page) | ||
509 | { | ||
510 | unsigned long start = page; | ||
511 | unsigned long end = page + PAGE_SIZE; | ||
512 | |||
513 | do { | ||
514 | cache64_unroll32(start,Hit_Writeback_Inv_SD); | ||
515 | start += 0x800; | ||
516 | } while (start < end); | ||
517 | } | ||
518 | |||
519 | static inline void blast_scache64_page_indexed(unsigned long page) | ||
520 | { | ||
521 | unsigned long start = page; | ||
522 | unsigned long end = start + PAGE_SIZE; | ||
523 | unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; | ||
524 | unsigned long ws_end = current_cpu_data.scache.ways << | ||
525 | current_cpu_data.scache.waybit; | ||
526 | unsigned long ws, addr; | ||
527 | |||
528 | for (ws = 0; ws < ws_end; ws += ws_inc) | ||
529 | for (addr = start; addr < end; addr += 0x800) | ||
530 | cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); | ||
531 | } | ||
532 | |||
533 | #define cache128_unroll32(base,op) \ | 221 | #define cache128_unroll32(base,op) \ |
534 | __asm__ __volatile__( \ | 222 | __asm__ __volatile__( \ |
535 | " .set push \n" \ | 223 | " .set push \n" \ |
@@ -556,43 +244,55 @@ static inline void blast_scache64_page_indexed(unsigned long page) | |||
556 | : "r" (base), \ | 244 | : "r" (base), \ |
557 | "i" (op)); | 245 | "i" (op)); |
558 | 246 | ||
559 | static inline void blast_scache128(void) | 247 | /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */ |
560 | { | 248 | #define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \ |
561 | unsigned long start = INDEX_BASE; | 249 | static inline void blast_##pfx##cache##lsize(void) \ |
562 | unsigned long end = start + current_cpu_data.scache.waysize; | 250 | { \ |
563 | unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; | 251 | unsigned long start = INDEX_BASE; \ |
564 | unsigned long ws_end = current_cpu_data.scache.ways << | 252 | unsigned long end = start + current_cpu_data.desc.waysize; \ |
565 | current_cpu_data.scache.waybit; | 253 | unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ |
566 | unsigned long ws, addr; | 254 | unsigned long ws_end = current_cpu_data.desc.ways << \ |
567 | 255 | current_cpu_data.desc.waybit; \ | |
568 | for (ws = 0; ws < ws_end; ws += ws_inc) | 256 | unsigned long ws, addr; \ |
569 | for (addr = start; addr < end; addr += 0x1000) | 257 | \ |
570 | cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); | 258 | for (ws = 0; ws < ws_end; ws += ws_inc) \ |
571 | } | 259 | for (addr = start; addr < end; addr += lsize * 32) \ |
572 | 260 | cache##lsize##_unroll32(addr|ws,indexop); \ | |
573 | static inline void blast_scache128_page(unsigned long page) | 261 | } \ |
574 | { | 262 | \ |
575 | unsigned long start = page; | 263 | static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \ |
576 | unsigned long end = page + PAGE_SIZE; | 264 | { \ |
577 | 265 | unsigned long start = page; \ | |
578 | do { | 266 | unsigned long end = page + PAGE_SIZE; \ |
579 | cache128_unroll32(start,Hit_Writeback_Inv_SD); | 267 | \ |
580 | start += 0x1000; | 268 | do { \ |
581 | } while (start < end); | 269 | cache##lsize##_unroll32(start,hitop); \ |
582 | } | 270 | start += lsize * 32; \ |
583 | 271 | } while (start < end); \ | |
584 | static inline void blast_scache128_page_indexed(unsigned long page) | 272 | } \ |
585 | { | 273 | \ |
586 | unsigned long start = page; | 274 | static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ |
587 | unsigned long end = start + PAGE_SIZE; | 275 | { \ |
588 | unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; | 276 | unsigned long start = page; \ |
589 | unsigned long ws_end = current_cpu_data.scache.ways << | 277 | unsigned long end = start + PAGE_SIZE; \ |
590 | current_cpu_data.scache.waybit; | 278 | unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ |
591 | unsigned long ws, addr; | 279 | unsigned long ws_end = current_cpu_data.desc.ways << \ |
592 | 280 | current_cpu_data.desc.waybit; \ | |
593 | for (ws = 0; ws < ws_end; ws += ws_inc) | 281 | unsigned long ws, addr; \ |
594 | for (addr = start; addr < end; addr += 0x1000) | 282 | \ |
595 | cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); | 283 | for (ws = 0; ws < ws_end; ws += ws_inc) \ |
596 | } | 284 | for (addr = start; addr < end; addr += lsize * 32) \ |
285 | cache##lsize##_unroll32(addr|ws,indexop); \ | ||
286 | } | ||
287 | |||
288 | __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16) | ||
289 | __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16) | ||
290 | __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16) | ||
291 | __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32) | ||
292 | __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) | ||
293 | __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32) | ||
294 | __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) | ||
295 | __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64) | ||
296 | __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) | ||
597 | 297 | ||
598 | #endif /* _ASM_R4KCACHE_H */ | 298 | #endif /* _ASM_R4KCACHE_H */ |
diff --git a/include/asm-mips/reboot.h b/include/asm-mips/reboot.h index 2f10ebcbe141..e48c0bfab257 100644 --- a/include/asm-mips/reboot.h +++ b/include/asm-mips/reboot.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 1997, 1999, 2001 by Ralf Baechle | 6 | * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle |
7 | * Copyright (C) 2001 MIPS Technologies, Inc. | 7 | * Copyright (C) 2001 MIPS Technologies, Inc. |
8 | */ | 8 | */ |
9 | #ifndef _ASM_REBOOT_H | 9 | #ifndef _ASM_REBOOT_H |
@@ -11,6 +11,5 @@ | |||
11 | 11 | ||
12 | extern void (*_machine_restart)(char *command); | 12 | extern void (*_machine_restart)(char *command); |
13 | extern void (*_machine_halt)(void); | 13 | extern void (*_machine_halt)(void); |
14 | extern void (*_machine_power_off)(void); | ||
15 | 14 | ||
16 | #endif /* _ASM_REBOOT_H */ | 15 | #endif /* _ASM_REBOOT_H */ |
diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h index 5a06f6d13899..907da600fddd 100644 --- a/include/asm-mips/string.h +++ b/include/asm-mips/string.h | |||
@@ -141,26 +141,4 @@ extern void *memcpy(void *__to, __const__ void *__from, size_t __n); | |||
141 | #define __HAVE_ARCH_MEMMOVE | 141 | #define __HAVE_ARCH_MEMMOVE |
142 | extern void *memmove(void *__dest, __const__ void *__src, size_t __n); | 142 | extern void *memmove(void *__dest, __const__ void *__src, size_t __n); |
143 | 143 | ||
144 | #ifdef CONFIG_32BIT | ||
145 | #define __HAVE_ARCH_MEMSCAN | ||
146 | static __inline__ void *memscan(void *__addr, int __c, size_t __size) | ||
147 | { | ||
148 | char *__end = (char *)__addr + __size; | ||
149 | unsigned char __uc = (unsigned char) __c; | ||
150 | |||
151 | __asm__(".set\tpush\n\t" | ||
152 | ".set\tnoat\n\t" | ||
153 | ".set\treorder\n\t" | ||
154 | "1:\tbeq\t%0,%1,2f\n\t" | ||
155 | "addiu\t%0,1\n\t" | ||
156 | "lbu\t$1,-1(%0)\n\t" | ||
157 | "bne\t$1,%z4,1b\n" | ||
158 | "2:\t.set\tpop" | ||
159 | : "=r" (__addr), "=r" (__end) | ||
160 | : "0" (__addr), "1" (__end), "Jr" (__uc)); | ||
161 | |||
162 | return __addr; | ||
163 | } | ||
164 | #endif /* CONFIG_32BIT */ | ||
165 | |||
166 | #endif /* _ASM_STRING_H */ | 144 | #endif /* _ASM_STRING_H */ |
diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h index 1612b3fe1080..fa193f861e71 100644 --- a/include/asm-mips/thread_info.h +++ b/include/asm-mips/thread_info.h | |||
@@ -114,6 +114,7 @@ register struct thread_info *__current_thread_info __asm__("$28"); | |||
114 | #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ | 114 | #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ |
115 | #define TIF_SYSCALL_AUDIT 4 /* syscall auditing active */ | 115 | #define TIF_SYSCALL_AUDIT 4 /* syscall auditing active */ |
116 | #define TIF_SECCOMP 5 /* secure computing */ | 116 | #define TIF_SECCOMP 5 /* secure computing */ |
117 | #define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ | ||
117 | #define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ | 118 | #define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ |
118 | #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ | 119 | #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ |
119 | #define TIF_MEMDIE 18 | 120 | #define TIF_MEMDIE 18 |
@@ -125,6 +126,7 @@ register struct thread_info *__current_thread_info __asm__("$28"); | |||
125 | #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) | 126 | #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) |
126 | #define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) | 127 | #define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) |
127 | #define _TIF_SECCOMP (1<<TIF_SECCOMP) | 128 | #define _TIF_SECCOMP (1<<TIF_SECCOMP) |
129 | #define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) | ||
128 | #define _TIF_USEDFPU (1<<TIF_USEDFPU) | 130 | #define _TIF_USEDFPU (1<<TIF_USEDFPU) |
129 | #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) | 131 | #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) |
130 | 132 | ||
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h index 3bb7f0087d68..de85bd2245f7 100644 --- a/include/asm-mips/tx4927/tx4927.h +++ b/include/asm-mips/tx4927/tx4927.h | |||
@@ -2,7 +2,7 @@ | |||
2 | * Author: MontaVista Software, Inc. | 2 | * Author: MontaVista Software, Inc. |
3 | * source@mvista.com | 3 | * source@mvista.com |
4 | * | 4 | * |
5 | * Copyright 2001-2002 MontaVista Software Inc. | 5 | * Copyright 2001-2006 MontaVista Software Inc. |
6 | * | 6 | * |
7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
8 | * under the terms of the GNU General Public License as published by the | 8 | * under the terms of the GNU General Public License as published by the |
@@ -30,10 +30,10 @@ | |||
30 | #include <asm/tx4927/tx4927_mips.h> | 30 | #include <asm/tx4927/tx4927_mips.h> |
31 | 31 | ||
32 | /* | 32 | /* |
33 | This register naming came from the intergrate cpu/controoler name TX4927 | 33 | This register naming came from the integrated CPU/controller name TX4927 |
34 | followed by the device name from table 4.2.2 on page 4-3 and then followed | 34 | followed by the device name from table 4.2.2 on page 4-3 and then followed |
35 | by the register name from table 4.2.3 on pages 4-4 to 4-8. The manaul | 35 | by the register name from table 4.2.3 on pages 4-4 to 4-8. The manaul |
36 | used is "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001". | 36 | used was "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001". |
37 | */ | 37 | */ |
38 | 38 | ||
39 | #define TX4927_SIO_0_BASE | 39 | #define TX4927_SIO_0_BASE |
@@ -251,8 +251,8 @@ | |||
251 | 251 | ||
252 | /* TX4927 Timer 0 (32-bit registers) */ | 252 | /* TX4927 Timer 0 (32-bit registers) */ |
253 | #define TX4927_TMR0_BASE 0xf000 | 253 | #define TX4927_TMR0_BASE 0xf000 |
254 | #define TX4927_TMR0_TMTCR0 0xf004 | 254 | #define TX4927_TMR0_TMTCR0 0xf000 |
255 | #define TX4927_TMR0_TMTISR0 0xf008 | 255 | #define TX4927_TMR0_TMTISR0 0xf004 |
256 | #define TX4927_TMR0_TMCPRA0 0xf008 | 256 | #define TX4927_TMR0_TMCPRA0 0xf008 |
257 | #define TX4927_TMR0_TMCPRB0 0xf00c | 257 | #define TX4927_TMR0_TMCPRB0 0xf00c |
258 | #define TX4927_TMR0_TMITMR0 0xf010 | 258 | #define TX4927_TMR0_TMITMR0 0xf010 |
@@ -264,8 +264,8 @@ | |||
264 | 264 | ||
265 | /* TX4927 Timer 1 (32-bit registers) */ | 265 | /* TX4927 Timer 1 (32-bit registers) */ |
266 | #define TX4927_TMR1_BASE 0xf100 | 266 | #define TX4927_TMR1_BASE 0xf100 |
267 | #define TX4927_TMR1_TMTCR1 0xf104 | 267 | #define TX4927_TMR1_TMTCR1 0xf100 |
268 | #define TX4927_TMR1_TMTISR1 0xf108 | 268 | #define TX4927_TMR1_TMTISR1 0xf104 |
269 | #define TX4927_TMR1_TMCPRA1 0xf108 | 269 | #define TX4927_TMR1_TMCPRA1 0xf108 |
270 | #define TX4927_TMR1_TMCPRB1 0xf10c | 270 | #define TX4927_TMR1_TMCPRB1 0xf10c |
271 | #define TX4927_TMR1_TMITMR1 0xf110 | 271 | #define TX4927_TMR1_TMITMR1 0xf110 |
@@ -277,13 +277,12 @@ | |||
277 | 277 | ||
278 | /* TX4927 Timer 2 (32-bit registers) */ | 278 | /* TX4927 Timer 2 (32-bit registers) */ |
279 | #define TX4927_TMR2_BASE 0xf200 | 279 | #define TX4927_TMR2_BASE 0xf200 |
280 | #define TX4927_TMR2_TMTCR2 0xf104 | 280 | #define TX4927_TMR2_TMTCR2 0xf200 |
281 | #define TX4927_TMR2_TMTISR2 0xf208 | 281 | #define TX4927_TMR2_TMTISR2 0xf204 |
282 | #define TX4927_TMR2_TMCPRA2 0xf208 | 282 | #define TX4927_TMR2_TMCPRA2 0xf208 |
283 | #define TX4927_TMR2_TMCPRB2 0xf20c | ||
284 | #define TX4927_TMR2_TMITMR2 0xf210 | 283 | #define TX4927_TMR2_TMITMR2 0xf210 |
285 | #define TX4927_TMR2_TMCCDR2 0xf220 | 284 | #define TX4927_TMR2_TMCCDR2 0xf220 |
286 | #define TX4927_TMR2_TMPGMR2 0xf230 | 285 | #define TX4927_TMR2_TMWTMR2 0xf240 |
287 | #define TX4927_TMR2_TMTRR2 0xf2f0 | 286 | #define TX4927_TMR2_TMTRR2 0xf2f0 |
288 | #define TX4927_TMR2_LIMIT 0xf2ff | 287 | #define TX4927_TMR2_LIMIT 0xf2ff |
289 | 288 | ||
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h index 165f6b8b217f..66c064690f41 100644 --- a/include/asm-mips/tx4927/tx4927_pci.h +++ b/include/asm-mips/tx4927/tx4927_pci.h | |||
@@ -253,6 +253,16 @@ struct tx4927_pcic_reg { | |||
253 | #define TX4927_CCFG_PCIDIVMODE_5 0x00001000 | 253 | #define TX4927_CCFG_PCIDIVMODE_5 0x00001000 |
254 | #define TX4927_CCFG_PCIDIVMODE_6 0x00001800 | 254 | #define TX4927_CCFG_PCIDIVMODE_6 0x00001800 |
255 | 255 | ||
256 | #define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 | ||
257 | #define TX4937_CCFG_PCIDIVMODE_8 0x00000000 | ||
258 | #define TX4937_CCFG_PCIDIVMODE_4 0x00000400 | ||
259 | #define TX4937_CCFG_PCIDIVMODE_9 0x00000800 | ||
260 | #define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00 | ||
261 | #define TX4937_CCFG_PCIDIVMODE_10 0x00001000 | ||
262 | #define TX4937_CCFG_PCIDIVMODE_5 0x00001400 | ||
263 | #define TX4937_CCFG_PCIDIVMODE_11 0x00001800 | ||
264 | #define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00 | ||
265 | |||
256 | /* PCFG : Pin Configuration */ | 266 | /* PCFG : Pin Configuration */ |
257 | #define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 | 267 | #define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 |
258 | #define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) | 268 | #define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) |
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h index 41bb96bb2120..91d813a37823 100644 --- a/include/asm-mips/uaccess.h +++ b/include/asm-mips/uaccess.h | |||
@@ -202,49 +202,49 @@ struct __large_struct { unsigned long buf[100]; }; | |||
202 | * Yuck. We need two variants, one for 64bit operation and one | 202 | * Yuck. We need two variants, one for 64bit operation and one |
203 | * for 32 bit mode and old iron. | 203 | * for 32 bit mode and old iron. |
204 | */ | 204 | */ |
205 | #ifdef __mips64 | 205 | #ifdef CONFIG_32BIT |
206 | #define __GET_USER_DW(ptr) __get_user_asm("ld", ptr) | 206 | #define __GET_USER_DW(val, ptr) __get_user_asm_ll32(val, ptr) |
207 | #else | 207 | #endif |
208 | #define __GET_USER_DW(ptr) __get_user_asm_ll32(ptr) | 208 | #ifdef CONFIG_64BIT |
209 | #define __GET_USER_DW(val, ptr) __get_user_asm(val, "ld", ptr) | ||
209 | #endif | 210 | #endif |
210 | 211 | ||
211 | #define __get_user_nocheck(x,ptr,size) \ | 212 | extern void __get_user_unknown(void); |
212 | ({ \ | 213 | |
213 | __typeof(*(ptr)) __gu_val = (__typeof(*(ptr))) 0; \ | 214 | #define __get_user_common(val, size, ptr) \ |
214 | long __gu_err = 0; \ | 215 | do { \ |
215 | \ | ||
216 | switch (size) { \ | 216 | switch (size) { \ |
217 | case 1: __get_user_asm("lb", ptr); break; \ | 217 | case 1: __get_user_asm(val, "lb", ptr); break; \ |
218 | case 2: __get_user_asm("lh", ptr); break; \ | 218 | case 2: __get_user_asm(val, "lh", ptr); break; \ |
219 | case 4: __get_user_asm("lw", ptr); break; \ | 219 | case 4: __get_user_asm(val, "lw", ptr); break; \ |
220 | case 8: __GET_USER_DW(ptr); break; \ | 220 | case 8: __GET_USER_DW(val, ptr); break; \ |
221 | default: __get_user_unknown(); break; \ | 221 | default: __get_user_unknown(); break; \ |
222 | } \ | 222 | } \ |
223 | (x) = (__typeof__(*(ptr))) __gu_val; \ | 223 | } while (0) |
224 | |||
225 | #define __get_user_nocheck(x,ptr,size) \ | ||
226 | ({ \ | ||
227 | long __gu_err; \ | ||
228 | \ | ||
229 | __get_user_common((x), size, ptr); \ | ||
224 | __gu_err; \ | 230 | __gu_err; \ |
225 | }) | 231 | }) |
226 | 232 | ||
227 | #define __get_user_check(x,ptr,size) \ | 233 | #define __get_user_check(x,ptr,size) \ |
228 | ({ \ | 234 | ({ \ |
229 | const __typeof__(*(ptr)) __user * __gu_addr = (ptr); \ | ||
230 | __typeof__(*(ptr)) __gu_val = 0; \ | ||
231 | long __gu_err = -EFAULT; \ | 235 | long __gu_err = -EFAULT; \ |
236 | const void __user * __gu_ptr = (ptr); \ | ||
237 | \ | ||
238 | if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) \ | ||
239 | __get_user_common((x), size, __gu_ptr); \ | ||
232 | \ | 240 | \ |
233 | if (likely(access_ok(VERIFY_READ, __gu_addr, size))) { \ | ||
234 | switch (size) { \ | ||
235 | case 1: __get_user_asm("lb", __gu_addr); break; \ | ||
236 | case 2: __get_user_asm("lh", __gu_addr); break; \ | ||
237 | case 4: __get_user_asm("lw", __gu_addr); break; \ | ||
238 | case 8: __GET_USER_DW(__gu_addr); break; \ | ||
239 | default: __get_user_unknown(); break; \ | ||
240 | } \ | ||
241 | } \ | ||
242 | (x) = (__typeof__(*(ptr))) __gu_val; \ | ||
243 | __gu_err; \ | 241 | __gu_err; \ |
244 | }) | 242 | }) |
245 | 243 | ||
246 | #define __get_user_asm(insn, addr) \ | 244 | #define __get_user_asm(val, insn, addr) \ |
247 | { \ | 245 | { \ |
246 | long __gu_tmp; \ | ||
247 | \ | ||
248 | __asm__ __volatile__( \ | 248 | __asm__ __volatile__( \ |
249 | "1: " insn " %1, %3 \n" \ | 249 | "1: " insn " %1, %3 \n" \ |
250 | "2: \n" \ | 250 | "2: \n" \ |
@@ -255,14 +255,16 @@ struct __large_struct { unsigned long buf[100]; }; | |||
255 | " .section __ex_table,\"a\" \n" \ | 255 | " .section __ex_table,\"a\" \n" \ |
256 | " "__UA_ADDR "\t1b, 3b \n" \ | 256 | " "__UA_ADDR "\t1b, 3b \n" \ |
257 | " .previous \n" \ | 257 | " .previous \n" \ |
258 | : "=r" (__gu_err), "=r" (__gu_val) \ | 258 | : "=r" (__gu_err), "=r" (__gu_tmp) \ |
259 | : "0" (0), "o" (__m(addr)), "i" (-EFAULT)); \ | 259 | : "0" (0), "o" (__m(addr)), "i" (-EFAULT)); \ |
260 | \ | ||
261 | (val) = (__typeof__(val)) __gu_tmp; \ | ||
260 | } | 262 | } |
261 | 263 | ||
262 | /* | 264 | /* |
263 | * Get a long long 64 using 32 bit registers. | 265 | * Get a long long 64 using 32 bit registers. |
264 | */ | 266 | */ |
265 | #define __get_user_asm_ll32(addr) \ | 267 | #define __get_user_asm_ll32(val, addr) \ |
266 | { \ | 268 | { \ |
267 | __asm__ __volatile__( \ | 269 | __asm__ __volatile__( \ |
268 | "1: lw %1, (%3) \n" \ | 270 | "1: lw %1, (%3) \n" \ |
@@ -278,21 +280,20 @@ struct __large_struct { unsigned long buf[100]; }; | |||
278 | " " __UA_ADDR " 1b, 4b \n" \ | 280 | " " __UA_ADDR " 1b, 4b \n" \ |
279 | " " __UA_ADDR " 2b, 4b \n" \ | 281 | " " __UA_ADDR " 2b, 4b \n" \ |
280 | " .previous \n" \ | 282 | " .previous \n" \ |
281 | : "=r" (__gu_err), "=&r" (__gu_val) \ | 283 | : "=r" (__gu_err), "=&r" (val) \ |
282 | : "0" (0), "r" (addr), "i" (-EFAULT)); \ | 284 | : "0" (0), "r" (addr), "i" (-EFAULT)); \ |
283 | } | 285 | } |
284 | 286 | ||
285 | extern void __get_user_unknown(void); | ||
286 | |||
287 | /* | 287 | /* |
288 | * Yuck. We need two variants, one for 64bit operation and one | 288 | * Yuck. We need two variants, one for 64bit operation and one |
289 | * for 32 bit mode and old iron. | 289 | * for 32 bit mode and old iron. |
290 | */ | 290 | */ |
291 | #ifdef __mips64 | 291 | #ifdef CONFIG_32BIT |
292 | #define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr) | ||
293 | #else | ||
294 | #define __PUT_USER_DW(ptr) __put_user_asm_ll32(ptr) | 292 | #define __PUT_USER_DW(ptr) __put_user_asm_ll32(ptr) |
295 | #endif | 293 | #endif |
294 | #ifdef CONFIG_64BIT | ||
295 | #define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr) | ||
296 | #endif | ||
296 | 297 | ||
297 | #define __put_user_nocheck(x,ptr,size) \ | 298 | #define __put_user_nocheck(x,ptr,size) \ |
298 | ({ \ | 299 | ({ \ |
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h index 89ea8b60e945..e7ff9b187783 100644 --- a/include/asm-mips/unistd.h +++ b/include/asm-mips/unistd.h | |||
@@ -307,17 +307,33 @@ | |||
307 | #define __NR_inotify_init (__NR_Linux + 284) | 307 | #define __NR_inotify_init (__NR_Linux + 284) |
308 | #define __NR_inotify_add_watch (__NR_Linux + 285) | 308 | #define __NR_inotify_add_watch (__NR_Linux + 285) |
309 | #define __NR_inotify_rm_watch (__NR_Linux + 286) | 309 | #define __NR_inotify_rm_watch (__NR_Linux + 286) |
310 | 310 | #define __NR_migrate_pages (__NR_Linux + 287) | |
311 | #define __NR_openat (__NR_Linux + 288) | ||
312 | #define __NR_mkdirat (__NR_Linux + 289) | ||
313 | #define __NR_mknodat (__NR_Linux + 290) | ||
314 | #define __NR_fchownat (__NR_Linux + 291) | ||
315 | #define __NR_futimesat (__NR_Linux + 292) | ||
316 | #define __NR_newfstatat (__NR_Linux + 293) | ||
317 | #define __NR_unlinkat (__NR_Linux + 294) | ||
318 | #define __NR_renameat (__NR_Linux + 295) | ||
319 | #define __NR_linkat (__NR_Linux + 296) | ||
320 | #define __NR_symlinkat (__NR_Linux + 297) | ||
321 | #define __NR_readlinkat (__NR_Linux + 298) | ||
322 | #define __NR_fchmodat (__NR_Linux + 299) | ||
323 | #define __NR_faccessat (__NR_Linux + 300) | ||
324 | #define __NR_pselect6 (__NR_Linux + 301) | ||
325 | #define __NR_ppoll (__NR_Linux + 302) | ||
326 | #define __NR_unshare (__NR_Linux + 303) | ||
311 | 327 | ||
312 | /* | 328 | /* |
313 | * Offset of the last Linux o32 flavoured syscall | 329 | * Offset of the last Linux o32 flavoured syscall |
314 | */ | 330 | */ |
315 | #define __NR_Linux_syscalls 286 | 331 | #define __NR_Linux_syscalls 303 |
316 | 332 | ||
317 | #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ | 333 | #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ |
318 | 334 | ||
319 | #define __NR_O32_Linux 4000 | 335 | #define __NR_O32_Linux 4000 |
320 | #define __NR_O32_Linux_syscalls 283 | 336 | #define __NR_O32_Linux_syscalls 303 |
321 | 337 | ||
322 | #if _MIPS_SIM == _MIPS_SIM_ABI64 | 338 | #if _MIPS_SIM == _MIPS_SIM_ABI64 |
323 | 339 | ||
@@ -571,16 +587,33 @@ | |||
571 | #define __NR_inotify_init (__NR_Linux + 243) | 587 | #define __NR_inotify_init (__NR_Linux + 243) |
572 | #define __NR_inotify_add_watch (__NR_Linux + 244) | 588 | #define __NR_inotify_add_watch (__NR_Linux + 244) |
573 | #define __NR_inotify_rm_watch (__NR_Linux + 245) | 589 | #define __NR_inotify_rm_watch (__NR_Linux + 245) |
590 | #define __NR_migrate_pages (__NR_Linux + 246) | ||
591 | #define __NR_openat (__NR_Linux + 247) | ||
592 | #define __NR_mkdirat (__NR_Linux + 248) | ||
593 | #define __NR_mknodat (__NR_Linux + 249) | ||
594 | #define __NR_fchownat (__NR_Linux + 250) | ||
595 | #define __NR_futimesat (__NR_Linux + 251) | ||
596 | #define __NR_newfstatat (__NR_Linux + 252) | ||
597 | #define __NR_unlinkat (__NR_Linux + 253) | ||
598 | #define __NR_renameat (__NR_Linux + 254) | ||
599 | #define __NR_linkat (__NR_Linux + 255) | ||
600 | #define __NR_symlinkat (__NR_Linux + 256) | ||
601 | #define __NR_readlinkat (__NR_Linux + 257) | ||
602 | #define __NR_fchmodat (__NR_Linux + 258) | ||
603 | #define __NR_faccessat (__NR_Linux + 259) | ||
604 | #define __NR_pselect6 (__NR_Linux + 260) | ||
605 | #define __NR_ppoll (__NR_Linux + 261) | ||
606 | #define __NR_unshare (__NR_Linux + 262) | ||
574 | 607 | ||
575 | /* | 608 | /* |
576 | * Offset of the last Linux 64-bit flavoured syscall | 609 | * Offset of the last Linux 64-bit flavoured syscall |
577 | */ | 610 | */ |
578 | #define __NR_Linux_syscalls 245 | 611 | #define __NR_Linux_syscalls 262 |
579 | 612 | ||
580 | #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ | 613 | #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ |
581 | 614 | ||
582 | #define __NR_64_Linux 5000 | 615 | #define __NR_64_Linux 5000 |
583 | #define __NR_64_Linux_syscalls 242 | 616 | #define __NR_64_Linux_syscalls 262 |
584 | 617 | ||
585 | #if _MIPS_SIM == _MIPS_SIM_NABI32 | 618 | #if _MIPS_SIM == _MIPS_SIM_NABI32 |
586 | 619 | ||
@@ -838,16 +871,33 @@ | |||
838 | #define __NR_inotify_init (__NR_Linux + 247) | 871 | #define __NR_inotify_init (__NR_Linux + 247) |
839 | #define __NR_inotify_add_watch (__NR_Linux + 248) | 872 | #define __NR_inotify_add_watch (__NR_Linux + 248) |
840 | #define __NR_inotify_rm_watch (__NR_Linux + 249) | 873 | #define __NR_inotify_rm_watch (__NR_Linux + 249) |
874 | #define __NR_migrate_pages (__NR_Linux + 250) | ||
875 | #define __NR_openat (__NR_Linux + 251) | ||
876 | #define __NR_mkdirat (__NR_Linux + 252) | ||
877 | #define __NR_mknodat (__NR_Linux + 253) | ||
878 | #define __NR_fchownat (__NR_Linux + 254) | ||
879 | #define __NR_futimesat (__NR_Linux + 255) | ||
880 | #define __NR_newfstatat (__NR_Linux + 256) | ||
881 | #define __NR_unlinkat (__NR_Linux + 257) | ||
882 | #define __NR_renameat (__NR_Linux + 258) | ||
883 | #define __NR_linkat (__NR_Linux + 259) | ||
884 | #define __NR_symlinkat (__NR_Linux + 260) | ||
885 | #define __NR_readlinkat (__NR_Linux + 261) | ||
886 | #define __NR_fchmodat (__NR_Linux + 262) | ||
887 | #define __NR_faccessat (__NR_Linux + 263) | ||
888 | #define __NR_pselect6 (__NR_Linux + 264) | ||
889 | #define __NR_ppoll (__NR_Linux + 265) | ||
890 | #define __NR_unshare (__NR_Linux + 266) | ||
841 | 891 | ||
842 | /* | 892 | /* |
843 | * Offset of the last N32 flavoured syscall | 893 | * Offset of the last N32 flavoured syscall |
844 | */ | 894 | */ |
845 | #define __NR_Linux_syscalls 249 | 895 | #define __NR_Linux_syscalls 266 |
846 | 896 | ||
847 | #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ | 897 | #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ |
848 | 898 | ||
849 | #define __NR_N32_Linux 6000 | 899 | #define __NR_N32_Linux 6000 |
850 | #define __NR_N32_Linux_syscalls 246 | 900 | #define __NR_N32_Linux_syscalls 266 |
851 | 901 | ||
852 | #ifndef __ASSEMBLY__ | 902 | #ifndef __ASSEMBLY__ |
853 | 903 | ||
diff --git a/include/asm-powerpc/compat.h b/include/asm-powerpc/compat.h index accb80c9a339..aacaabd28ac1 100644 --- a/include/asm-powerpc/compat.h +++ b/include/asm-powerpc/compat.h | |||
@@ -126,6 +126,11 @@ static inline void __user *compat_ptr(compat_uptr_t uptr) | |||
126 | return (void __user *)(unsigned long)uptr; | 126 | return (void __user *)(unsigned long)uptr; |
127 | } | 127 | } |
128 | 128 | ||
129 | static inline compat_uptr_t ptr_to_compat(void __user *uptr) | ||
130 | { | ||
131 | return (u32)(unsigned long)uptr; | ||
132 | } | ||
133 | |||
129 | static inline void __user *compat_alloc_user_space(long len) | 134 | static inline void __user *compat_alloc_user_space(long len) |
130 | { | 135 | { |
131 | struct pt_regs *regs = current->thread.regs; | 136 | struct pt_regs *regs = current->thread.regs; |
diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h index 837756ab7dc7..2ac63f569592 100644 --- a/include/asm-powerpc/dma-mapping.h +++ b/include/asm-powerpc/dma-mapping.h | |||
@@ -15,7 +15,6 @@ | |||
15 | #include <linux/mm.h> | 15 | #include <linux/mm.h> |
16 | #include <asm/scatterlist.h> | 16 | #include <asm/scatterlist.h> |
17 | #include <asm/io.h> | 17 | #include <asm/io.h> |
18 | #include <asm/bug.h> | ||
19 | 18 | ||
20 | #define DMA_ERROR_CODE (~(dma_addr_t)0x0) | 19 | #define DMA_ERROR_CODE (~(dma_addr_t)0x0) |
21 | 20 | ||
diff --git a/include/asm-powerpc/smu.h b/include/asm-powerpc/smu.h index 82ce47607774..2dc93632f210 100644 --- a/include/asm-powerpc/smu.h +++ b/include/asm-powerpc/smu.h | |||
@@ -521,6 +521,11 @@ struct smu_sdbp_cpupiddata { | |||
521 | extern struct smu_sdbp_header *smu_get_sdb_partition(int id, | 521 | extern struct smu_sdbp_header *smu_get_sdb_partition(int id, |
522 | unsigned int *size); | 522 | unsigned int *size); |
523 | 523 | ||
524 | /* Get "sdb" partition data from an SMU satellite */ | ||
525 | extern struct smu_sdbp_header *smu_sat_get_sdb_partition(unsigned int sat_id, | ||
526 | int id, unsigned int *size); | ||
527 | |||
528 | |||
524 | #endif /* __KERNEL__ */ | 529 | #endif /* __KERNEL__ */ |
525 | 530 | ||
526 | 531 | ||
diff --git a/include/asm-powerpc/thread_info.h b/include/asm-powerpc/thread_info.h index 67cdaf3ae9fc..c044ec16a879 100644 --- a/include/asm-powerpc/thread_info.h +++ b/include/asm-powerpc/thread_info.h | |||
@@ -37,7 +37,7 @@ struct thread_info { | |||
37 | int preempt_count; /* 0 => preemptable, | 37 | int preempt_count; /* 0 => preemptable, |
38 | <0 => BUG */ | 38 | <0 => BUG */ |
39 | struct restart_block restart_block; | 39 | struct restart_block restart_block; |
40 | void *nvgprs_frame; | 40 | void __user *nvgprs_frame; |
41 | /* low level flags - has atomic operations done on it */ | 41 | /* low level flags - has atomic operations done on it */ |
42 | unsigned long flags ____cacheline_aligned_in_smp; | 42 | unsigned long flags ____cacheline_aligned_in_smp; |
43 | }; | 43 | }; |
diff --git a/include/asm-powerpc/unistd.h b/include/asm-powerpc/unistd.h index a40cdff21a88..35556993f066 100644 --- a/include/asm-powerpc/unistd.h +++ b/include/asm-powerpc/unistd.h | |||
@@ -300,8 +300,9 @@ | |||
300 | #define __NR_spu_create 279 | 300 | #define __NR_spu_create 279 |
301 | #define __NR_pselect6 280 | 301 | #define __NR_pselect6 280 |
302 | #define __NR_ppoll 281 | 302 | #define __NR_ppoll 281 |
303 | #define __NR_unshare 282 | ||
303 | 304 | ||
304 | #define __NR_syscalls 282 | 305 | #define __NR_syscalls 283 |
305 | 306 | ||
306 | #ifdef __KERNEL__ | 307 | #ifdef __KERNEL__ |
307 | #define __NR__exit __NR_exit | 308 | #define __NR__exit __NR_exit |
diff --git a/include/asm-s390/uaccess.h b/include/asm-s390/uaccess.h index be104f21c70a..0b7c0ca4c3d7 100644 --- a/include/asm-s390/uaccess.h +++ b/include/asm-s390/uaccess.h | |||
@@ -61,7 +61,7 @@ | |||
61 | #define segment_eq(a,b) ((a).ar4 == (b).ar4) | 61 | #define segment_eq(a,b) ((a).ar4 == (b).ar4) |
62 | 62 | ||
63 | 63 | ||
64 | static inline int __access_ok(const void *addr, unsigned long size) | 64 | static inline int __access_ok(const void __user *addr, unsigned long size) |
65 | { | 65 | { |
66 | return 1; | 66 | return 1; |
67 | } | 67 | } |
@@ -208,25 +208,25 @@ extern int __put_user_bad(void) __attribute__((noreturn)); | |||
208 | case 1: { \ | 208 | case 1: { \ |
209 | unsigned char __x; \ | 209 | unsigned char __x; \ |
210 | __get_user_asm(__x, ptr, __gu_err); \ | 210 | __get_user_asm(__x, ptr, __gu_err); \ |
211 | (x) = *(__typeof__(*(ptr)) *) &__x; \ | 211 | (x) = *(__force __typeof__(*(ptr)) *) &__x; \ |
212 | break; \ | 212 | break; \ |
213 | }; \ | 213 | }; \ |
214 | case 2: { \ | 214 | case 2: { \ |
215 | unsigned short __x; \ | 215 | unsigned short __x; \ |
216 | __get_user_asm(__x, ptr, __gu_err); \ | 216 | __get_user_asm(__x, ptr, __gu_err); \ |
217 | (x) = *(__typeof__(*(ptr)) *) &__x; \ | 217 | (x) = *(__force __typeof__(*(ptr)) *) &__x; \ |
218 | break; \ | 218 | break; \ |
219 | }; \ | 219 | }; \ |
220 | case 4: { \ | 220 | case 4: { \ |
221 | unsigned int __x; \ | 221 | unsigned int __x; \ |
222 | __get_user_asm(__x, ptr, __gu_err); \ | 222 | __get_user_asm(__x, ptr, __gu_err); \ |
223 | (x) = *(__typeof__(*(ptr)) *) &__x; \ | 223 | (x) = *(__force __typeof__(*(ptr)) *) &__x; \ |
224 | break; \ | 224 | break; \ |
225 | }; \ | 225 | }; \ |
226 | case 8: { \ | 226 | case 8: { \ |
227 | unsigned long long __x; \ | 227 | unsigned long long __x; \ |
228 | __get_user_asm(__x, ptr, __gu_err); \ | 228 | __get_user_asm(__x, ptr, __gu_err); \ |
229 | (x) = *(__typeof__(*(ptr)) *) &__x; \ | 229 | (x) = *(__force __typeof__(*(ptr)) *) &__x; \ |
230 | break; \ | 230 | break; \ |
231 | }; \ | 231 | }; \ |
232 | default: \ | 232 | default: \ |
diff --git a/include/asm-sparc/unistd.h b/include/asm-sparc/unistd.h index 2ac64e65e336..0615d601a7c6 100644 --- a/include/asm-sparc/unistd.h +++ b/include/asm-sparc/unistd.h | |||
@@ -315,11 +315,12 @@ | |||
315 | #define __NR_faccessat 296 | 315 | #define __NR_faccessat 296 |
316 | #define __NR_pselect6 297 | 316 | #define __NR_pselect6 297 |
317 | #define __NR_ppoll 298 | 317 | #define __NR_ppoll 298 |
318 | #define __NR_unshare 299 | ||
318 | 319 | ||
319 | /* WARNING: You MAY NOT add syscall numbers larger than 298, since | 320 | /* WARNING: You MAY NOT add syscall numbers larger than 299, since |
320 | * all of the syscall tables in the Sparc kernel are | 321 | * all of the syscall tables in the Sparc kernel are |
321 | * sized to have 298 entries (starting at zero). Therefore | 322 | * sized to have 299 entries (starting at zero). Therefore |
322 | * find a free slot in the 0-298 range. | 323 | * find a free slot in the 0-299 range. |
323 | */ | 324 | */ |
324 | 325 | ||
325 | #define _syscall0(type,name) \ | 326 | #define _syscall0(type,name) \ |
diff --git a/include/asm-sparc64/unistd.h b/include/asm-sparc64/unistd.h index 84ac2bdb0902..c58ba8a096cf 100644 --- a/include/asm-sparc64/unistd.h +++ b/include/asm-sparc64/unistd.h | |||
@@ -317,11 +317,12 @@ | |||
317 | #define __NR_faccessat 296 | 317 | #define __NR_faccessat 296 |
318 | #define __NR_pselect6 297 | 318 | #define __NR_pselect6 297 |
319 | #define __NR_ppoll 298 | 319 | #define __NR_ppoll 298 |
320 | #define __NR_unshare 299 | ||
320 | 321 | ||
321 | /* WARNING: You MAY NOT add syscall numbers larger than 298, since | 322 | /* WARNING: You MAY NOT add syscall numbers larger than 299, since |
322 | * all of the syscall tables in the Sparc kernel are | 323 | * all of the syscall tables in the Sparc kernel are |
323 | * sized to have 298 entries (starting at zero). Therefore | 324 | * sized to have 299 entries (starting at zero). Therefore |
324 | * find a free slot in the 0-298 range. | 325 | * find a free slot in the 0-299 range. |
325 | */ | 326 | */ |
326 | 327 | ||
327 | #define _syscall0(type,name) \ | 328 | #define _syscall0(type,name) \ |
diff --git a/include/asm-x86_64/ia32_unistd.h b/include/asm-x86_64/ia32_unistd.h index 9afc0c7d3661..20468983d453 100644 --- a/include/asm-x86_64/ia32_unistd.h +++ b/include/asm-x86_64/ia32_unistd.h | |||
@@ -313,7 +313,10 @@ | |||
313 | #define __NR_ia32_readlinkat 305 | 313 | #define __NR_ia32_readlinkat 305 |
314 | #define __NR_ia32_fchmodat 306 | 314 | #define __NR_ia32_fchmodat 306 |
315 | #define __NR_ia32_faccessat 307 | 315 | #define __NR_ia32_faccessat 307 |
316 | #define __NR_ia32_pselect6 308 | ||
317 | #define __NR_ia32_ppoll 309 | ||
318 | #define __NR_ia32_unshare 310 | ||
316 | 319 | ||
317 | #define IA32_NR_syscalls 308 /* must be > than biggest syscall! */ | 320 | #define IA32_NR_syscalls 315 /* must be > than biggest syscall! */ |
318 | 321 | ||
319 | #endif /* _ASM_X86_64_IA32_UNISTD_H_ */ | 322 | #endif /* _ASM_X86_64_IA32_UNISTD_H_ */ |
diff --git a/include/asm-x86_64/numa.h b/include/asm-x86_64/numa.h index 34e434ce3268..dffe276ca2df 100644 --- a/include/asm-x86_64/numa.h +++ b/include/asm-x86_64/numa.h | |||
@@ -22,8 +22,15 @@ extern void numa_set_node(int cpu, int node); | |||
22 | extern unsigned char apicid_to_node[256]; | 22 | extern unsigned char apicid_to_node[256]; |
23 | #ifdef CONFIG_NUMA | 23 | #ifdef CONFIG_NUMA |
24 | extern void __init init_cpu_to_node(void); | 24 | extern void __init init_cpu_to_node(void); |
25 | |||
26 | static inline void clear_node_cpumask(int cpu) | ||
27 | { | ||
28 | clear_bit(cpu, &node_to_cpumask[cpu_to_node(cpu)]); | ||
29 | } | ||
30 | |||
25 | #else | 31 | #else |
26 | #define init_cpu_to_node() do {} while (0) | 32 | #define init_cpu_to_node() do {} while (0) |
33 | #define clear_node_cpumask(cpu) do {} while (0) | ||
27 | #endif | 34 | #endif |
28 | 35 | ||
29 | #define NUMA_NO_NODE 0xff | 36 | #define NUMA_NO_NODE 0xff |
diff --git a/include/asm-x86_64/unistd.h b/include/asm-x86_64/unistd.h index 436d099b5b6b..da0341c57949 100644 --- a/include/asm-x86_64/unistd.h +++ b/include/asm-x86_64/unistd.h | |||
@@ -599,8 +599,14 @@ __SYSCALL(__NR_readlinkat, sys_readlinkat) | |||
599 | __SYSCALL(__NR_fchmodat, sys_fchmodat) | 599 | __SYSCALL(__NR_fchmodat, sys_fchmodat) |
600 | #define __NR_faccessat 269 | 600 | #define __NR_faccessat 269 |
601 | __SYSCALL(__NR_faccessat, sys_faccessat) | 601 | __SYSCALL(__NR_faccessat, sys_faccessat) |
602 | 602 | #define __NR_pselect6 270 | |
603 | #define __NR_syscall_max __NR_faccessat | 603 | __SYSCALL(__NR_pselect6, sys_ni_syscall) /* for now */ |
604 | #define __NR_ppoll 271 | ||
605 | __SYSCALL(__NR_ppoll, sys_ni_syscall) /* for now */ | ||
606 | #define __NR_unshare 272 | ||
607 | __SYSCALL(__NR_unshare, sys_unshare) | ||
608 | |||
609 | #define __NR_syscall_max __NR_unshare | ||
604 | 610 | ||
605 | #ifndef __NO_STUBS | 611 | #ifndef __NO_STUBS |
606 | 612 | ||
diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h index 13e9f4a3ab26..20b446f26ecd 100644 --- a/include/linux/cpumask.h +++ b/include/linux/cpumask.h | |||
@@ -84,7 +84,6 @@ | |||
84 | #include <linux/kernel.h> | 84 | #include <linux/kernel.h> |
85 | #include <linux/threads.h> | 85 | #include <linux/threads.h> |
86 | #include <linux/bitmap.h> | 86 | #include <linux/bitmap.h> |
87 | #include <asm/bug.h> | ||
88 | 87 | ||
89 | typedef struct { DECLARE_BITMAP(bits, NR_CPUS); } cpumask_t; | 88 | typedef struct { DECLARE_BITMAP(bits, NR_CPUS); } cpumask_t; |
90 | extern cpumask_t _unused_cpumask_arg_; | 89 | extern cpumask_t _unused_cpumask_arg_; |
diff --git a/include/linux/dcache.h b/include/linux/dcache.h index a3f09947940e..4361f3789975 100644 --- a/include/linux/dcache.h +++ b/include/linux/dcache.h | |||
@@ -8,7 +8,6 @@ | |||
8 | #include <linux/spinlock.h> | 8 | #include <linux/spinlock.h> |
9 | #include <linux/cache.h> | 9 | #include <linux/cache.h> |
10 | #include <linux/rcupdate.h> | 10 | #include <linux/rcupdate.h> |
11 | #include <asm/bug.h> | ||
12 | 11 | ||
13 | struct nameidata; | 12 | struct nameidata; |
14 | struct vfsmount; | 13 | struct vfsmount; |
diff --git a/include/linux/dvb/video.h b/include/linux/dvb/video.h index b1999bfeaa56..b81e58b2ebf8 100644 --- a/include/linux/dvb/video.h +++ b/include/linux/dvb/video.h | |||
@@ -135,7 +135,7 @@ typedef struct video_spu { | |||
135 | 135 | ||
136 | typedef struct video_spu_palette { /* SPU Palette information */ | 136 | typedef struct video_spu_palette { /* SPU Palette information */ |
137 | int length; | 137 | int length; |
138 | uint8_t *palette; | 138 | uint8_t __user *palette; |
139 | } video_spu_palette_t; | 139 | } video_spu_palette_t; |
140 | 140 | ||
141 | 141 | ||
diff --git a/include/linux/elevator.h b/include/linux/elevator.h index 23fe746a1d51..18cf1f3e1184 100644 --- a/include/linux/elevator.h +++ b/include/linux/elevator.h | |||
@@ -82,6 +82,7 @@ struct elevator_queue | |||
82 | extern void elv_dispatch_sort(request_queue_t *, struct request *); | 82 | extern void elv_dispatch_sort(request_queue_t *, struct request *); |
83 | extern void elv_add_request(request_queue_t *, struct request *, int, int); | 83 | extern void elv_add_request(request_queue_t *, struct request *, int, int); |
84 | extern void __elv_add_request(request_queue_t *, struct request *, int, int); | 84 | extern void __elv_add_request(request_queue_t *, struct request *, int, int); |
85 | extern void elv_insert(request_queue_t *, struct request *, int); | ||
85 | extern int elv_merge(request_queue_t *, struct request **, struct bio *); | 86 | extern int elv_merge(request_queue_t *, struct request **, struct bio *); |
86 | extern void elv_merge_requests(request_queue_t *, struct request *, | 87 | extern void elv_merge_requests(request_queue_t *, struct request *, |
87 | struct request *); | 88 | struct request *); |
diff --git a/include/linux/i2c.h b/include/linux/i2c.h index 7863a59bd598..63f1d63cc1d8 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h | |||
@@ -100,6 +100,9 @@ extern s32 i2c_smbus_write_block_data(struct i2c_client * client, | |||
100 | /* Returns the number of read bytes */ | 100 | /* Returns the number of read bytes */ |
101 | extern s32 i2c_smbus_read_i2c_block_data(struct i2c_client * client, | 101 | extern s32 i2c_smbus_read_i2c_block_data(struct i2c_client * client, |
102 | u8 command, u8 *values); | 102 | u8 command, u8 *values); |
103 | extern s32 i2c_smbus_write_i2c_block_data(struct i2c_client * client, | ||
104 | u8 command, u8 length, | ||
105 | u8 *values); | ||
103 | 106 | ||
104 | /* | 107 | /* |
105 | * A driver is capable of handling one or more physical devices present on | 108 | * A driver is capable of handling one or more physical devices present on |
diff --git a/include/linux/ioc3.h b/include/linux/ioc3.h index e7906a72a4f1..da7c09e4ede6 100644 --- a/include/linux/ioc3.h +++ b/include/linux/ioc3.h | |||
@@ -27,7 +27,7 @@ struct ioc3_driver_data { | |||
27 | int id; /* IOC3 sequence number */ | 27 | int id; /* IOC3 sequence number */ |
28 | /* PCI mapping */ | 28 | /* PCI mapping */ |
29 | unsigned long pma; /* physical address */ | 29 | unsigned long pma; /* physical address */ |
30 | struct __iomem ioc3 *vma; /* pointer to registers */ | 30 | struct ioc3 __iomem *vma; /* pointer to registers */ |
31 | struct pci_dev *pdev; /* PCI device */ | 31 | struct pci_dev *pdev; /* PCI device */ |
32 | /* IRQ stuff */ | 32 | /* IRQ stuff */ |
33 | int dual_irq; /* set if separate IRQs are used */ | 33 | int dual_irq; /* set if separate IRQs are used */ |
diff --git a/include/linux/jbd.h b/include/linux/jbd.h index 751bb3849467..0fe4aa891ddc 100644 --- a/include/linux/jbd.h +++ b/include/linux/jbd.h | |||
@@ -239,7 +239,6 @@ typedef struct journal_superblock_s | |||
239 | 239 | ||
240 | #include <linux/fs.h> | 240 | #include <linux/fs.h> |
241 | #include <linux/sched.h> | 241 | #include <linux/sched.h> |
242 | #include <asm/bug.h> | ||
243 | 242 | ||
244 | #define JBD_ASSERTIONS | 243 | #define JBD_ASSERTIONS |
245 | #ifdef JBD_ASSERTIONS | 244 | #ifdef JBD_ASSERTIONS |
diff --git a/include/linux/mm.h b/include/linux/mm.h index 85854b867463..75e9f0724997 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h | |||
@@ -303,7 +303,7 @@ struct page { | |||
303 | */ | 303 | */ |
304 | #define put_page_testzero(p) \ | 304 | #define put_page_testzero(p) \ |
305 | ({ \ | 305 | ({ \ |
306 | BUG_ON(page_count(p) == 0); \ | 306 | BUG_ON(atomic_read(&(p)->_count) == -1);\ |
307 | atomic_add_negative(-1, &(p)->_count); \ | 307 | atomic_add_negative(-1, &(p)->_count); \ |
308 | }) | 308 | }) |
309 | 309 | ||
diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h index fedfbc8a287f..7dfd6e1fcde7 100644 --- a/include/linux/mtd/map.h +++ b/include/linux/mtd/map.h | |||
@@ -15,7 +15,6 @@ | |||
15 | #include <asm/unaligned.h> | 15 | #include <asm/unaligned.h> |
16 | #include <asm/system.h> | 16 | #include <asm/system.h> |
17 | #include <asm/io.h> | 17 | #include <asm/io.h> |
18 | #include <asm/bug.h> | ||
19 | 18 | ||
20 | #ifdef CONFIG_MTD_MAP_BANK_WIDTH_1 | 19 | #ifdef CONFIG_MTD_MAP_BANK_WIDTH_1 |
21 | #define map_bankwidth(map) 1 | 20 | #define map_bankwidth(map) 1 |
diff --git a/include/linux/namespace.h b/include/linux/namespace.h index 6731977c4c13..3abc8e3b4879 100644 --- a/include/linux/namespace.h +++ b/include/linux/namespace.h | |||
@@ -15,6 +15,7 @@ struct namespace { | |||
15 | 15 | ||
16 | extern int copy_namespace(int, struct task_struct *); | 16 | extern int copy_namespace(int, struct task_struct *); |
17 | extern void __put_namespace(struct namespace *namespace); | 17 | extern void __put_namespace(struct namespace *namespace); |
18 | extern struct namespace *dup_namespace(struct task_struct *, struct fs_struct *); | ||
18 | 19 | ||
19 | static inline void put_namespace(struct namespace *namespace) | 20 | static inline void put_namespace(struct namespace *namespace) |
20 | { | 21 | { |
diff --git a/include/linux/nodemask.h b/include/linux/nodemask.h index 4726ef7ba8e8..b959a4525cbd 100644 --- a/include/linux/nodemask.h +++ b/include/linux/nodemask.h | |||
@@ -84,7 +84,6 @@ | |||
84 | #include <linux/threads.h> | 84 | #include <linux/threads.h> |
85 | #include <linux/bitmap.h> | 85 | #include <linux/bitmap.h> |
86 | #include <linux/numa.h> | 86 | #include <linux/numa.h> |
87 | #include <asm/bug.h> | ||
88 | 87 | ||
89 | typedef struct { DECLARE_BITMAP(bits, MAX_NUMNODES); } nodemask_t; | 88 | typedef struct { DECLARE_BITMAP(bits, MAX_NUMNODES); } nodemask_t; |
90 | extern nodemask_t _unused_nodemask_arg_; | 89 | extern nodemask_t _unused_nodemask_arg_; |
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 92a619ba163f..7a61ccdcbc4b 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h | |||
@@ -1832,6 +1832,7 @@ | |||
1832 | #define PCI_VENDOR_ID_AFAVLAB 0x14db | 1832 | #define PCI_VENDOR_ID_AFAVLAB 0x14db |
1833 | #define PCI_DEVICE_ID_AFAVLAB_P028 0x2180 | 1833 | #define PCI_DEVICE_ID_AFAVLAB_P028 0x2180 |
1834 | #define PCI_DEVICE_ID_AFAVLAB_P030 0x2182 | 1834 | #define PCI_DEVICE_ID_AFAVLAB_P030 0x2182 |
1835 | #define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150 | ||
1835 | 1836 | ||
1836 | #define PCI_VENDOR_ID_BROADCOM 0x14e4 | 1837 | #define PCI_VENDOR_ID_BROADCOM 0x14e4 |
1837 | #define PCI_DEVICE_ID_TIGON3_5752 0x1600 | 1838 | #define PCI_DEVICE_ID_TIGON3_5752 0x1600 |
diff --git a/include/linux/sched.h b/include/linux/sched.h index 0cfcd1c7865e..9c1da0269a18 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h | |||
@@ -1098,7 +1098,7 @@ extern struct sigqueue *sigqueue_alloc(void); | |||
1098 | extern void sigqueue_free(struct sigqueue *); | 1098 | extern void sigqueue_free(struct sigqueue *); |
1099 | extern int send_sigqueue(int, struct sigqueue *, struct task_struct *); | 1099 | extern int send_sigqueue(int, struct sigqueue *, struct task_struct *); |
1100 | extern int send_group_sigqueue(int, struct sigqueue *, struct task_struct *); | 1100 | extern int send_group_sigqueue(int, struct sigqueue *, struct task_struct *); |
1101 | extern int do_sigaction(int, const struct k_sigaction *, struct k_sigaction *); | 1101 | extern int do_sigaction(int, struct k_sigaction *, struct k_sigaction *); |
1102 | extern int do_sigaltstack(const stack_t __user *, stack_t __user *, unsigned long); | 1102 | extern int do_sigaltstack(const stack_t __user *, stack_t __user *, unsigned long); |
1103 | 1103 | ||
1104 | /* These can be the second arg to send_sig_info/send_group_sig_info. */ | 1104 | /* These can be the second arg to send_sig_info/send_group_sig_info. */ |
diff --git a/include/linux/smp.h b/include/linux/smp.h index 9dfa3ee769ae..44153fdf73fc 100644 --- a/include/linux/smp.h +++ b/include/linux/smp.h | |||
@@ -17,7 +17,6 @@ extern void cpu_idle(void); | |||
17 | #include <linux/compiler.h> | 17 | #include <linux/compiler.h> |
18 | #include <linux/thread_info.h> | 18 | #include <linux/thread_info.h> |
19 | #include <asm/smp.h> | 19 | #include <asm/smp.h> |
20 | #include <asm/bug.h> | ||
21 | 20 | ||
22 | /* | 21 | /* |
23 | * main cross-CPU interfaces, handles INIT, TLB flush, STOP, etc. | 22 | * main cross-CPU interfaces, handles INIT, TLB flush, STOP, etc. |
diff --git a/include/linux/suspend.h b/include/linux/suspend.h index 43bcd13eb1ec..37c1c76fd547 100644 --- a/include/linux/suspend.h +++ b/include/linux/suspend.h | |||
@@ -42,13 +42,21 @@ extern void mark_free_pages(struct zone *zone); | |||
42 | #ifdef CONFIG_PM | 42 | #ifdef CONFIG_PM |
43 | /* kernel/power/swsusp.c */ | 43 | /* kernel/power/swsusp.c */ |
44 | extern int software_suspend(void); | 44 | extern int software_suspend(void); |
45 | |||
46 | #if defined(CONFIG_VT) && defined(CONFIG_VT_CONSOLE) | ||
47 | extern int pm_prepare_console(void); | ||
48 | extern void pm_restore_console(void); | ||
49 | #else | ||
50 | static inline int pm_prepare_console(void) { return 0; } | ||
51 | static inline void pm_restore_console(void) {} | ||
52 | #endif /* defined(CONFIG_VT) && defined(CONFIG_VT_CONSOLE) */ | ||
45 | #else | 53 | #else |
46 | static inline int software_suspend(void) | 54 | static inline int software_suspend(void) |
47 | { | 55 | { |
48 | printk("Warning: fake suspend called\n"); | 56 | printk("Warning: fake suspend called\n"); |
49 | return -EPERM; | 57 | return -EPERM; |
50 | } | 58 | } |
51 | #endif | 59 | #endif /* CONFIG_PM */ |
52 | 60 | ||
53 | #ifdef CONFIG_SUSPEND_SMP | 61 | #ifdef CONFIG_SUSPEND_SMP |
54 | extern void disable_nonboot_cpus(void); | 62 | extern void disable_nonboot_cpus(void); |
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h index 6f6c69777648..5208b12d5550 100644 --- a/include/linux/videodev2.h +++ b/include/linux/videodev2.h | |||
@@ -549,7 +549,7 @@ struct v4l2_framebuffer | |||
549 | struct v4l2_clip | 549 | struct v4l2_clip |
550 | { | 550 | { |
551 | struct v4l2_rect c; | 551 | struct v4l2_rect c; |
552 | struct v4l2_clip *next; | 552 | struct v4l2_clip __user *next; |
553 | }; | 553 | }; |
554 | 554 | ||
555 | struct v4l2_window | 555 | struct v4l2_window |
@@ -629,6 +629,7 @@ typedef __u64 v4l2_std_id; | |||
629 | #define V4L2_STD_NTSC_M ((v4l2_std_id)0x00001000) | 629 | #define V4L2_STD_NTSC_M ((v4l2_std_id)0x00001000) |
630 | #define V4L2_STD_NTSC_M_JP ((v4l2_std_id)0x00002000) | 630 | #define V4L2_STD_NTSC_M_JP ((v4l2_std_id)0x00002000) |
631 | #define V4L2_STD_NTSC_443 ((v4l2_std_id)0x00004000) | 631 | #define V4L2_STD_NTSC_443 ((v4l2_std_id)0x00004000) |
632 | #define V4L2_STD_NTSC_M_KR ((v4l2_std_id)0x00008000) | ||
632 | 633 | ||
633 | #define V4L2_STD_SECAM_B ((v4l2_std_id)0x00010000) | 634 | #define V4L2_STD_SECAM_B ((v4l2_std_id)0x00010000) |
634 | #define V4L2_STD_SECAM_D ((v4l2_std_id)0x00020000) | 635 | #define V4L2_STD_SECAM_D ((v4l2_std_id)0x00020000) |
@@ -661,7 +662,8 @@ typedef __u64 v4l2_std_id; | |||
661 | V4L2_STD_PAL_H |\ | 662 | V4L2_STD_PAL_H |\ |
662 | V4L2_STD_PAL_I) | 663 | V4L2_STD_PAL_I) |
663 | #define V4L2_STD_NTSC (V4L2_STD_NTSC_M |\ | 664 | #define V4L2_STD_NTSC (V4L2_STD_NTSC_M |\ |
664 | V4L2_STD_NTSC_M_JP) | 665 | V4L2_STD_NTSC_M_JP |\ |
666 | V4L2_STD_NTSC_M_KR) | ||
665 | #define V4L2_STD_SECAM_DK (V4L2_STD_SECAM_D |\ | 667 | #define V4L2_STD_SECAM_DK (V4L2_STD_SECAM_D |\ |
666 | V4L2_STD_SECAM_K |\ | 668 | V4L2_STD_SECAM_K |\ |
667 | V4L2_STD_SECAM_K1) | 669 | V4L2_STD_SECAM_K1) |