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authorLinus Torvalds <torvalds@woody.osdl.org>2006-12-06 11:10:55 -0500
committerLinus Torvalds <torvalds@woody.osdl.org>2006-12-06 11:10:55 -0500
commitdd6a7c19e4630f635467246a81b8e0cc818c05e6 (patch)
tree8fc93cdef4070183cbd3fa06019c84728380b389 /include
parentdd8856bda5f1308beb113281b248683992998a9e (diff)
parentea0f8feaa041f3ccec3d6b8ee51325b177daef06 (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (43 commits) sh: sh775x/titan fixes for irq header changes. sh: update r7780rp defconfig. sh: compile fixes for header cleanup. sh: Fixup pte_mkhuge() build failure. sh: set KBUILD_IMAGE to something sensible. sh: show held locks in stack trace with lockdep. sh: platform_pata support for R7780RP sh: stacktrace/lockdep/irqflags tracing support. sh: Fixup movli.l/movco.l atomic ops for gcc4. sh: dyntick infrastructure. sh: Clock framework tidying. sh: Turn off IRQs around get_timer_offset() calls. sh: Get the PGD right in oops case with 64-bit PTEs. sh: Fix store queue bitmap end. sh: More flexible + SH7780 earlyprintk SCIF support. sh: Fixup various PAGE_SIZE == 4096 assumptions. sh: Fixup 4K irq stacks. sh: dma-api channel capability extensions. sh: Drop name overload in dma-sh. sh: Make dma-isa depend on ISA_DMA_API. ...
Diffstat (limited to 'include')
-rw-r--r--include/asm-sh/atomic.h48
-rw-r--r--include/asm-sh/bugs.h8
-rw-r--r--include/asm-sh/clock.h12
-rw-r--r--include/asm-sh/cpu-sh2/cache.h22
-rw-r--r--include/asm-sh/cpu-sh2/freq.h18
-rw-r--r--include/asm-sh/cpu-sh2/mmu_context.h16
-rw-r--r--include/asm-sh/cpu-sh2/timer.h6
-rw-r--r--include/asm-sh/cpu-sh2a/addrspace.h1
-rw-r--r--include/asm-sh/cpu-sh2a/cache.h39
-rw-r--r--include/asm-sh/cpu-sh2a/cacheflush.h1
-rw-r--r--include/asm-sh/cpu-sh2a/dma.h1
-rw-r--r--include/asm-sh/cpu-sh2a/freq.h18
-rw-r--r--include/asm-sh/cpu-sh2a/mmu_context.h1
-rw-r--r--include/asm-sh/cpu-sh2a/timer.h1
-rw-r--r--include/asm-sh/cpu-sh2a/ubc.h1
-rw-r--r--include/asm-sh/cpu-sh2a/watchdog.h1
-rw-r--r--include/asm-sh/dma.h40
-rw-r--r--include/asm-sh/elf.h2
-rw-r--r--include/asm-sh/entry-macros.S33
-rw-r--r--include/asm-sh/irq-sh73180.h314
-rw-r--r--include/asm-sh/irq-sh7343.h317
-rw-r--r--include/asm-sh/irq-sh7780.h311
-rw-r--r--include/asm-sh/irq.h620
-rw-r--r--include/asm-sh/irqflags.h123
-rw-r--r--include/asm-sh/mmu_context.h44
-rw-r--r--include/asm-sh/page.h35
-rw-r--r--include/asm-sh/pgalloc.h20
-rw-r--r--include/asm-sh/pgtable-2level.h70
-rw-r--r--include/asm-sh/pgtable.h371
-rw-r--r--include/asm-sh/processor.h24
-rw-r--r--include/asm-sh/push-switch.h28
-rw-r--r--include/asm-sh/rwsem.h27
-rw-r--r--include/asm-sh/se7206.h13
-rw-r--r--include/asm-sh/system.h101
-rw-r--r--include/asm-sh/thread_info.h8
-rw-r--r--include/asm-sh/timer.h23
-rw-r--r--include/asm-sh/titan.h32
-rw-r--r--include/asm-sh/unistd.h32
38 files changed, 869 insertions, 1913 deletions
diff --git a/include/asm-sh/atomic.h b/include/asm-sh/atomic.h
index 8bdc1ba56f73..28305c3cbddf 100644
--- a/include/asm-sh/atomic.h
+++ b/include/asm-sh/atomic.h
@@ -28,11 +28,11 @@ static inline void atomic_add(int i, atomic_t *v)
28 unsigned long tmp; 28 unsigned long tmp;
29 29
30 __asm__ __volatile__ ( 30 __asm__ __volatile__ (
31"1: movli.l @%3, %0 ! atomic_add \n" 31"1: movli.l @%2, %0 ! atomic_add \n"
32" add %2, %0 \n" 32" add %1, %0 \n"
33" movco.l %0, @%3 \n" 33" movco.l %0, @%2 \n"
34" bf 1b \n" 34" bf 1b \n"
35 : "=&z" (tmp), "=r" (&v->counter) 35 : "=&z" (tmp)
36 : "r" (i), "r" (&v->counter) 36 : "r" (i), "r" (&v->counter)
37 : "t"); 37 : "t");
38#else 38#else
@@ -50,11 +50,11 @@ static inline void atomic_sub(int i, atomic_t *v)
50 unsigned long tmp; 50 unsigned long tmp;
51 51
52 __asm__ __volatile__ ( 52 __asm__ __volatile__ (
53"1: movli.l @%3, %0 ! atomic_sub \n" 53"1: movli.l @%2, %0 ! atomic_sub \n"
54" sub %2, %0 \n" 54" sub %1, %0 \n"
55" movco.l %0, @%3 \n" 55" movco.l %0, @%2 \n"
56" bf 1b \n" 56" bf 1b \n"
57 : "=&z" (tmp), "=r" (&v->counter) 57 : "=&z" (tmp)
58 : "r" (i), "r" (&v->counter) 58 : "r" (i), "r" (&v->counter)
59 : "t"); 59 : "t");
60#else 60#else
@@ -80,12 +80,12 @@ static inline int atomic_add_return(int i, atomic_t *v)
80 80
81#ifdef CONFIG_CPU_SH4A 81#ifdef CONFIG_CPU_SH4A
82 __asm__ __volatile__ ( 82 __asm__ __volatile__ (
83"1: movli.l @%3, %0 ! atomic_add_return \n" 83"1: movli.l @%2, %0 ! atomic_add_return \n"
84" add %2, %0 \n" 84" add %1, %0 \n"
85" movco.l %0, @%3 \n" 85" movco.l %0, @%2 \n"
86" bf 1b \n" 86" bf 1b \n"
87" synco \n" 87" synco \n"
88 : "=&z" (temp), "=r" (&v->counter) 88 : "=&z" (temp)
89 : "r" (i), "r" (&v->counter) 89 : "r" (i), "r" (&v->counter)
90 : "t"); 90 : "t");
91#else 91#else
@@ -109,12 +109,12 @@ static inline int atomic_sub_return(int i, atomic_t *v)
109 109
110#ifdef CONFIG_CPU_SH4A 110#ifdef CONFIG_CPU_SH4A
111 __asm__ __volatile__ ( 111 __asm__ __volatile__ (
112"1: movli.l @%3, %0 ! atomic_sub_return \n" 112"1: movli.l @%2, %0 ! atomic_sub_return \n"
113" sub %2, %0 \n" 113" sub %1, %0 \n"
114" movco.l %0, @%3 \n" 114" movco.l %0, @%2 \n"
115" bf 1b \n" 115" bf 1b \n"
116" synco \n" 116" synco \n"
117 : "=&z" (temp), "=r" (&v->counter) 117 : "=&z" (temp)
118 : "r" (i), "r" (&v->counter) 118 : "r" (i), "r" (&v->counter)
119 : "t"); 119 : "t");
120#else 120#else
@@ -186,11 +186,11 @@ static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
186 unsigned long tmp; 186 unsigned long tmp;
187 187
188 __asm__ __volatile__ ( 188 __asm__ __volatile__ (
189"1: movli.l @%3, %0 ! atomic_clear_mask \n" 189"1: movli.l @%2, %0 ! atomic_clear_mask \n"
190" and %2, %0 \n" 190" and %1, %0 \n"
191" movco.l %0, @%3 \n" 191" movco.l %0, @%2 \n"
192" bf 1b \n" 192" bf 1b \n"
193 : "=&z" (tmp), "=r" (&v->counter) 193 : "=&z" (tmp)
194 : "r" (~mask), "r" (&v->counter) 194 : "r" (~mask), "r" (&v->counter)
195 : "t"); 195 : "t");
196#else 196#else
@@ -208,11 +208,11 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
208 unsigned long tmp; 208 unsigned long tmp;
209 209
210 __asm__ __volatile__ ( 210 __asm__ __volatile__ (
211"1: movli.l @%3, %0 ! atomic_set_mask \n" 211"1: movli.l @%2, %0 ! atomic_set_mask \n"
212" or %2, %0 \n" 212" or %1, %0 \n"
213" movco.l %0, @%3 \n" 213" movco.l %0, @%2 \n"
214" bf 1b \n" 214" bf 1b \n"
215 : "=&z" (tmp), "=r" (&v->counter) 215 : "=&z" (tmp)
216 : "r" (mask), "r" (&v->counter) 216 : "r" (mask), "r" (&v->counter)
217 : "t"); 217 : "t");
218#else 218#else
diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h
index beeea40f549e..795047da5e17 100644
--- a/include/asm-sh/bugs.h
+++ b/include/asm-sh/bugs.h
@@ -23,16 +23,20 @@ static void __init check_bugs(void)
23 cpu_data->loops_per_jiffy = loops_per_jiffy; 23 cpu_data->loops_per_jiffy = loops_per_jiffy;
24 24
25 switch (cpu_data->type) { 25 switch (cpu_data->type) {
26 case CPU_SH7604: 26 case CPU_SH7604 ... CPU_SH7619:
27 *p++ = '2'; 27 *p++ = '2';
28 break; 28 break;
29 case CPU_SH7206:
30 *p++ = '2';
31 *p++ = 'a';
32 break;
29 case CPU_SH7705 ... CPU_SH7300: 33 case CPU_SH7705 ... CPU_SH7300:
30 *p++ = '3'; 34 *p++ = '3';
31 break; 35 break;
32 case CPU_SH7750 ... CPU_SH4_501: 36 case CPU_SH7750 ... CPU_SH4_501:
33 *p++ = '4'; 37 *p++ = '4';
34 break; 38 break;
35 case CPU_SH7770 ... CPU_SH7781: 39 case CPU_SH7770 ... CPU_SH7785:
36 *p++ = '4'; 40 *p++ = '4';
37 *p++ = 'a'; 41 *p++ = 'a';
38 break; 42 break;
diff --git a/include/asm-sh/clock.h b/include/asm-sh/clock.h
index fdfb75b30f0d..1df92807f8c5 100644
--- a/include/asm-sh/clock.h
+++ b/include/asm-sh/clock.h
@@ -4,6 +4,7 @@
4#include <linux/kref.h> 4#include <linux/kref.h>
5#include <linux/list.h> 5#include <linux/list.h>
6#include <linux/seq_file.h> 6#include <linux/seq_file.h>
7#include <linux/clk.h>
7 8
8struct clk; 9struct clk;
9 10
@@ -18,7 +19,7 @@ struct clk_ops {
18struct clk { 19struct clk {
19 struct list_head node; 20 struct list_head node;
20 const char *name; 21 const char *name;
21 22 int id;
22 struct module *owner; 23 struct module *owner;
23 24
24 struct clk *parent; 25 struct clk *parent;
@@ -40,22 +41,13 @@ void arch_init_clk_ops(struct clk_ops **, int type);
40int clk_init(void); 41int clk_init(void);
41 42
42int __clk_enable(struct clk *); 43int __clk_enable(struct clk *);
43int clk_enable(struct clk *);
44
45void __clk_disable(struct clk *); 44void __clk_disable(struct clk *);
46void clk_disable(struct clk *);
47 45
48int clk_set_rate(struct clk *, unsigned long rate);
49unsigned long clk_get_rate(struct clk *);
50void clk_recalc_rate(struct clk *); 46void clk_recalc_rate(struct clk *);
51 47
52struct clk *clk_get(const char *id);
53void clk_put(struct clk *);
54
55int clk_register(struct clk *); 48int clk_register(struct clk *);
56void clk_unregister(struct clk *); 49void clk_unregister(struct clk *);
57 50
58int show_clocks(struct seq_file *m); 51int show_clocks(struct seq_file *m);
59 52
60#endif /* __ASM_SH_CLOCK_H */ 53#endif /* __ASM_SH_CLOCK_H */
61
diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h
index cd96402e8562..20b9796842dc 100644
--- a/include/asm-sh/cpu-sh2/cache.h
+++ b/include/asm-sh/cpu-sh2/cache.h
@@ -12,6 +12,7 @@
12 12
13#define L1_CACHE_SHIFT 4 13#define L1_CACHE_SHIFT 4
14 14
15#if defined(CONFIG_CPU_SUBTYPE_SH7604)
15#define CCR 0xfffffe92 /* Address of Cache Control Register */ 16#define CCR 0xfffffe92 /* Address of Cache Control Register */
16 17
17#define CCR_CACHE_CE 0x01 /* Cache enable */ 18#define CCR_CACHE_CE 0x01 /* Cache enable */
@@ -27,5 +28,26 @@
27#define CCR_CACHE_ORA CCR_CACHE_TW 28#define CCR_CACHE_ORA CCR_CACHE_TW
28#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */ 29#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */
29 30
31#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
32#define CCR1 0xffffffec
33#define CCR CCR1
34
35#define CCR_CACHE_CE 0x01 /* Cache enable */
36#define CCR_CACHE_WT 0x06 /* CCR[bit1=1,bit2=1] */
37 /* 0x00000000-0x7fffffff: Write-through */
38 /* 0x80000000-0x9fffffff: Write-back */
39 /* 0xc0000000-0xdfffffff: Write-through */
40#define CCR_CACHE_CB 0x00 /* CCR[bit1=0,bit2=0] */
41 /* 0x00000000-0x7fffffff: Write-back */
42 /* 0x80000000-0x9fffffff: Write-through */
43 /* 0xc0000000-0xdfffffff: Write-back */
44#define CCR_CACHE_CF 0x08 /* Cache invalidate */
45
46#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
47#define CACHE_OC_DATA_ARRAY 0xf1000000
48
49#define CCR_CACHE_ENABLE CCR_CACHE_CE
50#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
51#endif
30#endif /* __ASM_CPU_SH2_CACHE_H */ 52#endif /* __ASM_CPU_SH2_CACHE_H */
31 53
diff --git a/include/asm-sh/cpu-sh2/freq.h b/include/asm-sh/cpu-sh2/freq.h
new file mode 100644
index 000000000000..31de475da70b
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/freq.h
@@ -0,0 +1,18 @@
1/*
2 * include/asm-sh/cpu-sh2/freq.h
3 *
4 * Copyright (C) 2006 Yoshinori Sato
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_FREQ_H
11#define __ASM_CPU_SH2_FREQ_H
12
13#if defined(CONFIG_CPU_SUBTYPE_SH7619)
14#define FREQCR 0xf815ff80
15#endif
16
17#endif /* __ASM_CPU_SH2_FREQ_H */
18
diff --git a/include/asm-sh/cpu-sh2/mmu_context.h b/include/asm-sh/cpu-sh2/mmu_context.h
new file mode 100644
index 000000000000..beeb299e01ec
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/mmu_context.h
@@ -0,0 +1,16 @@
1/*
2 * include/asm-sh/cpu-sh2/mmu_context.h
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_MMU_CONTEXT_H
11#define __ASM_CPU_SH2_MMU_CONTEXT_H
12
13/* No MMU */
14
15#endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */
16
diff --git a/include/asm-sh/cpu-sh2/timer.h b/include/asm-sh/cpu-sh2/timer.h
new file mode 100644
index 000000000000..a39c241e8195
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/timer.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_CPU_SH2_TIMER_H
2#define __ASM_CPU_SH2_TIMER_H
3
4/* Nothing needed yet */
5
6#endif /* __ASM_CPU_SH2_TIMER_H */
diff --git a/include/asm-sh/cpu-sh2a/addrspace.h b/include/asm-sh/cpu-sh2a/addrspace.h
new file mode 100644
index 000000000000..3d2e9aa21522
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/addrspace.h
@@ -0,0 +1 @@
#include <asm/cpu-sh2/addrspace.h>
diff --git a/include/asm-sh/cpu-sh2a/cache.h b/include/asm-sh/cpu-sh2a/cache.h
new file mode 100644
index 000000000000..3e4b9e480982
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/cache.h
@@ -0,0 +1,39 @@
1/*
2 * include/asm-sh/cpu-sh2a/cache.h
3 *
4 * Copyright (C) 2004 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2A_CACHE_H
11#define __ASM_CPU_SH2A_CACHE_H
12
13#define L1_CACHE_SHIFT 4
14
15#define CCR1 0xfffc1000
16#define CCR2 0xfffc1004
17
18/* CCR1 behaves more like the traditional CCR */
19#define CCR CCR1
20
21/*
22 * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
23 * listed here are reserved.
24 */
25#define CCR_CACHE_CB 0x0000 /* Hack */
26#define CCR_CACHE_OCE 0x0001
27#define CCR_CACHE_WT 0x0002
28#define CCR_CACHE_OCI 0x0008 /* OCF */
29#define CCR_CACHE_ICE 0x0100
30#define CCR_CACHE_ICI 0x0800 /* ICF */
31
32#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
33#define CACHE_OC_ADDRESS_ARRAY 0xf0800000
34
35#define CCR_CACHE_ENABLE (CCR_CACHE_OCE | CCR_CACHE_ICE)
36#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI | CCR_CACHE_ICI)
37
38#endif /* __ASM_CPU_SH2A_CACHE_H */
39
diff --git a/include/asm-sh/cpu-sh2a/cacheflush.h b/include/asm-sh/cpu-sh2a/cacheflush.h
new file mode 100644
index 000000000000..fa3186c73350
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/cacheflush.h
@@ -0,0 +1 @@
#include <asm/cpu-sh2/cacheflush.h>
diff --git a/include/asm-sh/cpu-sh2a/dma.h b/include/asm-sh/cpu-sh2a/dma.h
new file mode 100644
index 000000000000..0d5ad85c1de8
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/dma.h
@@ -0,0 +1 @@
#include <asm/cpu-sh2/dma.h>
diff --git a/include/asm-sh/cpu-sh2a/freq.h b/include/asm-sh/cpu-sh2a/freq.h
new file mode 100644
index 000000000000..e518fff6d10f
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/freq.h
@@ -0,0 +1,18 @@
1/*
2 * include/asm-sh/cpu-sh2a/freq.h
3 *
4 * Copyright (C) 2006 Yoshinori Sato
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2A_FREQ_H
11#define __ASM_CPU_SH2A_FREQ_H
12
13#if defined(CONFIG_CPU_SUBTYPE_SH7206)
14#define FREQCR 0xfffe0010
15#endif
16
17#endif /* __ASM_CPU_SH2A_FREQ_H */
18
diff --git a/include/asm-sh/cpu-sh2a/mmu_context.h b/include/asm-sh/cpu-sh2a/mmu_context.h
new file mode 100644
index 000000000000..cd2387f7db9e
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/mmu_context.h
@@ -0,0 +1 @@
#include <asm/cpu-sh2/mmu_context.h>
diff --git a/include/asm-sh/cpu-sh2a/timer.h b/include/asm-sh/cpu-sh2a/timer.h
new file mode 100644
index 000000000000..fee504adf11e
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/timer.h
@@ -0,0 +1 @@
#include <asm/cpu-sh2/timer.h>
diff --git a/include/asm-sh/cpu-sh2a/ubc.h b/include/asm-sh/cpu-sh2a/ubc.h
new file mode 100644
index 000000000000..cf28062b96a2
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/ubc.h
@@ -0,0 +1 @@
#include <asm/cpu-sh2/ubc.h>
diff --git a/include/asm-sh/cpu-sh2a/watchdog.h b/include/asm-sh/cpu-sh2a/watchdog.h
new file mode 100644
index 000000000000..c1b3e2488478
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/watchdog.h
@@ -0,0 +1 @@
#include <asm/cpu-sh2/watchdog.h>
diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h
index d9daa028689f..faf3051cd429 100644
--- a/include/asm-sh/dma.h
+++ b/include/asm-sh/dma.h
@@ -14,9 +14,7 @@
14#include <linux/spinlock.h> 14#include <linux/spinlock.h>
15#include <linux/wait.h> 15#include <linux/wait.h>
16#include <linux/sysdev.h> 16#include <linux/sysdev.h>
17#include <linux/device.h>
18#include <asm/cpu/dma.h> 17#include <asm/cpu/dma.h>
19#include <asm/semaphore.h>
20 18
21/* The maximum address that we can perform a DMA transfer to on this platform */ 19/* The maximum address that we can perform a DMA transfer to on this platform */
22/* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any 20/* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any
@@ -46,16 +44,21 @@
46 * DMAC (dma_info) flags 44 * DMAC (dma_info) flags
47 */ 45 */
48enum { 46enum {
49 DMAC_CHANNELS_CONFIGURED = 0x00, 47 DMAC_CHANNELS_CONFIGURED = 0x01,
50 DMAC_CHANNELS_TEI_CAPABLE = 0x01, 48 DMAC_CHANNELS_TEI_CAPABLE = 0x02, /* Transfer end interrupt */
51}; 49};
52 50
53/* 51/*
54 * DMA channel capabilities / flags 52 * DMA channel capabilities / flags
55 */ 53 */
56enum { 54enum {
57 DMA_TEI_CAPABLE = 0x01, 55 DMA_CONFIGURED = 0x01,
58 DMA_CONFIGURED = 0x02, 56
57 /*
58 * Transfer end interrupt, inherited from DMAC.
59 * wait_queue used in dma_wait_for_completion.
60 */
61 DMA_TEI_CAPABLE = 0x02,
59}; 62};
60 63
61extern spinlock_t dma_spin_lock; 64extern spinlock_t dma_spin_lock;
@@ -68,28 +71,31 @@ struct dma_ops {
68 71
69 int (*get_residue)(struct dma_channel *chan); 72 int (*get_residue)(struct dma_channel *chan);
70 int (*xfer)(struct dma_channel *chan); 73 int (*xfer)(struct dma_channel *chan);
71 void (*configure)(struct dma_channel *chan, unsigned long flags); 74 int (*configure)(struct dma_channel *chan, unsigned long flags);
75 int (*extend)(struct dma_channel *chan, unsigned long op, void *param);
72}; 76};
73 77
74struct dma_channel { 78struct dma_channel {
75 char dev_id[16]; 79 char dev_id[16]; /* unique name per DMAC of channel */
76 80
77 unsigned int chan; /* Physical channel number */ 81 unsigned int chan; /* DMAC channel number */
78 unsigned int vchan; /* Virtual channel number */ 82 unsigned int vchan; /* Virtual channel number */
83
79 unsigned int mode; 84 unsigned int mode;
80 unsigned int count; 85 unsigned int count;
81 86
82 unsigned long sar; 87 unsigned long sar;
83 unsigned long dar; 88 unsigned long dar;
84 89
90 const char **caps;
91
85 unsigned long flags; 92 unsigned long flags;
86 atomic_t busy; 93 atomic_t busy;
87 94
88 struct semaphore sem;
89 wait_queue_head_t wait_queue; 95 wait_queue_head_t wait_queue;
90 96
91 struct sys_device dev; 97 struct sys_device dev;
92 char *name; 98 void *priv_data;
93}; 99};
94 100
95struct dma_info { 101struct dma_info {
@@ -103,6 +109,12 @@ struct dma_info {
103 struct dma_channel *channels; 109 struct dma_channel *channels;
104 110
105 struct list_head list; 111 struct list_head list;
112 int first_channel_nr;
113};
114
115struct dma_chan_caps {
116 int ch_num;
117 const char **caplist;
106}; 118};
107 119
108#define to_dma_channel(channel) container_of(channel, struct dma_channel, dev) 120#define to_dma_channel(channel) container_of(channel, struct dma_channel, dev)
@@ -121,6 +133,8 @@ extern int dma_xfer(unsigned int chan, unsigned long from,
121#define dma_read_page(chan, from, to) \ 133#define dma_read_page(chan, from, to) \
122 dma_read(chan, from, to, PAGE_SIZE) 134 dma_read(chan, from, to, PAGE_SIZE)
123 135
136extern int request_dma_bycap(const char **dmac, const char **caps,
137 const char *dev_id);
124extern int request_dma(unsigned int chan, const char *dev_id); 138extern int request_dma(unsigned int chan, const char *dev_id);
125extern void free_dma(unsigned int chan); 139extern void free_dma(unsigned int chan);
126extern int get_dma_residue(unsigned int chan); 140extern int get_dma_residue(unsigned int chan);
@@ -131,6 +145,10 @@ extern void dma_configure_channel(unsigned int chan, unsigned long flags);
131 145
132extern int register_dmac(struct dma_info *info); 146extern int register_dmac(struct dma_info *info);
133extern void unregister_dmac(struct dma_info *info); 147extern void unregister_dmac(struct dma_info *info);
148extern struct dma_info *get_dma_info_by_name(const char *dmac_name);
149
150extern int dma_extend(unsigned int chan, unsigned long op, void *param);
151extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist);
134 152
135#ifdef CONFIG_SYSFS 153#ifdef CONFIG_SYSFS
136/* arch/sh/drivers/dma/dma-sysfs.c */ 154/* arch/sh/drivers/dma/dma-sysfs.c */
diff --git a/include/asm-sh/elf.h b/include/asm-sh/elf.h
index fc050fd7645e..43ca244564b1 100644
--- a/include/asm-sh/elf.h
+++ b/include/asm-sh/elf.h
@@ -74,7 +74,7 @@ typedef struct user_fpu_struct elf_fpregset_t;
74#define ELF_ARCH EM_SH 74#define ELF_ARCH EM_SH
75 75
76#define USE_ELF_CORE_DUMP 76#define USE_ELF_CORE_DUMP
77#define ELF_EXEC_PAGESIZE 4096 77#define ELF_EXEC_PAGESIZE PAGE_SIZE
78 78
79/* This is the location that an ET_DYN program is loaded if exec'ed. Typical 79/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
80 use of this is to invoke "./ld.so someprog" to test out a new version of 80 use of this is to invoke "./ld.so someprog" to test out a new version of
diff --git a/include/asm-sh/entry-macros.S b/include/asm-sh/entry-macros.S
new file mode 100644
index 000000000000..500030eae7aa
--- /dev/null
+++ b/include/asm-sh/entry-macros.S
@@ -0,0 +1,33 @@
1! entry.S macro define
2
3 .macro cli
4 stc sr, r0
5 or #0xf0, r0
6 ldc r0, sr
7 .endm
8
9 .macro sti
10 mov #0xf0, r11
11 extu.b r11, r11
12 not r11, r11
13 stc sr, r10
14 and r11, r10
15#ifdef CONFIG_HAS_SR_RB
16 stc k_g_imask, r11
17 or r11, r10
18#endif
19 ldc r10, sr
20 .endm
21
22 .macro get_current_thread_info, ti, tmp
23#ifdef CONFIG_HAS_SR_RB
24 stc r7_bank, \ti
25#else
26 mov #((THREAD_SIZE - 1) >> 10) ^ 0xff, \tmp
27 shll8 \tmp
28 shll2 \tmp
29 mov r15, \ti
30 and \tmp, \ti
31#endif
32 .endm
33
diff --git a/include/asm-sh/irq-sh73180.h b/include/asm-sh/irq-sh73180.h
deleted file mode 100644
index b28af9a69d72..000000000000
--- a/include/asm-sh/irq-sh73180.h
+++ /dev/null
@@ -1,314 +0,0 @@
1#ifndef __ASM_SH_IRQ_SH73180_H
2#define __ASM_SH_IRQ_SH73180_H
3
4/*
5 * linux/include/asm-sh/irq-sh73180.h
6 *
7 * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
8 */
9
10#undef INTC_IPRA
11#undef INTC_IPRB
12#undef INTC_IPRC
13#undef INTC_IPRD
14
15#undef DMTE0_IRQ
16#undef DMTE1_IRQ
17#undef DMTE2_IRQ
18#undef DMTE3_IRQ
19#undef DMTE4_IRQ
20#undef DMTE5_IRQ
21#undef DMTE6_IRQ
22#undef DMTE7_IRQ
23#undef DMAE_IRQ
24#undef DMA_IPR_ADDR
25#undef DMA_IPR_POS
26#undef DMA_PRIORITY
27
28#undef INTC_IMCR0
29#undef INTC_IMCR1
30#undef INTC_IMCR2
31#undef INTC_IMCR3
32#undef INTC_IMCR4
33#undef INTC_IMCR5
34#undef INTC_IMCR6
35#undef INTC_IMCR7
36#undef INTC_IMCR8
37#undef INTC_IMCR9
38#undef INTC_IMCR10
39
40
41#define INTC_IPRA 0xA4080000UL
42#define INTC_IPRB 0xA4080004UL
43#define INTC_IPRC 0xA4080008UL
44#define INTC_IPRD 0xA408000CUL
45#define INTC_IPRE 0xA4080010UL
46#define INTC_IPRF 0xA4080014UL
47#define INTC_IPRG 0xA4080018UL
48#define INTC_IPRH 0xA408001CUL
49#define INTC_IPRI 0xA4080020UL
50#define INTC_IPRJ 0xA4080024UL
51#define INTC_IPRK 0xA4080028UL
52
53#define INTC_IMR0 0xA4080080UL
54#define INTC_IMR1 0xA4080084UL
55#define INTC_IMR2 0xA4080088UL
56#define INTC_IMR3 0xA408008CUL
57#define INTC_IMR4 0xA4080090UL
58#define INTC_IMR5 0xA4080094UL
59#define INTC_IMR6 0xA4080098UL
60#define INTC_IMR7 0xA408009CUL
61#define INTC_IMR8 0xA40800A0UL
62#define INTC_IMR9 0xA40800A4UL
63#define INTC_IMR10 0xA40800A8UL
64#define INTC_IMR11 0xA40800ACUL
65
66#define INTC_IMCR0 0xA40800C0UL
67#define INTC_IMCR1 0xA40800C4UL
68#define INTC_IMCR2 0xA40800C8UL
69#define INTC_IMCR3 0xA40800CCUL
70#define INTC_IMCR4 0xA40800D0UL
71#define INTC_IMCR5 0xA40800D4UL
72#define INTC_IMCR6 0xA40800D8UL
73#define INTC_IMCR7 0xA40800DCUL
74#define INTC_IMCR8 0xA40800E0UL
75#define INTC_IMCR9 0xA40800E4UL
76#define INTC_IMCR10 0xA40800E8UL
77#define INTC_IMCR11 0xA40800ECUL
78
79#define INTC_ICR0 0xA4140000UL
80#define INTC_ICR1 0xA414001CUL
81
82#define INTMSK0 0xa4140044
83#define INTMSKCLR0 0xa4140064
84#define INTC_INTPRI0 0xa4140010
85
86/*
87 NOTE:
88
89 *_IRQ = (INTEVT2 - 0x200)/0x20
90*/
91
92/* TMU0 */
93#define TMU0_IRQ 16
94#define TMU0_IPR_ADDR INTC_IPRA
95#define TMU0_IPR_POS 3
96#define TMU0_PRIORITY 2
97
98#define TIMER_IRQ 16
99#define TIMER_IPR_ADDR INTC_IPRA
100#define TIMER_IPR_POS 3
101#define TIMER_PRIORITY 2
102
103/* TMU1 */
104#define TMU1_IRQ 17
105#define TMU1_IPR_ADDR INTC_IPRA
106#define TMU1_IPR_POS 2
107#define TMU1_PRIORITY 2
108
109/* TMU2 */
110#define TMU2_IRQ 18
111#define TMU2_IPR_ADDR INTC_IPRA
112#define TMU2_IPR_POS 1
113#define TMU2_PRIORITY 2
114
115/* LCDC */
116#define LCDC_IRQ 28
117#define LCDC_IPR_ADDR INTC_IPRB
118#define LCDC_IPR_POS 2
119#define LCDC_PRIORITY 2
120
121/* VIO (Video I/O) */
122#define CEU_IRQ 52
123#define BEU_IRQ 53
124#define VEU_IRQ 54
125#define VOU_IRQ 55
126#define VIO_IPR_ADDR INTC_IPRE
127#define VIO_IPR_POS 2
128#define VIO_PRIORITY 2
129
130/* MFI (Multi Functional Interface) */
131#define MFI_IRQ 56
132#define MFI_IPR_ADDR INTC_IPRE
133#define MFI_IPR_POS 1
134#define MFI_PRIORITY 2
135
136/* VPU (Video Processing Unit) */
137#define VPU_IRQ 60
138#define VPU_IPR_ADDR INTC_IPRE
139#define VPU_IPR_POS 0
140#define VPU_PRIORITY 2
141
142/* 3DG */
143#define TDG_IRQ 63
144#define TDG_IPR_ADDR INTC_IPRJ
145#define TDG_IPR_POS 2
146#define TDG_PRIORITY 2
147
148/* DMAC(1) */
149#define DMTE0_IRQ 48
150#define DMTE1_IRQ 49
151#define DMTE2_IRQ 50
152#define DMTE3_IRQ 51
153#define DMA1_IPR_ADDR INTC_IPRE
154#define DMA1_IPR_POS 3
155#define DMA1_PRIORITY 7
156
157/* DMAC(2) */
158#define DMTE4_IRQ 76
159#define DMTE5_IRQ 77
160#define DMA2_IPR_ADDR INTC_IPRF
161#define DMA2_IPR_POS 2
162#define DMA2_PRIORITY 7
163
164/* SCIF0 */
165#define SCIF_ERI_IRQ 80
166#define SCIF_RXI_IRQ 81
167#define SCIF_BRI_IRQ 82
168#define SCIF_TXI_IRQ 83
169#define SCIF_IPR_ADDR INTC_IPRG
170#define SCIF_IPR_POS 3
171#define SCIF_PRIORITY 3
172
173/* SIOF0 */
174#define SIOF0_IRQ 84
175#define SIOF0_IPR_ADDR INTC_IPRH
176#define SIOF0_IPR_POS 3
177#define SIOF0_PRIORITY 3
178
179/* FLCTL (Flash Memory Controller) */
180#define FLSTE_IRQ 92
181#define FLTEND_IRQ 93
182#define FLTRQ0_IRQ 94
183#define FLTRQ1_IRQ 95
184#define FLCTL_IPR_ADDR INTC_IPRH
185#define FLCTL_IPR_POS 1
186#define FLCTL_PRIORITY 3
187
188/* IIC(0) (IIC Bus Interface) */
189#define IIC0_ALI_IRQ 96
190#define IIC0_TACKI_IRQ 97
191#define IIC0_WAITI_IRQ 98
192#define IIC0_DTEI_IRQ 99
193#define IIC0_IPR_ADDR INTC_IPRH
194#define IIC0_IPR_POS 0
195#define IIC0_PRIORITY 3
196
197/* IIC(1) (IIC Bus Interface) */
198#define IIC1_ALI_IRQ 44
199#define IIC1_TACKI_IRQ 45
200#define IIC1_WAITI_IRQ 46
201#define IIC1_DTEI_IRQ 47
202#define IIC1_IPR_ADDR INTC_IPRG
203#define IIC1_IPR_POS 0
204#define IIC1_PRIORITY 3
205
206/* SIO0 */
207#define SIO0_IRQ 88
208#define SIO0_IPR_ADDR INTC_IPRI
209#define SIO0_IPR_POS 3
210#define SIO0_PRIORITY 3
211
212/* SDHI */
213#define SDHI_SDHII0_IRQ 100
214#define SDHI_SDHII1_IRQ 101
215#define SDHI_SDHII2_IRQ 102
216#define SDHI_SDHII3_IRQ 103
217#define SDHI_IPR_ADDR INTC_IPRK
218#define SDHI_IPR_POS 0
219#define SDHI_PRIORITY 3
220
221/* SIU (Sound Interface Unit) */
222#define SIU_IRQ 108
223#define SIU_IPR_ADDR INTC_IPRJ
224#define SIU_IPR_POS 1
225#define SIU_PRIORITY 3
226
227#define PORT_PACR 0xA4050100UL
228#define PORT_PBCR 0xA4050102UL
229#define PORT_PCCR 0xA4050104UL
230#define PORT_PDCR 0xA4050106UL
231#define PORT_PECR 0xA4050108UL
232#define PORT_PFCR 0xA405010AUL
233#define PORT_PGCR 0xA405010CUL
234#define PORT_PHCR 0xA405010EUL
235#define PORT_PJCR 0xA4050110UL
236#define PORT_PKCR 0xA4050112UL
237#define PORT_PLCR 0xA4050114UL
238#define PORT_SCPCR 0xA4050116UL
239#define PORT_PMCR 0xA4050118UL
240#define PORT_PNCR 0xA405011AUL
241#define PORT_PQCR 0xA405011CUL
242#define PORT_PRCR 0xA405011EUL
243#define PORT_PTCR 0xA405014CUL
244#define PORT_PUCR 0xA405014EUL
245#define PORT_PVCR 0xA4050150UL
246
247#define PORT_PSELA 0xA4050140UL
248#define PORT_PSELB 0xA4050142UL
249#define PORT_PSELC 0xA4050144UL
250#define PORT_PSELE 0xA4050158UL
251
252#define PORT_HIZCRA 0xA4050146UL
253#define PORT_HIZCRB 0xA4050148UL
254#define PORT_DRVCR 0xA405014AUL
255
256#define PORT_PADR 0xA4050120UL
257#define PORT_PBDR 0xA4050122UL
258#define PORT_PCDR 0xA4050124UL
259#define PORT_PDDR 0xA4050126UL
260#define PORT_PEDR 0xA4050128UL
261#define PORT_PFDR 0xA405012AUL
262#define PORT_PGDR 0xA405012CUL
263#define PORT_PHDR 0xA405012EUL
264#define PORT_PJDR 0xA4050130UL
265#define PORT_PKDR 0xA4050132UL
266#define PORT_PLDR 0xA4050134UL
267#define PORT_SCPDR 0xA4050136UL
268#define PORT_PMDR 0xA4050138UL
269#define PORT_PNDR 0xA405013AUL
270#define PORT_PQDR 0xA405013CUL
271#define PORT_PRDR 0xA405013EUL
272#define PORT_PTDR 0xA405016CUL
273#define PORT_PUDR 0xA405016EUL
274#define PORT_PVDR 0xA4050170UL
275
276#define IRQ0_IRQ 32
277#define IRQ1_IRQ 33
278#define IRQ2_IRQ 34
279#define IRQ3_IRQ 35
280#define IRQ4_IRQ 36
281#define IRQ5_IRQ 37
282#define IRQ6_IRQ 38
283#define IRQ7_IRQ 39
284
285#define INTPRI00 0xA4140010UL
286
287#define IRQ0_IPR_ADDR INTPRI00
288#define IRQ1_IPR_ADDR INTPRI00
289#define IRQ2_IPR_ADDR INTPRI00
290#define IRQ3_IPR_ADDR INTPRI00
291#define IRQ4_IPR_ADDR INTPRI00
292#define IRQ5_IPR_ADDR INTPRI00
293#define IRQ6_IPR_ADDR INTPRI00
294#define IRQ7_IPR_ADDR INTPRI00
295
296#define IRQ0_IPR_POS 7
297#define IRQ1_IPR_POS 6
298#define IRQ2_IPR_POS 5
299#define IRQ3_IPR_POS 4
300#define IRQ4_IPR_POS 3
301#define IRQ5_IPR_POS 2
302#define IRQ6_IPR_POS 1
303#define IRQ7_IPR_POS 0
304
305#define IRQ0_PRIORITY 1
306#define IRQ1_PRIORITY 1
307#define IRQ2_PRIORITY 1
308#define IRQ3_PRIORITY 1
309#define IRQ4_PRIORITY 1
310#define IRQ5_PRIORITY 1
311#define IRQ6_PRIORITY 1
312#define IRQ7_PRIORITY 1
313
314#endif /* __ASM_SH_IRQ_SH73180_H */
diff --git a/include/asm-sh/irq-sh7343.h b/include/asm-sh/irq-sh7343.h
deleted file mode 100644
index 5d15419b53b0..000000000000
--- a/include/asm-sh/irq-sh7343.h
+++ /dev/null
@@ -1,317 +0,0 @@
1#ifndef __ASM_SH_IRQ_SH7343_H
2#define __ASM_SH_IRQ_SH7343_H
3
4/*
5 * linux/include/asm-sh/irq-sh7343.h
6 *
7 * Copyright (C) 2006 Kenati Technologies Inc.
8 * Andre Mccurdy <andre@kenati.com>
9 * Ranjit Deshpande <ranjit@kenati.com>
10 */
11
12#undef INTC_IPRA
13#undef INTC_IPRB
14#undef INTC_IPRC
15#undef INTC_IPRD
16
17#undef DMTE0_IRQ
18#undef DMTE1_IRQ
19#undef DMTE2_IRQ
20#undef DMTE3_IRQ
21#undef DMTE4_IRQ
22#undef DMTE5_IRQ
23#undef DMTE6_IRQ
24#undef DMTE7_IRQ
25#undef DMAE_IRQ
26#undef DMA_IPR_ADDR
27#undef DMA_IPR_POS
28#undef DMA_PRIORITY
29
30#undef INTC_IMCR0
31#undef INTC_IMCR1
32#undef INTC_IMCR2
33#undef INTC_IMCR3
34#undef INTC_IMCR4
35#undef INTC_IMCR5
36#undef INTC_IMCR6
37#undef INTC_IMCR7
38#undef INTC_IMCR8
39#undef INTC_IMCR9
40#undef INTC_IMCR10
41
42
43#define INTC_IPRA 0xA4080000UL
44#define INTC_IPRB 0xA4080004UL
45#define INTC_IPRC 0xA4080008UL
46#define INTC_IPRD 0xA408000CUL
47#define INTC_IPRE 0xA4080010UL
48#define INTC_IPRF 0xA4080014UL
49#define INTC_IPRG 0xA4080018UL
50#define INTC_IPRH 0xA408001CUL
51#define INTC_IPRI 0xA4080020UL
52#define INTC_IPRJ 0xA4080024UL
53#define INTC_IPRK 0xA4080028UL
54#define INTC_IPRL 0xA408002CUL
55
56#define INTC_IMR0 0xA4080080UL
57#define INTC_IMR1 0xA4080084UL
58#define INTC_IMR2 0xA4080088UL
59#define INTC_IMR3 0xA408008CUL
60#define INTC_IMR4 0xA4080090UL
61#define INTC_IMR5 0xA4080094UL
62#define INTC_IMR6 0xA4080098UL
63#define INTC_IMR7 0xA408009CUL
64#define INTC_IMR8 0xA40800A0UL
65#define INTC_IMR9 0xA40800A4UL
66#define INTC_IMR10 0xA40800A8UL
67#define INTC_IMR11 0xA40800ACUL
68
69#define INTC_IMCR0 0xA40800C0UL
70#define INTC_IMCR1 0xA40800C4UL
71#define INTC_IMCR2 0xA40800C8UL
72#define INTC_IMCR3 0xA40800CCUL
73#define INTC_IMCR4 0xA40800D0UL
74#define INTC_IMCR5 0xA40800D4UL
75#define INTC_IMCR6 0xA40800D8UL
76#define INTC_IMCR7 0xA40800DCUL
77#define INTC_IMCR8 0xA40800E0UL
78#define INTC_IMCR9 0xA40800E4UL
79#define INTC_IMCR10 0xA40800E8UL
80#define INTC_IMCR11 0xA40800ECUL
81
82#define INTC_ICR0 0xA4140000UL
83#define INTC_ICR1 0xA414001CUL
84
85#define INTMSK0 0xa4140044
86#define INTMSKCLR0 0xa4140064
87#define INTC_INTPRI0 0xa4140010
88
89/*
90 NOTE:
91
92 *_IRQ = (INTEVT2 - 0x200)/0x20
93*/
94
95/* TMU0 */
96#define TMU0_IRQ 16
97#define TMU0_IPR_ADDR INTC_IPRA
98#define TMU0_IPR_POS 3
99#define TMU0_PRIORITY 2
100
101#define TIMER_IRQ 16
102#define TIMER_IPR_ADDR INTC_IPRA
103#define TIMER_IPR_POS 3
104#define TIMER_PRIORITY 2
105
106/* TMU1 */
107#define TMU1_IRQ 17
108#define TMU1_IPR_ADDR INTC_IPRA
109#define TMU1_IPR_POS 2
110#define TMU1_PRIORITY 2
111
112/* TMU2 */
113#define TMU2_IRQ 18
114#define TMU2_IPR_ADDR INTC_IPRA
115#define TMU2_IPR_POS 1
116#define TMU2_PRIORITY 2
117
118/* LCDC */
119#define LCDC_IRQ 28
120#define LCDC_IPR_ADDR INTC_IPRB
121#define LCDC_IPR_POS 2
122#define LCDC_PRIORITY 2
123
124/* VIO (Video I/O) */
125#define CEU_IRQ 52
126#define BEU_IRQ 53
127#define VEU_IRQ 54
128#define VOU_IRQ 55
129#define VIO_IPR_ADDR INTC_IPRE
130#define VIO_IPR_POS 2
131#define VIO_PRIORITY 2
132
133/* MFI (Multi Functional Interface) */
134#define MFI_IRQ 56
135#define MFI_IPR_ADDR INTC_IPRE
136#define MFI_IPR_POS 1
137#define MFI_PRIORITY 2
138
139/* VPU (Video Processing Unit) */
140#define VPU_IRQ 60
141#define VPU_IPR_ADDR INTC_IPRE
142#define VPU_IPR_POS 0
143#define VPU_PRIORITY 2
144
145/* 3DG */
146#define TDG_IRQ 63
147#define TDG_IPR_ADDR INTC_IPRJ
148#define TDG_IPR_POS 2
149#define TDG_PRIORITY 2
150
151/* DMAC(1) */
152#define DMTE0_IRQ 48
153#define DMTE1_IRQ 49
154#define DMTE2_IRQ 50
155#define DMTE3_IRQ 51
156#define DMA1_IPR_ADDR INTC_IPRE
157#define DMA1_IPR_POS 3
158#define DMA1_PRIORITY 7
159
160/* DMAC(2) */
161#define DMTE4_IRQ 76
162#define DMTE5_IRQ 77
163#define DMA2_IPR_ADDR INTC_IPRF
164#define DMA2_IPR_POS 2
165#define DMA2_PRIORITY 7
166
167/* SCIF0 */
168#define SCIF_ERI_IRQ 80
169#define SCIF_RXI_IRQ 81
170#define SCIF_BRI_IRQ 82
171#define SCIF_TXI_IRQ 83
172#define SCIF_IPR_ADDR INTC_IPRG
173#define SCIF_IPR_POS 3
174#define SCIF_PRIORITY 3
175
176/* SIOF0 */
177#define SIOF0_IRQ 84
178#define SIOF0_IPR_ADDR INTC_IPRH
179#define SIOF0_IPR_POS 3
180#define SIOF0_PRIORITY 3
181
182/* FLCTL (Flash Memory Controller) */
183#define FLSTE_IRQ 92
184#define FLTEND_IRQ 93
185#define FLTRQ0_IRQ 94
186#define FLTRQ1_IRQ 95
187#define FLCTL_IPR_ADDR INTC_IPRH
188#define FLCTL_IPR_POS 1
189#define FLCTL_PRIORITY 3
190
191/* IIC(0) (IIC Bus Interface) */
192#define IIC0_ALI_IRQ 96
193#define IIC0_TACKI_IRQ 97
194#define IIC0_WAITI_IRQ 98
195#define IIC0_DTEI_IRQ 99
196#define IIC0_IPR_ADDR INTC_IPRH
197#define IIC0_IPR_POS 0
198#define IIC0_PRIORITY 3
199
200/* IIC(1) (IIC Bus Interface) */
201#define IIC1_ALI_IRQ 44
202#define IIC1_TACKI_IRQ 45
203#define IIC1_WAITI_IRQ 46
204#define IIC1_DTEI_IRQ 47
205#define IIC1_IPR_ADDR INTC_IPRI
206#define IIC1_IPR_POS 0
207#define IIC1_PRIORITY 3
208
209/* SIO0 */
210#define SIO0_IRQ 88
211#define SIO0_IPR_ADDR INTC_IPRI
212#define SIO0_IPR_POS 3
213#define SIO0_PRIORITY 3
214
215/* SDHI */
216#define SDHI_SDHII0_IRQ 100
217#define SDHI_SDHII1_IRQ 101
218#define SDHI_SDHII2_IRQ 102
219#define SDHI_SDHII3_IRQ 103
220#define SDHI_IPR_ADDR INTC_IPRK
221#define SDHI_IPR_POS 0
222#define SDHI_PRIORITY 3
223
224/* SIU (Sound Interface Unit) */
225#define SIU_IRQ 108
226#define SIU_IPR_ADDR INTC_IPRJ
227#define SIU_IPR_POS 1
228#define SIU_PRIORITY 3
229
230#define PORT_PACR 0xA4050100UL
231#define PORT_PBCR 0xA4050102UL
232#define PORT_PCCR 0xA4050104UL
233#define PORT_PDCR 0xA4050106UL
234#define PORT_PECR 0xA4050108UL
235#define PORT_PFCR 0xA405010AUL
236#define PORT_PGCR 0xA405010CUL
237#define PORT_PHCR 0xA405010EUL
238#define PORT_PJCR 0xA4050110UL
239#define PORT_PKCR 0xA4050112UL
240#define PORT_PLCR 0xA4050114UL
241#define PORT_SCPCR 0xA4050116UL
242#define PORT_PMCR 0xA4050118UL
243#define PORT_PNCR 0xA405011AUL
244#define PORT_PQCR 0xA405011CUL
245#define PORT_PRCR 0xA405011EUL
246#define PORT_PTCR 0xA405014CUL
247#define PORT_PUCR 0xA405014EUL
248#define PORT_PVCR 0xA4050150UL
249
250#define PORT_PSELA 0xA4050140UL
251#define PORT_PSELB 0xA4050142UL
252#define PORT_PSELC 0xA4050144UL
253#define PORT_PSELE 0xA4050158UL
254
255#define PORT_HIZCRA 0xA4050146UL
256#define PORT_HIZCRB 0xA4050148UL
257#define PORT_DRVCR 0xA405014AUL
258
259#define PORT_PADR 0xA4050120UL
260#define PORT_PBDR 0xA4050122UL
261#define PORT_PCDR 0xA4050124UL
262#define PORT_PDDR 0xA4050126UL
263#define PORT_PEDR 0xA4050128UL
264#define PORT_PFDR 0xA405012AUL
265#define PORT_PGDR 0xA405012CUL
266#define PORT_PHDR 0xA405012EUL
267#define PORT_PJDR 0xA4050130UL
268#define PORT_PKDR 0xA4050132UL
269#define PORT_PLDR 0xA4050134UL
270#define PORT_SCPDR 0xA4050136UL
271#define PORT_PMDR 0xA4050138UL
272#define PORT_PNDR 0xA405013AUL
273#define PORT_PQDR 0xA405013CUL
274#define PORT_PRDR 0xA405013EUL
275#define PORT_PTDR 0xA405016CUL
276#define PORT_PUDR 0xA405016EUL
277#define PORT_PVDR 0xA4050170UL
278
279#define IRQ0_IRQ 32
280#define IRQ1_IRQ 33
281#define IRQ2_IRQ 34
282#define IRQ3_IRQ 35
283#define IRQ4_IRQ 36
284#define IRQ5_IRQ 37
285#define IRQ6_IRQ 38
286#define IRQ7_IRQ 39
287
288#define INTPRI00 0xA4140010UL
289
290#define IRQ0_IPR_ADDR INTPRI00
291#define IRQ1_IPR_ADDR INTPRI00
292#define IRQ2_IPR_ADDR INTPRI00
293#define IRQ3_IPR_ADDR INTPRI00
294#define IRQ4_IPR_ADDR INTPRI00
295#define IRQ5_IPR_ADDR INTPRI00
296#define IRQ6_IPR_ADDR INTPRI00
297#define IRQ7_IPR_ADDR INTPRI00
298
299#define IRQ0_IPR_POS 7
300#define IRQ1_IPR_POS 6
301#define IRQ2_IPR_POS 5
302#define IRQ3_IPR_POS 4
303#define IRQ4_IPR_POS 3
304#define IRQ5_IPR_POS 2
305#define IRQ6_IPR_POS 1
306#define IRQ7_IPR_POS 0
307
308#define IRQ0_PRIORITY 1
309#define IRQ1_PRIORITY 1
310#define IRQ2_PRIORITY 1
311#define IRQ3_PRIORITY 1
312#define IRQ4_PRIORITY 1
313#define IRQ5_PRIORITY 1
314#define IRQ6_PRIORITY 1
315#define IRQ7_PRIORITY 1
316
317#endif /* __ASM_SH_IRQ_SH7343_H */
diff --git a/include/asm-sh/irq-sh7780.h b/include/asm-sh/irq-sh7780.h
deleted file mode 100644
index 19912ae6a7f7..000000000000
--- a/include/asm-sh/irq-sh7780.h
+++ /dev/null
@@ -1,311 +0,0 @@
1#ifndef __ASM_SH_IRQ_SH7780_H
2#define __ASM_SH_IRQ_SH7780_H
3
4/*
5 * linux/include/asm-sh/irq-sh7780.h
6 *
7 * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
8 */
9#define INTC_BASE 0xffd00000
10#define INTC_ICR0 (INTC_BASE+0x0)
11#define INTC_ICR1 (INTC_BASE+0x1c)
12#define INTC_INTPRI (INTC_BASE+0x10)
13#define INTC_INTREQ (INTC_BASE+0x24)
14#define INTC_INTMSK0 (INTC_BASE+0x44)
15#define INTC_INTMSK1 (INTC_BASE+0x48)
16#define INTC_INTMSK2 (INTC_BASE+0x40080)
17#define INTC_INTMSKCLR0 (INTC_BASE+0x64)
18#define INTC_INTMSKCLR1 (INTC_BASE+0x68)
19#define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
20#define INTC_NMIFCR (INTC_BASE+0xc0)
21#define INTC_USERIMASK (INTC_BASE+0x30000)
22
23#define INTC_INT2PRI0 (INTC_BASE+0x40000)
24#define INTC_INT2PRI1 (INTC_BASE+0x40004)
25#define INTC_INT2PRI2 (INTC_BASE+0x40008)
26#define INTC_INT2PRI3 (INTC_BASE+0x4000c)
27#define INTC_INT2PRI4 (INTC_BASE+0x40010)
28#define INTC_INT2PRI5 (INTC_BASE+0x40014)
29#define INTC_INT2PRI6 (INTC_BASE+0x40018)
30#define INTC_INT2PRI7 (INTC_BASE+0x4001c)
31#define INTC_INT2A0 (INTC_BASE+0x40030)
32#define INTC_INT2A1 (INTC_BASE+0x40034)
33#define INTC_INT2MSKR (INTC_BASE+0x40038)
34#define INTC_INT2MSKCR (INTC_BASE+0x4003c)
35#define INTC_INT2B0 (INTC_BASE+0x40040)
36#define INTC_INT2B1 (INTC_BASE+0x40044)
37#define INTC_INT2B2 (INTC_BASE+0x40048)
38#define INTC_INT2B3 (INTC_BASE+0x4004c)
39#define INTC_INT2B4 (INTC_BASE+0x40050)
40#define INTC_INT2B5 (INTC_BASE+0x40054)
41#define INTC_INT2B6 (INTC_BASE+0x40058)
42#define INTC_INT2B7 (INTC_BASE+0x4005c)
43#define INTC_INT2GPIC (INTC_BASE+0x40090)
44/*
45 NOTE:
46 *_IRQ = (INTEVT2 - 0x200)/0x20
47*/
48/* IRQ 0-7 line external int*/
49#define IRQ0_IRQ 2
50#define IRQ0_IPR_ADDR INTC_INTPRI
51#define IRQ0_IPR_POS 7
52#define IRQ0_PRIORITY 2
53
54#define IRQ1_IRQ 4
55#define IRQ1_IPR_ADDR INTC_INTPRI
56#define IRQ1_IPR_POS 6
57#define IRQ1_PRIORITY 2
58
59#define IRQ2_IRQ 6
60#define IRQ2_IPR_ADDR INTC_INTPRI
61#define IRQ2_IPR_POS 5
62#define IRQ2_PRIORITY 2
63
64#define IRQ3_IRQ 8
65#define IRQ3_IPR_ADDR INTC_INTPRI
66#define IRQ3_IPR_POS 4
67#define IRQ3_PRIORITY 2
68
69#define IRQ4_IRQ 10
70#define IRQ4_IPR_ADDR INTC_INTPRI
71#define IRQ4_IPR_POS 3
72#define IRQ4_PRIORITY 2
73
74#define IRQ5_IRQ 12
75#define IRQ5_IPR_ADDR INTC_INTPRI
76#define IRQ5_IPR_POS 2
77#define IRQ5_PRIORITY 2
78
79#define IRQ6_IRQ 14
80#define IRQ6_IPR_ADDR INTC_INTPRI
81#define IRQ6_IPR_POS 1
82#define IRQ6_PRIORITY 2
83
84#define IRQ7_IRQ 0
85#define IRQ7_IPR_ADDR INTC_INTPRI
86#define IRQ7_IPR_POS 0
87#define IRQ7_PRIORITY 2
88
89/* TMU */
90/* ch0 */
91#define TMU_IRQ 28
92#define TMU_IPR_ADDR INTC_INT2PRI0
93#define TMU_IPR_POS 3
94#define TMU_PRIORITY 2
95
96#define TIMER_IRQ 28
97#define TIMER_IPR_ADDR INTC_INT2PRI0
98#define TIMER_IPR_POS 3
99#define TIMER_PRIORITY 2
100
101/* ch 1*/
102#define TMU_CH1_IRQ 29
103#define TMU_CH1_IPR_ADDR INTC_INT2PRI0
104#define TMU_CH1_IPR_POS 2
105#define TMU_CH1_PRIORITY 2
106
107#define TIMER1_IRQ 29
108#define TIMER1_IPR_ADDR INTC_INT2PRI0
109#define TIMER1_IPR_POS 2
110#define TIMER1_PRIORITY 2
111
112/* ch 2*/
113#define TMU_CH2_IRQ 30
114#define TMU_CH2_IPR_ADDR INTC_INT2PRI0
115#define TMU_CH2_IPR_POS 1
116#define TMU_CH2_PRIORITY 2
117/* ch 2 Input capture */
118#define TMU_CH2IC_IRQ 31
119#define TMU_CH2IC_IPR_ADDR INTC_INT2PRI0
120#define TMU_CH2IC_IPR_POS 0
121#define TMU_CH2IC_PRIORITY 2
122/* ch 3 */
123#define TMU_CH3_IRQ 96
124#define TMU_CH3_IPR_ADDR INTC_INT2PRI1
125#define TMU_CH3_IPR_POS 3
126#define TMU_CH3_PRIORITY 2
127/* ch 4 */
128#define TMU_CH4_IRQ 97
129#define TMU_CH4_IPR_ADDR INTC_INT2PRI1
130#define TMU_CH4_IPR_POS 2
131#define TMU_CH4_PRIORITY 2
132/* ch 5*/
133#define TMU_CH5_IRQ 98
134#define TMU_CH5_IPR_ADDR INTC_INT2PRI1
135#define TMU_CH5_IPR_POS 1
136#define TMU_CH5_PRIORITY 2
137
138/* SCIF0 */
139#define SCIF0_ERI_IRQ 40
140#define SCIF0_RXI_IRQ 41
141#define SCIF0_BRI_IRQ 42
142#define SCIF0_TXI_IRQ 43
143#define SCIF0_IPR_ADDR INTC_INT2PRI2
144#define SCIF0_IPR_POS 3
145#define SCIF0_PRIORITY 3
146
147/* SCIF1 */
148#define SCIF1_ERI_IRQ 76
149#define SCIF1_RXI_IRQ 77
150#define SCIF1_BRI_IRQ 78
151#define SCIF1_TXI_IRQ 79
152#define SCIF1_IPR_ADDR INTC_INT2PRI2
153#define SCIF1_IPR_POS 2
154#define SCIF1_PRIORITY 3
155
156#define WDT_IRQ 27
157#define WDT_IPR_ADDR INTC_INT2PRI2
158#define WDT_IPR_POS 1
159#define WDT_PRIORITY 2
160
161/* DMAC(0) */
162#define DMINT0_IRQ 34
163#define DMINT1_IRQ 35
164#define DMINT2_IRQ 36
165#define DMINT3_IRQ 37
166#define DMINT4_IRQ 44
167#define DMINT5_IRQ 45
168#define DMINT6_IRQ 46
169#define DMINT7_IRQ 47
170#define DMAE_IRQ 38
171#define DMA0_IPR_ADDR INTC_INT2PRI3
172#define DMA0_IPR_POS 2
173#define DMA0_PRIORITY 7
174
175/* DMAC(1) */
176#define DMINT8_IRQ 92
177#define DMINT9_IRQ 93
178#define DMINT10_IRQ 94
179#define DMINT11_IRQ 95
180#define DMA1_IPR_ADDR INTC_INT2PRI3
181#define DMA1_IPR_POS 1
182#define DMA1_PRIORITY 7
183
184#define DMTE0_IRQ DMINT0_IRQ
185#define DMTE4_IRQ DMINT4_IRQ
186#define DMA_IPR_ADDR DMA0_IPR_ADDR
187#define DMA_IPR_POS DMA0_IPR_POS
188#define DMA_PRIORITY DMA0_PRIORITY
189
190/* CMT */
191#define CMT_IRQ 56
192#define CMT_IPR_ADDR INTC_INT2PRI4
193#define CMT_IPR_POS 3
194#define CMT_PRIORITY 0
195
196/* HAC */
197#define HAC_IRQ 60
198#define HAC_IPR_ADDR INTC_INT2PRI4
199#define HAC_IPR_POS 2
200#define CMT_PRIORITY 0
201
202/* PCIC(0) */
203#define PCIC0_IRQ 64
204#define PCIC0_IPR_ADDR INTC_INT2PRI4
205#define PCIC0_IPR_POS 1
206#define PCIC0_PRIORITY 2
207
208/* PCIC(1) */
209#define PCIC1_IRQ 65
210#define PCIC1_IPR_ADDR INTC_INT2PRI4
211#define PCIC1_IPR_POS 0
212#define PCIC1_PRIORITY 2
213
214/* PCIC(2) */
215#define PCIC2_IRQ 66
216#define PCIC2_IPR_ADDR INTC_INT2PRI5
217#define PCIC2_IPR_POS 3
218#define PCIC2_PRIORITY 2
219
220/* PCIC(3) */
221#define PCIC3_IRQ 67
222#define PCIC3_IPR_ADDR INTC_INT2PRI5
223#define PCIC3_IPR_POS 2
224#define PCIC3_PRIORITY 2
225
226/* PCIC(4) */
227#define PCIC4_IRQ 68
228#define PCIC4_IPR_ADDR INTC_INT2PRI5
229#define PCIC4_IPR_POS 1
230#define PCIC4_PRIORITY 2
231
232/* PCIC(5) */
233#define PCICERR_IRQ 69
234#define PCICPWD3_IRQ 70
235#define PCICPWD2_IRQ 71
236#define PCICPWD1_IRQ 72
237#define PCICPWD0_IRQ 73
238#define PCIC5_IPR_ADDR INTC_INT2PRI5
239#define PCIC5_IPR_POS 0
240#define PCIC5_PRIORITY 2
241
242/* SIOF */
243#define SIOF_IRQ 80
244#define SIOF_IPR_ADDR INTC_INT2PRI6
245#define SIOF_IPR_POS 3
246#define SIOF_PRIORITY 3
247
248/* HSPI */
249#define HSPI_IRQ 84
250#define HSPI_IPR_ADDR INTC_INT2PRI6
251#define HSPI_IPR_POS 2
252#define HSPI_PRIORITY 3
253
254/* MMCIF */
255#define MMCIF_FSTAT_IRQ 88
256#define MMCIF_TRAN_IRQ 89
257#define MMCIF_ERR_IRQ 90
258#define MMCIF_FRDY_IRQ 91
259#define MMCIF_IPR_ADDR INTC_INT2PRI6
260#define MMCIF_IPR_POS 1
261#define HSPI_PRIORITY 3
262
263/* SSI */
264#define SSI_IRQ 100
265#define SSI_IPR_ADDR INTC_INT2PRI6
266#define SSI_IPR_POS 0
267#define SSI_PRIORITY 3
268
269/* FLCTL */
270#define FLCTL_FLSTE_IRQ 104
271#define FLCTL_FLTEND_IRQ 105
272#define FLCTL_FLTRQ0_IRQ 106
273#define FLCTL_FLTRQ1_IRQ 107
274#define FLCTL_IPR_ADDR INTC_INT2PRI7
275#define FLCTL_IPR_POS 3
276#define FLCTL_PRIORITY 3
277
278/* GPIO */
279#define GPIO0_IRQ 108
280#define GPIO1_IRQ 109
281#define GPIO2_IRQ 110
282#define GPIO3_IRQ 111
283#define GPIO_IPR_ADDR INTC_INT2PRI7
284#define GPIO_IPR_POS 2
285#define GPIO_PRIORITY 3
286
287#define INTC_TMU0_MSK 0
288#define INTC_TMU3_MSK 1
289#define INTC_RTC_MSK 2
290#define INTC_SCIF0_MSK 3
291#define INTC_SCIF1_MSK 4
292#define INTC_WDT_MSK 5
293#define INTC_HUID_MSK 7
294#define INTC_DMAC0_MSK 8
295#define INTC_DMAC1_MSK 9
296#define INTC_CMT_MSK 12
297#define INTC_HAC_MSK 13
298#define INTC_PCIC0_MSK 14
299#define INTC_PCIC1_MSK 15
300#define INTC_PCIC2_MSK 16
301#define INTC_PCIC3_MSK 17
302#define INTC_PCIC4_MSK 18
303#define INTC_PCIC5_MSK 19
304#define INTC_SIOF_MSK 20
305#define INTC_HSPI_MSK 21
306#define INTC_MMCIF_MSK 22
307#define INTC_SSI_MSK 23
308#define INTC_FLCTL_MSK 24
309#define INTC_GPIO_MSK 25
310
311#endif /* __ASM_SH_IRQ_SH7780_H */
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index 6cd3e9e2a76a..fd576088e47e 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -1,233 +1,9 @@
1#ifndef __ASM_SH_IRQ_H 1#ifndef __ASM_SH_IRQ_H
2#define __ASM_SH_IRQ_H 2#define __ASM_SH_IRQ_H
3 3
4/*
5 *
6 * linux/include/asm-sh/irq.h
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2003 Paul Mundt
11 *
12 */
13
14#include <asm/machvec.h> 4#include <asm/machvec.h>
15#include <asm/ptrace.h> /* for pt_regs */ 5#include <asm/ptrace.h> /* for pt_regs */
16 6
17#ifndef CONFIG_CPU_SUBTYPE_SH7780
18
19#define INTC_DMAC0_MSK 0
20
21#if defined(CONFIG_CPU_SH3)
22#define INTC_IPRA 0xfffffee2UL
23#define INTC_IPRB 0xfffffee4UL
24#elif defined(CONFIG_CPU_SH4)
25#define INTC_IPRA 0xffd00004UL
26#define INTC_IPRB 0xffd00008UL
27#define INTC_IPRC 0xffd0000cUL
28#define INTC_IPRD 0xffd00010UL
29#endif
30
31#define TIMER_IRQ 16
32#define TIMER_IPR_ADDR INTC_IPRA
33#define TIMER_IPR_POS 3
34#define TIMER_PRIORITY 2
35
36#define TIMER1_IRQ 17
37#define TIMER1_IPR_ADDR INTC_IPRA
38#define TIMER1_IPR_POS 2
39#define TIMER1_PRIORITY 4
40
41#define RTC_IRQ 22
42#define RTC_IPR_ADDR INTC_IPRA
43#define RTC_IPR_POS 0
44#define RTC_PRIORITY TIMER_PRIORITY
45
46#if defined(CONFIG_CPU_SH3)
47#define DMTE0_IRQ 48
48#define DMTE1_IRQ 49
49#define DMTE2_IRQ 50
50#define DMTE3_IRQ 51
51#define DMA_IPR_ADDR INTC_IPRE
52#define DMA_IPR_POS 3
53#define DMA_PRIORITY 7
54#if defined(CONFIG_CPU_SUBTYPE_SH7300)
55/* TMU2 */
56#define TIMER2_IRQ 18
57#define TIMER2_IPR_ADDR INTC_IPRA
58#define TIMER2_IPR_POS 1
59#define TIMER2_PRIORITY 2
60
61/* WDT */
62#define WDT_IRQ 27
63#define WDT_IPR_ADDR INTC_IPRB
64#define WDT_IPR_POS 3
65#define WDT_PRIORITY 2
66
67/* SIM (SIM Card Module) */
68#define SIM_ERI_IRQ 23
69#define SIM_RXI_IRQ 24
70#define SIM_TXI_IRQ 25
71#define SIM_TEND_IRQ 26
72#define SIM_IPR_ADDR INTC_IPRB
73#define SIM_IPR_POS 1
74#define SIM_PRIORITY 2
75
76/* VIO (Video I/O) */
77#define VIO_IRQ 52
78#define VIO_IPR_ADDR INTC_IPRE
79#define VIO_IPR_POS 2
80#define VIO_PRIORITY 2
81
82/* MFI (Multi Functional Interface) */
83#define MFI_IRQ 56
84#define MFI_IPR_ADDR INTC_IPRE
85#define MFI_IPR_POS 1
86#define MFI_PRIORITY 2
87
88/* VPU (Video Processing Unit) */
89#define VPU_IRQ 60
90#define VPU_IPR_ADDR INTC_IPRE
91#define VPU_IPR_POS 0
92#define VPU_PRIORITY 2
93
94/* KEY (Key Scan Interface) */
95#define KEY_IRQ 79
96#define KEY_IPR_ADDR INTC_IPRF
97#define KEY_IPR_POS 3
98#define KEY_PRIORITY 2
99
100/* CMT (Compare Match Timer) */
101#define CMT_IRQ 104
102#define CMT_IPR_ADDR INTC_IPRF
103#define CMT_IPR_POS 0
104#define CMT_PRIORITY 2
105
106/* DMAC(1) */
107#define DMTE0_IRQ 48
108#define DMTE1_IRQ 49
109#define DMTE2_IRQ 50
110#define DMTE3_IRQ 51
111#define DMA1_IPR_ADDR INTC_IPRE
112#define DMA1_IPR_POS 3
113#define DMA1_PRIORITY 7
114
115/* DMAC(2) */
116#define DMTE4_IRQ 76
117#define DMTE5_IRQ 77
118#define DMA2_IPR_ADDR INTC_IPRF
119#define DMA2_IPR_POS 2
120#define DMA2_PRIORITY 7
121
122/* SIOF0 */
123#define SIOF0_IRQ 84
124#define SIOF0_IPR_ADDR INTC_IPRH
125#define SIOF0_IPR_POS 3
126#define SIOF0_PRIORITY 3
127
128/* FLCTL (Flash Memory Controller) */
129#define FLSTE_IRQ 92
130#define FLTEND_IRQ 93
131#define FLTRQ0_IRQ 94
132#define FLTRQ1_IRQ 95
133#define FLCTL_IPR_ADDR INTC_IPRH
134#define FLCTL_IPR_POS 1
135#define FLCTL_PRIORITY 3
136
137/* IIC (IIC Bus Interface) */
138#define IIC_ALI_IRQ 96
139#define IIC_TACKI_IRQ 97
140#define IIC_WAITI_IRQ 98
141#define IIC_DTEI_IRQ 99
142#define IIC_IPR_ADDR INTC_IPRH
143#define IIC_IPR_POS 0
144#define IIC_PRIORITY 3
145
146/* SIO0 */
147#define SIO0_IRQ 88
148#define SIO0_IPR_ADDR INTC_IPRI
149#define SIO0_IPR_POS 3
150#define SIO0_PRIORITY 3
151
152/* SIU (Sound Interface Unit) */
153#define SIU_IRQ 108
154#define SIU_IPR_ADDR INTC_IPRJ
155#define SIU_IPR_POS 1
156#define SIU_PRIORITY 3
157
158#endif
159#elif defined(CONFIG_CPU_SH4)
160#define DMTE0_IRQ 34
161#define DMTE1_IRQ 35
162#define DMTE2_IRQ 36
163#define DMTE3_IRQ 37
164#define DMTE4_IRQ 44 /* 7751R only */
165#define DMTE5_IRQ 45 /* 7751R only */
166#define DMTE6_IRQ 46 /* 7751R only */
167#define DMTE7_IRQ 47 /* 7751R only */
168#define DMAE_IRQ 38
169#define DMA_IPR_ADDR INTC_IPRC
170#define DMA_IPR_POS 2
171#define DMA_PRIORITY 7
172#endif
173
174#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
175 defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
176 defined (CONFIG_CPU_SUBTYPE_SH7751) || defined (CONFIG_CPU_SUBTYPE_SH7706)
177#define SCI_ERI_IRQ 23
178#define SCI_RXI_IRQ 24
179#define SCI_TXI_IRQ 25
180#define SCI_IPR_ADDR INTC_IPRB
181#define SCI_IPR_POS 1
182#define SCI_PRIORITY 3
183#endif
184
185#if defined(CONFIG_CPU_SUBTYPE_SH7300)
186#define SCIF0_IRQ 80
187#define SCIF0_IPR_ADDR INTC_IPRG
188#define SCIF0_IPR_POS 3
189#define SCIF0_PRIORITY 3
190#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
191 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
192 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
193 defined(CONFIG_CPU_SUBTYPE_SH7709)
194#define SCIF_ERI_IRQ 56
195#define SCIF_RXI_IRQ 57
196#define SCIF_BRI_IRQ 58
197#define SCIF_TXI_IRQ 59
198#define SCIF_IPR_ADDR INTC_IPRE
199#define SCIF_IPR_POS 1
200#define SCIF_PRIORITY 3
201
202#define IRDA_ERI_IRQ 52
203#define IRDA_RXI_IRQ 53
204#define IRDA_BRI_IRQ 54
205#define IRDA_TXI_IRQ 55
206#define IRDA_IPR_ADDR INTC_IPRE
207#define IRDA_IPR_POS 2
208#define IRDA_PRIORITY 3
209#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
210 defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
211#define SCIF_ERI_IRQ 40
212#define SCIF_RXI_IRQ 41
213#define SCIF_BRI_IRQ 42
214#define SCIF_TXI_IRQ 43
215#define SCIF_IPR_ADDR INTC_IPRC
216#define SCIF_IPR_POS 1
217#define SCIF_PRIORITY 3
218#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
219#define SCIF1_ERI_IRQ 23
220#define SCIF1_RXI_IRQ 24
221#define SCIF1_BRI_IRQ 25
222#define SCIF1_TXI_IRQ 26
223#define SCIF1_IPR_ADDR INTC_IPRB
224#define SCIF1_IPR_POS 1
225#define SCIF1_PRIORITY 3
226#endif /* ST40STB1 */
227
228#endif /* 775x / SH4-202 / ST40STB1 */
229#endif /* 7780 */
230
231/* NR_IRQS is made from three components: 7/* NR_IRQS is made from three components:
232 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules 8 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
233 * 2. PINT_NR_IRQS - number of PINT interrupts 9 * 2. PINT_NR_IRQS - number of PINT interrupts
@@ -265,6 +41,10 @@
265# define ONCHIP_NR_IRQS 109 41# define ONCHIP_NR_IRQS 109
266#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 42#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
267# define ONCHIP_NR_IRQS 111 43# define ONCHIP_NR_IRQS 111
44#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
45# define ONCHIP_NR_IRQS 256
46#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
47# define ONCHIP_NR_IRQS 128
268#elif defined(CONFIG_SH_UNKNOWN) /* Most be last */ 48#elif defined(CONFIG_SH_UNKNOWN) /* Most be last */
269# define ONCHIP_NR_IRQS 144 49# define ONCHIP_NR_IRQS 144
270#endif 50#endif
@@ -312,9 +92,11 @@
312/* NR_IRQS. 1+2+3 */ 92/* NR_IRQS. 1+2+3 */
313#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS) 93#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
314 94
315extern void disable_irq(unsigned int); 95/*
316extern void disable_irq_nosync(unsigned int); 96 * Convert back and forth between INTEVT and IRQ values.
317extern void enable_irq(unsigned int); 97 */
98#define evt2irq(evt) (((evt) >> 5) - 16)
99#define irq2evt(irq) (((irq) + 16) << 5)
318 100
319/* 101/*
320 * Simple Mask Register Support 102 * Simple Mask Register Support
@@ -327,362 +109,36 @@ extern unsigned short *irq_mask_register;
327 */ 109 */
328void init_IRQ_pint(void); 110void init_IRQ_pint(void);
329 111
112/*
113 * The shift value is now the number of bits to shift, not the number of
114 * bits/4. This is to make it easier to read the value directly from the
115 * datasheets. The IPR address, addr, will be set from ipr_idx via the
116 * map_ipridx_to_addr function.
117 */
330struct ipr_data { 118struct ipr_data {
331 unsigned int irq; 119 unsigned int irq;
332 unsigned int addr; /* Address of Interrupt Priority Register */ 120 int ipr_idx; /* Index for the IPR registered */
333 int shift; /* Shifts of the 16-bit data */ 121 int shift; /* Number of bits to shift the data */
334 int priority; /* The priority */ 122 int priority; /* The priority */
123 unsigned int addr; /* Address of Interrupt Priority Register */
335}; 124};
336 125
337/* 126/*
338 * Function for "on chip support modules". 127 * Given an IPR IDX, map the value to an IPR register address.
339 */ 128 */
340extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs); 129unsigned int map_ipridx_to_addr(int idx);
341extern void make_imask_irq(unsigned int irq);
342
343#if defined(CONFIG_CPU_SUBTYPE_SH7300)
344#undef INTC_IPRA
345#undef INTC_IPRB
346#define INTC_IPRA 0xA414FEE2UL
347#define INTC_IPRB 0xA414FEE4UL
348#define INTC_IPRC 0xA4140016UL
349#define INTC_IPRD 0xA4140018UL
350#define INTC_IPRE 0xA414001AUL
351#define INTC_IPRF 0xA4080000UL
352#define INTC_IPRG 0xA4080002UL
353#define INTC_IPRH 0xA4080004UL
354#define INTC_IPRI 0xA4080006UL
355#define INTC_IPRJ 0xA4080008UL
356
357#define INTC_IMR0 0xA4080040UL
358#define INTC_IMR1 0xA4080042UL
359#define INTC_IMR2 0xA4080044UL
360#define INTC_IMR3 0xA4080046UL
361#define INTC_IMR4 0xA4080048UL
362#define INTC_IMR5 0xA408004AUL
363#define INTC_IMR6 0xA408004CUL
364#define INTC_IMR7 0xA408004EUL
365#define INTC_IMR8 0xA4080050UL
366#define INTC_IMR9 0xA4080052UL
367#define INTC_IMR10 0xA4080054UL
368
369#define INTC_IMCR0 0xA4080060UL
370#define INTC_IMCR1 0xA4080062UL
371#define INTC_IMCR2 0xA4080064UL
372#define INTC_IMCR3 0xA4080066UL
373#define INTC_IMCR4 0xA4080068UL
374#define INTC_IMCR5 0xA408006AUL
375#define INTC_IMCR6 0xA408006CUL
376#define INTC_IMCR7 0xA408006EUL
377#define INTC_IMCR8 0xA4080070UL
378#define INTC_IMCR9 0xA4080072UL
379#define INTC_IMCR10 0xA4080074UL
380
381#define INTC_ICR0 0xA414FEE0UL
382#define INTC_ICR1 0xA4140010UL
383
384#define INTC_IRR0 0xA4140004UL
385
386#define PORT_PACR 0xA4050100UL
387#define PORT_PBCR 0xA4050102UL
388#define PORT_PCCR 0xA4050104UL
389#define PORT_PDCR 0xA4050106UL
390#define PORT_PECR 0xA4050108UL
391#define PORT_PFCR 0xA405010AUL
392#define PORT_PGCR 0xA405010CUL
393#define PORT_PHCR 0xA405010EUL
394#define PORT_PJCR 0xA4050110UL
395#define PORT_PKCR 0xA4050112UL
396#define PORT_PLCR 0xA4050114UL
397#define PORT_SCPCR 0xA4050116UL
398#define PORT_PMCR 0xA4050118UL
399#define PORT_PNCR 0xA405011AUL
400#define PORT_PQCR 0xA405011CUL
401
402#define PORT_PSELA 0xA4050140UL
403#define PORT_PSELB 0xA4050142UL
404#define PORT_PSELC 0xA4050144UL
405
406#define PORT_HIZCRA 0xA4050146UL
407#define PORT_HIZCRB 0xA4050148UL
408#define PORT_DRVCR 0xA4050150UL
409
410#define PORT_PADR 0xA4050120UL
411#define PORT_PBDR 0xA4050122UL
412#define PORT_PCDR 0xA4050124UL
413#define PORT_PDDR 0xA4050126UL
414#define PORT_PEDR 0xA4050128UL
415#define PORT_PFDR 0xA405012AUL
416#define PORT_PGDR 0xA405012CUL
417#define PORT_PHDR 0xA405012EUL
418#define PORT_PJDR 0xA4050130UL
419#define PORT_PKDR 0xA4050132UL
420#define PORT_PLDR 0xA4050134UL
421#define PORT_SCPDR 0xA4050136UL
422#define PORT_PMDR 0xA4050138UL
423#define PORT_PNDR 0xA405013AUL
424#define PORT_PQDR 0xA405013CUL
425
426#define IRQ0_IRQ 32
427#define IRQ1_IRQ 33
428#define IRQ2_IRQ 34
429#define IRQ3_IRQ 35
430#define IRQ4_IRQ 36
431#define IRQ5_IRQ 37
432
433#define IRQ0_IPR_ADDR INTC_IPRC
434#define IRQ1_IPR_ADDR INTC_IPRC
435#define IRQ2_IPR_ADDR INTC_IPRC
436#define IRQ3_IPR_ADDR INTC_IPRC
437#define IRQ4_IPR_ADDR INTC_IPRD
438#define IRQ5_IPR_ADDR INTC_IPRD
439
440#define IRQ0_IPR_POS 0
441#define IRQ1_IPR_POS 1
442#define IRQ2_IPR_POS 2
443#define IRQ3_IPR_POS 3
444#define IRQ4_IPR_POS 0
445#define IRQ5_IPR_POS 1
446 130
447#define IRQ0_PRIORITY 1 131/*
448#define IRQ1_PRIORITY 1 132 * Enable individual interrupt mode for external IPR IRQs.
449#define IRQ2_PRIORITY 1 133 */
450#define IRQ3_PRIORITY 1 134void ipr_irq_enable_irlm(void);
451#define IRQ4_PRIORITY 1
452#define IRQ5_PRIORITY 1
453
454extern int ipr_irq_demux(int irq);
455#define __irq_demux(irq) ipr_irq_demux(irq)
456
457#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
458#define INTC_IPRA 0xfffffee2UL
459#define INTC_IPRB 0xfffffe60UL
460
461#define INTC_VCRA 0xfffffe62UL
462#define INTC_VCRB 0xfffffe64UL
463#define INTC_VCRC 0xfffffe66UL
464#define INTC_VCRD 0xfffffe68UL
465
466#define INTC_VCRWDT 0xfffffee4UL
467#define INTC_VCRDIV 0xffffff0cUL
468#define INTC_VCRDMA0 0xffffffa0UL
469#define INTC_VCRDMA1 0xffffffa8UL
470
471#define INTC_ICR 0xfffffee0UL
472#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
473 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
474 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
475 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
476 defined(CONFIG_CPU_SUBTYPE_SH7710)
477#define INTC_IRR0 0xa4000004UL
478#define INTC_IRR1 0xa4000006UL
479#define INTC_IRR2 0xa4000008UL
480
481#define INTC_ICR0 0xfffffee0UL
482#define INTC_ICR1 0xa4000010UL
483#define INTC_ICR2 0xa4000012UL
484#define INTC_INTER 0xa4000014UL
485
486#define INTC_IPRC 0xa4000016UL
487#define INTC_IPRD 0xa4000018UL
488#define INTC_IPRE 0xa400001aUL
489#if defined(CONFIG_CPU_SUBTYPE_SH7707)
490#define INTC_IPRF 0xa400001cUL
491#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
492#define INTC_IPRF 0xa4080000UL
493#define INTC_IPRG 0xa4080002UL
494#define INTC_IPRH 0xa4080004UL
495#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
496/* Interrupt Controller Registers */
497#undef INTC_IPRA
498#undef INTC_IPRB
499#define INTC_IPRA 0xA414FEE2UL
500#define INTC_IPRB 0xA414FEE4UL
501#define INTC_IPRF 0xA4080000UL
502#define INTC_IPRG 0xA4080002UL
503#define INTC_IPRH 0xA4080004UL
504#define INTC_IPRI 0xA4080006UL
505
506#undef INTC_ICR0
507#undef INTC_ICR1
508#define INTC_ICR0 0xA414FEE0UL
509#define INTC_ICR1 0xA4140010UL
510
511#define INTC_IRR0 0xa4000004UL
512#define INTC_IRR1 0xa4000006UL
513#define INTC_IRR2 0xa4000008UL
514#define INTC_IRR3 0xa400000AUL
515#define INTC_IRR4 0xa400000CUL
516#define INTC_IRR5 0xa4080020UL
517#define INTC_IRR7 0xa4080024UL
518#define INTC_IRR8 0xa4080026UL
519
520/* Interrupt numbers */
521#define TIMER2_IRQ 18
522#define TIMER2_IPR_ADDR INTC_IPRA
523#define TIMER2_IPR_POS 1
524#define TIMER2_PRIORITY 2
525
526/* WDT */
527#define WDT_IRQ 27
528#define WDT_IPR_ADDR INTC_IPRB
529#define WDT_IPR_POS 3
530#define WDT_PRIORITY 2
531
532#define SCIF0_ERI_IRQ 52
533#define SCIF0_RXI_IRQ 53
534#define SCIF0_BRI_IRQ 54
535#define SCIF0_TXI_IRQ 55
536#define SCIF0_IPR_ADDR INTC_IPRE
537#define SCIF0_IPR_POS 2
538#define SCIF0_PRIORITY 3
539
540#define DMTE4_IRQ 76
541#define DMTE5_IRQ 77
542#define DMA2_IPR_ADDR INTC_IPRF
543#define DMA2_IPR_POS 2
544#define DMA2_PRIORITY 7
545
546#define IPSEC_IRQ 79
547#define IPSEC_IPR_ADDR INTC_IPRF
548#define IPSEC_IPR_POS 3
549#define IPSEC_PRIORITY 3
550
551/* EDMAC */
552#define EDMAC0_IRQ 80
553#define EDMAC0_IPR_ADDR INTC_IPRG
554#define EDMAC0_IPR_POS 3
555#define EDMAC0_PRIORITY 3
556
557#define EDMAC1_IRQ 81
558#define EDMAC1_IPR_ADDR INTC_IPRG
559#define EDMAC1_IPR_POS 2
560#define EDMAC1_PRIORITY 3
561
562#define EDMAC2_IRQ 82
563#define EDMAC2_IPR_ADDR INTC_IPRG
564#define EDMAC2_IPR_POS 1
565#define EDMAC2_PRIORITY 3
566
567/* SIOF */
568#define SIOF0_ERI_IRQ 96
569#define SIOF0_TXI_IRQ 97
570#define SIOF0_RXI_IRQ 98
571#define SIOF0_CCI_IRQ 99
572#define SIOF0_IPR_ADDR INTC_IPRH
573#define SIOF0_IPR_POS 0
574#define SIOF0_PRIORITY 7
575
576#define SIOF1_ERI_IRQ 100
577#define SIOF1_TXI_IRQ 101
578#define SIOF1_RXI_IRQ 102
579#define SIOF1_CCI_IRQ 103
580#define SIOF1_IPR_ADDR INTC_IPRI
581#define SIOF1_IPR_POS 1
582#define SIOF1_PRIORITY 7
583#endif /* CONFIG_CPU_SUBTYPE_SH7710 */
584
585#if defined(CONFIG_CPU_SUBTYPE_SH7710)
586#define PORT_PACR 0xa4050100UL
587#define PORT_PBCR 0xa4050102UL
588#define PORT_PCCR 0xa4050104UL
589#define PORT_PETCR 0xa4050106UL
590#define PORT_PADR 0xa4050120UL
591#define PORT_PBDR 0xa4050122UL
592#define PORT_PCDR 0xa4050124UL
593#else
594#define PORT_PACR 0xa4000100UL
595#define PORT_PBCR 0xa4000102UL
596#define PORT_PCCR 0xa4000104UL
597#define PORT_PFCR 0xa400010aUL
598#define PORT_PADR 0xa4000120UL
599#define PORT_PBDR 0xa4000122UL
600#define PORT_PCDR 0xa4000124UL
601#define PORT_PFDR 0xa400012aUL
602#endif
603
604#define IRQ0_IRQ 32
605#define IRQ1_IRQ 33
606#define IRQ2_IRQ 34
607#define IRQ3_IRQ 35
608#define IRQ4_IRQ 36
609#define IRQ5_IRQ 37
610
611#define IRQ0_IPR_ADDR INTC_IPRC
612#define IRQ1_IPR_ADDR INTC_IPRC
613#define IRQ2_IPR_ADDR INTC_IPRC
614#define IRQ3_IPR_ADDR INTC_IPRC
615#define IRQ4_IPR_ADDR INTC_IPRD
616#define IRQ5_IPR_ADDR INTC_IPRD
617
618#define IRQ0_IPR_POS 0
619#define IRQ1_IPR_POS 1
620#define IRQ2_IPR_POS 2
621#define IRQ3_IPR_POS 3
622#define IRQ4_IPR_POS 0
623#define IRQ5_IPR_POS 1
624
625#define IRQ0_PRIORITY 1
626#define IRQ1_PRIORITY 1
627#define IRQ2_PRIORITY 1
628#define IRQ3_PRIORITY 1
629#define IRQ4_PRIORITY 1
630#define IRQ5_PRIORITY 1
631
632#define PINT0_IRQ 40
633#define PINT8_IRQ 41
634
635#define PINT0_IPR_ADDR INTC_IPRD
636#define PINT8_IPR_ADDR INTC_IPRD
637
638#define PINT0_IPR_POS 3
639#define PINT8_IPR_POS 2
640#define PINT0_PRIORITY 2
641#define PINT8_PRIORITY 2
642
643extern int ipr_irq_demux(int irq);
644#define __irq_demux(irq) ipr_irq_demux(irq)
645#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
646
647#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
648 defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
649#define INTC_ICR 0xffd00000
650#define INTC_ICR_NMIL (1<<15)
651#define INTC_ICR_MAI (1<<14)
652#define INTC_ICR_NMIB (1<<9)
653#define INTC_ICR_NMIE (1<<8)
654#define INTC_ICR_IRLM (1<<7)
655#endif
656
657#ifdef CONFIG_CPU_SUBTYPE_SH7780
658#include <asm/irq-sh7780.h>
659#endif
660
661/* SH with INTC2-style interrupts */
662#ifdef CONFIG_CPU_HAS_INTC2_IRQ
663#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
664#define INTC2_BASE 0xfe080000
665#define INTC2_FIRST_IRQ 64
666#define INTC2_INTREQ_OFFSET 0x20
667#define INTC2_INTMSK_OFFSET 0x40
668#define INTC2_INTMSKCLR_OFFSET 0x60
669#define NR_INTC2_IRQS 25
670#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
671#define INTC2_BASE 0xfe080000
672#define INTC2_FIRST_IRQ 48 /* INTEVT 0x800 */
673#define INTC2_INTREQ_OFFSET 0x20
674#define INTC2_INTMSK_OFFSET 0x40
675#define INTC2_INTMSKCLR_OFFSET 0x60
676#define NR_INTC2_IRQS 64
677#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
678#define INTC2_BASE 0xffd40000
679#define INTC2_FIRST_IRQ 21
680#define INTC2_INTMSK_OFFSET (0x38)
681#define INTC2_INTMSKCLR_OFFSET (0x3c)
682#define NR_INTC2_IRQS 60
683#endif
684 135
685#define INTC2_INTPRI_OFFSET 0x00 136/*
137 * Function for "on chip support modules".
138 */
139void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
140void make_imask_irq(unsigned int irq);
141void init_IRQ_ipr(void);
686 142
687struct intc2_data { 143struct intc2_data {
688 unsigned short irq; 144 unsigned short irq;
@@ -693,20 +149,14 @@ struct intc2_data {
693 149
694void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs); 150void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs);
695void init_IRQ_intc2(void); 151void init_IRQ_intc2(void);
696#endif
697
698extern int shmse_irq_demux(int irq);
699 152
700static inline int generic_irq_demux(int irq) 153static inline int generic_irq_demux(int irq)
701{ 154{
702 return irq; 155 return irq;
703} 156}
704 157
705#ifndef __irq_demux
706#define __irq_demux(irq) (irq)
707#endif
708#define irq_canonicalize(irq) (irq) 158#define irq_canonicalize(irq) (irq)
709#define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq)) 159#define irq_demux(irq) sh_mv.mv_irq_demux(irq)
710 160
711#ifdef CONFIG_4KSTACKS 161#ifdef CONFIG_4KSTACKS
712extern void irq_ctx_init(int cpu); 162extern void irq_ctx_init(int cpu);
@@ -717,12 +167,4 @@ extern void irq_ctx_exit(int cpu);
717# define irq_ctx_exit(cpu) do { } while (0) 167# define irq_ctx_exit(cpu) do { } while (0)
718#endif 168#endif
719 169
720#if defined(CONFIG_CPU_SUBTYPE_SH73180)
721#include <asm/irq-sh73180.h>
722#endif
723
724#if defined(CONFIG_CPU_SUBTYPE_SH7343)
725#include <asm/irq-sh7343.h>
726#endif
727
728#endif /* __ASM_SH_IRQ_H */ 170#endif /* __ASM_SH_IRQ_H */
diff --git a/include/asm-sh/irqflags.h b/include/asm-sh/irqflags.h
new file mode 100644
index 000000000000..9dedc1b693e3
--- /dev/null
+++ b/include/asm-sh/irqflags.h
@@ -0,0 +1,123 @@
1#ifndef __ASM_SH_IRQFLAGS_H
2#define __ASM_SH_IRQFLAGS_H
3
4static inline void raw_local_irq_enable(void)
5{
6 unsigned long __dummy0, __dummy1;
7
8 __asm__ __volatile__ (
9 "stc sr, %0\n\t"
10 "and %1, %0\n\t"
11#ifdef CONFIG_CPU_HAS_SR_RB
12 "stc r6_bank, %1\n\t"
13 "or %1, %0\n\t"
14#endif
15 "ldc %0, sr\n\t"
16 : "=&r" (__dummy0), "=r" (__dummy1)
17 : "1" (~0x000000f0)
18 : "memory"
19 );
20}
21
22static inline void raw_local_irq_disable(void)
23{
24 unsigned long flags;
25
26 __asm__ __volatile__ (
27 "stc sr, %0\n\t"
28 "or #0xf0, %0\n\t"
29 "ldc %0, sr\n\t"
30 : "=&z" (flags)
31 : /* no inputs */
32 : "memory"
33 );
34}
35
36static inline void set_bl_bit(void)
37{
38 unsigned long __dummy0, __dummy1;
39
40 __asm__ __volatile__ (
41 "stc sr, %0\n\t"
42 "or %2, %0\n\t"
43 "and %3, %0\n\t"
44 "ldc %0, sr\n\t"
45 : "=&r" (__dummy0), "=r" (__dummy1)
46 : "r" (0x10000000), "r" (0xffffff0f)
47 : "memory"
48 );
49}
50
51static inline void clear_bl_bit(void)
52{
53 unsigned long __dummy0, __dummy1;
54
55 __asm__ __volatile__ (
56 "stc sr, %0\n\t"
57 "and %2, %0\n\t"
58 "ldc %0, sr\n\t"
59 : "=&r" (__dummy0), "=r" (__dummy1)
60 : "1" (~0x10000000)
61 : "memory"
62 );
63}
64
65static inline unsigned long __raw_local_save_flags(void)
66{
67 unsigned long flags;
68
69 __asm__ __volatile__ (
70 "stc sr, %0\n\t"
71 "and #0xf0, %0\n\t"
72 : "=&z" (flags)
73 : /* no inputs */
74 : "memory"
75 );
76
77 return flags;
78}
79
80#define raw_local_save_flags(flags) \
81 do { (flags) = __raw_local_save_flags(); } while (0)
82
83static inline int raw_irqs_disabled_flags(unsigned long flags)
84{
85 return (flags != 0);
86}
87
88static inline int raw_irqs_disabled(void)
89{
90 unsigned long flags = __raw_local_save_flags();
91
92 return raw_irqs_disabled_flags(flags);
93}
94
95static inline unsigned long __raw_local_irq_save(void)
96{
97 unsigned long flags, __dummy;
98
99 __asm__ __volatile__ (
100 "stc sr, %1\n\t"
101 "mov %1, %0\n\t"
102 "or #0xf0, %0\n\t"
103 "ldc %0, sr\n\t"
104 "mov %1, %0\n\t"
105 "and #0xf0, %0\n\t"
106 : "=&z" (flags), "=&r" (__dummy)
107 : /* no inputs */
108 : "memory"
109 );
110
111 return flags;
112}
113
114#define raw_local_irq_save(flags) \
115 do { (flags) = __raw_local_irq_save(); } while (0)
116
117static inline void raw_local_irq_restore(unsigned long flags)
118{
119 if ((flags & 0xf0) != 0xf0)
120 raw_local_irq_enable();
121}
122
123#endif /* __ASM_SH_IRQFLAGS_H */
diff --git a/include/asm-sh/mmu_context.h b/include/asm-sh/mmu_context.h
index c7088efe579a..46f04e23bd45 100644
--- a/include/asm-sh/mmu_context.h
+++ b/include/asm-sh/mmu_context.h
@@ -10,7 +10,6 @@
10 10
11#include <asm/cpu/mmu_context.h> 11#include <asm/cpu/mmu_context.h>
12#include <asm/tlbflush.h> 12#include <asm/tlbflush.h>
13#include <asm/pgalloc.h>
14#include <asm/uaccess.h> 13#include <asm/uaccess.h>
15#include <asm/io.h> 14#include <asm/io.h>
16 15
@@ -42,10 +41,8 @@ extern unsigned long mmu_context_cache;
42/* 41/*
43 * Get MMU context if needed. 42 * Get MMU context if needed.
44 */ 43 */
45static __inline__ void 44static inline void get_mmu_context(struct mm_struct *mm)
46get_mmu_context(struct mm_struct *mm)
47{ 45{
48 extern void flush_tlb_all(void);
49 unsigned long mc = mmu_context_cache; 46 unsigned long mc = mmu_context_cache;
50 47
51 /* Check if we have old version of context. */ 48 /* Check if we have old version of context. */
@@ -61,6 +58,7 @@ get_mmu_context(struct mm_struct *mm)
61 * Flush all TLB and start new cycle. 58 * Flush all TLB and start new cycle.
62 */ 59 */
63 flush_tlb_all(); 60 flush_tlb_all();
61
64 /* 62 /*
65 * Fix version; Note that we avoid version #0 63 * Fix version; Note that we avoid version #0
66 * to distingush NO_CONTEXT. 64 * to distingush NO_CONTEXT.
@@ -75,11 +73,10 @@ get_mmu_context(struct mm_struct *mm)
75 * Initialize the context related info for a new mm_struct 73 * Initialize the context related info for a new mm_struct
76 * instance. 74 * instance.
77 */ 75 */
78static __inline__ int init_new_context(struct task_struct *tsk, 76static inline int init_new_context(struct task_struct *tsk,
79 struct mm_struct *mm) 77 struct mm_struct *mm)
80{ 78{
81 mm->context.id = NO_CONTEXT; 79 mm->context.id = NO_CONTEXT;
82
83 return 0; 80 return 0;
84} 81}
85 82
@@ -87,12 +84,12 @@ static __inline__ int init_new_context(struct task_struct *tsk,
87 * Destroy context related info for an mm_struct that is about 84 * Destroy context related info for an mm_struct that is about
88 * to be put to rest. 85 * to be put to rest.
89 */ 86 */
90static __inline__ void destroy_context(struct mm_struct *mm) 87static inline void destroy_context(struct mm_struct *mm)
91{ 88{
92 /* Do nothing */ 89 /* Do nothing */
93} 90}
94 91
95static __inline__ void set_asid(unsigned long asid) 92static inline void set_asid(unsigned long asid)
96{ 93{
97 unsigned long __dummy; 94 unsigned long __dummy;
98 95
@@ -105,7 +102,7 @@ static __inline__ void set_asid(unsigned long asid)
105 "r" (0xffffff00)); 102 "r" (0xffffff00));
106} 103}
107 104
108static __inline__ unsigned long get_asid(void) 105static inline unsigned long get_asid(void)
109{ 106{
110 unsigned long asid; 107 unsigned long asid;
111 108
@@ -120,24 +117,29 @@ static __inline__ unsigned long get_asid(void)
120 * After we have set current->mm to a new value, this activates 117 * After we have set current->mm to a new value, this activates
121 * the context for the new mm so we see the new mappings. 118 * the context for the new mm so we see the new mappings.
122 */ 119 */
123static __inline__ void activate_context(struct mm_struct *mm) 120static inline void activate_context(struct mm_struct *mm)
124{ 121{
125 get_mmu_context(mm); 122 get_mmu_context(mm);
126 set_asid(mm->context.id & MMU_CONTEXT_ASID_MASK); 123 set_asid(mm->context.id & MMU_CONTEXT_ASID_MASK);
127} 124}
128 125
129/* MMU_TTB can be used for optimizing the fault handling. 126/* MMU_TTB is used for optimizing the fault handling. */
130 (Currently not used) */ 127static inline void set_TTB(pgd_t *pgd)
131static __inline__ void switch_mm(struct mm_struct *prev,
132 struct mm_struct *next,
133 struct task_struct *tsk)
134{ 128{
135 if (likely(prev != next)) { 129 ctrl_outl((unsigned long)pgd, MMU_TTB);
136 unsigned long __pgdir = (unsigned long)next->pgd; 130}
137 131
138 __asm__ __volatile__("mov.l %0, %1" 132static inline pgd_t *get_TTB(void)
139 : /* no output */ 133{
140 : "r" (__pgdir), "m" (__m(MMU_TTB))); 134 return (pgd_t *)ctrl_inl(MMU_TTB);
135}
136
137static inline void switch_mm(struct mm_struct *prev,
138 struct mm_struct *next,
139 struct task_struct *tsk)
140{
141 if (likely(prev != next)) {
142 set_TTB(next->pgd);
141 activate_context(next); 143 activate_context(next);
142 } 144 }
143} 145}
@@ -147,7 +149,7 @@ static __inline__ void switch_mm(struct mm_struct *prev,
147#define activate_mm(prev, next) \ 149#define activate_mm(prev, next) \
148 switch_mm((prev),(next),NULL) 150 switch_mm((prev),(next),NULL)
149 151
150static __inline__ void 152static inline void
151enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 153enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
152{ 154{
153} 155}
diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h
index ca8b26d90475..380fd62dd05a 100644
--- a/include/asm-sh/page.h
+++ b/include/asm-sh/page.h
@@ -13,9 +13,16 @@
13 [ P4 control ] 0xE0000000 13 [ P4 control ] 0xE0000000
14 */ 14 */
15 15
16
17/* PAGE_SHIFT determines the page size */ 16/* PAGE_SHIFT determines the page size */
18#define PAGE_SHIFT 12 17#if defined(CONFIG_PAGE_SIZE_4KB)
18# define PAGE_SHIFT 12
19#elif defined(CONFIG_PAGE_SIZE_8KB)
20# define PAGE_SHIFT 13
21#elif defined(CONFIG_PAGE_SIZE_64KB)
22# define PAGE_SHIFT 16
23#else
24# error "Bogus kernel page size?"
25#endif
19 26
20#ifdef __ASSEMBLY__ 27#ifdef __ASSEMBLY__
21#define PAGE_SIZE (1 << PAGE_SHIFT) 28#define PAGE_SIZE (1 << PAGE_SHIFT)
@@ -28,8 +35,14 @@
28 35
29#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K) 36#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
30#define HPAGE_SHIFT 16 37#define HPAGE_SHIFT 16
38#elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
39#define HPAGE_SHIFT 18
31#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB) 40#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
32#define HPAGE_SHIFT 20 41#define HPAGE_SHIFT 20
42#elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
43#define HPAGE_SHIFT 22
44#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
45#define HPAGE_SHIFT 26
33#endif 46#endif
34 47
35#ifdef CONFIG_HUGETLB_PAGE 48#ifdef CONFIG_HUGETLB_PAGE
@@ -69,15 +82,25 @@ extern void __copy_user_page(void *to, void *from, void *orig_to);
69/* 82/*
70 * These are used to make use of C type-checking.. 83 * These are used to make use of C type-checking..
71 */ 84 */
72typedef struct { unsigned long pte; } pte_t; 85#ifdef CONFIG_X2TLB
73typedef struct { unsigned long pgd; } pgd_t; 86typedef struct { unsigned long pte_low, pte_high; } pte_t;
87typedef struct { unsigned long long pgprot; } pgprot_t;
88#define pte_val(x) \
89 ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
90#define __pte(x) \
91 ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
92#else
93typedef struct { unsigned long pte_low; } pte_t;
74typedef struct { unsigned long pgprot; } pgprot_t; 94typedef struct { unsigned long pgprot; } pgprot_t;
95#define pte_val(x) ((x).pte_low)
96#define __pte(x) ((pte_t) { (x) } )
97#endif
98
99typedef struct { unsigned long pgd; } pgd_t;
75 100
76#define pte_val(x) ((x).pte)
77#define pgd_val(x) ((x).pgd) 101#define pgd_val(x) ((x).pgd)
78#define pgprot_val(x) ((x).pgprot) 102#define pgprot_val(x) ((x).pgprot)
79 103
80#define __pte(x) ((pte_t) { (x) } )
81#define __pgd(x) ((pgd_t) { (x) } ) 104#define __pgd(x) ((pgd_t) { (x) } )
82#define __pgprot(x) ((pgprot_t) { (x) } ) 105#define __pgprot(x) ((pgprot_t) { (x) } )
83 106
diff --git a/include/asm-sh/pgalloc.h b/include/asm-sh/pgalloc.h
index e841465ab4d2..888e4529e6fe 100644
--- a/include/asm-sh/pgalloc.h
+++ b/include/asm-sh/pgalloc.h
@@ -1,13 +1,16 @@
1#ifndef __ASM_SH_PGALLOC_H 1#ifndef __ASM_SH_PGALLOC_H
2#define __ASM_SH_PGALLOC_H 2#define __ASM_SH_PGALLOC_H
3 3
4#define pmd_populate_kernel(mm, pmd, pte) \ 4static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
5 set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte))) 5 pte_t *pte)
6{
7 set_pmd(pmd, __pmd((unsigned long)pte));
8}
6 9
7static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, 10static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
8 struct page *pte) 11 struct page *pte)
9{ 12{
10 set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte))); 13 set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
11} 14}
12 15
13/* 16/*
@@ -15,7 +18,16 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
15 */ 18 */
16static inline pgd_t *pgd_alloc(struct mm_struct *mm) 19static inline pgd_t *pgd_alloc(struct mm_struct *mm)
17{ 20{
18 return (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO); 21 pgd_t *pgd = (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT);
22
23 if (pgd) {
24 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
25 memcpy(pgd + USER_PTRS_PER_PGD,
26 swapper_pg_dir + USER_PTRS_PER_PGD,
27 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
28 }
29
30 return pgd;
19} 31}
20 32
21static inline void pgd_free(pgd_t *pgd) 33static inline void pgd_free(pgd_t *pgd)
diff --git a/include/asm-sh/pgtable-2level.h b/include/asm-sh/pgtable-2level.h
deleted file mode 100644
index b525db6f61c6..000000000000
--- a/include/asm-sh/pgtable-2level.h
+++ /dev/null
@@ -1,70 +0,0 @@
1#ifndef __ASM_SH_PGTABLE_2LEVEL_H
2#define __ASM_SH_PGTABLE_2LEVEL_H
3
4/*
5 * traditional two-level paging structure:
6 */
7
8#define PGDIR_SHIFT 22
9#define PTRS_PER_PGD 1024
10
11/*
12 * this is two-level, so we don't really have any
13 * PMD directory physically.
14 */
15#define PMD_SHIFT 22
16#define PTRS_PER_PMD 1
17
18#define PTRS_PER_PTE 1024
19
20#ifndef __ASSEMBLY__
21#define pte_ERROR(e) \
22 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
23#define pmd_ERROR(e) \
24 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
25#define pgd_ERROR(e) \
26 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
27
28/*
29 * The "pgd_xxx()" functions here are trivial for a folded two-level
30 * setup: the pgd is never bad, and a pmd always exists (as it's folded
31 * into the pgd entry)
32 */
33static inline int pgd_none(pgd_t pgd) { return 0; }
34static inline int pgd_bad(pgd_t pgd) { return 0; }
35static inline int pgd_present(pgd_t pgd) { return 1; }
36static inline void pgd_clear (pgd_t * pgdp) { }
37
38/*
39 * Certain architectures need to do special things when PTEs
40 * within a page table are directly modified. Thus, the following
41 * hook is made available.
42 */
43#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
44#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
45
46/*
47 * (pmds are folded into pgds so this doesn't get actually called,
48 * but the define is needed for a generic inline function.)
49 */
50#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
51#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
52
53#define pgd_page_vaddr(pgd) \
54((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
55
56#define pgd_page(pgd) \
57 (phys_to_page(pgd_val(pgd)))
58
59static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
60{
61 return (pmd_t *) dir;
62}
63
64#define pte_pfn(x) ((unsigned long)(((x).pte >> PAGE_SHIFT)))
65#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
66#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
67
68#endif /* !__ASSEMBLY__ */
69
70#endif /* __ASM_SH_PGTABLE_2LEVEL_H */
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h
index 2c8682ad1012..c84901dbd8e5 100644
--- a/include/asm-sh/pgtable.h
+++ b/include/asm-sh/pgtable.h
@@ -15,15 +15,10 @@
15#include <asm-generic/pgtable-nopmd.h> 15#include <asm-generic/pgtable-nopmd.h>
16#include <asm/page.h> 16#include <asm/page.h>
17 17
18#define PTRS_PER_PGD 1024
19
20#ifndef __ASSEMBLY__ 18#ifndef __ASSEMBLY__
21#include <asm/addrspace.h> 19#include <asm/addrspace.h>
22#include <asm/fixmap.h> 20#include <asm/fixmap.h>
23 21
24extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
25extern void paging_init(void);
26
27/* 22/*
28 * ZERO_PAGE is a global shared page that is always zero: used 23 * ZERO_PAGE is a global shared page that is always zero: used
29 * for zero-mapped memory areas etc.. 24 * for zero-mapped memory areas etc..
@@ -33,15 +28,28 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
33 28
34#endif /* !__ASSEMBLY__ */ 29#endif /* !__ASSEMBLY__ */
35 30
36/* traditional two-level paging structure */ 31/*
37#define PGDIR_SHIFT 22 32 * traditional two-level paging structure
38#define PTRS_PER_PMD 1 33 */
39#define PTRS_PER_PTE 1024 34/* PTE bits */
40#define PMD_SIZE (1UL << PMD_SHIFT) 35#ifdef CONFIG_X2TLB
41#define PMD_MASK (~(PMD_SIZE-1)) 36# define PTE_MAGNITUDE 3 /* 64-bit PTEs on extended mode SH-X2 TLB */
42#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 37#else
38# define PTE_MAGNITUDE 2 /* 32-bit PTEs */
39#endif
40#define PTE_SHIFT PAGE_SHIFT
41#define PTE_BITS (PTE_SHIFT - PTE_MAGNITUDE)
42
43/* PGD bits */
44#define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS)
45#define PGDIR_BITS (32 - PGDIR_SHIFT)
46#define PGDIR_SIZE (1 << PGDIR_SHIFT)
43#define PGDIR_MASK (~(PGDIR_SIZE-1)) 47#define PGDIR_MASK (~(PGDIR_SIZE-1))
44 48
49/* Entries per level */
50#define PTRS_PER_PTE (PAGE_SIZE / 4)
51#define PTRS_PER_PGD (PAGE_SIZE / 4)
52
45#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) 53#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
46#define FIRST_USER_ADDRESS 0 54#define FIRST_USER_ADDRESS 0
47 55
@@ -49,7 +57,7 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
49 57
50/* 58/*
51 * First 1MB map is used by fixed purpose. 59 * First 1MB map is used by fixed purpose.
52 * Currently only 4-enty (16kB) is used (see arch/sh/mm/cache.c) 60 * Currently only 4-entry (16kB) is used (see arch/sh/mm/cache.c)
53 */ 61 */
54#define VMALLOC_START (P3SEG+0x00100000) 62#define VMALLOC_START (P3SEG+0x00100000)
55#define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) 63#define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
@@ -57,7 +65,8 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
57/* 65/*
58 * Linux PTEL encoding. 66 * Linux PTEL encoding.
59 * 67 *
60 * Hardware and software bit definitions for the PTEL value: 68 * Hardware and software bit definitions for the PTEL value (see below for
69 * notes on SH-X2 MMUs and 64-bit PTEs):
61 * 70 *
62 * - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4). 71 * - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4).
63 * 72 *
@@ -76,20 +85,57 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
76 * 85 *
77 * - Bits 31, 30, and 29 remain unused by everyone and can be used for future 86 * - Bits 31, 30, and 29 remain unused by everyone and can be used for future
78 * software flags, although care must be taken to update _PAGE_CLEAR_FLAGS. 87 * software flags, although care must be taken to update _PAGE_CLEAR_FLAGS.
88 *
89 * XXX: Leave the _PAGE_FILE and _PAGE_WT overhaul for a rainy day.
90 *
91 * SH-X2 MMUs and extended PTEs
92 *
93 * SH-X2 supports an extended mode TLB with split data arrays due to the
94 * number of bits needed for PR and SZ (now EPR and ESZ) encodings. The PR and
95 * SZ bit placeholders still exist in data array 1, but are implemented as
96 * reserved bits, with the real logic existing in data array 2.
97 *
98 * The downside to this is that we can no longer fit everything in to a 32-bit
99 * PTE encoding, so a 64-bit pte_t is necessary for these parts. On the plus
100 * side, this gives us quite a few spare bits to play with for future usage.
79 */ 101 */
102/* Legacy and compat mode bits */
80#define _PAGE_WT 0x001 /* WT-bit on SH-4, 0 on SH-3 */ 103#define _PAGE_WT 0x001 /* WT-bit on SH-4, 0 on SH-3 */
81#define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */ 104#define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */
82#define _PAGE_DIRTY 0x004 /* D-bit : page changed */ 105#define _PAGE_DIRTY 0x004 /* D-bit : page changed */
83#define _PAGE_CACHABLE 0x008 /* C-bit : cachable */ 106#define _PAGE_CACHABLE 0x008 /* C-bit : cachable */
84#define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */ 107#ifndef CONFIG_X2TLB
85#define _PAGE_RW 0x020 /* PR0-bit : write access allowed */ 108# define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */
86#define _PAGE_USER 0x040 /* PR1-bit : user space access allowed */ 109# define _PAGE_RW 0x020 /* PR0-bit : write access allowed */
87#define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */ 110# define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/
111# define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */
112#endif
88#define _PAGE_PRESENT 0x100 /* V-bit : page is valid */ 113#define _PAGE_PRESENT 0x100 /* V-bit : page is valid */
89#define _PAGE_PROTNONE 0x200 /* software: if not present */ 114#define _PAGE_PROTNONE 0x200 /* software: if not present */
90#define _PAGE_ACCESSED 0x400 /* software: page referenced */ 115#define _PAGE_ACCESSED 0x400 /* software: page referenced */
91#define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */ 116#define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */
92 117
118/* Extended mode bits */
119#define _PAGE_EXT_ESZ0 0x0010 /* ESZ0-bit: Size of page */
120#define _PAGE_EXT_ESZ1 0x0020 /* ESZ1-bit: Size of page */
121#define _PAGE_EXT_ESZ2 0x0040 /* ESZ2-bit: Size of page */
122#define _PAGE_EXT_ESZ3 0x0080 /* ESZ3-bit: Size of page */
123
124#define _PAGE_EXT_USER_EXEC 0x0100 /* EPR0-bit: User space executable */
125#define _PAGE_EXT_USER_WRITE 0x0200 /* EPR1-bit: User space writable */
126#define _PAGE_EXT_USER_READ 0x0400 /* EPR2-bit: User space readable */
127
128#define _PAGE_EXT_KERN_EXEC 0x0800 /* EPR3-bit: Kernel space executable */
129#define _PAGE_EXT_KERN_WRITE 0x1000 /* EPR4-bit: Kernel space writable */
130#define _PAGE_EXT_KERN_READ 0x2000 /* EPR5-bit: Kernel space readable */
131
132/* Wrapper for extended mode pgprot twiddling */
133#ifdef CONFIG_X2TLB
134# define _PAGE_EXT(x) ((unsigned long long)(x) << 32)
135#else
136# define _PAGE_EXT(x) (0)
137#endif
138
93/* software: moves to PTEA.TC (Timing Control) */ 139/* software: moves to PTEA.TC (Timing Control) */
94#define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */ 140#define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */
95#define _PAGE_PCC_AREA6 0x80000000 /* use BSC registers for area6 */ 141#define _PAGE_PCC_AREA6 0x80000000 /* use BSC registers for area6 */
@@ -114,37 +160,160 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
114 160
115#define _PAGE_FLAGS_HARDWARE_MASK (0x1fffffff & ~(_PAGE_CLEAR_FLAGS)) 161#define _PAGE_FLAGS_HARDWARE_MASK (0x1fffffff & ~(_PAGE_CLEAR_FLAGS))
116 162
117/* Hardware flags: SZ0=1 (4k-byte) */ 163/* Hardware flags, page size encoding */
118#define _PAGE_FLAGS_HARD _PAGE_SZ0 164#if defined(CONFIG_X2TLB)
165# if defined(CONFIG_PAGE_SIZE_4KB)
166# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ0)
167# elif defined(CONFIG_PAGE_SIZE_8KB)
168# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ1)
169# elif defined(CONFIG_PAGE_SIZE_64KB)
170# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ2)
171# endif
172#else
173# if defined(CONFIG_PAGE_SIZE_4KB)
174# define _PAGE_FLAGS_HARD _PAGE_SZ0
175# elif defined(CONFIG_PAGE_SIZE_64KB)
176# define _PAGE_FLAGS_HARD _PAGE_SZ1
177# endif
178#endif
119 179
120#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K) 180#if defined(CONFIG_X2TLB)
121#define _PAGE_SZHUGE (_PAGE_SZ1) 181# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
122#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB) 182# define _PAGE_SZHUGE (_PAGE_EXT_ESZ2)
123#define _PAGE_SZHUGE (_PAGE_SZ0 | _PAGE_SZ1) 183# elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
184# define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ2)
185# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
186# define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ1 | _PAGE_EXT_ESZ2)
187# elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
188# define _PAGE_SZHUGE (_PAGE_EXT_ESZ3)
189# elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
190# define _PAGE_SZHUGE (_PAGE_EXT_ESZ2 | _PAGE_EXT_ESZ3)
191# endif
192#else
193# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
194# define _PAGE_SZHUGE (_PAGE_SZ1)
195# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
196# define _PAGE_SZHUGE (_PAGE_SZ0 | _PAGE_SZ1)
197# endif
198#endif
199
200/*
201 * Stub out _PAGE_SZHUGE if we don't have a good definition for it,
202 * to make pte_mkhuge() happy.
203 */
204#ifndef _PAGE_SZHUGE
205# define _PAGE_SZHUGE (_PAGE_FLAGS_HARD)
124#endif 206#endif
125 207
126#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY) 208#define _PAGE_CHG_MASK \
127#define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY) 209 (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY)
128#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY)
129 210
130#ifndef __ASSEMBLY__ 211#ifndef __ASSEMBLY__
131 212
132#ifdef CONFIG_MMU 213#if defined(CONFIG_X2TLB) /* SH-X2 TLB */
133#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE |_PAGE_ACCESSED | _PAGE_FLAGS_HARD) 214#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
134#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_CACHABLE |_PAGE_ACCESSED | _PAGE_FLAGS_HARD) 215 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
135#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_FLAGS_HARD) 216
136#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_FLAGS_HARD) 217#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
137#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD) 218 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
219 _PAGE_EXT(_PAGE_EXT_USER_READ | \
220 _PAGE_EXT_USER_WRITE))
221
222#define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
223 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
224 _PAGE_EXT(_PAGE_EXT_USER_EXEC | \
225 _PAGE_EXT_USER_READ))
226
227#define PAGE_COPY PAGE_EXECREAD
228
229#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
230 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
231 _PAGE_EXT(_PAGE_EXT_USER_READ))
232
233#define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
234 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
235 _PAGE_EXT(_PAGE_EXT_USER_WRITE))
236
237#define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
238 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
239 _PAGE_EXT(_PAGE_EXT_USER_WRITE | \
240 _PAGE_EXT_USER_READ | \
241 _PAGE_EXT_USER_EXEC))
242
243#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
244 _PAGE_DIRTY | _PAGE_ACCESSED | \
245 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
246 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
247 _PAGE_EXT_KERN_WRITE | \
248 _PAGE_EXT_KERN_EXEC))
249
138#define PAGE_KERNEL_NOCACHE \ 250#define PAGE_KERNEL_NOCACHE \
139 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD) 251 __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
140#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD) 252 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
253 _PAGE_FLAGS_HARD | \
254 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
255 _PAGE_EXT_KERN_WRITE | \
256 _PAGE_EXT_KERN_EXEC))
257
258#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
259 _PAGE_DIRTY | _PAGE_ACCESSED | \
260 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
261 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
262 _PAGE_EXT_KERN_EXEC))
263
264#define PAGE_KERNEL_PCC(slot, type) \
265 __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
266 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
267 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
268 _PAGE_EXT_KERN_WRITE | \
269 _PAGE_EXT_KERN_EXEC) \
270 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
271 (type))
272
273#elif defined(CONFIG_MMU) /* SH-X TLB */
274#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
275 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
276
277#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
278 _PAGE_CACHABLE | _PAGE_ACCESSED | \
279 _PAGE_FLAGS_HARD)
280
281#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
282 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
283
284#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
285 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
286
287#define PAGE_EXECREAD PAGE_READONLY
288#define PAGE_RWX PAGE_SHARED
289#define PAGE_WRITEONLY PAGE_SHARED
290
291#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | \
292 _PAGE_DIRTY | _PAGE_ACCESSED | \
293 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
294
295#define PAGE_KERNEL_NOCACHE \
296 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
297 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
298 _PAGE_FLAGS_HARD)
299
300#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
301 _PAGE_DIRTY | _PAGE_ACCESSED | \
302 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
303
141#define PAGE_KERNEL_PCC(slot, type) \ 304#define PAGE_KERNEL_PCC(slot, type) \
142 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_FLAGS_HARD | (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | (type)) 305 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
306 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
307 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
308 (type))
143#else /* no mmu */ 309#else /* no mmu */
144#define PAGE_NONE __pgprot(0) 310#define PAGE_NONE __pgprot(0)
145#define PAGE_SHARED __pgprot(0) 311#define PAGE_SHARED __pgprot(0)
146#define PAGE_COPY __pgprot(0) 312#define PAGE_COPY __pgprot(0)
313#define PAGE_EXECREAD __pgprot(0)
314#define PAGE_RWX __pgprot(0)
147#define PAGE_READONLY __pgprot(0) 315#define PAGE_READONLY __pgprot(0)
316#define PAGE_WRITEONLY __pgprot(0)
148#define PAGE_KERNEL __pgprot(0) 317#define PAGE_KERNEL __pgprot(0)
149#define PAGE_KERNEL_NOCACHE __pgprot(0) 318#define PAGE_KERNEL_NOCACHE __pgprot(0)
150#define PAGE_KERNEL_RO __pgprot(0) 319#define PAGE_KERNEL_RO __pgprot(0)
@@ -154,27 +323,32 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
154#endif /* __ASSEMBLY__ */ 323#endif /* __ASSEMBLY__ */
155 324
156/* 325/*
157 * As i386 and MIPS, SuperH can't do page protection for execute, and 326 * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
158 * considers that the same as a read. Also, write permissions imply 327 * protection for execute, and considers it the same as a read. Also, write
159 * read permissions. This is the closest we can get.. 328 * permission implies read permission. This is the closest we can get..
329 *
330 * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
331 * not only supporting separate execute, read, and write bits, but having
332 * completely separate permission bits for user and kernel space.
160 */ 333 */
334 /*xwr*/
161#define __P000 PAGE_NONE 335#define __P000 PAGE_NONE
162#define __P001 PAGE_READONLY 336#define __P001 PAGE_READONLY
163#define __P010 PAGE_COPY 337#define __P010 PAGE_COPY
164#define __P011 PAGE_COPY 338#define __P011 PAGE_COPY
165#define __P100 PAGE_READONLY 339#define __P100 PAGE_EXECREAD
166#define __P101 PAGE_READONLY 340#define __P101 PAGE_EXECREAD
167#define __P110 PAGE_COPY 341#define __P110 PAGE_COPY
168#define __P111 PAGE_COPY 342#define __P111 PAGE_COPY
169 343
170#define __S000 PAGE_NONE 344#define __S000 PAGE_NONE
171#define __S001 PAGE_READONLY 345#define __S001 PAGE_READONLY
172#define __S010 PAGE_SHARED 346#define __S010 PAGE_WRITEONLY
173#define __S011 PAGE_SHARED 347#define __S011 PAGE_SHARED
174#define __S100 PAGE_READONLY 348#define __S100 PAGE_EXECREAD
175#define __S101 PAGE_READONLY 349#define __S101 PAGE_EXECREAD
176#define __S110 PAGE_SHARED 350#define __S110 PAGE_RWX
177#define __S111 PAGE_SHARED 351#define __S111 PAGE_RWX
178 352
179#ifndef __ASSEMBLY__ 353#ifndef __ASSEMBLY__
180 354
@@ -183,7 +357,17 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
183 * within a page table are directly modified. Thus, the following 357 * within a page table are directly modified. Thus, the following
184 * hook is made available. 358 * hook is made available.
185 */ 359 */
360#ifdef CONFIG_X2TLB
361static inline void set_pte(pte_t *ptep, pte_t pte)
362{
363 ptep->pte_high = pte.pte_high;
364 smp_wmb();
365 ptep->pte_low = pte.pte_low;
366}
367#else
186#define set_pte(pteptr, pteval) (*(pteptr) = pteval) 368#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
369#endif
370
187#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 371#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
188 372
189/* 373/*
@@ -192,18 +376,18 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
192 */ 376 */
193#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) 377#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
194 378
195#define pte_pfn(x) ((unsigned long)(((x).pte >> PAGE_SHIFT))) 379#define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
196#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) 380#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
197#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) 381#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
198 382
199#define pte_none(x) (!pte_val(x)) 383#define pte_none(x) (!pte_val(x))
200#define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE)) 384#define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
201#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0) 385#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
202 386
203#define pmd_none(x) (!pmd_val(x)) 387#define pmd_none(x) (!pmd_val(x))
204#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT) 388#define pmd_present(x) (pmd_val(x))
205#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0) 389#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
206#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE) 390#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
207 391
208#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT)) 392#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
209#define pte_page(x) phys_to_page(pte_val(x)&PTE_PHYS_MASK) 393#define pte_page(x) phys_to_page(pte_val(x)&PTE_PHYS_MASK)
@@ -212,28 +396,52 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
212 * The following only work if pte_present() is true. 396 * The following only work if pte_present() is true.
213 * Undefined behaviour if not.. 397 * Undefined behaviour if not..
214 */ 398 */
215static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; } 399#define pte_not_present(pte) (!(pte_val(pte) & _PAGE_PRESENT))
216static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_USER; } 400#define pte_dirty(pte) (pte_val(pte) & _PAGE_DIRTY)
217static inline int pte_dirty(pte_t pte){ return pte_val(pte) & _PAGE_DIRTY; } 401#define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
218static inline int pte_young(pte_t pte){ return pte_val(pte) & _PAGE_ACCESSED; } 402#define pte_file(pte) (pte_val(pte) & _PAGE_FILE)
219static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } 403
220static inline int pte_write(pte_t pte){ return pte_val(pte) & _PAGE_RW; } 404#ifdef CONFIG_X2TLB
221static inline int pte_not_present(pte_t pte){ return !(pte_val(pte) & _PAGE_PRESENT); } 405#define pte_read(pte) ((pte).pte_high & _PAGE_EXT_USER_READ)
222 406#define pte_exec(pte) ((pte).pte_high & _PAGE_EXT_USER_EXEC)
223static inline pte_t pte_rdprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; } 407#define pte_write(pte) ((pte).pte_high & _PAGE_EXT_USER_WRITE)
224static inline pte_t pte_exprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; } 408#else
225static inline pte_t pte_mkclean(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; } 409#define pte_read(pte) (pte_val(pte) & _PAGE_USER)
226static inline pte_t pte_mkold(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; } 410#define pte_exec(pte) (pte_val(pte) & _PAGE_USER)
227static inline pte_t pte_wrprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_RW)); return pte; } 411#define pte_write(pte) (pte_val(pte) & _PAGE_RW)
228static inline pte_t pte_mkread(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; }
229static inline pte_t pte_mkexec(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; }
230static inline pte_t pte_mkdirty(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
231static inline pte_t pte_mkyoung(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
232static inline pte_t pte_mkwrite(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_RW)); return pte; }
233#ifdef CONFIG_HUGETLB_PAGE
234static inline pte_t pte_mkhuge(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SZHUGE)); return pte; }
235#endif 412#endif
236 413
414#define PTE_BIT_FUNC(h,fn,op) \
415static inline pte_t pte_##fn(pte_t pte) { pte.pte_##h op; return pte; }
416
417#ifdef CONFIG_X2TLB
418/*
419 * We cheat a bit in the SH-X2 TLB case. As the permission bits are
420 * individually toggled (and user permissions are entirely decoupled from
421 * kernel permissions), we attempt to couple them a bit more sanely here.
422 */
423PTE_BIT_FUNC(high, rdprotect, &= ~_PAGE_EXT_USER_READ);
424PTE_BIT_FUNC(high, mkread, |= _PAGE_EXT_USER_READ | _PAGE_EXT_KERN_READ);
425PTE_BIT_FUNC(high, wrprotect, &= ~_PAGE_EXT_USER_WRITE);
426PTE_BIT_FUNC(high, mkwrite, |= _PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE);
427PTE_BIT_FUNC(high, exprotect, &= ~_PAGE_EXT_USER_EXEC);
428PTE_BIT_FUNC(high, mkexec, |= _PAGE_EXT_USER_EXEC | _PAGE_EXT_KERN_EXEC);
429PTE_BIT_FUNC(high, mkhuge, |= _PAGE_SZHUGE);
430#else
431PTE_BIT_FUNC(low, rdprotect, &= ~_PAGE_USER);
432PTE_BIT_FUNC(low, mkread, |= _PAGE_USER);
433PTE_BIT_FUNC(low, wrprotect, &= ~_PAGE_RW);
434PTE_BIT_FUNC(low, mkwrite, |= _PAGE_RW);
435PTE_BIT_FUNC(low, exprotect, &= ~_PAGE_USER);
436PTE_BIT_FUNC(low, mkexec, |= _PAGE_USER);
437PTE_BIT_FUNC(low, mkhuge, |= _PAGE_SZHUGE);
438#endif
439
440PTE_BIT_FUNC(low, mkclean, &= ~_PAGE_DIRTY);
441PTE_BIT_FUNC(low, mkdirty, |= _PAGE_DIRTY);
442PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED);
443PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
444
237/* 445/*
238 * Macro and implementation to make a page protection as uncachable. 446 * Macro and implementation to make a page protection as uncachable.
239 */ 447 */
@@ -258,13 +466,14 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
258#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 466#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
259 467
260static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 468static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
261{ set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; } 469{
262 470 set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) |
263#define pmd_page_vaddr(pmd) \ 471 pgprot_val(newprot)));
264((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) 472 return pte;
473}
265 474
266#define pmd_page(pmd) \ 475#define pmd_page_vaddr(pmd) pmd_val(pmd)
267 (phys_to_page(pmd_val(pmd))) 476#define pmd_page(pmd) (virt_to_page(pmd_val(pmd)))
268 477
269/* to find an entry in a page-table-directory. */ 478/* to find an entry in a page-table-directory. */
270#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 479#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
@@ -283,8 +492,15 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
283#define pte_unmap(pte) do { } while (0) 492#define pte_unmap(pte) do { } while (0)
284#define pte_unmap_nested(pte) do { } while (0) 493#define pte_unmap_nested(pte) do { } while (0)
285 494
495#ifdef CONFIG_X2TLB
496#define pte_ERROR(e) \
497 printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \
498 &(e), (e).pte_high, (e).pte_low)
499#else
286#define pte_ERROR(e) \ 500#define pte_ERROR(e) \
287 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 501 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
502#endif
503
288#define pgd_ERROR(e) \ 504#define pgd_ERROR(e) \
289 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 505 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
290 506
@@ -337,6 +553,9 @@ extern unsigned int kobjsize(const void *objp);
337extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 553extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
338#endif 554#endif
339 555
556extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
557extern void paging_init(void);
558
340#include <asm-generic/pgtable.h> 559#include <asm-generic/pgtable.h>
341 560
342#endif /* !__ASSEMBLY__ */ 561#endif /* !__ASSEMBLY__ */
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 45bb74e35d32..6f1dd7ca1b1d 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -36,7 +36,10 @@
36 */ 36 */
37enum cpu_type { 37enum cpu_type {
38 /* SH-2 types */ 38 /* SH-2 types */
39 CPU_SH7604, 39 CPU_SH7604, CPU_SH7619,
40
41 /* SH-2A types */
42 CPU_SH7206,
40 43
41 /* SH-3 types */ 44 /* SH-3 types */
42 CPU_SH7705, CPU_SH7706, CPU_SH7707, 45 CPU_SH7705, CPU_SH7706, CPU_SH7707,
@@ -47,7 +50,10 @@ enum cpu_type {
47 /* SH-4 types */ 50 /* SH-4 types */
48 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, 51 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
49 CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501, 52 CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
53
54 /* SH-4A types */
50 CPU_SH73180, CPU_SH7343, CPU_SH7770, CPU_SH7780, CPU_SH7781, 55 CPU_SH73180, CPU_SH7343, CPU_SH7770, CPU_SH7780, CPU_SH7781,
56 CPU_SH7785,
51 57
52 /* Unknown subtype */ 58 /* Unknown subtype */
53 CPU_SH_NONE 59 CPU_SH_NONE
@@ -130,12 +136,11 @@ union sh_fpu_union {
130}; 136};
131 137
132struct thread_struct { 138struct thread_struct {
139 /* Saved registers when thread is descheduled */
133 unsigned long sp; 140 unsigned long sp;
134 unsigned long pc; 141 unsigned long pc;
135 142
136 unsigned long trap_no, error_code; 143 /* Hardware debugging registers */
137 unsigned long address;
138 /* Hardware debugging registers may come here */
139 unsigned long ubc_pc; 144 unsigned long ubc_pc;
140 145
141 /* floating point info */ 146 /* floating point info */
@@ -150,12 +155,7 @@ typedef struct {
150extern int ubc_usercnt; 155extern int ubc_usercnt;
151 156
152#define INIT_THREAD { \ 157#define INIT_THREAD { \
153 sizeof(init_stack) + (long) &init_stack, /* sp */ \ 158 .sp = sizeof(init_stack) + (long) &init_stack, \
154 0, /* pc */ \
155 0, 0, \
156 0, \
157 0, \
158 {{{0,}},} /* fpu state */ \
159} 159}
160 160
161/* 161/*
@@ -259,8 +259,8 @@ void show_trace(struct task_struct *tsk, unsigned long *sp,
259 struct pt_regs *regs); 259 struct pt_regs *regs);
260extern unsigned long get_wchan(struct task_struct *p); 260extern unsigned long get_wchan(struct task_struct *p);
261 261
262#define KSTK_EIP(tsk) ((tsk)->thread.pc) 262#define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc)
263#define KSTK_ESP(tsk) ((tsk)->thread.sp) 263#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[15])
264 264
265#define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory") 265#define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory")
266#define cpu_relax() barrier() 266#define cpu_relax() barrier()
diff --git a/include/asm-sh/push-switch.h b/include/asm-sh/push-switch.h
new file mode 100644
index 000000000000..dfc6bad567f0
--- /dev/null
+++ b/include/asm-sh/push-switch.h
@@ -0,0 +1,28 @@
1#ifndef __ASM_SH_PUSH_SWITCH_H
2#define __ASM_SH_PUSH_SWITCH_H
3
4#include <linux/timer.h>
5#include <linux/interrupt.h>
6#include <linux/workqueue.h>
7
8struct push_switch {
9 /* switch state */
10 unsigned int state:1;
11 /* debounce timer */
12 struct timer_list debounce;
13 /* workqueue */
14 struct work_struct work;
15};
16
17struct push_switch_platform_info {
18 /* IRQ handler */
19 irqreturn_t (*irq_handler)(int irq, void *data);
20 /* Special IRQ flags */
21 unsigned int irq_flags;
22 /* Bit location of switch */
23 unsigned int bit;
24 /* Symbolic switch name */
25 const char *name;
26};
27
28#endif /* __ASM_SH_PUSH_SWITCH_H */
diff --git a/include/asm-sh/rwsem.h b/include/asm-sh/rwsem.h
index 9d2aea5e8488..4931ba817d73 100644
--- a/include/asm-sh/rwsem.h
+++ b/include/asm-sh/rwsem.h
@@ -25,11 +25,21 @@ struct rw_semaphore {
25#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) 25#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
26 spinlock_t wait_lock; 26 spinlock_t wait_lock;
27 struct list_head wait_list; 27 struct list_head wait_list;
28#ifdef CONFIG_DEBUG_LOCK_ALLOC
29 struct lockdep_map dep_map;
30#endif
28}; 31};
29 32
33#ifdef CONFIG_DEBUG_LOCK_ALLOC
34# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
35#else
36# define __RWSEM_DEP_MAP_INIT(lockname)
37#endif
38
30#define __RWSEM_INITIALIZER(name) \ 39#define __RWSEM_INITIALIZER(name) \
31 { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \ 40 { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
32 LIST_HEAD_INIT((name).wait_list) } 41 LIST_HEAD_INIT((name).wait_list) \
42 __RWSEM_DEP_MAP_INIT(name) }
33 43
34#define DECLARE_RWSEM(name) \ 44#define DECLARE_RWSEM(name) \
35 struct rw_semaphore name = __RWSEM_INITIALIZER(name) 45 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
@@ -39,6 +49,16 @@ extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
39extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem); 49extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
40extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem); 50extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
41 51
52extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
53 struct lock_class_key *key);
54
55#define init_rwsem(sem) \
56do { \
57 static struct lock_class_key __key; \
58 \
59 __init_rwsem((sem), #sem, &__key); \
60} while (0)
61
42static inline void init_rwsem(struct rw_semaphore *sem) 62static inline void init_rwsem(struct rw_semaphore *sem)
43{ 63{
44 sem->count = RWSEM_UNLOCKED_VALUE; 64 sem->count = RWSEM_UNLOCKED_VALUE;
@@ -141,6 +161,11 @@ static inline void __downgrade_write(struct rw_semaphore *sem)
141 rwsem_downgrade_wake(sem); 161 rwsem_downgrade_wake(sem);
142} 162}
143 163
164static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
165{
166 __down_write(sem);
167}
168
144/* 169/*
145 * implement exchange and add functionality 170 * implement exchange and add functionality
146 */ 171 */
diff --git a/include/asm-sh/se7206.h b/include/asm-sh/se7206.h
new file mode 100644
index 000000000000..698eb80389ab
--- /dev/null
+++ b/include/asm-sh/se7206.h
@@ -0,0 +1,13 @@
1#ifndef __ASM_SH_SE7206_H
2#define __ASM_SH_SE7206_H
3
4#define PA_SMSC 0x30000000
5#define PA_MRSHPC 0x34000000
6#define PA_LED 0x31400000
7
8void init_se7206_IRQ(void);
9
10#define __IO_PREFIX se7206
11#include <asm/io_generic.h>
12
13#endif /* __ASM_SH_SE7206_H */
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
index 3340126f4e0f..b1e42e7f998b 100644
--- a/include/asm-sh/system.h
+++ b/include/asm-sh/system.h
@@ -6,6 +6,7 @@
6 * Copyright (C) 2002 Paul Mundt 6 * Copyright (C) 2002 Paul Mundt
7 */ 7 */
8 8
9#include <linux/irqflags.h>
9#include <asm/types.h> 10#include <asm/types.h>
10 11
11/* 12/*
@@ -131,103 +132,6 @@ static inline unsigned long tas(volatile int *m)
131 132
132#define set_mb(var, value) do { xchg(&var, value); } while (0) 133#define set_mb(var, value) do { xchg(&var, value); } while (0)
133 134
134/* Interrupt Control */
135#ifdef CONFIG_CPU_HAS_SR_RB
136static inline void local_irq_enable(void)
137{
138 unsigned long __dummy0, __dummy1;
139
140 __asm__ __volatile__("stc sr, %0\n\t"
141 "and %1, %0\n\t"
142 "stc r6_bank, %1\n\t"
143 "or %1, %0\n\t"
144 "ldc %0, sr"
145 : "=&r" (__dummy0), "=r" (__dummy1)
146 : "1" (~0x000000f0)
147 : "memory");
148}
149#else
150static inline void local_irq_enable(void)
151{
152 unsigned long __dummy0, __dummy1;
153
154 __asm__ __volatile__ (
155 "stc sr, %0\n\t"
156 "and %1, %0\n\t"
157 "ldc %0, sr\n\t"
158 : "=&r" (__dummy0), "=r" (__dummy1)
159 : "1" (~0x000000f0)
160 : "memory");
161}
162#endif
163
164static inline void local_irq_disable(void)
165{
166 unsigned long __dummy;
167 __asm__ __volatile__("stc sr, %0\n\t"
168 "or #0xf0, %0\n\t"
169 "ldc %0, sr"
170 : "=&z" (__dummy)
171 : /* no inputs */
172 : "memory");
173}
174
175static inline void set_bl_bit(void)
176{
177 unsigned long __dummy0, __dummy1;
178
179 __asm__ __volatile__ ("stc sr, %0\n\t"
180 "or %2, %0\n\t"
181 "and %3, %0\n\t"
182 "ldc %0, sr"
183 : "=&r" (__dummy0), "=r" (__dummy1)
184 : "r" (0x10000000), "r" (0xffffff0f)
185 : "memory");
186}
187
188static inline void clear_bl_bit(void)
189{
190 unsigned long __dummy0, __dummy1;
191
192 __asm__ __volatile__ ("stc sr, %0\n\t"
193 "and %2, %0\n\t"
194 "ldc %0, sr"
195 : "=&r" (__dummy0), "=r" (__dummy1)
196 : "1" (~0x10000000)
197 : "memory");
198}
199
200#define local_save_flags(x) \
201 __asm__("stc sr, %0; and #0xf0, %0" : "=&z" (x) :/**/: "memory" )
202
203#define irqs_disabled() \
204({ \
205 unsigned long flags; \
206 local_save_flags(flags); \
207 (flags != 0); \
208})
209
210static inline unsigned long local_irq_save(void)
211{
212 unsigned long flags, __dummy;
213
214 __asm__ __volatile__("stc sr, %1\n\t"
215 "mov %1, %0\n\t"
216 "or #0xf0, %0\n\t"
217 "ldc %0, sr\n\t"
218 "mov %1, %0\n\t"
219 "and #0xf0, %0"
220 : "=&z" (flags), "=&r" (__dummy)
221 :/**/
222 : "memory" );
223 return flags;
224}
225
226#define local_irq_restore(x) do { \
227 if ((x & 0x000000f0) != 0x000000f0) \
228 local_irq_enable(); \
229} while (0)
230
231/* 135/*
232 * Jump to P2 area. 136 * Jump to P2 area.
233 * When handling TLB or caches, we need to do it from P2 area. 137 * When handling TLB or caches, we need to do it from P2 area.
@@ -264,9 +168,6 @@ do { \
264 : "=&r" (__dummy)); \ 168 : "=&r" (__dummy)); \
265} while (0) 169} while (0)
266 170
267/* For spinlocks etc */
268#define local_irq_save(x) x = local_irq_save()
269
270static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) 171static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
271{ 172{
272 unsigned long flags, retval; 173 unsigned long flags, retval;
diff --git a/include/asm-sh/thread_info.h b/include/asm-sh/thread_info.h
index 3ebc3f9039eb..0c01dc550819 100644
--- a/include/asm-sh/thread_info.h
+++ b/include/asm-sh/thread_info.h
@@ -90,13 +90,7 @@ static inline struct thread_info *current_thread_info(void)
90#endif 90#endif
91#define free_thread_info(ti) kfree(ti) 91#define free_thread_info(ti) kfree(ti)
92 92
93#else /* !__ASSEMBLY__ */ 93#endif /* __ASSEMBLY__ */
94
95/* how to get the thread information struct from ASM */
96#define GET_THREAD_INFO(reg) \
97 stc r7_bank, reg
98
99#endif
100 94
101/* 95/*
102 * thread information flags 96 * thread information flags
diff --git a/include/asm-sh/timer.h b/include/asm-sh/timer.h
index 5df842bcf7b6..17b5e76a4c31 100644
--- a/include/asm-sh/timer.h
+++ b/include/asm-sh/timer.h
@@ -18,11 +18,32 @@ struct sys_timer {
18 18
19 struct sys_device dev; 19 struct sys_device dev;
20 struct sys_timer_ops *ops; 20 struct sys_timer_ops *ops;
21
22#ifdef CONFIG_NO_IDLE_HZ
23 struct dyn_tick_timer *dyn_tick;
24#endif
21}; 25};
22 26
27#ifdef CONFIG_NO_IDLE_HZ
28#define DYN_TICK_ENABLED (1 << 1)
29
30struct dyn_tick_timer {
31 spinlock_t lock;
32 unsigned int state; /* Current state */
33 int (*enable)(void); /* Enables dynamic tick */
34 int (*disable)(void); /* Disables dynamic tick */
35 void (*reprogram)(unsigned long); /* Reprograms the timer */
36 int (*handler)(int, void *);
37};
38
39void timer_dyn_reprogram(void);
40#else
41#define timer_dyn_reprogram() do { } while (0)
42#endif
43
23#define TICK_SIZE (tick_nsec / 1000) 44#define TICK_SIZE (tick_nsec / 1000)
24 45
25extern struct sys_timer tmu_timer; 46extern struct sys_timer tmu_timer, cmt_timer, mtu2_timer;
26extern struct sys_timer *sys_timer; 47extern struct sys_timer *sys_timer;
27 48
28#ifndef CONFIG_GENERIC_TIME 49#ifndef CONFIG_GENERIC_TIME
diff --git a/include/asm-sh/titan.h b/include/asm-sh/titan.h
index 270a4f4bc8a9..03f3583c8918 100644
--- a/include/asm-sh/titan.h
+++ b/include/asm-sh/titan.h
@@ -1,9 +1,8 @@
1/* 1/*
2 * Platform defintions for Titan 2 * Platform defintions for Titan
3 */ 3 */
4 4#ifndef _ASM_SH_TITAN_H
5#ifndef _ASM_SH_TITAN_TITAN_H 5#define _ASM_SH_TITAN_H
6#define _ASM_SH_TITAN_TITAN_H
7 6
8#define __IO_PREFIX titan 7#define __IO_PREFIX titan
9#include <asm/io_generic.h> 8#include <asm/io_generic.h>
@@ -15,29 +14,4 @@
15#define TITAN_IRQ_MPCIB 11 /* mPCI B */ 14#define TITAN_IRQ_MPCIB 11 /* mPCI B */
16#define TITAN_IRQ_USB 11 /* USB */ 15#define TITAN_IRQ_USB 11 /* USB */
17 16
18/* 17#endif /* __ASM_SH_TITAN_H */
19 * The external interrupt lines, these take up ints 0 - 15 inclusive
20 * depending on the priority for the interrupt. In fact the priority
21 * is the interrupt :-)
22 */
23#define IRL0_IRQ 0
24#define IRL0_IPR_ADDR INTC_IPRD
25#define IRL0_IPR_POS 3
26#define IRL0_PRIORITY 8
27
28#define IRL1_IRQ 1
29#define IRL1_IPR_ADDR INTC_IPRD
30#define IRL1_IPR_POS 2
31#define IRL1_PRIORITY 8
32
33#define IRL2_IRQ 2
34#define IRL2_IPR_ADDR INTC_IPRD
35#define IRL2_IPR_POS 1
36#define IRL2_PRIORITY 8
37
38#define IRL3_IRQ 3
39#define IRL3_IPR_ADDR INTC_IPRD
40#define IRL3_IPR_POS 0
41#define IRL3_PRIORITY 8
42
43#endif
diff --git a/include/asm-sh/unistd.h b/include/asm-sh/unistd.h
index 1c2abde122cd..0cae1d248761 100644
--- a/include/asm-sh/unistd.h
+++ b/include/asm-sh/unistd.h
@@ -349,12 +349,30 @@ do { \
349 return (type) (res); \ 349 return (type) (res); \
350} while (0) 350} while (0)
351 351
352#if defined(__sh2__) || defined(__SH2E__) || defined(__SH2A__)
353#define SYSCALL_ARG0 "trapa #0x20"
354#define SYSCALL_ARG1 "trapa #0x21"
355#define SYSCALL_ARG2 "trapa #0x22"
356#define SYSCALL_ARG3 "trapa #0x23"
357#define SYSCALL_ARG4 "trapa #0x24"
358#define SYSCALL_ARG5 "trapa #0x25"
359#define SYSCALL_ARG6 "trapa #0x26"
360#else
361#define SYSCALL_ARG0 "trapa #0x10"
362#define SYSCALL_ARG1 "trapa #0x11"
363#define SYSCALL_ARG2 "trapa #0x12"
364#define SYSCALL_ARG3 "trapa #0x13"
365#define SYSCALL_ARG4 "trapa #0x14"
366#define SYSCALL_ARG5 "trapa #0x15"
367#define SYSCALL_ARG6 "trapa #0x16"
368#endif
369
352/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ 370/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
353#define _syscall0(type,name) \ 371#define _syscall0(type,name) \
354type name(void) \ 372type name(void) \
355{ \ 373{ \
356register long __sc0 __asm__ ("r3") = __NR_##name; \ 374register long __sc0 __asm__ ("r3") = __NR_##name; \
357__asm__ __volatile__ ("trapa #0x10" \ 375__asm__ __volatile__ (SYSCALL_ARG0 \
358 : "=z" (__sc0) \ 376 : "=z" (__sc0) \
359 : "0" (__sc0) \ 377 : "0" (__sc0) \
360 : "memory" ); \ 378 : "memory" ); \
@@ -366,7 +384,7 @@ type name(type1 arg1) \
366{ \ 384{ \
367register long __sc0 __asm__ ("r3") = __NR_##name; \ 385register long __sc0 __asm__ ("r3") = __NR_##name; \
368register long __sc4 __asm__ ("r4") = (long) arg1; \ 386register long __sc4 __asm__ ("r4") = (long) arg1; \
369__asm__ __volatile__ ("trapa #0x11" \ 387__asm__ __volatile__ (SYSCALL_ARG1 \
370 : "=z" (__sc0) \ 388 : "=z" (__sc0) \
371 : "0" (__sc0), "r" (__sc4) \ 389 : "0" (__sc0), "r" (__sc4) \
372 : "memory"); \ 390 : "memory"); \
@@ -379,7 +397,7 @@ type name(type1 arg1,type2 arg2) \
379register long __sc0 __asm__ ("r3") = __NR_##name; \ 397register long __sc0 __asm__ ("r3") = __NR_##name; \
380register long __sc4 __asm__ ("r4") = (long) arg1; \ 398register long __sc4 __asm__ ("r4") = (long) arg1; \
381register long __sc5 __asm__ ("r5") = (long) arg2; \ 399register long __sc5 __asm__ ("r5") = (long) arg2; \
382__asm__ __volatile__ ("trapa #0x12" \ 400__asm__ __volatile__ (SYSCALL_ARG2 \
383 : "=z" (__sc0) \ 401 : "=z" (__sc0) \
384 : "0" (__sc0), "r" (__sc4), "r" (__sc5) \ 402 : "0" (__sc0), "r" (__sc4), "r" (__sc5) \
385 : "memory"); \ 403 : "memory"); \
@@ -393,7 +411,7 @@ register long __sc0 __asm__ ("r3") = __NR_##name; \
393register long __sc4 __asm__ ("r4") = (long) arg1; \ 411register long __sc4 __asm__ ("r4") = (long) arg1; \
394register long __sc5 __asm__ ("r5") = (long) arg2; \ 412register long __sc5 __asm__ ("r5") = (long) arg2; \
395register long __sc6 __asm__ ("r6") = (long) arg3; \ 413register long __sc6 __asm__ ("r6") = (long) arg3; \
396__asm__ __volatile__ ("trapa #0x13" \ 414__asm__ __volatile__ (SYSCALL_ARG3 \
397 : "=z" (__sc0) \ 415 : "=z" (__sc0) \
398 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6) \ 416 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6) \
399 : "memory"); \ 417 : "memory"); \
@@ -408,7 +426,7 @@ register long __sc4 __asm__ ("r4") = (long) arg1; \
408register long __sc5 __asm__ ("r5") = (long) arg2; \ 426register long __sc5 __asm__ ("r5") = (long) arg2; \
409register long __sc6 __asm__ ("r6") = (long) arg3; \ 427register long __sc6 __asm__ ("r6") = (long) arg3; \
410register long __sc7 __asm__ ("r7") = (long) arg4; \ 428register long __sc7 __asm__ ("r7") = (long) arg4; \
411__asm__ __volatile__ ("trapa #0x14" \ 429__asm__ __volatile__ (SYSCALL_ARG4 \
412 : "=z" (__sc0) \ 430 : "=z" (__sc0) \
413 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), \ 431 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), \
414 "r" (__sc7) \ 432 "r" (__sc7) \
@@ -425,7 +443,7 @@ register long __sc5 __asm__ ("r5") = (long) arg2; \
425register long __sc6 __asm__ ("r6") = (long) arg3; \ 443register long __sc6 __asm__ ("r6") = (long) arg3; \
426register long __sc7 __asm__ ("r7") = (long) arg4; \ 444register long __sc7 __asm__ ("r7") = (long) arg4; \
427register long __sc0 __asm__ ("r0") = (long) arg5; \ 445register long __sc0 __asm__ ("r0") = (long) arg5; \
428__asm__ __volatile__ ("trapa #0x15" \ 446__asm__ __volatile__ (SYSCALL_ARG5 \
429 : "=z" (__sc0) \ 447 : "=z" (__sc0) \
430 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \ 448 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \
431 "r" (__sc3) \ 449 "r" (__sc3) \
@@ -443,7 +461,7 @@ register long __sc6 __asm__ ("r6") = (long) arg3; \
443register long __sc7 __asm__ ("r7") = (long) arg4; \ 461register long __sc7 __asm__ ("r7") = (long) arg4; \
444register long __sc0 __asm__ ("r0") = (long) arg5; \ 462register long __sc0 __asm__ ("r0") = (long) arg5; \
445register long __sc1 __asm__ ("r1") = (long) arg6; \ 463register long __sc1 __asm__ ("r1") = (long) arg6; \
446__asm__ __volatile__ ("trapa #0x16" \ 464__asm__ __volatile__ (SYSCALL_ARG6 \
447 : "=z" (__sc0) \ 465 : "=z" (__sc0) \
448 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \ 466 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \
449 "r" (__sc3), "r" (__sc1) \ 467 "r" (__sc3), "r" (__sc1) \
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 20:12:32 -0500