diff options
author | Larry Finger <Larry.Finger@lwfinger.net> | 2007-11-09 17:58:20 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-01-28 18:04:44 -0500 |
commit | d3c319f9c8d9ee2c042c60b8a1bbd909dcc42782 (patch) | |
tree | a80dc345690edae76d7eea864ec25966869b08b3 /include | |
parent | 7797aa384870e3bb5bfd3b6a0eae61e7c7a4c993 (diff) |
ssb: Remove the old, now unused, data structures
The old, now unused, data structures and SPROM extraction routines
are removed.
Signed-off-by: Larry Finger<Larry.Finger@lwfinger.net>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/ssb/ssb.h | 74 | ||||
-rw-r--r-- | include/linux/ssb/ssb_regs.h | 49 |
2 files changed, 28 insertions, 95 deletions
diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index 745de2aac85f..a21ab29ff363 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h | |||
@@ -15,72 +15,8 @@ struct pcmcia_device; | |||
15 | struct ssb_bus; | 15 | struct ssb_bus; |
16 | struct ssb_driver; | 16 | struct ssb_driver; |
17 | 17 | ||
18 | |||
19 | struct ssb_sprom_r1 { | ||
20 | u16 pci_spid; /* Subsystem Product ID for PCI */ | ||
21 | u16 pci_svid; /* Subsystem Vendor ID for PCI */ | ||
22 | u16 pci_pid; /* Product ID for PCI */ | ||
23 | u8 il0mac[6]; /* MAC address for 802.11b/g */ | ||
24 | u8 et0mac[6]; /* MAC address for Ethernet */ | ||
25 | u8 et1mac[6]; /* MAC address for 802.11a */ | ||
26 | u8 et0phyaddr:5; /* MII address for enet0 */ | ||
27 | u8 et1phyaddr:5; /* MII address for enet1 */ | ||
28 | u8 et0mdcport:1; /* MDIO for enet0 */ | ||
29 | u8 et1mdcport:1; /* MDIO for enet1 */ | ||
30 | u8 board_rev; /* Board revision */ | ||
31 | u8 country_code:4; /* Country Code */ | ||
32 | u8 antenna_a:2; /* Antenna 0/1 available for A-PHY */ | ||
33 | u8 antenna_bg:2; /* Antenna 0/1 available for B-PHY and G-PHY */ | ||
34 | u16 pa0b0; | ||
35 | u16 pa0b1; | ||
36 | u16 pa0b2; | ||
37 | u16 pa1b0; | ||
38 | u16 pa1b1; | ||
39 | u16 pa1b2; | ||
40 | u8 gpio0; /* GPIO pin 0 */ | ||
41 | u8 gpio1; /* GPIO pin 1 */ | ||
42 | u8 gpio2; /* GPIO pin 2 */ | ||
43 | u8 gpio3; /* GPIO pin 3 */ | ||
44 | u16 maxpwr_a; /* A-PHY Power Amplifier Max Power (in dBm Q5.2) */ | ||
45 | u16 maxpwr_bg; /* B/G-PHY Power Amplifier Max Power (in dBm Q5.2) */ | ||
46 | u8 itssi_a; /* Idle TSSI Target for A-PHY */ | ||
47 | u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */ | ||
48 | u16 boardflags_lo; /* Boardflags (low 16 bits) */ | ||
49 | u8 antenna_gain_a; /* A-PHY Antenna gain (in dBm Q5.2) */ | ||
50 | u8 antenna_gain_bg; /* B/G-PHY Antenna gain (in dBm Q5.2) */ | ||
51 | u8 oem[8]; /* OEM string (rev 1 only) */ | ||
52 | }; | ||
53 | |||
54 | struct ssb_sprom_r2 { | ||
55 | u16 boardflags_hi; /* Boardflags (high 16 bits) */ | ||
56 | u8 maxpwr_a_lo; /* A-PHY Max Power Low */ | ||
57 | u8 maxpwr_a_hi; /* A-PHY Max Power High */ | ||
58 | u16 pa1lob0; /* A-PHY PA Low Settings */ | ||
59 | u16 pa1lob1; /* A-PHY PA Low Settings */ | ||
60 | u16 pa1lob2; /* A-PHY PA Low Settings */ | ||
61 | u16 pa1hib0; /* A-PHY PA High Settings */ | ||
62 | u16 pa1hib1; /* A-PHY PA High Settings */ | ||
63 | u16 pa1hib2; /* A-PHY PA High Settings */ | ||
64 | u8 ofdm_pwr_off; /* OFDM Power Offset from CCK Level */ | ||
65 | u8 country_str[2]; /* Two char Country Code */ | ||
66 | }; | ||
67 | |||
68 | struct ssb_sprom_r3 { | ||
69 | u32 ofdmapo; /* A-PHY OFDM Mid Power Offset */ | ||
70 | u32 ofdmalpo; /* A-PHY OFDM Low Power Offset */ | ||
71 | u32 ofdmahpo; /* A-PHY OFDM High Power Offset */ | ||
72 | u8 gpioldc_on_cnt; /* GPIO LED Powersave Duty Cycle ON count */ | ||
73 | u8 gpioldc_off_cnt; /* GPIO LED Powersave Duty Cycle OFF count */ | ||
74 | u8 cckpo_1M:4; /* CCK Power Offset for Rate 1M */ | ||
75 | u8 cckpo_2M:4; /* CCK Power Offset for Rate 2M */ | ||
76 | u8 cckpo_55M:4; /* CCK Power Offset for Rate 5.5M */ | ||
77 | u8 cckpo_11M:4; /* CCK Power Offset for Rate 11M */ | ||
78 | u32 ofdmgpo; /* G-PHY OFDM Power Offset */ | ||
79 | }; | ||
80 | |||
81 | struct ssb_sprom { | 18 | struct ssb_sprom { |
82 | u8 revision; | 19 | u8 revision; |
83 | u8 temp_fill[2 * sizeof(struct ssb_sprom_r1)]; | ||
84 | u8 il0mac[6]; /* MAC address for 802.11b/g */ | 20 | u8 il0mac[6]; /* MAC address for 802.11b/g */ |
85 | u8 et0mac[6]; /* MAC address for Ethernet */ | 21 | u8 et0mac[6]; /* MAC address for Ethernet */ |
86 | u8 et1mac[6]; /* MAC address for 802.11a */ | 22 | u8 et1mac[6]; /* MAC address for 802.11a */ |
@@ -106,16 +42,6 @@ struct ssb_sprom { | |||
106 | u8 antenna_gain_bg; /* B/G-PHY Antenna gain (in dBm Q5.2) */ | 42 | u8 antenna_gain_bg; /* B/G-PHY Antenna gain (in dBm Q5.2) */ |
107 | 43 | ||
108 | /* TODO - add any parameters needed from rev 2, 3, or 4 SPROMs */ | 44 | /* TODO - add any parameters needed from rev 2, 3, or 4 SPROMs */ |
109 | /* The valid r# fields are selected by the "revision". | ||
110 | * Revision 3 and lower inherit from lower revisions. | ||
111 | */ | ||
112 | union { | ||
113 | struct { | ||
114 | struct ssb_sprom_r1 r1; | ||
115 | struct ssb_sprom_r2 r2; | ||
116 | struct ssb_sprom_r3 r3; | ||
117 | }; | ||
118 | }; | ||
119 | }; | 45 | }; |
120 | 46 | ||
121 | /* Information about the PCB the circuitry is soldered on. */ | 47 | /* Information about the PCB the circuitry is soldered on. */ |
diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h index 96bba69b1271..30222e89ad16 100644 --- a/include/linux/ssb/ssb_regs.h +++ b/include/linux/ssb/ssb_regs.h | |||
@@ -175,6 +175,7 @@ | |||
175 | #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */ | 175 | #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */ |
176 | #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */ | 176 | #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */ |
177 | #define SSB_SPROM_REVISION_CRC_SHIFT 8 | 177 | #define SSB_SPROM_REVISION_CRC_SHIFT 8 |
178 | |||
178 | /* SPROM Revision 1 */ | 179 | /* SPROM Revision 1 */ |
179 | #define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */ | 180 | #define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */ |
180 | #define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */ | 181 | #define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */ |
@@ -223,7 +224,7 @@ | |||
223 | #define SSB_SPROM1_AGAIN_A 0x00FF /* A-PHY */ | 224 | #define SSB_SPROM1_AGAIN_A 0x00FF /* A-PHY */ |
224 | #define SSB_SPROM1_AGAIN_BG 0xFF00 /* B-PHY and G-PHY */ | 225 | #define SSB_SPROM1_AGAIN_BG 0xFF00 /* B-PHY and G-PHY */ |
225 | #define SSB_SPROM1_AGAIN_BG_SHIFT 8 | 226 | #define SSB_SPROM1_AGAIN_BG_SHIFT 8 |
226 | #define SSB_SPROM1_OEM 0x1076 /* 8 bytes OEM string (rev 1 only) */ | 227 | |
227 | /* SPROM Revision 2 (inherits from rev 1) */ | 228 | /* SPROM Revision 2 (inherits from rev 1) */ |
228 | #define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */ | 229 | #define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */ |
229 | #define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */ | 230 | #define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */ |
@@ -240,6 +241,7 @@ | |||
240 | #define SSB_SPROM2_OPO_VALUE 0x00FF | 241 | #define SSB_SPROM2_OPO_VALUE 0x00FF |
241 | #define SSB_SPROM2_OPO_UNUSED 0xFF00 | 242 | #define SSB_SPROM2_OPO_UNUSED 0xFF00 |
242 | #define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */ | 243 | #define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */ |
244 | |||
243 | /* SPROM Revision 3 (inherits most data from rev 2) */ | 245 | /* SPROM Revision 3 (inherits most data from rev 2) */ |
244 | #define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */ | 246 | #define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */ |
245 | #define SSB_SPROM3_ET0MAC 0x1050 /* 6 bytes MAC address for Ethernet ?? */ | 247 | #define SSB_SPROM3_ET0MAC 0x1050 /* 6 bytes MAC address for Ethernet ?? */ |
@@ -261,11 +263,12 @@ | |||
261 | #define SSB_SPROM3_CCKPO_11M 0xF000 /* 11M Rate PO */ | 263 | #define SSB_SPROM3_CCKPO_11M 0xF000 /* 11M Rate PO */ |
262 | #define SSB_SPROM3_CCKPO_11M_SHIFT 12 | 264 | #define SSB_SPROM3_CCKPO_11M_SHIFT 12 |
263 | #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */ | 265 | #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */ |
266 | |||
264 | /* SPROM Revision 4 entries with ?? in comment are unknown */ | 267 | /* SPROM Revision 4 entries with ?? in comment are unknown */ |
265 | #define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for b/g */ | 268 | #define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */ |
266 | #define SSB_SPROM4_ET0MAC 0x1018 /* 6 bytes MAC address for Ethernet ?? */ | 269 | #define SSB_SPROM4_ET0MAC 0x1018 /* 6 bytes MAC address for Ethernet ?? */ |
267 | #define SSB_SPROM4_ET1MAC 0x1018 /* 6 bytes MAC address for 802.11a ?? */ | 270 | #define SSB_SPROM4_ET1MAC 0x1018 /* 6 bytes MAC address for 802.11a ?? */ |
268 | #define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings */ | 271 | #define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */ |
269 | #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ | 272 | #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ |
270 | #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ | 273 | #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ |
271 | #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 | 274 | #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 |
@@ -280,24 +283,28 @@ | |||
280 | #define SSB_SPROM4_AGAIN_1 0xFF00 /* Antenna 1 */ | 283 | #define SSB_SPROM4_AGAIN_1 0xFF00 /* Antenna 1 */ |
281 | #define SSB_SPROM4_AGAIN_1_SHIFT 8 | 284 | #define SSB_SPROM4_AGAIN_1_SHIFT 8 |
282 | #define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */ | 285 | #define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */ |
283 | #define SSB_SPROM4_MAXP_A 0x1000 /* Max Power A ?? */ | 286 | #define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */ |
284 | #define SSB_SPROM4_MAXP_A_HI 0x00FF /* Mask for Hi */ | 287 | #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */ |
285 | #define SSB_SPROM4_MAXP_A_LO 0xFF00 /* Mask for Lo */ | 288 | #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ |
286 | #define SSB_SPROM4_MAXP_A_LO_SHIFT 16 /* Shift for Lo */ | 289 | #define SSB_SPROM4_ITSSI_BG_SHIFT 8 |
287 | #define SSB_SPROM4_PA1LOB0 0x1000 /* ?? */ | 290 | #define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */ |
288 | #define SSB_SPROM4_PA1LOB1 0x1000 /* ?? */ | 291 | #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */ |
289 | #define SSB_SPROM4_PA1LOB2 0x1000 /* ?? */ | 292 | #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */ |
290 | #define SSB_SPROM4_PA1HIB0 0x1000 /* ?? */ | 293 | #define SSB_SPROM4_ITSSI_A_SHIFT 8 |
291 | #define SSB_SPROM4_PA1HIB1 0x1000 /* ?? */ | 294 | #define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */ |
292 | #define SSB_SPROM4_PA1HIB2 0x1000 /* ?? */ | 295 | #define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */ |
293 | #define SSB_SPROM4_OPO 0x1000 /* ?? */ | 296 | #define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */ |
294 | #define SSB_SPROM4_OPO_VALUE 0x0000 /* ?? */ | 297 | #define SSB_SPROM4_GPIOA_P1_SHIFT 8 |
295 | #define SSB_SPROM4_GPIOLDC 0x105A /* LED Powersave Duty Cycle */ | 298 | #define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */ |
296 | #define SSB_SPROM4_GPIOLDC_OFF 0x0000FF00 /* Off Count */ | 299 | #define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */ |
297 | #define SSB_SPROM4_GPIOLDC_OFF_SHIFT 8 | 300 | #define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */ |
298 | #define SSB_SPROM4_GPIOLDC_ON 0x00FF0000 /* On Count */ | 301 | #define SSB_SPROM4_GPIOB_P3_SHIFT 8 |
299 | #define SSB_SPROM4_GPIOLDC_ON_SHIFT 16 | 302 | #define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */ |
300 | 303 | #define SSB_SPROM4_PA0B1 0x1084 /* only guesses */ | |
304 | #define SSB_SPROM4_PA0B2 0x1086 | ||
305 | #define SSB_SPROM4_PA1B0 0x108E | ||
306 | #define SSB_SPROM4_PA1B1 0x1090 | ||
307 | #define SSB_SPROM4_PA1B2 0x1092 | ||
301 | 308 | ||
302 | /* Values for SSB_SPROM1_BINF_CCODE */ | 309 | /* Values for SSB_SPROM1_BINF_CCODE */ |
303 | enum { | 310 | enum { |