Merge branch 'forlinus' of git://parisc-linux.org/home/kyle/git/parisc-2.6

21 files changed, 1270 insertions, 240 deletions

diff --git a/include/asm-parisc/assembly.h b/include/asm-parisc/assembly.h
index 30b023411fef..3ce3440d1b0c 100644
--- a/include/asm-parisc/assembly.h
+++ b/include/asm-parisc/assembly.h
@@ -21,7 +21,9 @@
 #ifndef _PARISC_ASSEMBLY_H
 #define _PARISC_ASSEMBLY_H
 
-#ifdef __LP64__
+#define CALLEE_FLOAT_FRAME_SIZE 80
+
+#ifdef CONFIG_64BIT
 #define LDREG   ldd
 #define STREG   std
 #define LDREGX  ldd,s
@@ -30,8 +32,8 @@
 #define SHRREG  shrd
 #define RP_OFFSET       16
 #define FRAME_SIZE      128
-#define CALLEE_SAVE_FRAME_SIZE  144
-#else
+#define CALLEE_REG_FRAME_SIZE   144
+#else   /* CONFIG_64BIT */
 #define LDREG   ldw
 #define STREG   stw
 #define LDREGX  ldwx,s
@@ -40,9 +42,11 @@
 #define SHRREG  shr
 #define RP_OFFSET       20
 #define FRAME_SIZE      64
-#define CALLEE_SAVE_FRAME_SIZE  128
+#define CALLEE_REG_FRAME_SIZE   128
 #endif
 
+#define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
+
 #ifdef CONFIG_PA20
 #define BL              b,l
 # ifdef CONFIG_64BIT
@@ -300,9 +304,35 @@
         fldd,mb -8(\regs),       %fr0
         .endm
 
+        .macro  callee_save_float
+        fstd,ma  %fr12, 8(%r30)
+        fstd,ma  %fr13, 8(%r30)
+        fstd,ma  %fr14, 8(%r30)
+        fstd,ma  %fr15, 8(%r30)
+        fstd,ma  %fr16, 8(%r30)
+        fstd,ma  %fr17, 8(%r30)
+        fstd,ma  %fr18, 8(%r30)
+        fstd,ma  %fr19, 8(%r30)
+        fstd,ma  %fr20, 8(%r30)
+        fstd,ma  %fr21, 8(%r30)
+        .endm
+
+        .macro  callee_rest_float
+        fldd,mb -8(%r30),   %fr21
+        fldd,mb -8(%r30),   %fr20
+        fldd,mb -8(%r30),   %fr19
+        fldd,mb -8(%r30),   %fr18
+        fldd,mb -8(%r30),   %fr17
+        fldd,mb -8(%r30),   %fr16
+        fldd,mb -8(%r30),   %fr15
+        fldd,mb -8(%r30),   %fr14
+        fldd,mb -8(%r30),   %fr13
+        fldd,mb -8(%r30),   %fr12
+        .endm
+
 #ifdef __LP64__
         .macro  callee_save
-        std,ma    %r3,  CALLEE_SAVE_FRAME_SIZE(%r30)
+        std,ma    %r3,   CALLEE_REG_FRAME_SIZE(%r30)
         mfctl     %cr27, %r3
         std       %r4,  -136(%r30)
         std       %r5,  -128(%r30)
@@ -340,13 +370,13 @@
         ldd     -128(%r30),    %r5
         ldd     -136(%r30),    %r4
         mtctl   %r3, %cr27
-        ldd,mb  -CALLEE_SAVE_FRAME_SIZE(%r30),    %r3
+        ldd,mb  -CALLEE_REG_FRAME_SIZE(%r30),    %r3
         .endm
 
 #else /* ! __LP64__ */
 
         .macro  callee_save
-        stw,ma   %r3,   CALLEE_SAVE_FRAME_SIZE(%r30)
+        stw,ma   %r3,   CALLEE_REG_FRAME_SIZE(%r30)
         mfctl    %cr27, %r3
         stw      %r4,   -124(%r30)
         stw      %r5,   -120(%r30)
@@ -384,7 +414,7 @@
         ldw     -120(%r30),   %r5
         ldw     -124(%r30),   %r4
         mtctl   %r3, %cr27
-        ldw,mb  -CALLEE_SAVE_FRAME_SIZE(%r30),   %r3
+        ldw,mb  -CALLEE_REG_FRAME_SIZE(%r30),   %r3
         .endm
 #endif /* ! __LP64__ */
 
@@ -450,5 +480,30 @@
         REST_CR (%cr22, PT_PSW  (\regs))
         .endm
 
+
+        /* First step to create a "relied upon translation"
+         * See PA 2.0 Arch. page F-4 and F-5.
+         *
+         * The ssm was originally necessary due to a "PCxT bug".
+         * But someone decided it needed to be added to the architecture
+         * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
+         * It's been carried forward into PA 2.0 Arch as well. :^(
+         *
+         * "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
+         * rsm/ssm prevents the ifetch unit from speculatively fetching
+         * instructions past this line in the code stream.
+         * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
+         */
+        .macro  pcxt_ssm_bug
+        rsm     PSW_SM_I,%r0
+        nop     /* 1 */
+        nop     /* 2 */
+        nop     /* 3 */
+        nop     /* 4 */
+        nop     /* 5 */
+        nop     /* 6 */
+        nop     /* 7 */
+        .endm
+
 #endif /* __ASSEMBLY__ */
 #endif
diff --git a/include/asm-parisc/bitops.h b/include/asm-parisc/bitops.h
index af7db694b22d..55b98c67fd82 100644
--- a/include/asm-parisc/bitops.h
+++ b/include/asm-parisc/bitops.h
@@ -2,7 +2,7 @@
 #define _PARISC_BITOPS_H
 
 #include <linux/compiler.h>
-#include <asm/spinlock.h>
+#include <asm/types.h>          /* for BITS_PER_LONG/SHIFT_PER_LONG */
 #include <asm/byteorder.h>
 #include <asm/atomic.h>
 
@@ -12,193 +12,157 @@
  * to include/asm-i386/bitops.h or kerneldoc
  */
 
-#ifdef __LP64__
-#   define SHIFT_PER_LONG 6
-#ifndef BITS_PER_LONG
-#   define BITS_PER_LONG 64
-#endif
-#else
-#   define SHIFT_PER_LONG 5
-#ifndef BITS_PER_LONG
-#   define BITS_PER_LONG 32
-#endif
-#endif
-
-#define CHOP_SHIFTCOUNT(x) ((x) & (BITS_PER_LONG - 1))
+#define CHOP_SHIFTCOUNT(x) (((unsigned long) (x)) & (BITS_PER_LONG - 1))
 
 
 #define smp_mb__before_clear_bit()      smp_mb()
 #define smp_mb__after_clear_bit()       smp_mb()
 
-static __inline__ void set_bit(int nr, volatile unsigned long * address)
+/* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion
+ * on use of volatile and __*_bit() (set/clear/change):
+ *      *_bit() want use of volatile.
+ *      __*_bit() are "relaxed" and don't use spinlock or volatile.
+ */
+
+static __inline__ void set_bit(int nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
         unsigned long flags;
 
         addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
         _atomic_spin_lock_irqsave(addr, flags);
         *addr |= mask;
         _atomic_spin_unlock_irqrestore(addr, flags);
 }
 
-static __inline__ void __set_bit(int nr, volatile unsigned long * address)
+static __inline__ void __set_bit(unsigned long nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
+        unsigned long *m = (unsigned long *) addr + (nr >> SHIFT_PER_LONG);
 
-        addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
-        *addr |= mask;
+        *m |= 1UL << CHOP_SHIFTCOUNT(nr);
 }
 
-static __inline__ void clear_bit(int nr, volatile unsigned long * address)
+static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
+        unsigned long mask = ~(1UL << CHOP_SHIFTCOUNT(nr));
         unsigned long flags;
 
         addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
         _atomic_spin_lock_irqsave(addr, flags);
-        *addr &= ~mask;
+        *addr &= mask;
         _atomic_spin_unlock_irqrestore(addr, flags);
 }
 
-static __inline__ void __clear_bit(unsigned long nr, volatile unsigned long * address)
+static __inline__ void __clear_bit(unsigned long nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
+        unsigned long *m = (unsigned long *) addr + (nr >> SHIFT_PER_LONG);
 
-        addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
-        *addr &= ~mask;
+        *m &= ~(1UL << CHOP_SHIFTCOUNT(nr));
 }
 
-static __inline__ void change_bit(int nr, volatile unsigned long * address)
+static __inline__ void change_bit(int nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
         unsigned long flags;
 
         addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
         _atomic_spin_lock_irqsave(addr, flags);
         *addr ^= mask;
         _atomic_spin_unlock_irqrestore(addr, flags);
 }
 
-static __inline__ void __change_bit(int nr, volatile unsigned long * address)
+static __inline__ void __change_bit(unsigned long nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
+        unsigned long *m = (unsigned long *) addr + (nr >> SHIFT_PER_LONG);
 
-        addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
-        *addr ^= mask;
+        *m ^= 1UL << CHOP_SHIFTCOUNT(nr);
 }
 
-static __inline__ int test_and_set_bit(int nr, volatile unsigned long * address)
+static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
-        int oldbit;
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
+        unsigned long oldbit;
         unsigned long flags;
 
         addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
         _atomic_spin_lock_irqsave(addr, flags);
-        oldbit = (*addr & mask) ? 1 : 0;
-        *addr |= mask;
+        oldbit = *addr;
+        *addr = oldbit | mask;
         _atomic_spin_unlock_irqrestore(addr, flags);
 
-        return oldbit;
+        return (oldbit & mask) ? 1 : 0;
 }
 
 static __inline__ int __test_and_set_bit(int nr, volatile unsigned long * address)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
-        int oldbit;
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
+        unsigned long oldbit;
+        unsigned long *addr = (unsigned long *)address + (nr >> SHIFT_PER_LONG);
 
-        addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
-        oldbit = (*addr & mask) ? 1 : 0;
-        *addr |= mask;
+        oldbit = *addr;
+        *addr = oldbit | mask;
 
-        return oldbit;
+        return (oldbit & mask) ? 1 : 0;
 }
 
-static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * address)
+static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
-        int oldbit;
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
+        unsigned long oldbit;
         unsigned long flags;
 
         addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
         _atomic_spin_lock_irqsave(addr, flags);
-        oldbit = (*addr & mask) ? 1 : 0;
-        *addr &= ~mask;
+        oldbit = *addr;
+        *addr = oldbit & ~mask;
         _atomic_spin_unlock_irqrestore(addr, flags);
 
-        return oldbit;
+        return (oldbit & mask) ? 1 : 0;
 }
 
 static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long * address)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
-        int oldbit;
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
+        unsigned long *addr = (unsigned long *)address + (nr >> SHIFT_PER_LONG);
+        unsigned long oldbit;
 
-        addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
-        oldbit = (*addr & mask) ? 1 : 0;
-        *addr &= ~mask;
+        oldbit = *addr;
+        *addr = oldbit & ~mask;
 
-        return oldbit;
+        return (oldbit & mask) ? 1 : 0;
 }
 
-static __inline__ int test_and_change_bit(int nr, volatile unsigned long * address)
+static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
-        int oldbit;
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
+        unsigned long oldbit;
         unsigned long flags;
 
         addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
         _atomic_spin_lock_irqsave(addr, flags);
-        oldbit = (*addr & mask) ? 1 : 0;
-        *addr ^= mask;
+        oldbit = *addr;
+        *addr = oldbit ^ mask;
         _atomic_spin_unlock_irqrestore(addr, flags);
 
-        return oldbit;
+        return (oldbit & mask) ? 1 : 0;
 }
 
 static __inline__ int __test_and_change_bit(int nr, volatile unsigned long * address)
 {
-        unsigned long mask;
-        unsigned long *addr = (unsigned long *) address;
-        int oldbit;
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
+        unsigned long *addr = (unsigned long *)address + (nr >> SHIFT_PER_LONG);
+        unsigned long oldbit;
 
-        addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
-        oldbit = (*addr & mask) ? 1 : 0;
-        *addr ^= mask;
+        oldbit = *addr;
+        *addr = oldbit ^ mask;
 
-        return oldbit;
+        return (oldbit & mask) ? 1 : 0;
 }
 
 static __inline__ int test_bit(int nr, const volatile unsigned long *address)
 {
-        unsigned long mask;
-        const unsigned long *addr = (const unsigned long *)address;
-        
-        addr += (nr >> SHIFT_PER_LONG);
-        mask = 1L << CHOP_SHIFTCOUNT(nr);
+        unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
+        const unsigned long *addr = (const unsigned long *)address + (nr >> SHIFT_PER_LONG);
         
         return !!(*addr & mask);
 }
@@ -229,7 +193,7 @@ static __inline__ unsigned long __ffs(unsigned long x)
         unsigned long ret;
 
         __asm__(
-#if BITS_PER_LONG > 32
+#ifdef __LP64__
                 " ldi       63,%1\n"
                 " extrd,u,*<>  %0,63,32,%%r0\n"
                 " extrd,u,*TR  %0,31,32,%0\n"   /* move top 32-bits down */
@@ -304,14 +268,7 @@ static __inline__ int fls(int x)
  * hweightN: returns the hamming weight (i.e. the number
  * of bits set) of a N-bit word
  */
-#define hweight64(x)                                            \
-({                                                              \
-        unsigned long __x = (x);                                \
-        unsigned int __w;                                       \
-        __w = generic_hweight32((unsigned int) __x);            \
-        __w += generic_hweight32((unsigned int) (__x>>32));     \
-        __w;                                                    \
-})
+#define hweight64(x) generic_hweight64(x)
 #define hweight32(x) generic_hweight32(x)
 #define hweight16(x) generic_hweight16(x)
 #define hweight8(x) generic_hweight8(x)
@@ -324,7 +281,13 @@ static __inline__ int fls(int x)
  */
 static inline int sched_find_first_bit(const unsigned long *b)
 {
-#ifndef __LP64__
+#ifdef __LP64__
+        if (unlikely(b[0]))
+                return __ffs(b[0]);
+        if (unlikely(b[1]))
+                return __ffs(b[1]) + 64;
+        return __ffs(b[2]) + 128;
+#else
         if (unlikely(b[0]))
                 return __ffs(b[0]);
         if (unlikely(b[1]))
@@ -334,14 +297,6 @@ static inline int sched_find_first_bit(const unsigned long *b)
         if (b[3])
                 return __ffs(b[3]) + 96;
         return __ffs(b[4]) + 128;
-#else
-        if (unlikely(b[0]))
-                return __ffs(b[0]);
-        if (unlikely(((unsigned int)b[1])))
-                return __ffs(b[1]) + 64;
-        if (b[1] >> 32)
-                return __ffs(b[1] >> 32) + 96;
-        return __ffs(b[2]) + 128;
 #endif
 }
 
@@ -391,7 +346,7 @@ found_middle:
 
 static __inline__ unsigned long find_next_bit(const unsigned long *addr, unsigned long size, unsigned long offset)
 {
-        const unsigned long *p = addr + (offset >> 6);
+        const unsigned long *p = addr + (offset >> SHIFT_PER_LONG);
         unsigned long result = offset & ~(BITS_PER_LONG-1);
         unsigned long tmp;
 
@@ -445,71 +400,90 @@ found_middle:
  * test_and_{set,clear}_bit guarantee atomicity without
  * disabling interrupts.
  */
-#ifdef __LP64__
-#define ext2_set_bit(nr, addr)          __test_and_set_bit((nr) ^ 0x38, (unsigned long *)addr)
-#define ext2_set_bit_atomic(l,nr,addr)  test_and_set_bit((nr) ^ 0x38, (unsigned long *)addr)
-#define ext2_clear_bit(nr, addr)        __test_and_clear_bit((nr) ^ 0x38, (unsigned long *)addr)
-#define ext2_clear_bit_atomic(l,nr,addr) test_and_clear_bit((nr) ^ 0x38, (unsigned long *)addr)
-#else
-#define ext2_set_bit(nr, addr)          __test_and_set_bit((nr) ^ 0x18, (unsigned long *)addr)
-#define ext2_set_bit_atomic(l,nr,addr)  test_and_set_bit((nr) ^ 0x18, (unsigned long *)addr)
-#define ext2_clear_bit(nr, addr)        __test_and_clear_bit((nr) ^ 0x18, (unsigned long *)addr)
-#define ext2_clear_bit_atomic(l,nr,addr) test_and_clear_bit((nr) ^ 0x18, (unsigned long *)addr)
-#endif
 
-#endif  /* __KERNEL__ */
+/* '3' is bits per byte */
+#define LE_BYTE_ADDR ((sizeof(unsigned long) - 1) << 3)
 
-static __inline__ int ext2_test_bit(int nr, __const__ void * addr)
-{
-        __const__ unsigned char *ADDR = (__const__ unsigned char *) addr;
+#define ext2_test_bit(nr, addr) \
+                        test_bit((nr)   ^ LE_BYTE_ADDR, (unsigned long *)addr)
+#define ext2_set_bit(nr, addr)  \
+                __test_and_set_bit((nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
+#define ext2_clear_bit(nr, addr) \
+                __test_and_clear_bit((nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
 
-        return (ADDR[nr >> 3] >> (nr & 7)) & 1;
-}
+#define ext2_set_bit_atomic(l,nr,addr) \
+                test_and_set_bit((nr)   ^ LE_BYTE_ADDR, (unsigned long *)addr)
+#define ext2_clear_bit_atomic(l,nr,addr) \
+                test_and_clear_bit( (nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
+
+#endif  /* __KERNEL__ */
 
-/*
- * This implementation of ext2_find_{first,next}_zero_bit was stolen from
- * Linus' asm-alpha/bitops.h and modified for a big-endian machine.
- */
 
 #define ext2_find_first_zero_bit(addr, size) \
-        ext2_find_next_zero_bit((addr), (size), 0)
+        ext2_find_next_zero_bit((addr), (size), 0)
 
-extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
-        unsigned long size, unsigned long offset)
+/* include/linux/byteorder does not support "unsigned long" type */
+static inline unsigned long ext2_swabp(unsigned long * x)
 {
-        unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
-        unsigned int result = offset & ~31UL;
-        unsigned int tmp;
+#ifdef __LP64__
+        return (unsigned long) __swab64p((u64 *) x);
+#else
+        return (unsigned long) __swab32p((u32 *) x);
+#endif
+}
+
+/* include/linux/byteorder doesn't support "unsigned long" type */
+static inline unsigned long ext2_swab(unsigned long y)
+{
+#ifdef __LP64__
+        return (unsigned long) __swab64((u64) y);
+#else
+        return (unsigned long) __swab32((u32) y);
+#endif
+}
+
+static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
+{
+        unsigned long *p = (unsigned long *) addr + (offset >> SHIFT_PER_LONG);
+        unsigned long result = offset & ~(BITS_PER_LONG - 1);
+        unsigned long tmp;
 
         if (offset >= size)
                 return size;
         size -= result;
-        offset &= 31UL;
+        offset &= (BITS_PER_LONG - 1UL);
         if (offset) {
-                tmp = cpu_to_le32p(p++);
-                tmp |= ~0UL >> (32-offset);
-                if (size < 32)
+                tmp = ext2_swabp(p++);
+                tmp |= (~0UL >> (BITS_PER_LONG - offset));
+                if (size < BITS_PER_LONG)
                         goto found_first;
-                if (tmp != ~0U)
+                if (~tmp)
                         goto found_middle;
-                size -= 32;
-                result += 32;
+                size -= BITS_PER_LONG;
+                result += BITS_PER_LONG;
         }
-        while (size >= 32) {
-                if ((tmp = cpu_to_le32p(p++)) != ~0U)
-                        goto found_middle;
-                result += 32;
-                size -= 32;
+
+        while (size & ~(BITS_PER_LONG - 1)) {
+                if (~(tmp = *(p++)))
+                        goto found_middle_swap;
+                result += BITS_PER_LONG;
+                size -= BITS_PER_LONG;
         }
         if (!size)
                 return result;
-        tmp = cpu_to_le32p(p);
+        tmp = ext2_swabp(p);
 found_first:
-        tmp |= ~0U << size;
+        tmp |= ~0UL << size;
+        if (tmp == ~0UL)        /* Are any bits zero? */
+                return result + size; /* Nope. Skip ffz */
 found_middle:
         return result + ffz(tmp);
+
+found_middle_swap:
+        return result + ffz(ext2_swab(tmp));
 }
 
+
 /* Bitmap functions for the minix filesystem.  */
 #define minix_test_and_set_bit(nr,addr) ext2_set_bit(nr,addr)
 #define minix_set_bit(nr,addr) ((void)ext2_set_bit(nr,addr))
diff --git a/include/asm-parisc/errno.h b/include/asm-parisc/errno.h
index 08464c405471..e2f3ddc796be 100644
--- a/include/asm-parisc/errno.h
+++ b/include/asm-parisc/errno.h
@@ -114,6 +114,7 @@
 
 #define ENOTSUP         252     /* Function not implemented (POSIX.4 / HPUX) */
 #define ECANCELLED      253     /* aio request was canceled before complete (POSIX.4 / HPUX) */
+#define ECANCELED       ECANCELLED      /* SuSv3 and Solaris wants one 'L' */
 
 /* for robust mutexes */
 #define EOWNERDEAD      254     /* Owner died */
diff --git a/include/asm-parisc/grfioctl.h b/include/asm-parisc/grfioctl.h
index d3cfc0168fb1..6a910311b56b 100644
--- a/include/asm-parisc/grfioctl.h
+++ b/include/asm-parisc/grfioctl.h
@@ -69,6 +69,8 @@
 #define CRT_ID_TVRX             S9000_ID_98765  /* TVRX (gto/falcon) */
 #define CRT_ID_ARTIST           S9000_ID_ARTIST /* Artist */
 #define CRT_ID_SUMMIT           0x2FC1066B      /* Summit FX2, FX4, FX6 ... */
+#define CRT_ID_LEGO             0x35ACDA30      /* Lego FX5, FX10 ... */
+#define CRT_ID_PINNACLE         0x35ACDA16      /* Pinnacle FXe */ 
 
 /* structure for ioctl(GCDESCRIBE) */
 
diff --git a/include/asm-parisc/led.h b/include/asm-parisc/led.h
index 1ac8ab6c580d..efadfd543ec6 100644
--- a/include/asm-parisc/led.h
+++ b/include/asm-parisc/led.h
@@ -23,9 +23,6 @@
 
 #define LED_CMD_REG_NONE 0              /* NULL == no addr for the cmd register */
 
-/* led tasklet struct */
-extern struct tasklet_struct led_tasklet;
-
 /* register_led_driver() */
 int __init register_led_driver(int model, unsigned long cmd_reg, unsigned long data_reg);
 
diff --git a/include/asm-parisc/parisc-device.h b/include/asm-parisc/parisc-device.h
index ef69ab4b17a9..1d247e32a608 100644
--- a/include/asm-parisc/parisc-device.h
+++ b/include/asm-parisc/parisc-device.h
@@ -1,7 +1,7 @@
 #include <linux/device.h>
 
 struct parisc_device {
-        unsigned long   hpa;            /* Hard Physical Address */
+        struct resource hpa;            /* Hard Physical Address */
         struct parisc_device_id id;
         struct parisc_driver *driver;   /* Driver for this device */
         char            name[80];       /* The hardware description */
@@ -39,6 +39,11 @@ struct parisc_driver {
 #define to_parisc_driver(d)     container_of(d, struct parisc_driver, drv)
 #define parisc_parent(d)        to_parisc_device(d->dev.parent)
 
+static inline char *parisc_pathname(struct parisc_device *d)
+{
+        return d->dev.bus_id;
+}
+
 static inline void
 parisc_set_drvdata(struct parisc_device *d, void *p)
 {
diff --git a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h
index d0b761f690b5..fa39d07d49e9 100644
--- a/include/asm-parisc/pci.h
+++ b/include/asm-parisc/pci.h
@@ -69,7 +69,7 @@ struct pci_hba_data {
 #define PCI_PORT_HBA(a)         ((a) >> HBA_PORT_SPACE_BITS)
 #define PCI_PORT_ADDR(a)        ((a) & (HBA_PORT_SPACE_SIZE - 1))
 
-#if CONFIG_64BIT
+#ifdef CONFIG_64BIT
 #define PCI_F_EXTEND            0xffffffff00000000UL
 #define PCI_IS_LMMIO(hba,a)     pci_is_lmmio(hba,a)
 
diff --git a/include/asm-parisc/pgtable.h b/include/asm-parisc/pgtable.h
index 820c6e712cd7..c28fb6f48c6c 100644
--- a/include/asm-parisc/pgtable.h
+++ b/include/asm-parisc/pgtable.h
@@ -501,6 +501,8 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 
+#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
+
 #define MK_IOSPACE_PFN(space, pfn)      (pfn)
 #define GET_IOSPACE(pfn)                0
 #define GET_PFN(pfn)                    (pfn)
diff --git a/include/asm-parisc/processor.h b/include/asm-parisc/processor.h
index a9dfadd05658..aae40e8c3aa8 100644
--- a/include/asm-parisc/processor.h
+++ b/include/asm-parisc/processor.h
@@ -122,8 +122,27 @@ struct thread_struct {
 }; 
 
 /* Thread struct flags. */
+#define PARISC_UAC_NOPRINT      (1UL << 0)      /* see prctl and unaligned.c */
+#define PARISC_UAC_SIGBUS       (1UL << 1)
 #define PARISC_KERNEL_DEATH     (1UL << 31)     /* see die_if_kernel()... */
 
+#define PARISC_UAC_SHIFT        0
+#define PARISC_UAC_MASK         (PARISC_UAC_NOPRINT|PARISC_UAC_SIGBUS)
+
+#define SET_UNALIGN_CTL(task,value)                                       \
+        ({                                                                \
+        (task)->thread.flags = (((task)->thread.flags & ~PARISC_UAC_MASK) \
+                                | (((value) << PARISC_UAC_SHIFT) &        \
+                                   PARISC_UAC_MASK));                     \
+        0;                                                                \
+        })
+
+#define GET_UNALIGN_CTL(task,addr)                                        \
+        ({                                                                \
+        put_user(((task)->thread.flags & PARISC_UAC_MASK)                 \
+                 >> PARISC_UAC_SHIFT, (int __user *) (addr));             \
+        })
+
 #define INIT_THREAD { \
         regs:   {       gr: { 0, }, \
                         fr: { 0, }, \
diff --git a/include/asm-parisc/psw.h b/include/asm-parisc/psw.h
index 51323029f377..4334d6ca2add 100644
--- a/include/asm-parisc/psw.h
+++ b/include/asm-parisc/psw.h
@@ -1,4 +1,7 @@
 #ifndef _PARISC_PSW_H
+
+#include <linux/config.h>
+
 #define PSW_I   0x00000001
 #define PSW_D   0x00000002
 #define PSW_P   0x00000004
@@ -9,6 +12,16 @@
 #define PSW_G   0x00000040      /* PA1.x only */
 #define PSW_O   0x00000080      /* PA2.0 only */
 
+/* ssm/rsm instructions number PSW_W and PSW_E differently */
+#define PSW_SM_I        PSW_I   /* Enable External Interrupts */
+#define PSW_SM_D        PSW_D
+#define PSW_SM_P        PSW_P
+#define PSW_SM_Q        PSW_Q   /* Enable Interrupt State Collection */
+#define PSW_SM_R        PSW_R   /* Enable Recover Counter Trap */
+#define PSW_SM_W        0x200   /* PA2.0 only : Enable Wide Mode */
+
+#define PSW_SM_QUIET    PSW_SM_R+PSW_SM_Q+PSW_SM_P+PSW_SM_D+PSW_SM_I
+
 #define PSW_CB  0x0000ff00
 
 #define PSW_M   0x00010000
@@ -30,33 +43,21 @@
 #define PSW_Z   0x40000000      /* PA1.x only */
 #define PSW_Y   0x80000000      /* PA1.x only */
 
-#ifdef __LP64__
-#define PSW_HI_CB 0x000000ff    /* PA2.0 only */
+#ifdef CONFIG_64BIT
+#  define PSW_HI_CB 0x000000ff    /* PA2.0 only */
 #endif
 
-/* PSW bits to be used with ssm/rsm */
-#define PSW_SM_I        0x1
-#define PSW_SM_D        0x2
-#define PSW_SM_P        0x4
-#define PSW_SM_Q        0x8
-#define PSW_SM_R        0x10
-#define PSW_SM_F        0x20
-#define PSW_SM_G        0x40
-#define PSW_SM_O        0x80
-#define PSW_SM_E        0x100
-#define PSW_SM_W        0x200
-
-#ifdef __LP64__
-#  define USER_PSW      (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I)
-#  define KERNEL_PSW    (PSW_W | PSW_C | PSW_Q | PSW_P | PSW_D)
-#  define REAL_MODE_PSW (PSW_W | PSW_Q)
-#  define USER_PSW_MASK (PSW_W | PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB)
-#  define USER_PSW_HI_MASK (PSW_HI_CB)
-#else
-#  define USER_PSW      (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I)
-#  define KERNEL_PSW    (PSW_C | PSW_Q | PSW_P | PSW_D)
-#  define REAL_MODE_PSW (PSW_Q)
-#  define USER_PSW_MASK (PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB)
+#ifdef CONFIG_64BIT
+#  define USER_PSW_HI_MASK      PSW_HI_CB
+#  define WIDE_PSW              PSW_W
+#else 
+#  define WIDE_PSW              0
 #endif
 
+/* Used when setting up for rfi */
+#define KERNEL_PSW    (WIDE_PSW | PSW_C | PSW_Q | PSW_P | PSW_D)
+#define REAL_MODE_PSW (WIDE_PSW | PSW_Q)
+#define USER_PSW_MASK (WIDE_PSW | PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB)
+#define USER_PSW      (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I)
+
 #endif
diff --git a/include/asm-parisc/ptrace.h b/include/asm-parisc/ptrace.h
index 3f428aa371a4..93f990e418f1 100644
--- a/include/asm-parisc/ptrace.h
+++ b/include/asm-parisc/ptrace.h
@@ -49,7 +49,7 @@ struct pt_regs {
 #define user_mode(regs)                 (((regs)->iaoq[0] & 3) ? 1 : 0)
 #define user_space(regs)                (((regs)->iasq[1] != 0) ? 1 : 0)
 #define instruction_pointer(regs)       ((regs)->iaoq[0] & ~3)
-#define profile_pc(regs) instruction_pointer(regs)
+unsigned long profile_pc(struct pt_regs *);
 extern void show_regs(struct pt_regs *);
 #endif
 
diff --git a/include/asm-parisc/spinlock.h b/include/asm-parisc/spinlock.h
index 43eaa6e742e0..7c3f406a746a 100644
--- a/include/asm-parisc/spinlock.h
+++ b/include/asm-parisc/spinlock.h
@@ -5,11 +5,6 @@
 #include <asm/processor.h>
 #include <asm/spinlock_types.h>
 
-/* Note that PA-RISC has to use `1' to mean unlocked and `0' to mean locked
- * since it only has load-and-zero. Moreover, at least on some PA processors,
- * the semaphore address has to be 16-byte aligned.
- */
-
 static inline int __raw_spin_is_locked(raw_spinlock_t *x)
 {
         volatile unsigned int *a = __ldcw_align(x);
diff --git a/include/asm-parisc/spinlock_types.h b/include/asm-parisc/spinlock_types.h
index 785bba822fbf..d6b479bdb886 100644
--- a/include/asm-parisc/spinlock_types.h
+++ b/include/asm-parisc/spinlock_types.h
@@ -6,11 +6,15 @@
 #endif
 
 typedef struct {
+#ifdef CONFIG_PA20
+        volatile unsigned int slock;
+# define __RAW_SPIN_LOCK_UNLOCKED { 1 }
+#else
         volatile unsigned int lock[4];
+# define __RAW_SPIN_LOCK_UNLOCKED       { { 1, 1, 1, 1 } }
+#endif
 } raw_spinlock_t;
 
-#define __RAW_SPIN_LOCK_UNLOCKED        { { 1, 1, 1, 1 } }
-
 typedef struct {
         raw_spinlock_t lock;
         volatile int counter;
diff --git a/include/asm-parisc/system.h b/include/asm-parisc/system.h
index 26ff844a21c1..f3928d3a80cb 100644
--- a/include/asm-parisc/system.h
+++ b/include/asm-parisc/system.h
@@ -138,13 +138,7 @@ static inline void set_eiem(unsigned long val)
 #define set_wmb(var, value)             do { var = value; wmb(); } while (0)
 
 
-/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.  */
-#define __ldcw(a) ({ \
-        unsigned __ret; \
-        __asm__ __volatile__("ldcw 0(%1),%0" : "=r" (__ret) : "r" (a)); \
-        __ret; \
-})
-
+#ifndef CONFIG_PA20
 /* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
    and GCC only guarantees 8-byte alignment for stack locals, we can't
    be assured of 16-byte alignment for atomic lock data even if we
@@ -152,37 +146,41 @@ static inline void set_eiem(unsigned long val)
    we use a struct containing an array of four ints for the atomic lock
    type and dynamically select the 16-byte aligned int from the array
    for the semaphore.  */
+
 #define __PA_LDCW_ALIGNMENT 16
 #define __ldcw_align(a) ({ \
   unsigned long __ret = (unsigned long) &(a)->lock[0];                  \
   __ret = (__ret + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1); \
   (volatile unsigned int *) __ret;                                      \
 })
+#define LDCW    "ldcw"
 
-#ifdef CONFIG_SMP
-# define __lock_aligned __attribute__((__section__(".data.lock_aligned")))
-#endif
+#else /*CONFIG_PA20*/
+/* From: "Jim Hull" <jim.hull of hp.com>
+   I've attached a summary of the change, but basically, for PA 2.0, as
+   long as the ",CO" (coherent operation) completer is specified, then the
+   16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
+   they only require "natural" alignment (4-byte for ldcw, 8-byte for
+   ldcd). */
 
-#define KERNEL_START (0x10100000 - 0x1000)
+#define __PA_LDCW_ALIGNMENT 4
+#define __ldcw_align(a) ((volatile unsigned int *)a)
+#define LDCW    "ldcw,co"
 
-/* This is for the serialisation of PxTLB broadcasts.  At least on the
- * N class systems, only one PxTLB inter processor broadcast can be
- * active at any one time on the Merced bus.  This tlb purge
- * synchronisation is fairly lightweight and harmless so we activate
- * it on all SMP systems not just the N class. */
-#ifdef CONFIG_SMP
-extern spinlock_t pa_tlb_lock;
+#endif /*!CONFIG_PA20*/
 
-#define purge_tlb_start(x) spin_lock(&pa_tlb_lock)
-#define purge_tlb_end(x) spin_unlock(&pa_tlb_lock)
-
-#else
-
-#define purge_tlb_start(x) do { } while(0)
-#define purge_tlb_end(x) do { } while (0)
+/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.  */
+#define __ldcw(a) ({ \
+        unsigned __ret; \
+        __asm__ __volatile__(LDCW " 0(%1),%0" : "=r" (__ret) : "r" (a)); \
+        __ret; \
+})
 
+#ifdef CONFIG_SMP
+# define __lock_aligned __attribute__((__section__(".data.lock_aligned")))
 #endif
 
+#define KERNEL_START (0x10100000 - 0x1000)
 #define arch_align_stack(x) (x)
 
 #endif
diff --git a/include/asm-parisc/tlbflush.h b/include/asm-parisc/tlbflush.h
index eb27b78930e8..84af4ab1fe51 100644
--- a/include/asm-parisc/tlbflush.h
+++ b/include/asm-parisc/tlbflush.h
@@ -7,6 +7,26 @@
 #include <linux/mm.h>
 #include <asm/mmu_context.h>
 
+
+/* This is for the serialisation of PxTLB broadcasts.  At least on the
+ * N class systems, only one PxTLB inter processor broadcast can be
+ * active at any one time on the Merced bus.  This tlb purge
+ * synchronisation is fairly lightweight and harmless so we activate
+ * it on all SMP systems not just the N class. */
+#ifdef CONFIG_SMP
+extern spinlock_t pa_tlb_lock;
+
+#define purge_tlb_start(x) spin_lock(&pa_tlb_lock)
+#define purge_tlb_end(x) spin_unlock(&pa_tlb_lock)
+
+#else
+
+#define purge_tlb_start(x) do { } while(0)
+#define purge_tlb_end(x) do { } while (0)
+
+#endif
+
+
 extern void flush_tlb_all(void);
 
 /*
@@ -64,29 +84,26 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
 {
         unsigned long npages;
 
-        
         npages = ((end - (start & PAGE_MASK)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
-        if (npages >= 512)  /* XXX arbitrary, should be tuned */
+        if (npages >= 512)  /* 2MB of space: arbitrary, should be tuned */
                 flush_tlb_all();
         else {
 
                 mtsp(vma->vm_mm->context,1);
+                purge_tlb_start();
                 if (split_tlb) {
-                        purge_tlb_start();
                         while (npages--) {
                                 pdtlb(start);
                                 pitlb(start);
                                 start += PAGE_SIZE;
                         }
-                        purge_tlb_end();
                 } else {
-                        purge_tlb_start();
                         while (npages--) {
                                 pdtlb(start);
                                 start += PAGE_SIZE;
                         }
-                        purge_tlb_end();
                 }
+                purge_tlb_end();
         }
 }
 
diff --git a/include/asm-parisc/types.h b/include/asm-parisc/types.h
index d21b9d0d63ea..34fdce361a5a 100644
--- a/include/asm-parisc/types.h
+++ b/include/asm-parisc/types.h
@@ -33,8 +33,10 @@ typedef unsigned long long __u64;
 
 #ifdef __LP64__
 #define BITS_PER_LONG 64
+#define SHIFT_PER_LONG 6
 #else
 #define BITS_PER_LONG 32
+#define SHIFT_PER_LONG 5
 #endif
 
 #ifndef __ASSEMBLY__
diff --git a/include/asm-parisc/unistd.h b/include/asm-parisc/unistd.h
index 6a9f0cadff58..e7a620c5c5e6 100644
--- a/include/asm-parisc/unistd.h
+++ b/include/asm-parisc/unistd.h
@@ -687,8 +687,8 @@
 #define __NR_shmget             (__NR_Linux + 194)
 #define __NR_shmctl             (__NR_Linux + 195)
 
-#define __NR_getpmsg            (__NR_Linux + 196)      /* some people actually want streams */
-#define __NR_putpmsg            (__NR_Linux + 197)      /* some people actually want streams */
+#define __NR_getpmsg            (__NR_Linux + 196) /* Somebody *wants* streams? */
+#define __NR_putpmsg            (__NR_Linux + 197)
 
 #define __NR_lstat64            (__NR_Linux + 198)
 #define __NR_truncate64         (__NR_Linux + 199)
@@ -755,8 +755,14 @@
 #define __NR_mbind              (__NR_Linux + 260)
 #define __NR_get_mempolicy      (__NR_Linux + 261)
 #define __NR_set_mempolicy      (__NR_Linux + 262)
+#define __NR_vserver            (__NR_Linux + 263)
+#define __NR_add_key            (__NR_Linux + 264)
+#define __NR_request_key        (__NR_Linux + 265)
+#define __NR_keyctl             (__NR_Linux + 266)
+#define __NR_ioprio_set         (__NR_Linux + 267)
+#define __NR_ioprio_get         (__NR_Linux + 268)
 
-#define __NR_Linux_syscalls     263
+#define __NR_Linux_syscalls     269
 
 #define HPUX_GATEWAY_ADDR       0xC0000004
 #define LINUX_GATEWAY_ADDR      0x100
@@ -807,10 +813,10 @@
 #define K_INLINE_SYSCALL(name, nr, args...)     ({                      \
         long __sys_res;                                                 \
         {                                                               \
-                register unsigned long __res asm("r28");                \
+                register unsigned long __res __asm__("r28");            \
                 K_LOAD_ARGS_##nr(args)                                  \
                 /* FIXME: HACK stw/ldw r19 around syscall */            \
-                asm volatile(                                           \
+                __asm__ volatile(                                       \
                         K_STW_ASM_PIC                                   \
                         "       ble  0x100(%%sr2, %%r0)\n"              \
                         "       ldi %1, %%r20\n"                        \
diff --git a/include/linux/hil.h b/include/linux/hil.h
new file mode 100644
index 000000000000..13352d7d0caf
--- /dev/null
+++ b/include/linux/hil.h
@@ -0,0 +1,483 @@
+#ifndef _HIL_H_
+#define _HIL_H_
+
+/*
+ * Hewlett Packard Human Interface Loop (HP-HIL) Protocol -- header.
+ *
+ * Copyright (c) 2001 Brian S. Julin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification.
+ * 2. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL").
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *
+ * References:
+ * HP-HIL Technical Reference Manual.  Hewlett Packard Product No. 45918A
+ *
+ * A note of thanks to HP for providing and shipping reference materials
+ * free of charge to help in the development of HIL support for Linux.
+ *
+ */
+
+#include <asm/types.h>
+
+/* Physical constants relevant to raw loop/device timing. 
+ */ 
+
+#define HIL_CLOCK               8MHZ
+#define HIL_EK1_CLOCK           30HZ
+#define HIL_EK2_CLOCK           60HZ
+
+#define HIL_TIMEOUT_DEV         5       /* ms */
+#define HIL_TIMEOUT_DEVS        10      /* ms */
+#define HIL_TIMEOUT_NORESP      10      /* ms */
+#define HIL_TIMEOUT_DEVS_DATA   16      /* ms */
+#define HIL_TIMEOUT_SELFTEST    200     /* ms */
+
+
+/* Actual wire line coding.  These will only be useful if someone is 
+ * implementing a software MLC to run HIL devices on a non-parisc machine.
+ */
+
+#define HIL_WIRE_PACKET_LEN     15
+enum hil_wire_bitpos {
+        HIL_WIRE_START          = 0,
+        HIL_WIRE_ADDR2,
+        HIL_WIRE_ADDR1,
+        HIL_WIRE_ADDR0,
+        HIL_WIRE_COMMAND,
+        HIL_WIRE_DATA7,
+        HIL_WIRE_DATA6,
+        HIL_WIRE_DATA5,
+        HIL_WIRE_DATA4,
+        HIL_WIRE_DATA3,
+        HIL_WIRE_DATA2,
+        HIL_WIRE_DATA1,
+        HIL_WIRE_DATA0,
+        HIL_WIRE_PARITY,
+        HIL_WIRE_STOP
+};
+
+/* HP documentation uses these bit positions to refer to commands;
+ * we will call these "packets".
+ */
+enum hil_pkt_bitpos {
+        HIL_PKT_CMD             = 0x00000800,
+        HIL_PKT_ADDR2           = 0x00000400,
+        HIL_PKT_ADDR1           = 0x00000200,
+        HIL_PKT_ADDR0           = 0x00000100,
+        HIL_PKT_ADDR_MASK       = 0x00000700,
+        HIL_PKT_ADDR_SHIFT      = 8,
+        HIL_PKT_DATA7           = 0x00000080,
+        HIL_PKT_DATA6           = 0x00000040,
+        HIL_PKT_DATA5           = 0x00000020,
+        HIL_PKT_DATA4           = 0x00000010,
+        HIL_PKT_DATA3           = 0x00000008,
+        HIL_PKT_DATA2           = 0x00000004,
+        HIL_PKT_DATA1           = 0x00000002,
+        HIL_PKT_DATA0           = 0x00000001,
+        HIL_PKT_DATA_MASK       = 0x000000FF,
+        HIL_PKT_DATA_SHIFT      = 0
+};
+
+/* The HIL MLC also has several error/status/control bits.  We extend the 
+ * "packet" to include these when direct access to the MLC is available,
+ * or emulate them in cases where they are not available. 
+ *
+ * This way the device driver knows that the underlying MLC driver
+ * has had to deal with loop errors.
+ */
+enum hil_error_bitpos {
+        HIL_ERR_OB      = 0x00000800, /* MLC is busy sending an auto-poll, 
+                                         or we have filled up the output 
+                                         buffer and must wait. */
+        HIL_ERR_INT     = 0x00010000, /* A normal interrupt has occurred. */
+        HIL_ERR_NMI     = 0x00020000, /* An NMI has occurred. */
+        HIL_ERR_LERR    = 0x00040000, /* A poll didn't come back. */
+        HIL_ERR_PERR    = 0x01000000, /* There was a Parity Error. */
+        HIL_ERR_FERR    = 0x02000000, /* There was a Framing Error. */
+        HIL_ERR_FOF     = 0x04000000  /* Input FIFO Overflowed. */
+};
+
+enum hil_control_bitpos {
+        HIL_CTRL_TEST   = 0x00010000,
+        HIL_CTRL_IPF    = 0x00040000,
+        HIL_CTRL_APE    = 0x02000000
+};
+
+/* Bits 30,31 are unused, we use them to control write behavior. */
+#define HIL_DO_ALTER_CTRL  0x40000000 /* Write MSW of packet to control 
+                                          before writing LSW to loop */
+#define HIL_CTRL_ONLY      0xc0000000 /* *Only* alter the control registers */
+
+/* This gives us a 32-bit "packet" 
+ */
+typedef u32 hil_packet;
+
+
+/* HIL Loop commands 
+ */
+enum hil_command {
+        HIL_CMD_IFC     = 0x00, /* Interface Clear */
+        HIL_CMD_EPT     = 0x01, /* Enter Pass-Thru Mode */
+        HIL_CMD_ELB     = 0x02, /* Enter Loop-Back Mode */
+        HIL_CMD_IDD     = 0x03, /* Identify and Describe */
+        HIL_CMD_DSR     = 0x04, /* Device Soft Reset */
+        HIL_CMD_PST     = 0x05, /* Perform Self Test */
+        HIL_CMD_RRG     = 0x06, /* Read Register */
+        HIL_CMD_WRG     = 0x07, /* Write Register */
+        HIL_CMD_ACF     = 0x08, /* Auto Configure */
+        HIL_CMDID_ACF   = 0x07, /* Auto Configure bits with incremented ID */
+        HIL_CMD_POL     = 0x10, /* Poll */
+        HIL_CMDCT_POL   = 0x0f, /* Poll command bits with item count  */
+        HIL_CMD_RPL     = 0x20, /* RePoll */
+        HIL_CMDCT_RPL   = 0x0f, /* RePoll command bits with item count */
+        HIL_CMD_RNM     = 0x30, /* Report Name */
+        HIL_CMD_RST     = 0x31, /* Report Status */
+        HIL_CMD_EXD     = 0x32, /* Extended Describe */
+        HIL_CMD_RSC     = 0x33, /* Report Security Code */
+
+        /* 0x34 to 0x3c reserved for future use  */
+
+        HIL_CMD_DKA     = 0x3d, /* Disable Keyswitch Autorepeat */
+        HIL_CMD_EK1     = 0x3e, /* Enable Keyswitch Autorepeat 1 */
+        HIL_CMD_EK2     = 0x3f, /* Enable Keyswitch Autorepeat 2 */
+        HIL_CMD_PR1     = 0x40, /* Prompt1 */  
+        HIL_CMD_PR2     = 0x41, /* Prompt2 */
+        HIL_CMD_PR3     = 0x42, /* Prompt3 */
+        HIL_CMD_PR4     = 0x43, /* Prompt4 */
+        HIL_CMD_PR5     = 0x44, /* Prompt5 */
+        HIL_CMD_PR6     = 0x45, /* Prompt6 */
+        HIL_CMD_PR7     = 0x46, /* Prompt7 */
+        HIL_CMD_PRM     = 0x47, /* Prompt (General Purpose) */
+        HIL_CMD_AK1     = 0x48, /* Acknowlege1 */  
+        HIL_CMD_AK2     = 0x49, /* Acknowlege2 */
+        HIL_CMD_AK3     = 0x4a, /* Acknowlege3 */
+        HIL_CMD_AK4     = 0x4b, /* Acknowlege4 */
+        HIL_CMD_AK5     = 0x4c, /* Acknowlege5 */
+        HIL_CMD_AK6     = 0x4d, /* Acknowlege6 */
+        HIL_CMD_AK7     = 0x4e, /* Acknowlege7 */
+        HIL_CMD_ACK     = 0x4f, /* Acknowlege (General Purpose) */
+
+        /* 0x50 to 0x78 reserved for future use  */
+        /* 0x80 to 0xEF device-specific commands */
+        /* 0xf0 to 0xf9 reserved for future use  */
+
+        HIL_CMD_RIO     = 0xfa, /* Register I/O Error */
+        HIL_CMD_SHR     = 0xfb, /* System Hard Reset */
+        HIL_CMD_TER     = 0xfc, /* Transmission Error */
+        HIL_CMD_CAE     = 0xfd, /* Configuration Address Error */
+        HIL_CMD_DHR     = 0xfe, /* Device Hard Reset */
+
+        /* 0xff is prohibited from use. */
+};
+
+
+/* 
+ * Response "records" to HIL commands
+ */
+
+/* Device ID byte 
+ */
+#define HIL_IDD_DID_TYPE_MASK           0xe0    /* Primary type bits */
+#define HIL_IDD_DID_TYPE_KB_INTEGRAL    0xa0    /* Integral keyboard */
+#define HIL_IDD_DID_TYPE_KB_ITF         0xc0    /* ITD keyboard */
+#define HIL_IDD_DID_TYPE_KB_RSVD        0xe0    /* Reserved keyboard type */
+#define HIL_IDD_DID_TYPE_KB_LANG_MASK   0x1f    /* Keyboard locale bits */
+#define HIL_IDD_DID_KBLANG_USE_ESD      0x00    /* Use ESD Locale instead */
+#define HIL_IDD_DID_TYPE_ABS            0x80    /* Absolute Positioners */
+#define HIL_IDD_DID_ABS_RSVD1_MASK      0xf8    /* Reserved */
+#define HIL_IDD_DID_ABS_RSVD1           0x98
+#define HIL_IDD_DID_ABS_TABLET_MASK     0xf8    /* Tablets and digitizers */
+#define HIL_IDD_DID_ABS_TABLET          0x90
+#define HIL_IDD_DID_ABS_TSCREEN_MASK    0xfc    /* Touch screens */
+#define HIL_IDD_DID_ABS_TSCREEN         0x8c
+#define HIL_IDD_DID_ABS_RSVD2_MASK      0xfc    /* Reserved */
+#define HIL_IDD_DID_ABS_RSVD2           0x88
+#define HIL_IDD_DID_ABS_RSVD3_MASK      0xfc    /* Reserved */
+#define HIL_IDD_DID_ABS_RSVD3           0x80
+#define HIL_IDD_DID_TYPE_REL            0x60    /* Relative Positioners */
+#define HIL_IDD_DID_REL_RSVD1_MASK      0xf0    /* Reserved */
+#define HIL_IDD_DID_REL_RSVD1           0x70
+#define HIL_IDD_DID_REL_RSVD2_MASK      0xfc    /* Reserved */
+#define HIL_IDD_DID_REL_RSVD2           0x6c
+#define HIL_IDD_DID_REL_MOUSE_MASK      0xfc    /* Mouse */
+#define HIL_IDD_DID_REL_MOUSE           0x68
+#define HIL_IDD_DID_REL_QUAD_MASK       0xf8    /* Other Quadrature Devices */
+#define HIL_IDD_DID_REL_QUAD            0x60
+#define HIL_IDD_DID_TYPE_CHAR           0x40    /* Character Entry */
+#define HIL_IDD_DID_CHAR_BARCODE_MASK   0xfc    /* Barcode Reader */
+#define HIL_IDD_DID_CHAR_BARCODE        0x5c
+#define HIL_IDD_DID_CHAR_RSVD1_MASK     0xfc    /* Reserved */
+#define HIL_IDD_DID_CHAR_RSVD1          0x58
+#define HIL_IDD_DID_CHAR_RSVD2_MASK     0xf8    /* Reserved */
+#define HIL_IDD_DID_CHAR_RSVD2          0x50
+#define HIL_IDD_DID_CHAR_RSVD3_MASK     0xf0    /* Reserved */
+#define HIL_IDD_DID_CHAR_RSVD3          0x40
+#define HIL_IDD_DID_TYPE_OTHER          0x20    /* Miscellaneous */
+#define HIL_IDD_DID_OTHER_RSVD1_MASK    0xf0    /* Reserved */
+#define HIL_IDD_DID_OTHER_RSVD1         0x30
+#define HIL_IDD_DID_OTHER_BARCODE_MASK  0xfc    /* Tone Generator */
+#define HIL_IDD_DID_OTHER_BARCODE       0x2c
+#define HIL_IDD_DID_OTHER_RSVD2_MASK    0xfc    /* Reserved */
+#define HIL_IDD_DID_OTHER_RSVD2         0x28
+#define HIL_IDD_DID_OTHER_RSVD3_MASK    0xf8    /* Reserved */
+#define HIL_IDD_DID_OTHER_RSVD3         0x20
+#define HIL_IDD_DID_TYPE_KEYPAD         0x00    /* Vectra Keyboard */
+
+/* IDD record header 
+ */
+#define HIL_IDD_HEADER_AXSET_MASK       0x03    /* Number of axis in a set */
+#define HIL_IDD_HEADER_RSC              0x04    /* Supports RSC command */
+#define HIL_IDD_HEADER_EXD              0x08    /* Supports EXD command */
+#define HIL_IDD_HEADER_IOD              0x10    /* IOD byte to follow */
+#define HIL_IDD_HEADER_16BIT            0x20    /* 16 (vs. 8) bit resolution */
+#define HIL_IDD_HEADER_ABS              0x40    /* Reports Absolute Position */
+#define HIL_IDD_HEADER_2X_AXIS          0x80    /* Two sets of 1-3 axis */
+
+/* I/O Descriptor
+ */
+#define HIL_IDD_IOD_NBUTTON_MASK        0x07    /* Number of buttons */
+#define HIL_IDD_IOD_PROXIMITY           0x08    /* Proximity in/out events */
+#define HIL_IDD_IOD_PROMPT_MASK         0x70    /* Number of prompts/acks */
+#define HIL_IDD_IOD_PROMPT_SHIFT        4
+#define HIL_IDD_IOD_PROMPT              0x80    /* Generic prompt/ack */
+
+#define HIL_IDD_NUM_AXES_PER_SET(header_packet) \
+((header_packet) & HIL_IDD_HEADER_AXSET_MASK)
+
+#define HIL_IDD_NUM_AXSETS(header_packet) \
+(2 - !((header_packet) & HIL_IDD_HEADER_2X_AXIS))
+
+#define HIL_IDD_LEN(header_packet) \
+((4 - !(header_packet & HIL_IDD_HEADER_IOD) -                   \
+  2 * !(HIL_IDD_NUM_AXES_PER_SET(header_packet))) +             \
+  2 * HIL_IDD_NUM_AXES_PER_SET(header_packet) *                 \
+ !!((header_packet) & HIL_IDD_HEADER_ABS))
+
+/* The following HIL_IDD_* macros assume you have an array of 
+ * packets and/or unpacked 8-bit data in the order that they 
+ * were received.
+ */
+
+#define HIL_IDD_AXIS_COUNTS_PER_M(header_ptr) \
+(!(HIL_IDD_NUM_AXSETS(*(header_ptr))) ? -1 :                    \
+(((*(header_ptr + 1) & HIL_PKT_DATA_MASK) +                     \
+  ((*(header_ptr + 2) & HIL_PKT_DATA_MASK)) << 8)               \
+* ((*(header_ptr) & HIL_IDD_HEADER_16BIT) ? 100 : 1)))
+
+#define HIL_IDD_AXIS_MAX(header_ptr, __axnum) \
+((!(*(header_ptr) & HIL_IDD_HEADER_ABS) ||                      \
+  (HIL_IDD_NUM_AXES_PER_SET(*(header_ptr)) <= __axnum)) ? 0 :   \
+ ((HIL_PKT_DATA_MASK & *((header_ptr) + 3 + 2 * __axnum)) +     \
+  ((HIL_PKT_DATA_MASK & *((header_ptr) + 4 + 2 * __axnum)) << 8)))
+
+#define HIL_IDD_IOD(header_ptr) \
+(*(header_ptr + HIL_IDD_LEN((*header_ptr)) - 1))
+
+#define HIL_IDD_HAS_GEN_PROMPT(header_ptr) \
+((*header_ptr & HIL_IDD_HEADER_IOD) &&                          \
+ (HIL_IDD_IOD(header_ptr) & HIL_IDD_IOD_PROMPT))
+
+#define HIL_IDD_HAS_GEN_PROXIMITY(header_ptr) \
+((*header_ptr & HIL_IDD_HEADER_IOD) &&                          \
+ (HIL_IDD_IOD(header_ptr) & HIL_IDD_IOD_PROXIMITY))
+
+#define HIL_IDD_NUM_BUTTONS(header_ptr) \
+((*header_ptr & HIL_IDD_HEADER_IOD) ?                           \
+ (HIL_IDD_IOD(header_ptr) & HIL_IDD_IOD_NBUTTON_MASK) : 0)
+
+#define HIL_IDD_NUM_PROMPTS(header_ptr) \
+((*header_ptr & HIL_IDD_HEADER_IOD) ?                           \
+ ((HIL_IDD_IOD(header_ptr) & HIL_IDD_IOD_NPROMPT_MASK)          \
+  >> HIL_IDD_IOD_PROMPT_SHIFT) : 0)
+
+/* The response to HIL EXD commands -- the "extended describe record" */
+#define HIL_EXD_HEADER_WRG              0x03    /* Supports type2 WRG */
+#define HIL_EXD_HEADER_WRG_TYPE1        0x01    /* Supports type1 WRG */
+#define HIL_EXD_HEADER_WRG_TYPE2        0x02    /* Supports type2 WRG */
+#define HIL_EXD_HEADER_RRG              0x04    /* Supports RRG command */
+#define HIL_EXD_HEADER_RNM              0x10    /* Supports RNM command */
+#define HIL_EXD_HEADER_RST              0x20    /* Supports RST command */
+#define HIL_EXD_HEADER_LOCALE           0x40    /* Contains locale code */
+
+#define HIL_EXD_NUM_RRG(header_ptr) \
+((*header_ptr & HIL_EXD_HEADER_RRG) ? \
+ (*(header_ptr + 1) & HIL_PKT_DATA_MASK) : 0)
+
+#define HIL_EXD_NUM_WWG(header_ptr) \
+((*header_ptr & HIL_EXD_HEADER_WRG) ?                           \
+ (*(header_ptr + 2 - !(*header_ptr & HIL_EXD_HEADER_RRG)) &     \
+    HIL_PKT_DATA_MASK) : 0)
+
+#define HIL_EXD_LEN(header_ptr) \
+(!!(*header_ptr & HIL_EXD_HEADER_RRG) +                         \
+ !!(*header_ptr & HIL_EXD_HEADER_WRG) +                         \
+ !!(*header_ptr & HIL_EXD_HEADER_LOCALE) +                      \
+ 2 * !!(*header_ptr & HIL_EXD_HEADER_WRG_TYPE2) + 1)
+
+#define HIL_EXD_LOCALE(header_ptr) \
+(!(*header_ptr & HIL_EXD_HEADER_LOCALE) ? -1 :                  \
+ (*(header_ptr + HIL_EXD_LEN(header_ptr) - 1) & HIL_PKT_DATA_MASK))
+
+#define HIL_EXD_WRG_TYPE2_LEN(header_ptr) \
+(!(*header_ptr & HIL_EXD_HEADER_WRG_TYPE2) ? -1 :                       \
+ (*(header_ptr + HIL_EXD_LEN(header_ptr) - 2 -                          \
+    !!(*header_ptr & HIL_EXD_HEADER_LOCALE)) & HIL_PKT_DATA_MASK) +     \
+ ((*(header_ptr + HIL_EXD_LEN(header_ptr) - 1 -                         \
+     !!(*header_ptr & HIL_EXD_HEADER_LOCALE)) & HIL_PKT_DATA_MASK) << 8))
+
+/* Device locale codes. */ 
+
+/* Last defined locale code.  Everything above this is "Reserved",
+   and note that this same table applies to the Device ID Byte where 
+   keyboards may have a nationality code which is only 5 bits. */
+#define HIL_LOCALE_MAX 0x1f
+
+/* Map to hopefully useful strings.  I was trying to make these look
+   like locale.aliases strings do; maybe that isn't the right table to
+   emulate.  In either case, I didn't have much to work on. */
+#define HIL_LOCALE_MAP \
+"",                     /* 0x00 Reserved */             \
+"",                     /* 0x01 Reserved */             \
+"",                     /* 0x02 Reserved */             \
+"swiss.french",         /* 0x03 Swiss/French */         \
+"portuguese",           /* 0x04 Portuguese */           \
+"arabic",               /* 0x05 Arabic */               \
+"hebrew",               /* 0x06 Hebrew */               \
+"english.canadian",     /* 0x07 Canadian English */     \
+"turkish",              /* 0x08 Turkish */              \
+"greek",                /* 0x09 Greek */                \
+"thai",                 /* 0x0a Thai (Thailand) */      \
+"italian",              /* 0x0b Italian */              \
+"korean",               /* 0x0c Hangul (Korea) */       \
+"dutch",                /* 0x0d Dutch */                \
+"swedish",              /* 0x0e Swedish */              \
+"german",               /* 0x0f German */               \
+"chinese",              /* 0x10 Chinese-PRC */          \
+"chinese",              /* 0x11 Chinese-ROC */          \
+"swiss.french",         /* 0x12 Swiss/French II */      \
+"spanish",              /* 0x13 Spanish */              \
+"swiss.german",         /* 0x14 Swiss/German II */      \
+"flemish",              /* 0x15 Belgian (Flemish) */    \
+"finnish",              /* 0x16 Finnish */              \
+"english.uk",           /* 0x17 United Kingdom */       \
+"french.canadian",      /* 0x18 French/Canadian */      \
+"swiss.german",         /* 0x19 Swiss/German */         \
+"norwegian",            /* 0x1a Norwegian */            \
+"french",               /* 0x1b French */               \
+"danish",               /* 0x1c Danish */               \
+"japanese",             /* 0x1d Katakana */             \
+"spanish",              /* 0x1e Latin American/Spanish*/\
+"english.us"            /* 0x1f United States */        \
+
+
+/* HIL keycodes */
+#define HIL_KEYCODES_SET1_TBLSIZE 128
+#define HIL_KEYCODES_SET1       \
+   KEY_5,               KEY_RESERVED,   KEY_RIGHTALT,   KEY_LEFTALT,    \
+   KEY_RIGHTSHIFT,      KEY_LEFTSHIFT,  KEY_LEFTCTRL,   KEY_SYSRQ,      \
+   KEY_KP4,             KEY_KP8,        KEY_KP5,        KEY_KP9,        \
+   KEY_KP6,             KEY_KP7,        KEY_KPCOMMA,    KEY_KPENTER,    \
+   KEY_KP1,             KEY_KPSLASH,    KEY_KP2,        KEY_KPPLUS,     \
+   KEY_KP3,             KEY_KPASTERISK, KEY_KP0,        KEY_KPMINUS,    \
+   KEY_B,               KEY_V,          KEY_C,          KEY_X,          \
+   KEY_Z,               KEY_RESERVED,   KEY_RESERVED,   KEY_ESC,        \
+   KEY_6,               KEY_F10,        KEY_3,          KEY_F11,        \
+   KEY_KPDOT,           KEY_F9,         KEY_TAB /*KP*/, KEY_F12,        \
+   KEY_H,               KEY_G,          KEY_F,          KEY_D,          \
+   KEY_S,               KEY_A,          KEY_RESERVED,   KEY_CAPSLOCK,   \
+   KEY_U,               KEY_Y,          KEY_T,          KEY_R,          \
+   KEY_E,               KEY_W,          KEY_Q,          KEY_TAB,        \
+   KEY_7,               KEY_6,          KEY_5,          KEY_4,          \
+   KEY_3,               KEY_2,          KEY_1,          KEY_GRAVE,      \
+   KEY_F13,             KEY_F14,        KEY_F15,        KEY_F16,        \
+   KEY_F17,             KEY_F18,        KEY_F19,        KEY_F20,        \
+   KEY_MENU,            KEY_F4,         KEY_F3,         KEY_F2,         \
+   KEY_F1,              KEY_VOLUMEUP,   KEY_STOP,       KEY_SENDFILE,   \
+   KEY_SYSRQ,           KEY_F5,         KEY_F6,         KEY_F7,         \
+   KEY_F8,              KEY_VOLUMEDOWN, KEY_DEL_EOL,    KEY_DEL_EOS,    \
+   KEY_8,               KEY_9,          KEY_0,          KEY_MINUS,      \
+   KEY_EQUAL,           KEY_BACKSPACE,  KEY_INS_LINE,   KEY_DEL_LINE,   \
+   KEY_I,               KEY_O,          KEY_P,          KEY_LEFTBRACE,  \
+   KEY_RIGHTBRACE,      KEY_BACKSLASH,  KEY_INSERT,     KEY_DELETE,     \
+   KEY_J,               KEY_K,          KEY_L,          KEY_SEMICOLON,  \
+   KEY_APOSTROPHE,      KEY_ENTER,      KEY_HOME,       KEY_PAGEUP,     \
+   KEY_M,               KEY_COMMA,      KEY_DOT,        KEY_SLASH,      \
+   KEY_BACKSLASH,       KEY_SELECT,     KEY_102ND,      KEY_PAGEDOWN,   \
+   KEY_N,               KEY_SPACE,      KEY_NEXT,       KEY_RESERVED,   \
+   KEY_LEFT,            KEY_DOWN,       KEY_UP,         KEY_RIGHT
+
+
+#define HIL_KEYCODES_SET3_TBLSIZE 128
+#define HIL_KEYCODES_SET3       \
+  KEY_RESERVED, KEY_ESC,        KEY_1,          KEY_2,                  \
+  KEY_3,        KEY_4,          KEY_5,          KEY_6,                  \
+  KEY_7,        KEY_8,          KEY_9,          KEY_0,                  \
+  KEY_MINUS,    KEY_EQUAL,      KEY_BACKSPACE,  KEY_TAB,                \
+  KEY_Q,        KEY_W,          KEY_E,          KEY_R,                  \
+  KEY_T,        KEY_Y,          KEY_U,          KEY_I,                  \
+  KEY_O,        KEY_P,          KEY_LEFTBRACE,  KEY_RIGHTBRACE,         \
+  KEY_ENTER,    KEY_LEFTCTRL,   KEY_A,          KEY_S,                  \
+  KEY_D,        KEY_F,          KEY_G,          KEY_H,                  \
+  KEY_J,        KEY_K,          KEY_L,          KEY_SEMICOLON,          \
+  KEY_APOSTROPHE,KEY_GRAVE,     KEY_LEFTSHIFT,  KEY_BACKSLASH,          \
+  KEY_Z,        KEY_X,          KEY_C,          KEY_V,                  \
+  KEY_B,        KEY_N,          KEY_M,          KEY_COMMA,              \
+  KEY_DOT,      KEY_SLASH,      KEY_RIGHTSHIFT, KEY_KPASTERISK,         \
+  KEY_LEFTALT,  KEY_SPACE,      KEY_CAPSLOCK,   KEY_F1,                 \
+  KEY_F2,       KEY_F3,         KEY_F4,         KEY_F5,                 \
+  KEY_F6,       KEY_F7,         KEY_F8,         KEY_F9,                 \
+  KEY_F10,      KEY_NUMLOCK,    KEY_SCROLLLOCK, KEY_KP7,                \
+  KEY_KP8,      KEY_KP9,        KEY_KPMINUS,    KEY_KP4,                \
+  KEY_KP5,      KEY_KP6,        KEY_KPPLUS,     KEY_KP1,                \
+  KEY_KP2,      KEY_KP3,        KEY_KP0,        KEY_KPDOT,              \
+  KEY_SYSRQ,    KEY_RESERVED,   KEY_RESERVED,   KEY_RESERVED,           \
+  KEY_RESERVED, KEY_RESERVED,   KEY_RESERVED,   KEY_RESERVED,           \
+  KEY_RESERVED, KEY_RESERVED,   KEY_RESERVED,   KEY_RESERVED,           \
+  KEY_UP,       KEY_LEFT,       KEY_DOWN,       KEY_RIGHT,              \
+  KEY_HOME,     KEY_PAGEUP,     KEY_END,        KEY_PAGEDOWN,           \
+  KEY_INSERT,   KEY_DELETE,     KEY_102ND,      KEY_RESERVED,           \
+  KEY_RESERVED, KEY_RESERVED,   KEY_RESERVED,   KEY_RESERVED,           \
+  KEY_F1,       KEY_F2,         KEY_F3,         KEY_F4,                 \
+  KEY_F5,       KEY_F6,         KEY_F7,         KEY_F8,                 \
+  KEY_RESERVED, KEY_RESERVED,   KEY_RESERVED,   KEY_RESERVED,           \
+  KEY_RESERVED, KEY_RESERVED,   KEY_RESERVED,   KEY_RESERVED
+
+
+/* Response to POL command, the "poll record header" */
+
+#define HIL_POL_NUM_AXES_MASK   0x03    /* Number of axis reported */
+#define HIL_POL_CTS             0x04    /* Device ready to receive data */
+#define HIL_POL_STATUS_PENDING  0x08    /* Device has status to report */
+#define HIL_POL_CHARTYPE_MASK   0x70    /* Type of character data to follow */
+#define HIL_POL_CHARTYPE_NONE   0x00    /* No character data to follow */
+#define HIL_POL_CHARTYPE_RSVD1  0x10    /* Reserved Set 1 */
+#define HIL_POL_CHARTYPE_ASCII  0x20    /* U.S. ASCII */
+#define HIL_POL_CHARTYPE_BINARY 0x30    /* Binary data */
+#define HIL_POL_CHARTYPE_SET1   0x40    /* Keycode Set 1 */
+#define HIL_POL_CHARTYPE_RSVD2  0x50    /* Reserved Set 2 */
+#define HIL_POL_CHARTYPE_SET2   0x60    /* Keycode Set 2 */
+#define HIL_POL_CHARTYPE_SET3   0x70    /* Keycode Set 3 */
+#define HIL_POL_AXIS_ALT        0x80    /* Data is from axis set 2 */
+
+
+#endif /* _HIL_H_ */
diff --git a/include/linux/hil_mlc.h b/include/linux/hil_mlc.h
new file mode 100644
index 000000000000..8df29ca48a13
--- /dev/null
+++ b/include/linux/hil_mlc.h
@@ -0,0 +1,168 @@
+/*
+ * HP Human Interface Loop Master Link Controller driver.
+ *
+ * Copyright (c) 2001 Brian S. Julin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification.
+ * 2. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL").
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *
+ * References:
+ * HP-HIL Technical Reference Manual.  Hewlett Packard Product No. 45918A
+ *
+ */
+
+#include <linux/hil.h>
+#include <linux/time.h>
+#include <linux/interrupt.h>
+#include <asm/semaphore.h>
+#include <linux/serio.h>
+#include <linux/list.h>
+
+typedef struct hil_mlc hil_mlc;
+
+/* The HIL has a complicated state engine.
+ * We define the structure of nodes in the state engine here.
+ */
+enum hilse_act {
+        /* HILSE_OUT prepares to receive input if the next node
+         * is an IN or EXPECT, and then sends the given packet.
+         */
+        HILSE_OUT = 0,
+
+        /* HILSE_CTS checks if the loop is busy. */
+        HILSE_CTS,
+
+        /* HILSE_OUT_LAST sends the given command packet to 
+         * the last configured/running device on the loop.
+         */
+        HILSE_OUT_LAST,
+
+        /* HILSE_OUT_DISC sends the given command packet to
+         * the next device past the last configured/running one.
+         */
+        HILSE_OUT_DISC,
+
+        /* HILSE_FUNC runs a callback function with given arguments.
+         * a positive return value causes the "ugly" branch to be taken.
+         */
+        HILSE_FUNC,
+
+        /* HILSE_IN simply expects any non-errored packet to arrive 
+         * within arg usecs.
+         */
+        HILSE_IN                = 0x100,
+
+        /* HILSE_EXPECT expects a particular packet to arrive 
+         * within arg usecs, any other packet is considered an error.
+         */
+        HILSE_EXPECT,
+
+        /* HILSE_EXPECT_LAST as above but dev field should be last 
+         * discovered/operational device.
+         */
+        HILSE_EXPECT_LAST,
+
+        /* HILSE_EXPECT_LAST as above but dev field should be first 
+         * undiscovered/inoperational device.
+         */
+        HILSE_EXPECT_DISC
+};
+
+typedef int     (hilse_func) (hil_mlc *mlc, int arg);
+struct hilse_node {
+        enum hilse_act          act;    /* How to process this node         */
+        union {
+                hilse_func      *func;  /* Function to call if HILSE_FUNC   */
+                hil_packet      packet; /* Packet to send or to compare     */
+        } object;
+        int                     arg;    /* Timeout in usec or parm for func */
+        int                     good;   /* Node to jump to on success       */
+        int                     bad;    /* Node to jump to on error         */
+        int                     ugly;   /* Node to jump to on timeout       */
+};
+
+/* Methods for back-end drivers, e.g. hp_sdc_mlc */
+typedef int     (hil_mlc_cts) (hil_mlc *mlc);
+typedef void    (hil_mlc_out) (hil_mlc *mlc);
+typedef int     (hil_mlc_in)  (hil_mlc *mlc, suseconds_t timeout);
+
+struct hil_mlc_devinfo {
+        uint8_t idd[16];        /* Device ID Byte and Describe Record */
+        uint8_t rsc[16];        /* Security Code Header and Record */
+        uint8_t exd[16];        /* Extended Describe Record */
+        uint8_t rnm[16];        /* Device name as returned by RNM command */
+};
+
+struct hil_mlc_serio_map {
+        hil_mlc *mlc;
+        int di_revmap;
+        int didx;
+};
+
+/* How many (possibly old/detached) devices the we try to keep track of */
+#define HIL_MLC_DEVMEM 16
+
+struct hil_mlc {
+        struct list_head        list;   /* hil_mlc is organized as linked list */
+
+        rwlock_t                lock;
+
+        void *priv; /* Data specific to a particular type of MLC */
+
+        int                     seidx;  /* Current node in state engine */
+        int                     istarted, ostarted;
+
+        hil_mlc_cts             *cts;
+        struct semaphore        csem;   /* Raised when loop idle */
+
+        hil_mlc_out             *out;
+        struct semaphore        osem;   /* Raised when outpacket dispatched */
+        hil_packet              opacket;
+
+        hil_mlc_in              *in;
+        struct semaphore        isem;   /* Raised when a packet arrives */
+        hil_packet              ipacket[16];
+        hil_packet              imatch;
+        int                     icount;
+        struct timeval          instart;
+        suseconds_t             intimeout;
+
+        int                     ddi;    /* Last operational device id */
+        int                     lcv;    /* LCV to throttle loops */
+        struct timeval          lcv_tv; /* Time loop was started */
+
+        int                     di_map[7]; /* Maps below items to live devs */
+        struct hil_mlc_devinfo  di[HIL_MLC_DEVMEM];
+        struct serio            *serio[HIL_MLC_DEVMEM];
+        struct hil_mlc_serio_map serio_map[HIL_MLC_DEVMEM];
+        hil_packet              serio_opacket[HIL_MLC_DEVMEM];
+        int                     serio_oidx[HIL_MLC_DEVMEM];
+        struct hil_mlc_devinfo  di_scratch; /* Temporary area */
+
+        int                     opercnt;
+
+        struct tasklet_struct   *tasklet;
+};
+
+int hil_mlc_register(hil_mlc *mlc);
+int hil_mlc_unregister(hil_mlc *mlc);
diff --git a/include/linux/hp_sdc.h b/include/linux/hp_sdc.h
new file mode 100644
index 000000000000..debd71515312
--- /dev/null
+++ b/include/linux/hp_sdc.h
@@ -0,0 +1,300 @@
+/*
+ * HP i8042 System Device Controller -- header
+ *
+ * Copyright (c) 2001 Brian S. Julin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification.
+ * 2. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL").
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ *
+ * References:
+ * 
+ * HP-HIL Technical Reference Manual.  Hewlett Packard Product No. 45918A
+ *
+ * System Device Controller Microprocessor Firmware Theory of Operation
+ *      for Part Number 1820-4784 Revision B.  Dwg No. A-1820-4784-2
+ *
+ */
+
+#ifndef _LINUX_HP_SDC_H
+#define _LINUX_HP_SDC_H
+
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/time.h>
+#include <linux/timer.h>
+#if defined(__hppa__)
+#include <asm/hardware.h>
+#endif
+
+
+/* No 4X status reads take longer than this (in usec).
+ */
+#define HP_SDC_MAX_REG_DELAY 20000
+
+typedef void (hp_sdc_irqhook) (int irq, void *dev_id, 
+                               uint8_t status, uint8_t data);
+
+int hp_sdc_request_timer_irq(hp_sdc_irqhook *callback);
+int hp_sdc_request_hil_irq(hp_sdc_irqhook *callback);
+int hp_sdc_request_cooked_irq(hp_sdc_irqhook *callback);
+int hp_sdc_release_timer_irq(hp_sdc_irqhook *callback);
+int hp_sdc_release_hil_irq(hp_sdc_irqhook *callback);
+int hp_sdc_release_cooked_irq(hp_sdc_irqhook *callback);
+
+typedef struct {
+        int actidx;     /* Start of act.  Acts are atomic WRT I/O to SDC */
+        int idx;        /* Index within the act */
+        int endidx;     /* transaction is over and done if idx == endidx */
+        uint8_t *seq;   /* commands/data for the transaction */
+        union {
+          hp_sdc_irqhook   *irqhook;    /* Callback, isr or tasklet context */
+          struct semaphore *semaphore;  /* Semaphore to sleep on. */
+        } act;
+} hp_sdc_transaction;
+int hp_sdc_enqueue_transaction(hp_sdc_transaction *this);
+int hp_sdc_dequeue_transaction(hp_sdc_transaction *this);
+
+/* The HP_SDC_ACT* values are peculiar to this driver.
+ * Nuance: never HP_SDC_ACT_DATAIN | HP_SDC_ACT_DEALLOC, use another
+ * act to perform the dealloc.
+ */
+#define HP_SDC_ACT_PRECMD       0x01            /* Send a command first */
+#define HP_SDC_ACT_DATAREG      0x02            /* Set data registers */
+#define HP_SDC_ACT_DATAOUT      0x04            /* Send data bytes */
+#define HP_SDC_ACT_POSTCMD      0x08            /* Send command after */
+#define HP_SDC_ACT_DATAIN       0x10            /* Collect data after */
+#define HP_SDC_ACT_DURING       0x1f
+#define HP_SDC_ACT_SEMAPHORE    0x20            /* Raise semaphore after */
+#define HP_SDC_ACT_CALLBACK     0x40            /* Pass data to IRQ handler */
+#define HP_SDC_ACT_DEALLOC      0x80            /* Destroy transaction after */
+#define HP_SDC_ACT_AFTER        0xe0
+#define HP_SDC_ACT_DEAD         0x60            /* Act timed out. */
+
+/* Rest of the flags are straightforward representation of the SDC interface */
+#define HP_SDC_STATUS_IBF       0x02    /* Input buffer full */
+
+#define HP_SDC_STATUS_IRQMASK   0xf0    /* Bits containing "level 1" irq */
+#define HP_SDC_STATUS_PERIODIC  0x10    /* Periodic 10ms timer */
+#define HP_SDC_STATUS_USERTIMER 0x20    /* "Special purpose" timer */
+#define HP_SDC_STATUS_TIMER     0x30    /* Both PERIODIC and USERTIMER */
+#define HP_SDC_STATUS_REG       0x40    /* Data from an i8042 register */
+#define HP_SDC_STATUS_HILCMD    0x50    /* Command from HIL MLC */
+#define HP_SDC_STATUS_HILDATA   0x60    /* Data from HIL MLC */
+#define HP_SDC_STATUS_PUP       0x70    /* Sucessful power-up self test */
+#define HP_SDC_STATUS_KCOOKED   0x80    /* Key from cooked kbd */
+#define HP_SDC_STATUS_KRPG      0xc0    /* Key from Repeat Gen */
+#define HP_SDC_STATUS_KMOD_SUP  0x10    /* Shift key is up */
+#define HP_SDC_STATUS_KMOD_CUP  0x20    /* Control key is up */
+
+#define HP_SDC_NMISTATUS_FHS    0x40    /* NMI is a fast handshake irq */
+
+/* Internal i8042 registers (there are more, but they are not too useful). */
+
+#define HP_SDC_USE              0x02    /* Resource usage (including OB bit) */
+#define HP_SDC_IM               0x04    /* Interrupt mask */
+#define HP_SDC_CFG              0x11    /* Configuration register */
+#define HP_SDC_KBLANGUAGE       0x12    /* Keyboard language */
+
+#define HP_SDC_D0               0x70    /* General purpose data buffer 0 */
+#define HP_SDC_D1               0x71    /* General purpose data buffer 1 */
+#define HP_SDC_D2               0x72    /* General purpose data buffer 2 */
+#define HP_SDC_D3               0x73    /* General purpose data buffer 3 */
+#define HP_SDC_VT1              0x74    /* Timer for voice 1 */
+#define HP_SDC_VT2              0x75    /* Timer for voice 2 */
+#define HP_SDC_VT3              0x76    /* Timer for voice 3 */
+#define HP_SDC_VT4              0x77    /* Timer for voice 4 */
+#define HP_SDC_KBN              0x78    /* Which HIL devs are Nimitz */
+#define HP_SDC_KBC              0x79    /* Which HIL devs are cooked kbds */
+#define HP_SDC_LPS              0x7a    /* i8042's view of HIL status */
+#define HP_SDC_LPC              0x7b    /* i8042's view of HIL "control" */
+#define HP_SDC_RSV              0x7c    /* Reserved "for testing" */
+#define HP_SDC_LPR              0x7d    /* i8042 count of HIL reconfigs */
+#define HP_SDC_XTD              0x7e    /* "Extended Configuration" register */
+#define HP_SDC_STR              0x7f    /* i8042 self-test result */
+
+/* Bitfields for above registers */
+#define HP_SDC_USE_LOOP         0x04    /* Command is currently on the loop. */
+
+#define HP_SDC_IM_MASK          0x1f    /* these bits not part of cmd/status */
+#define HP_SDC_IM_FH            0x10    /* Mask the fast handshake irq */
+#define HP_SDC_IM_PT            0x08    /* Mask the periodic timer irq */
+#define HP_SDC_IM_TIMERS        0x04    /* Mask the MT/DT/CT irq */
+#define HP_SDC_IM_RESET         0x02    /* Mask the reset key irq */
+#define HP_SDC_IM_HIL           0x01    /* Mask the HIL MLC irq */
+
+#define HP_SDC_CFG_ROLLOVER     0x08    /* WTF is "N-key rollover"? */
+#define HP_SDC_CFG_KBD          0x10    /* There is a keyboard */
+#define HP_SDC_CFG_NEW          0x20    /* Supports/uses HIL MLC */
+#define HP_SDC_CFG_KBD_OLD      0x03    /* keyboard code for non-HIL */
+#define HP_SDC_CFG_KBD_NEW      0x07    /* keyboard code from HIL autoconfig */
+#define HP_SDC_CFG_REV          0x40    /* Code revision bit */
+#define HP_SDC_CFG_IDPROM       0x80    /* IDPROM present in kbd (not HIL) */
+
+#define HP_SDC_LPS_NDEV         0x07    /* # devices autoconfigured on HIL */
+#define HP_SDC_LPS_ACSUCC       0x08    /* loop autoconfigured successfully */
+#define HP_SDC_LPS_ACFAIL       0x80    /* last loop autoconfigure failed */
+
+#define HP_SDC_LPC_APE_IPF      0x01    /* HIL MLC APE/IPF (autopoll) set */
+#define HP_SDC_LPC_ARCONERR     0x02    /* i8042 autoreconfigs loop on err */
+#define HP_SDC_LPC_ARCQUIET     0x03    /* i8042 doesn't report autoreconfigs*/
+#define HP_SDC_LPC_COOK         0x10    /* i8042 cooks devices in _KBN */
+#define HP_SDC_LPC_RC           0x80    /* causes autoreconfig */
+
+#define HP_SDC_XTD_REV          0x07    /* contains revision code */
+#define HP_SDC_XTD_REV_STRINGS(val, str) \
+switch (val) {                                          \
+        case 0x1: str = "1820-3712"; break;             \
+        case 0x2: str = "1820-4379"; break;             \
+        case 0x3: str = "1820-4784"; break;             \
+        default: str = "unknown";                       \
+};
+#define HP_SDC_XTD_BEEPER       0x08    /* TI SN76494 beeper available */
+#define HP_SDC_XTD_BBRTC        0x20    /* OKI MSM-58321 BBRTC present */
+
+#define HP_SDC_CMD_LOAD_RT      0x31    /* Load real time (from 8042) */
+#define HP_SDC_CMD_LOAD_FHS     0x36    /* Load the fast handshake timer */
+#define HP_SDC_CMD_LOAD_MT      0x38    /* Load the match timer */
+#define HP_SDC_CMD_LOAD_DT      0x3B    /* Load the delay timer */
+#define HP_SDC_CMD_LOAD_CT      0x3E    /* Load the cycle timer */
+
+#define HP_SDC_CMD_SET_IM       0x40    /* 010xxxxx == set irq mask */
+
+/* The documents provided do not explicitly state that all registers betweem 
+ * 0x01 and 0x1f inclusive can be read by sending their register index as a 
+ * command, but this is implied and appears to be the case.
+ */
+#define HP_SDC_CMD_READ_RAM     0x00    /* Load from i8042 RAM (autoinc) */
+#define HP_SDC_CMD_READ_USE     0x02    /* Undocumented! Load from usage reg */
+#define HP_SDC_CMD_READ_IM      0x04    /* Load current interrupt mask */
+#define HP_SDC_CMD_READ_KCC     0x11    /* Load primary kbd config code */
+#define HP_SDC_CMD_READ_KLC     0x12    /* Load primary kbd language code */
+#define HP_SDC_CMD_READ_T1      0x13    /* Load timer output buffer byte 1 */
+#define HP_SDC_CMD_READ_T2      0x14    /* Load timer output buffer byte 1 */
+#define HP_SDC_CMD_READ_T3      0x15    /* Load timer output buffer byte 1 */
+#define HP_SDC_CMD_READ_T4      0x16    /* Load timer output buffer byte 1 */
+#define HP_SDC_CMD_READ_T5      0x17    /* Load timer output buffer byte 1 */
+#define HP_SDC_CMD_READ_D0      0xf0    /* Load from i8042 RAM location 0x70 */
+#define HP_SDC_CMD_READ_D1      0xf1    /* Load from i8042 RAM location 0x71 */
+#define HP_SDC_CMD_READ_D2      0xf2    /* Load from i8042 RAM location 0x72 */
+#define HP_SDC_CMD_READ_D3      0xf3    /* Load from i8042 RAM location 0x73 */
+#define HP_SDC_CMD_READ_VT1     0xf4    /* Load from i8042 RAM location 0x74 */
+#define HP_SDC_CMD_READ_VT2     0xf5    /* Load from i8042 RAM location 0x75 */
+#define HP_SDC_CMD_READ_VT3     0xf6    /* Load from i8042 RAM location 0x76 */
+#define HP_SDC_CMD_READ_VT4     0xf7    /* Load from i8042 RAM location 0x77 */
+#define HP_SDC_CMD_READ_KBN     0xf8    /* Load from i8042 RAM location 0x78 */
+#define HP_SDC_CMD_READ_KBC     0xf9    /* Load from i8042 RAM location 0x79 */
+#define HP_SDC_CMD_READ_LPS     0xfa    /* Load from i8042 RAM location 0x7a */
+#define HP_SDC_CMD_READ_LPC     0xfb    /* Load from i8042 RAM location 0x7b */
+#define HP_SDC_CMD_READ_RSV     0xfc    /* Load from i8042 RAM location 0x7c */
+#define HP_SDC_CMD_READ_LPR     0xfd    /* Load from i8042 RAM location 0x7d */
+#define HP_SDC_CMD_READ_XTD     0xfe    /* Load from i8042 RAM location 0x7e */
+#define HP_SDC_CMD_READ_STR     0xff    /* Load from i8042 RAM location 0x7f */
+
+#define HP_SDC_CMD_SET_ARD      0xA0    /* Set emulated autorepeat delay */
+#define HP_SDC_CMD_SET_ARR      0xA2    /* Set emulated autorepeat rate */
+#define HP_SDC_CMD_SET_BELL     0xA3    /* Set voice 3 params for "beep" cmd */
+#define HP_SDC_CMD_SET_RPGR     0xA6    /* Set "RPG" irq rate (doesn't work) */
+#define HP_SDC_CMD_SET_RTMS     0xAD    /* Set the RTC time (milliseconds) */
+#define HP_SDC_CMD_SET_RTD      0xAF    /* Set the RTC time (days) */
+#define HP_SDC_CMD_SET_FHS      0xB2    /* Set fast handshake timer */
+#define HP_SDC_CMD_SET_MT       0xB4    /* Set match timer */
+#define HP_SDC_CMD_SET_DT       0xB7    /* Set delay timer */
+#define HP_SDC_CMD_SET_CT       0xBA    /* Set cycle timer */
+#define HP_SDC_CMD_SET_RAMP     0xC1    /* Reset READ_RAM autoinc counter */
+#define HP_SDC_CMD_SET_D0       0xe0    /* Load to i8042 RAM location 0x70 */
+#define HP_SDC_CMD_SET_D1       0xe1    /* Load to i8042 RAM location 0x71 */
+#define HP_SDC_CMD_SET_D2       0xe2    /* Load to i8042 RAM location 0x72 */
+#define HP_SDC_CMD_SET_D3       0xe3    /* Load to i8042 RAM location 0x73 */
+#define HP_SDC_CMD_SET_VT1      0xe4    /* Load to i8042 RAM location 0x74 */
+#define HP_SDC_CMD_SET_VT2      0xe5    /* Load to i8042 RAM location 0x75 */
+#define HP_SDC_CMD_SET_VT3      0xe6    /* Load to i8042 RAM location 0x76 */
+#define HP_SDC_CMD_SET_VT4      0xe7    /* Load to i8042 RAM location 0x77 */
+#define HP_SDC_CMD_SET_KBN      0xe8    /* Load to i8042 RAM location 0x78 */
+#define HP_SDC_CMD_SET_KBC      0xe9    /* Load to i8042 RAM location 0x79 */
+#define HP_SDC_CMD_SET_LPS      0xea    /* Load to i8042 RAM location 0x7a */
+#define HP_SDC_CMD_SET_LPC      0xeb    /* Load to i8042 RAM location 0x7b */
+#define HP_SDC_CMD_SET_RSV      0xec    /* Load to i8042 RAM location 0x7c */
+#define HP_SDC_CMD_SET_LPR      0xed    /* Load to i8042 RAM location 0x7d */
+#define HP_SDC_CMD_SET_XTD      0xee    /* Load to i8042 RAM location 0x7e */
+#define HP_SDC_CMD_SET_STR      0xef    /* Load to i8042 RAM location 0x7f */
+
+#define HP_SDC_CMD_DO_RTCW      0xc2    /* i8042 RAM 0x70 --> RTC */
+#define HP_SDC_CMD_DO_RTCR      0xc3    /* RTC[0x70 0:3] --> irq/status/data */
+#define HP_SDC_CMD_DO_BEEP      0xc4    /* i8042 RAM 0x70-74  --> beeper,VT3 */
+#define HP_SDC_CMD_DO_HIL       0xc5    /* i8042 RAM 0x70-73 --> 
+                                           HIL MLC R0,R1 i8042 HIL watchdog */
+
+/* Values used to (de)mangle input/output to/from the HIL MLC */
+#define HP_SDC_DATA             0x40    /* Data from an 8042 register */
+#define HP_SDC_HIL_CMD          0x50    /* Data from HIL MLC R1/8042 */
+#define HP_SDC_HIL_R1MASK       0x0f    /* Contents of HIL MLC R1 0:3 */
+#define HP_SDC_HIL_AUTO         0x10    /* Set if POL results from i8042 */   
+#define HP_SDC_HIL_ISERR        0x80    /* Has meaning as in next 4 values */
+#define HP_SDC_HIL_RC_DONE      0x80    /* i8042 auto-configured loop */
+#define HP_SDC_HIL_ERR          0x81    /* HIL MLC R2 had a bit set */
+#define HP_SDC_HIL_TO           0x82    /* i8042 HIL watchdog expired */
+#define HP_SDC_HIL_RC           0x84    /* i8042 is auto-configuring loop */
+#define HP_SDC_HIL_DAT          0x60    /* Data from HIL MLC R0 */
+
+
+typedef struct {
+        rwlock_t        ibf_lock;
+        rwlock_t        lock;           /* user/tasklet lock */
+        rwlock_t        rtq_lock;       /* isr/tasklet lock */
+        rwlock_t        hook_lock;      /* isr/user lock for handler add/del */
+
+        unsigned int    irq, nmi;       /* Our IRQ lines */
+        unsigned long   base_io, status_io, data_io; /* Our IO ports */
+
+        uint8_t         im;             /* Interrupt mask */
+        int             set_im;         /* Interrupt mask needs to be set. */
+
+        int             ibf;            /* Last known status of IBF flag */
+        uint8_t         wi;             /* current i8042 write index */
+        uint8_t         r7[4];          /* current i8042[0x70 - 0x74] values */
+        uint8_t         r11, r7e;       /* Values from version/revision regs */
+
+        hp_sdc_irqhook  *timer, *reg, *hil, *pup, *cooked;
+
+#define HP_SDC_QUEUE_LEN 16
+        hp_sdc_transaction *tq[HP_SDC_QUEUE_LEN]; /* All pending read/writes */
+
+        int             rcurr, rqty;    /* Current read transact in process */
+        struct timeval  rtv;            /* Time when current read started */
+        int             wcurr;          /* Current write transact in process */
+
+        int             dev_err;        /* carries status from registration */
+#if defined(__hppa__)
+        struct parisc_device    *dev;
+#elif defined(__mc68000__)
+        void            *dev;
+#else
+#error No support for device registration on this arch yet.
+#endif
+
+        struct timer_list kicker;       /* Keeps below task alive */
+        struct tasklet_struct   task;
+
+} hp_i8042_sdc;
+
+#endif /* _LINUX_HP_SDC_H */
diff --git a/include/linux/input.h b/include/linux/input.h
index e8c296ff6257..d7836311ada9 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -644,6 +644,7 @@ struct input_absinfo {
 #define BUS_ADB                 0x17
 #define BUS_I2C                 0x18
 #define BUS_HOST                0x19
+#define BUS_GSC                 0x1A
 
 /*
  * Values describing the status of an effect