spi/pxa2xx: Add chipselect support for Sodaville

The SPI core on Sodaville supports chip selects. Its configuration
moved into the SSSR register at bit 0 and 1. Thus Sodaville can be hooked
up with up to 4 devices.
This patch ensures that the bits which are otherwiese reserved are only
touched on Sodaville and not on any other PXAs. Also it makes sure that
the status register does not lose the CS information while clearing the
ROR bit.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h
index c3aa334cbb9b..2f691e4e6222 100644
--- a/include/linux/pxa2xx_ssp.h
+++ b/include/linux/pxa2xx_ssp.h
@@ -72,6 +72,7 @@
 #define SSCR1_SPH       (1 << 4)        /* Motorola SPI SSPSCLK phase setting */
 #define SSCR1_MWDS      (1 << 5)        /* Microwire Transmit Data Size */
 
+#define SSSR_ALT_FRM_MASK       3       /* Masks the SFRM signal number */
 #define SSSR_TNF        (1 << 2)        /* Transmit FIFO Not Full */
 #define SSSR_RNE        (1 << 3)        /* Receive FIFO Not Empty */
 #define SSSR_BSY        (1 << 4)        /* SSP Busy */
@@ -160,6 +161,7 @@ enum pxa_ssp_type {
         PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
         PXA27x_SSP,
         PXA168_SSP,
+        CE4100_SSP,
 };
 
 struct ssp_device {