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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2006-07-13 04:33:24 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-07-13 16:26:20 -0400
commitf26811e0d89d412a2f5d8e16760e71d3b5c2702c (patch)
treece621e2103a5eda53bc5bc59c038165576ba52cc /include
parentefcb487a8e9a86874cf63c3fbf6c85bbf87e6d87 (diff)
[MIPS] vr41xx: Update e55 setup function
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-mips/vr41xx/e55.h43
1 files changed, 0 insertions, 43 deletions
diff --git a/include/asm-mips/vr41xx/e55.h b/include/asm-mips/vr41xx/e55.h
deleted file mode 100644
index 558f2269bf37..000000000000
--- a/include/asm-mips/vr41xx/e55.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * e55.h, Include file for CASIO CASSIOPEIA E-10/15/55/65.
3 *
4 * Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __CASIO_E55_H
21#define __CASIO_E55_H
22
23#include <asm/addrspace.h>
24#include <asm/vr41xx/vr41xx.h>
25
26/*
27 * Board specific address mapping
28 */
29#define VR41XX_ISA_MEM_BASE 0x10000000
30#define VR41XX_ISA_MEM_SIZE 0x04000000
31
32/* VR41XX_ISA_IO_BASE includes offset from real base. */
33#define VR41XX_ISA_IO_BASE 0x1400c000
34#define VR41XX_ISA_IO_SIZE 0x03ff4000
35
36#define ISA_BUS_IO_BASE 0
37#define ISA_BUS_IO_SIZE VR41XX_ISA_IO_SIZE
38
39#define IO_PORT_BASE KSEG1ADDR(VR41XX_ISA_IO_BASE)
40#define IO_PORT_RESOURCE_START ISA_BUS_IO_BASE
41#define IO_PORT_RESOURCE_END (ISA_BUS_IO_BASE + ISA_BUS_IO_SIZE - 1)
42
43#endif /* __CASIO_E55_H */