diff options
author | Sonic Zhang <sonic.zhang@analog.com> | 2008-02-02 04:05:02 -0500 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-02-02 04:05:02 -0500 |
commit | db288381e26e592b11572ce8199bedeadf0c0830 (patch) | |
tree | e10eaa7b1a5b0bfefecd9417be43d12f5e82e006 /include | |
parent | 4cb4f22b19237e63c460c53fbd1c417cdaf63014 (diff) |
[Blackfin] serial driver: Add flow control support to bf54x
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-blackfin/mach-bf548/bfin_serial_5xx.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h index c459c4846469..7e6339f62a50 100644 --- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h | |||
@@ -24,6 +24,8 @@ | |||
24 | #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) | 24 | #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) |
25 | #define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) | 25 | #define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) |
26 | #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) | 26 | #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) |
27 | #define UART_GET_MSR(uart) bfin_read16(((uart)->port.membase + OFFSET_MSR)) | ||
28 | #define UART_GET_MCR(uart) bfin_read16(((uart)->port.membase + OFFSET_MCR)) | ||
27 | 29 | ||
28 | #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) | 30 | #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) |
29 | #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) | 31 | #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) |
@@ -34,6 +36,7 @@ | |||
34 | #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) | 36 | #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) |
35 | #define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1) | 37 | #define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1) |
36 | #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) | 38 | #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) |
39 | #define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v) | ||
37 | 40 | ||
38 | #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) | 41 | #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) |
39 | # define CONFIG_SERIAL_BFIN_CTSRTS | 42 | # define CONFIG_SERIAL_BFIN_CTSRTS |