Merge ../linux-2.6

46 files changed, 1615 insertions, 278 deletions

diff --git a/include/asm-arm/arch-iop13xx/adma.h b/include/asm-arm/arch-iop13xx/adma.h
index 90d14ee564f5..ef4f5da2029f 100644
--- a/include/asm-arm/arch-iop13xx/adma.h
+++ b/include/asm-arm/arch-iop13xx/adma.h
@@ -198,17 +198,13 @@ iop_chan_memset_slot_count(size_t len, int *slots_per_op)
 static inline int
 iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
 {
-        int num_slots;
-        /* slots_to_find = 1 for basic descriptor + 1 per 4 sources above 1
-         * (1 source => 8 bytes) (1 slot => 32 bytes)
-         */
-        num_slots = 1 + (((src_cnt - 1) << 3) >> 5);
-        if (((src_cnt - 1) << 3) & 0x1f)
-                num_slots++;
-
-        *slots_per_op = num_slots;
-
-        return num_slots;
+        static const char slot_count_table[] = { 1, 2, 2, 2,
+                                                 2, 3, 3, 3,
+                                                 3, 4, 4, 4,
+                                                 4, 5, 5, 5,
+                                                };
+        *slots_per_op = slot_count_table[src_cnt - 1];
+        return *slots_per_op;
 }
 
 #define ADMA_MAX_BYTE_COUNT     (16 * 1024 * 1024)
diff --git a/include/asm-arm/arch-pxa/cm-x270.h b/include/asm-arm/arch-pxa/cm-x270.h
deleted file mode 100644
index f8fac9e18009..000000000000
--- a/include/asm-arm/arch-pxa/cm-x270.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * linux/include/asm/arch-pxa/cm-x270.h
- *
- * Copyright Compulab Ltd., 2003, 2007
- * Mike Rapoport <mike@compulab.co.il>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-
-/* CM-x270 device physical addresses */
-#define CMX270_CS1_PHYS         (PXA_CS1_PHYS)
-#define MARATHON_PHYS           (PXA_CS2_PHYS)
-#define CMX270_IDE104_PHYS      (PXA_CS3_PHYS)
-#define CMX270_IT8152_PHYS      (PXA_CS4_PHYS)
-
-/* Statically mapped regions */
-#define CMX270_VIRT_BASE                (0xe8000000)
-#define CMX270_IT8152_VIRT              (CMX270_VIRT_BASE)
-#define CMX270_IDE104_VIRT              (CMX270_IT8152_VIRT + SZ_64M)
-
-/* GPIO related definitions */
-#define GPIO_IT8152_IRQ                 (22)
-
-#define IRQ_GPIO_IT8152_IRQ     IRQ_GPIO(GPIO_IT8152_IRQ)
-#define PME_IRQ                 IRQ_GPIO(0)
-#define CMX270_IDE_IRQ          IRQ_GPIO(100)
-#define CMX270_GPIRQ1           IRQ_GPIO(101)
-#define CMX270_TOUCHIRQ         IRQ_GPIO(96)
-#define CMX270_ETHIRQ           IRQ_GPIO(10)
-#define CMX270_GFXIRQ           IRQ_GPIO(95)
-#define CMX270_NANDIRQ          IRQ_GPIO(89)
-#define CMX270_MMC_IRQ          IRQ_GPIO(83)
-
-/* PCMCIA related definitions */
-#define PCC_DETECT(x)   (GPLR(84 - (x)) & GPIO_bit(84 - (x)))
-#define PCC_READY(x)    (GPLR(82 - (x)) & GPIO_bit(82 - (x)))
-
-#define PCMCIA_S0_CD_VALID              IRQ_GPIO(84)
-#define PCMCIA_S0_CD_VALID_EDGE         GPIO_BOTH_EDGES
-
-#define PCMCIA_S1_CD_VALID              IRQ_GPIO(83)
-#define PCMCIA_S1_CD_VALID_EDGE         GPIO_BOTH_EDGES
-
-#define PCMCIA_S0_RDYINT                IRQ_GPIO(82)
-#define PCMCIA_S1_RDYINT                IRQ_GPIO(81)
-
-#define PCMCIA_RESET_GPIO               53
diff --git a/include/asm-arm/arch-pxa/eseries-gpio.h b/include/asm-arm/arch-pxa/eseries-gpio.h
new file mode 100644
index 000000000000..4c90b1310270
--- /dev/null
+++ b/include/asm-arm/arch-pxa/eseries-gpio.h
@@ -0,0 +1,50 @@
+/*
+ *  eseries-gpio.h
+ *
+ *  Copyright (C) Ian Molton <spyro@f2s.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+
+/* e-series power button */
+#define GPIO_ESERIES_POWERBTN     0
+
+/* UDC GPIO definitions */
+#define GPIO_E7XX_USB_DISC       13
+#define GPIO_E7XX_USB_PULLUP      3
+
+#define GPIO_E800_USB_DISC        4
+#define GPIO_E800_USB_PULLUP     84
+
+/* e740 PCMCIA GPIO definitions */
+/* Note: PWR1 seems to be inverted */
+#define GPIO_E740_PCMCIA_CD0      8
+#define GPIO_E740_PCMCIA_CD1     44
+#define GPIO_E740_PCMCIA_RDY0    11
+#define GPIO_E740_PCMCIA_RDY1     6
+#define GPIO_E740_PCMCIA_RST0    27
+#define GPIO_E740_PCMCIA_RST1    24
+#define GPIO_E740_PCMCIA_PWR0    20
+#define GPIO_E740_PCMCIA_PWR1    23
+
+/* e750 PCMCIA GPIO definitions */
+#define GPIO_E750_PCMCIA_CD0      8
+#define GPIO_E750_PCMCIA_RDY0    12
+#define GPIO_E750_PCMCIA_RST0    27
+#define GPIO_E750_PCMCIA_PWR0    20
+
+/* e800 PCMCIA GPIO definitions */
+#define GPIO_E800_PCMCIA_RST0    69
+#define GPIO_E800_PCMCIA_RST1    72
+#define GPIO_E800_PCMCIA_PWR0    20
+#define GPIO_E800_PCMCIA_PWR1    73
+
+/* e7xx IrDA power control */
+#define GPIO_E7XX_IR_ON          38
+
+/* ASIC related GPIOs */
+#define GPIO_ESERIES_TMIO_IRQ        5
+#define GPIO_E800_ANGELX_IRQ      8
diff --git a/include/asm-arm/arch-pxa/eseries-irq.h b/include/asm-arm/arch-pxa/eseries-irq.h
new file mode 100644
index 000000000000..f2a93d5e31d3
--- /dev/null
+++ b/include/asm-arm/arch-pxa/eseries-irq.h
@@ -0,0 +1,27 @@
+/*
+ *  eseries-irq.h
+ *
+ *  Copyright (C) Ian Molton <spyro@f2s.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+
+#define ANGELX_IRQ_BASE (IRQ_BOARD_START+8)
+#define IRQ_ANGELX(n) (ANGELX_IRQ_BASE + (n))
+
+#define ANGELX_RDY0_IRQ IRQ_ANGELX(0)
+#define ANGELX_ST0_IRQ  IRQ_ANGELX(1)
+#define ANGELX_CD0_IRQ  IRQ_ANGELX(2)
+#define ANGELX_RDY1_IRQ IRQ_ANGELX(3)
+#define ANGELX_ST1_IRQ  IRQ_ANGELX(4)
+#define ANGELX_CD1_IRQ  IRQ_ANGELX(5)
+
+#define TMIO_IRQ_BASE (IRQ_BOARD_START+0)
+#define IRQ_TMIO(n) (TMIO_IRQ_BASE + (n))
+
+#define TMIO_SD_IRQ     IRQ_TMIO(1)
+#define TMIO_USB_IRQ    IRQ_TMIO(2)
+
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index d9af6dabc899..979a45695d7d 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -69,6 +69,12 @@
                 _id == 0x212;                           \
         })
 
+#define __cpu_is_pxa255(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                _id == 0x2d0;                           \
+         })
+
 #define __cpu_is_pxa25x(id)                             \
         ({                                              \
                 unsigned int _id = (id) >> 4 & 0xfff;   \
@@ -76,6 +82,7 @@
         })
 #else
 #define __cpu_is_pxa21x(id)     (0)
+#define __cpu_is_pxa255(id)     (0)
 #define __cpu_is_pxa25x(id)     (0)
 #endif
 
@@ -119,11 +126,26 @@
 #define __cpu_is_pxa320(id)     (0)
 #endif
 
+#ifdef CONFIG_CPU_PXA930
+#define __cpu_is_pxa930(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                _id == 0x683;           \
+         })
+#else
+#define __cpu_is_pxa930(id)     (0)
+#endif
+
 #define cpu_is_pxa21x()                                 \
         ({                                              \
                 __cpu_is_pxa21x(read_cpuid_id());       \
         })
 
+#define cpu_is_pxa255()                                 \
+        ({                                              \
+                __cpu_is_pxa255(read_cpuid_id());       \
+        })
+
 #define cpu_is_pxa25x()                                 \
         ({                                              \
                 __cpu_is_pxa25x(read_cpuid_id());       \
@@ -149,6 +171,12 @@
                 __cpu_is_pxa320(read_cpuid_id());       \
          })
 
+#define cpu_is_pxa930()                                 \
+        ({                                              \
+                unsigned int id = read_cpuid(CPUID_ID); \
+                __cpu_is_pxa930(id);                    \
+         })
+
 /*
  * CPUID Core Generation Bit
  * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
@@ -196,6 +224,11 @@ extern void pxa_gpio_set_value(unsigned gpio, int value);
  */
 extern unsigned int get_memclk_frequency_10khz(void);
 
+/*
+ * register GPIO as reset generator
+ */
+extern int init_gpio_reset(int gpio);
+
 #endif
 
 #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index b6c8fe377683..9413121b0ed9 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -180,10 +180,13 @@
 #define NR_IRQS                 (IRQ_LOCOMO_SPI_TEND + 1)
 #elif defined(CONFIG_ARCH_LUBBOCK) || \
       defined(CONFIG_MACH_LOGICPD_PXA270) || \
+      defined(CONFIG_MACH_TOSA) || \
       defined(CONFIG_MACH_MAINSTONE) || \
       defined(CONFIG_MACH_PCM027) || \
       defined(CONFIG_MACH_MAGICIAN)
 #define NR_IRQS                 (IRQ_BOARD_END)
+#elif defined(CONFIG_MACH_ZYLONITE)
+#define NR_IRQS                 (IRQ_BOARD_START + 32)
 #else
 #define NR_IRQS                 (IRQ_BOARD_START)
 #endif
diff --git a/include/asm-arm/arch-pxa/mfp-pxa2xx.h b/include/asm-arm/arch-pxa/mfp-pxa2xx.h
index db8d890d237c..8de1c0dae624 100644
--- a/include/asm-arm/arch-pxa/mfp-pxa2xx.h
+++ b/include/asm-arm/arch-pxa/mfp-pxa2xx.h
@@ -128,5 +128,6 @@
 #define GPIO84_GPIO     MFP_CFG_IN(GPIO84, AF0)
 
 extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num);
+extern void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm);
 extern int gpio_set_wake(unsigned int gpio, unsigned int on);
 #endif /* __ASM_ARCH_MFP_PXA2XX_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa930.h b/include/asm-arm/arch-pxa/mfp-pxa930.h
new file mode 100644
index 000000000000..c4e945ab1923
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa930.h
@@ -0,0 +1,491 @@
+/*
+ * linux/include/asm-arm/arch-pxa/mfp-pxa930.h
+ *
+ * PXA930 specific MFP configuration definitions
+ *
+ * Copyright (C) 2007-2008 Marvell International Ltd.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MFP_PXA9xx_H
+#define __ASM_ARCH_MFP_PXA9xx_H
+
+#include <asm/arch/mfp.h>
+#include <asm/arch/mfp-pxa3xx.h>
+
+/* GPIO */
+#define GPIO46_GPIO             MFP_CFG(GPIO46, AF0)
+#define GPIO49_GPIO             MFP_CFG(GPIO49, AF0)
+#define GPIO50_GPIO             MFP_CFG(GPIO50, AF0)
+#define GPIO51_GPIO             MFP_CFG(GPIO51, AF0)
+#define GPIO52_GPIO             MFP_CFG(GPIO52, AF0)
+#define GPIO56_GPIO             MFP_CFG(GPIO56, AF0)
+#define GPIO58_GPIO             MFP_CFG(GPIO58, AF0)
+#define GPIO59_GPIO             MFP_CFG(GPIO59, AF0)
+#define GPIO60_GPIO             MFP_CFG(GPIO60, AF0)
+#define GPIO61_GPIO             MFP_CFG(GPIO61, AF0)
+#define GPIO62_GPIO             MFP_CFG(GPIO62, AF0)
+
+#define GSIM_UCLK_GPIO_79       MFP_CFG(GSIM_UCLK, AF0)
+#define GSIM_UIO_GPIO_80        MFP_CFG(GSIM_UIO, AF0)
+#define GSIM_nURST_GPIO_81      MFP_CFG(GSIM_nURST, AF0)
+#define GSIM_UDET_GPIO_82       MFP_CFG(GSIM_UDET, AF0)
+
+#define DF_IO15_GPIO_28         MFP_CFG(DF_IO15, AF0)
+#define DF_IO14_GPIO_29         MFP_CFG(DF_IO14, AF0)
+#define DF_IO13_GPIO_30         MFP_CFG(DF_IO13, AF0)
+#define DF_IO12_GPIO_31         MFP_CFG(DF_IO12, AF0)
+#define DF_IO11_GPIO_32         MFP_CFG(DF_IO11, AF0)
+#define DF_IO10_GPIO_33         MFP_CFG(DF_IO10, AF0)
+#define DF_IO9_GPIO_34          MFP_CFG(DF_IO9, AF0)
+#define DF_IO8_GPIO_35          MFP_CFG(DF_IO8, AF0)
+#define DF_IO7_GPIO_36          MFP_CFG(DF_IO7, AF0)
+#define DF_IO6_GPIO_37          MFP_CFG(DF_IO6, AF0)
+#define DF_IO5_GPIO_38          MFP_CFG(DF_IO5, AF0)
+#define DF_IO4_GPIO_39          MFP_CFG(DF_IO4, AF0)
+#define DF_IO3_GPIO_40          MFP_CFG(DF_IO3, AF0)
+#define DF_IO2_GPIO_41          MFP_CFG(DF_IO2, AF0)
+#define DF_IO1_GPIO_42          MFP_CFG(DF_IO1, AF0)
+#define DF_IO0_GPIO_43          MFP_CFG(DF_IO0, AF0)
+#define DF_nCS0_GPIO_44         MFP_CFG(DF_nCS0, AF0)
+#define DF_nCS1_GPIO_45         MFP_CFG(DF_nCS1, AF0)
+#define DF_nWE_GPIO_46          MFP_CFG(DF_nWE, AF0)
+#define DF_nRE_nOE_GPIO_47      MFP_CFG(DF_nRE_nOE, AF0)
+#define DF_CLE_nOE_GPIO_48      MFP_CFG(DF_CLE_nOE, AF0)
+#define DF_nADV1_ALE_GPIO_49    MFP_CFG(DF_nADV1_ALE, AF0)
+#define DF_nADV2_ALE_GPIO_50    MFP_CFG(DF_nADV2_ALE, AF0)
+#define DF_INT_RnB_GPIO_51      MFP_CFG(DF_INT_RnB, AF0)
+#define DF_SCLK_E_GPIO_52       MFP_CFG(DF_SCLK_E, AF0)
+
+#define DF_ADDR0_GPIO_53        MFP_CFG(DF_ADDR0, AF0)
+#define DF_ADDR1_GPIO_54        MFP_CFG(DF_ADDR1, AF0)
+#define DF_ADDR2_GPIO_55        MFP_CFG(DF_ADDR2, AF0)
+#define DF_ADDR3_GPIO_56        MFP_CFG(DF_ADDR3, AF0)
+#define nXCVREN_GPIO_57         MFP_CFG(nXCVREN, AF0)
+#define nLUA_GPIO_58            MFP_CFG(nLUA, AF0)
+#define nLLA_GPIO_59            MFP_CFG(nLLA, AF0)
+#define nBE0_GPIO_60            MFP_CFG(nBE0, AF0)
+#define nBE1_GPIO_61            MFP_CFG(nBE1, AF0)
+#define RDY_GPIO_62             MFP_CFG(RDY, AF0)
+
+/* Chip Select */
+#define DF_nCS0_nCS2            MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH)
+#define DF_nCS1_nCS3            MFP_CFG_LPM(DF_nCS1, AF3, PULL_HIGH)
+
+/* AC97 */
+#define GPIO83_BAC97_SYSCLK     MFP_CFG(GPIO83, AF3)
+#define GPIO84_BAC97_SDATA_IN0  MFP_CFG(GPIO84, AF3)
+#define GPIO85_BAC97_BITCLK     MFP_CFG(GPIO85, AF3)
+#define GPIO86_BAC97_nRESET     MFP_CFG(GPIO86, AF3)
+#define GPIO87_BAC97_SYNC       MFP_CFG(GPIO87, AF3)
+#define GPIO88_BAC97_SDATA_OUT  MFP_CFG(GPIO88, AF3)
+
+/* I2C */
+#define GPIO39_CI2C_SCL         MFP_CFG_LPM(GPIO39, AF3, PULL_HIGH)
+#define GPIO40_CI2C_SDA         MFP_CFG_LPM(GPIO40, AF3, PULL_HIGH)
+
+#define GPIO51_CI2C_SCL         MFP_CFG_LPM(GPIO51, AF3, PULL_HIGH)
+#define GPIO52_CI2C_SDA         MFP_CFG_LPM(GPIO52, AF3, PULL_HIGH)
+
+#define GPIO63_CI2C_SCL         MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH)
+#define GPIO64_CI2C_SDA         MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH)
+
+#define GPIO77_CI2C_SCL         MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH)
+#define GPIO78_CI2C_SDA         MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH)
+
+#define GPIO89_CI2C_SCL         MFP_CFG_LPM(GPIO89, AF1, PULL_HIGH)
+#define GPIO90_CI2C_SDA         MFP_CFG_LPM(GPIO90, AF1, PULL_HIGH)
+
+#define GPIO95_CI2C_SCL         MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
+#define GPIO96_CI2C_SDA         MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
+
+#define GPIO97_CI2C_SCL         MFP_CFG_LPM(GPIO97, AF3, PULL_HIGH)
+#define GPIO98_CI2C_SDA         MFP_CFG_LPM(GPIO98, AF3, PULL_HIGH)
+
+/* QCI */
+#define GPIO63_CI_DD_9          MFP_CFG_LPM(GPIO63, AF1, PULL_LOW)
+#define GPIO64_CI_DD_8          MFP_CFG_LPM(GPIO64, AF1, PULL_LOW)
+#define GPIO65_CI_DD_7          MFP_CFG_LPM(GPIO65, AF1, PULL_LOW)
+#define GPIO66_CI_DD_6          MFP_CFG_LPM(GPIO66, AF1, PULL_LOW)
+#define GPIO67_CI_DD_5          MFP_CFG_LPM(GPIO67, AF1, PULL_LOW)
+#define GPIO68_CI_DD_4          MFP_CFG_LPM(GPIO68, AF1, PULL_LOW)
+#define GPIO69_CI_DD_3          MFP_CFG_LPM(GPIO69, AF1, PULL_LOW)
+#define GPIO70_CI_DD_2          MFP_CFG_LPM(GPIO70, AF1, PULL_LOW)
+#define GPIO71_CI_DD_1          MFP_CFG_LPM(GPIO71, AF1, PULL_LOW)
+#define GPIO72_CI_DD_0          MFP_CFG_LPM(GPIO72, AF1, PULL_LOW)
+#define GPIO73_CI_HSYNC         MFP_CFG_LPM(GPIO73, AF1, PULL_LOW)
+#define GPIO74_CI_VSYNC         MFP_CFG_LPM(GPIO74, AF1, PULL_LOW)
+#define GPIO75_CI_MCLK          MFP_CFG_LPM(GPIO75, AF1, PULL_LOW)
+#define GPIO76_CI_PCLK          MFP_CFG_LPM(GPIO76, AF1, PULL_LOW)
+
+/* KEYPAD */
+#define GPIO4_KP_DKIN_4         MFP_CFG_LPM(GPIO4, AF3, FLOAT)
+#define GPIO5_KP_DKIN_5         MFP_CFG_LPM(GPIO5, AF3, FLOAT)
+#define GPIO6_KP_DKIN_6         MFP_CFG_LPM(GPIO6, AF3, FLOAT)
+#define GPIO7_KP_DKIN_7         MFP_CFG_LPM(GPIO7, AF3, FLOAT)
+#define GPIO8_KP_DKIN_4         MFP_CFG_LPM(GPIO8, AF3, FLOAT)
+#define GPIO9_KP_DKIN_5         MFP_CFG_LPM(GPIO9, AF3, FLOAT)
+#define GPIO10_KP_DKIN_6        MFP_CFG_LPM(GPIO10, AF3, FLOAT)
+#define GPIO11_KP_DKIN_7        MFP_CFG_LPM(GPIO11, AF3, FLOAT)
+
+#define GPIO12_KP_DKIN_0        MFP_CFG_LPM(GPIO12, AF2, FLOAT)
+#define GPIO13_KP_DKIN_1        MFP_CFG_LPM(GPIO13, AF2, FLOAT)
+#define GPIO14_KP_DKIN_2        MFP_CFG_LPM(GPIO14, AF2, FLOAT)
+#define GPIO15_KP_DKIN_3        MFP_CFG_LPM(GPIO15, AF2, FLOAT)
+
+#define GPIO41_KP_DKIN_0        MFP_CFG_LPM(GPIO41, AF2, FLOAT)
+#define GPIO42_KP_DKIN_1        MFP_CFG_LPM(GPIO42, AF2, FLOAT)
+#define GPIO43_KP_DKIN_2        MFP_CFG_LPM(GPIO43, AF2, FLOAT)
+#define GPIO44_KP_DKIN_3        MFP_CFG_LPM(GPIO44, AF2, FLOAT)
+#define GPIO41_KP_DKIN_4        MFP_CFG_LPM(GPIO41, AF4, FLOAT)
+#define GPIO42_KP_DKIN_5        MFP_CFG_LPM(GPIO42, AF4, FLOAT)
+
+#define GPIO0_KP_MKIN_0         MFP_CFG_LPM(GPIO0, AF1, FLOAT)
+#define GPIO2_KP_MKIN_1         MFP_CFG_LPM(GPIO2, AF1, FLOAT)
+#define GPIO4_KP_MKIN_2         MFP_CFG_LPM(GPIO4, AF1, FLOAT)
+#define GPIO6_KP_MKIN_3         MFP_CFG_LPM(GPIO6, AF1, FLOAT)
+#define GPIO8_KP_MKIN_4         MFP_CFG_LPM(GPIO8, AF1, FLOAT)
+#define GPIO10_KP_MKIN_5        MFP_CFG_LPM(GPIO10, AF1, FLOAT)
+#define GPIO12_KP_MKIN_6        MFP_CFG_LPM(GPIO12, AF1, FLOAT)
+#define GPIO14_KP_MKIN_7        MFP_CFG(GPIO14, AF1)
+#define GPIO35_KP_MKIN_5        MFP_CFG(GPIO35, AF4)
+
+#define GPIO1_KP_MKOUT_0        MFP_CFG_LPM(GPIO1, AF1, DRIVE_HIGH)
+#define GPIO3_KP_MKOUT_1        MFP_CFG_LPM(GPIO3, AF1, DRIVE_HIGH)
+#define GPIO5_KP_MKOUT_2        MFP_CFG_LPM(GPIO5, AF1, DRIVE_HIGH)
+#define GPIO7_KP_MKOUT_3        MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH)
+#define GPIO9_KP_MKOUT_4        MFP_CFG_LPM(GPIO9, AF1, DRIVE_HIGH)
+#define GPIO11_KP_MKOUT_5       MFP_CFG_LPM(GPIO11, AF1, DRIVE_HIGH)
+#define GPIO13_KP_MKOUT_6       MFP_CFG_LPM(GPIO13, AF1, DRIVE_HIGH)
+#define GPIO15_KP_MKOUT_7       MFP_CFG_LPM(GPIO15, AF1, DRIVE_HIGH)
+#define GPIO36_KP_MKOUT_5       MFP_CFG_LPM(GPIO36, AF4, DRIVE_HIGH)
+
+/* LCD */
+#define GPIO17_LCD_FCLK_RD      MFP_CFG(GPIO17, AF1)
+#define GPIO18_LCD_LCLK_A0      MFP_CFG(GPIO18, AF1)
+#define GPIO19_LCD_PCLK_WR      MFP_CFG(GPIO19, AF1)
+#define GPIO20_LCD_BIAS         MFP_CFG(GPIO20, AF1)
+#define GPIO21_LCD_CS           MFP_CFG(GPIO21, AF1)
+#define GPIO22_LCD_CS2          MFP_CFG(GPIO22, AF2)
+#define GPIO22_LCD_VSYNC        MFP_CFG(GPIO22, AF1)
+#define GPIO23_LCD_DD0          MFP_CFG(GPIO23, AF1)
+#define GPIO24_LCD_DD1          MFP_CFG(GPIO24, AF1)
+#define GPIO25_LCD_DD2          MFP_CFG(GPIO25, AF1)
+#define GPIO26_LCD_DD3          MFP_CFG(GPIO26, AF1)
+#define GPIO27_LCD_DD4          MFP_CFG(GPIO27, AF1)
+#define GPIO28_LCD_DD5          MFP_CFG(GPIO28, AF1)
+#define GPIO29_LCD_DD6          MFP_CFG(GPIO29, AF1)
+#define GPIO30_LCD_DD7          MFP_CFG(GPIO30, AF1)
+#define GPIO31_LCD_DD8          MFP_CFG(GPIO31, AF1)
+#define GPIO32_LCD_DD9          MFP_CFG(GPIO32, AF1)
+#define GPIO33_LCD_DD10         MFP_CFG(GPIO33, AF1)
+#define GPIO34_LCD_DD11         MFP_CFG(GPIO34, AF1)
+#define GPIO35_LCD_DD12         MFP_CFG(GPIO35, AF1)
+#define GPIO36_LCD_DD13         MFP_CFG(GPIO36, AF1)
+#define GPIO37_LCD_DD14         MFP_CFG(GPIO37, AF1)
+#define GPIO38_LCD_DD15         MFP_CFG(GPIO38, AF1)
+#define GPIO39_LCD_DD16         MFP_CFG(GPIO39, AF1)
+#define GPIO40_LCD_DD17         MFP_CFG(GPIO40, AF1)
+#define GPIO41_LCD_CS2          MFP_CFG(GPIO41, AF3)
+#define GPIO42_LCD_VSYNC2       MFP_CFG(GPIO42, AF3)
+#define GPIO44_LCD_DD7          MFP_CFG(GPIO44, AF1)
+
+/* Mini-LCD */
+#define GPIO17_MLCD_FCLK        MFP_CFG(GPIO17, AF3)
+#define GPIO18_MLCD_LCLK        MFP_CFG(GPIO18, AF3)
+#define GPIO19_MLCD_PCLK        MFP_CFG(GPIO19, AF3)
+#define GPIO20_MLCD_BIAS        MFP_CFG(GPIO20, AF3)
+#define GPIO23_MLCD_DD0         MFP_CFG(GPIO23, AF3)
+#define GPIO24_MLCD_DD1         MFP_CFG(GPIO24, AF3)
+#define GPIO25_MLCD_DD2         MFP_CFG(GPIO25, AF3)
+#define GPIO26_MLCD_DD3         MFP_CFG(GPIO26, AF3)
+#define GPIO27_MLCD_DD4         MFP_CFG(GPIO27, AF3)
+#define GPIO28_MLCD_DD5         MFP_CFG(GPIO28, AF3)
+#define GPIO29_MLCD_DD6         MFP_CFG(GPIO29, AF3)
+#define GPIO30_MLCD_DD7         MFP_CFG(GPIO30, AF3)
+#define GPIO31_MLCD_DD8         MFP_CFG(GPIO31, AF3)
+#define GPIO32_MLCD_DD9         MFP_CFG(GPIO32, AF3)
+#define GPIO33_MLCD_DD10        MFP_CFG(GPIO33, AF3)
+#define GPIO34_MLCD_DD11        MFP_CFG(GPIO34, AF3)
+#define GPIO35_MLCD_DD12        MFP_CFG(GPIO35, AF3)
+#define GPIO36_MLCD_DD13        MFP_CFG(GPIO36, AF3)
+#define GPIO37_MLCD_DD14        MFP_CFG(GPIO37, AF3)
+#define GPIO38_MLCD_DD15        MFP_CFG(GPIO38, AF3)
+#define GPIO44_MLCD_DD7         MFP_CFG(GPIO44, AF5)
+
+/* MMC1 */
+#define GPIO10_MMC1_DAT3        MFP_CFG(GPIO10, AF4)
+#define GPIO11_MMC1_DAT2        MFP_CFG(GPIO11, AF4)
+#define GPIO12_MMC1_DAT1        MFP_CFG(GPIO12, AF4)
+#define GPIO13_MMC1_DAT0        MFP_CFG(GPIO13, AF4)
+#define GPIO14_MMC1_CMD         MFP_CFG(GPIO14, AF4)
+#define GPIO15_MMC1_CLK         MFP_CFG(GPIO15, AF4)
+#define GPIO55_MMC1_CMD         MFP_CFG(GPIO55, AF3)
+#define GPIO56_MMC1_CLK         MFP_CFG(GPIO56, AF3)
+#define GPIO57_MMC1_DAT0        MFP_CFG(GPIO57, AF3)
+#define GPIO58_MMC1_DAT1        MFP_CFG(GPIO58, AF3)
+#define GPIO59_MMC1_DAT2        MFP_CFG(GPIO59, AF3)
+#define GPIO60_MMC1_DAT3        MFP_CFG(GPIO60, AF3)
+
+#define DF_ADDR0_MMC1_CLK       MFP_CFG(DF_ADDR0, AF2)
+#define DF_ADDR1_MMC1_CMD       MFP_CFG(DF_ADDR1, AF2)
+#define DF_ADDR2_MMC1_DAT0      MFP_CFG(DF_ADDR2, AF2)
+#define DF_ADDR3_MMC1_DAT1      MFP_CFG(DF_ADDR3, AF3)
+#define nXCVREN_MMC1_DAT2       MFP_CFG(nXCVREN, AF2)
+
+/* MMC2 */
+#define GPIO31_MMC2_CMD         MFP_CFG(GPIO31, AF7)
+#define GPIO32_MMC2_CLK         MFP_CFG(GPIO32, AF7)
+#define GPIO33_MMC2_DAT0        MFP_CFG(GPIO33, AF7)
+#define GPIO34_MMC2_DAT1        MFP_CFG(GPIO34, AF7)
+#define GPIO35_MMC2_DAT2        MFP_CFG(GPIO35, AF7)
+#define GPIO36_MMC2_DAT3        MFP_CFG(GPIO36, AF7)
+
+#define GPIO101_MMC2_DAT3       MFP_CFG(GPIO101, AF1)
+#define GPIO102_MMC2_DAT2       MFP_CFG(GPIO102, AF1)
+#define GPIO103_MMC2_DAT1       MFP_CFG(GPIO103, AF1)
+#define GPIO104_MMC2_DAT0       MFP_CFG(GPIO104, AF1)
+#define GPIO105_MMC2_CMD        MFP_CFG(GPIO105, AF1)
+#define GPIO106_MMC2_CLK        MFP_CFG(GPIO106, AF1)
+
+#define DF_IO10_MMC2_DAT3       MFP_CFG(DF_IO10, AF3)
+#define DF_IO11_MMC2_DAT2       MFP_CFG(DF_IO11, AF3)
+#define DF_IO12_MMC2_DAT1       MFP_CFG(DF_IO12, AF3)
+#define DF_IO13_MMC2_DAT0       MFP_CFG(DF_IO13, AF3)
+#define DF_IO14_MMC2_CLK        MFP_CFG(DF_IO14, AF3)
+#define DF_IO15_MMC2_CMD        MFP_CFG(DF_IO15, AF3)
+
+/* BSSP1 */
+#define GPIO12_BSSP1_CLK        MFP_CFG(GPIO12, AF3)
+#define GPIO13_BSSP1_FRM        MFP_CFG(GPIO13, AF3)
+#define GPIO14_BSSP1_RXD        MFP_CFG(GPIO14, AF3)
+#define GPIO15_BSSP1_TXD        MFP_CFG(GPIO15, AF3)
+#define GPIO97_BSSP1_CLK        MFP_CFG(GPIO97, AF5)
+#define GPIO98_BSSP1_FRM        MFP_CFG(GPIO98, AF5)
+
+/* BSSP2 */
+#define GPIO84_BSSP2_SDATA_IN   MFP_CFG(GPIO84, AF1)
+#define GPIO85_BSSP2_BITCLK     MFP_CFG(GPIO85, AF1)
+#define GPIO86_BSSP2_SYSCLK     MFP_CFG(GPIO86, AF1)
+#define GPIO87_BSSP2_SYNC       MFP_CFG(GPIO87, AF1)
+#define GPIO88_BSSP2_DATA_OUT   MFP_CFG(GPIO88, AF1)
+#define GPIO86_BSSP2_SDATA_IN   MFP_CFG(GPIO86, AF4)
+
+/* BSSP3 */
+#define GPIO79_BSSP3_CLK        MFP_CFG(GPIO79, AF1)
+#define GPIO80_BSSP3_FRM        MFP_CFG(GPIO80, AF1)
+#define GPIO81_BSSP3_TXD        MFP_CFG(GPIO81, AF1)
+#define GPIO82_BSSP3_RXD        MFP_CFG(GPIO82, AF1)
+#define GPIO83_BSSP3_SYSCLK     MFP_CFG(GPIO83, AF1)
+
+/* BSSP4 */
+#define GPIO43_BSSP4_CLK        MFP_CFG(GPIO43, AF4)
+#define GPIO44_BSSP4_FRM        MFP_CFG(GPIO44, AF4)
+#define GPIO45_BSSP4_TXD        MFP_CFG(GPIO45, AF4)
+#define GPIO46_BSSP4_RXD        MFP_CFG(GPIO46, AF4)
+
+#define GPIO51_BSSP4_CLK        MFP_CFG(GPIO51, AF4)
+#define GPIO52_BSSP4_FRM        MFP_CFG(GPIO52, AF4)
+#define GPIO53_BSSP4_TXD        MFP_CFG(GPIO53, AF4)
+#define GPIO54_BSSP4_RXD        MFP_CFG(GPIO54, AF4)
+
+/* GSSP1 */
+#define GPIO79_GSSP1_CLK        MFP_CFG(GPIO79, AF2)
+#define GPIO80_GSSP1_FRM        MFP_CFG(GPIO80, AF2)
+#define GPIO81_GSSP1_TXD        MFP_CFG(GPIO81, AF2)
+#define GPIO82_GSSP1_RXD        MFP_CFG(GPIO82, AF2)
+#define GPIO83_GSSP1_SYSCLK     MFP_CFG(GPIO83, AF2)
+
+#define GPIO93_GSSP1_CLK        MFP_CFG(GPIO93, AF4)
+#define GPIO94_GSSP1_FRM        MFP_CFG(GPIO94, AF4)
+#define GPIO95_GSSP1_TXD        MFP_CFG(GPIO95, AF4)
+#define GPIO96_GSSP1_RXD        MFP_CFG(GPIO96, AF4)
+
+/* GSSP2 */
+#define GPIO47_GSSP2_CLK        MFP_CFG(GPIO47, AF4)
+#define GPIO48_GSSP2_FRM        MFP_CFG(GPIO48, AF4)
+#define GPIO49_GSSP2_RXD        MFP_CFG(GPIO49, AF4)
+#define GPIO50_GSSP2_TXD        MFP_CFG(GPIO50, AF4)
+
+#define GPIO69_GSSP2_CLK        MFP_CFG(GPIO69, AF4)
+#define GPIO70_GSSP2_FRM        MFP_CFG(GPIO70, AF4)
+#define GPIO71_GSSP2_RXD        MFP_CFG(GPIO71, AF4)
+#define GPIO72_GSSP2_TXD        MFP_CFG(GPIO72, AF4)
+
+#define GPIO84_GSSP2_RXD        MFP_CFG(GPIO84, AF2)
+#define GPIO85_GSSP2_CLK        MFP_CFG(GPIO85, AF2)
+#define GPIO86_GSSP2_SYSCLK     MFP_CFG(GPIO86, AF2)
+#define GPIO87_GSSP2_FRM        MFP_CFG(GPIO87, AF2)
+#define GPIO88_GSSP2_TXD        MFP_CFG(GPIO88, AF2)
+#define GPIO86_GSSP2_RXD        MFP_CFG(GPIO86, AF5)
+
+#define GPIO103_GSSP2_CLK       MFP_CFG(GPIO103, AF2)
+#define GPIO104_GSSP2_FRM       MFP_CFG(GPIO104, AF2)
+#define GPIO105_GSSP2_RXD       MFP_CFG(GPIO105, AF2)
+#define GPIO106_GSSP2_TXD       MFP_CFG(GPIO106, AF2)
+
+/* UART1 - FFUART */
+#define GPIO47_UART1_DSR_N      MFP_CFG(GPIO47, AF1)
+#define GPIO48_UART1_DTR_N      MFP_CFG(GPIO48, AF1)
+#define GPIO49_UART1_RI         MFP_CFG(GPIO49, AF1)
+#define GPIO50_UART1_DCD        MFP_CFG(GPIO50, AF1)
+#define GPIO51_UART1_CTS        MFP_CFG(GPIO51, AF1)
+#define GPIO52_UART1_RTS        MFP_CFG(GPIO52, AF1)
+#define GPIO53_UART1_RXD        MFP_CFG(GPIO53, AF1)
+#define GPIO54_UART1_TXD        MFP_CFG(GPIO54, AF1)
+
+#define GPIO63_UART1_TXD        MFP_CFG(GPIO63, AF2)
+#define GPIO64_UART1_RXD        MFP_CFG(GPIO64, AF2)
+#define GPIO65_UART1_DSR        MFP_CFG(GPIO65, AF2)
+#define GPIO66_UART1_DTR        MFP_CFG(GPIO66, AF2)
+#define GPIO67_UART1_RI         MFP_CFG(GPIO67, AF2)
+#define GPIO68_UART1_DCD        MFP_CFG(GPIO68, AF2)
+#define GPIO69_UART1_CTS        MFP_CFG(GPIO69, AF2)
+#define GPIO70_UART1_RTS        MFP_CFG(GPIO70, AF2)
+
+/* UART2 - BTUART */
+#define GPIO91_UART2_RXD        MFP_CFG(GPIO91, AF1)
+#define GPIO92_UART2_TXD        MFP_CFG(GPIO92, AF1)
+#define GPIO93_UART2_CTS        MFP_CFG(GPIO93, AF1)
+#define GPIO94_UART2_RTS        MFP_CFG(GPIO94, AF1)
+
+/* UART3 - STUART */
+#define GPIO43_UART3_RTS        MFP_CFG(GPIO43, AF3)
+#define GPIO44_UART3_CTS        MFP_CFG(GPIO44, AF3)
+#define GPIO45_UART3_RXD        MFP_CFG(GPIO45, AF3)
+#define GPIO46_UART3_TXD        MFP_CFG(GPIO46, AF3)
+
+#define GPIO75_UART3_RTS        MFP_CFG(GPIO75, AF5)
+#define GPIO76_UART3_CTS        MFP_CFG(GPIO76, AF5)
+#define GPIO77_UART3_TXD        MFP_CFG(GPIO77, AF5)
+#define GPIO78_UART3_RXD        MFP_CFG(GPIO78, AF5)
+
+/* DFI */
+#define DF_IO0_DF_IO0           MFP_CFG(DF_IO0, AF2)
+#define DF_IO1_DF_IO1           MFP_CFG(DF_IO1, AF2)
+#define DF_IO2_DF_IO2           MFP_CFG(DF_IO2, AF2)
+#define DF_IO3_DF_IO3           MFP_CFG(DF_IO3, AF2)
+#define DF_IO4_DF_IO4           MFP_CFG(DF_IO4, AF2)
+#define DF_IO5_DF_IO5           MFP_CFG(DF_IO5, AF2)
+#define DF_IO6_DF_IO6           MFP_CFG(DF_IO6, AF2)
+#define DF_IO7_DF_IO7           MFP_CFG(DF_IO7, AF2)
+#define DF_IO8_DF_IO8           MFP_CFG(DF_IO8, AF2)
+#define DF_IO9_DF_IO9           MFP_CFG(DF_IO9, AF2)
+#define DF_IO10_DF_IO10         MFP_CFG(DF_IO10, AF2)
+#define DF_IO11_DF_IO11         MFP_CFG(DF_IO11, AF2)
+#define DF_IO12_DF_IO12         MFP_CFG(DF_IO12, AF2)
+#define DF_IO13_DF_IO13         MFP_CFG(DF_IO13, AF2)
+#define DF_IO14_DF_IO14         MFP_CFG(DF_IO14, AF2)
+#define DF_IO15_DF_IO15         MFP_CFG(DF_IO15, AF2)
+#define DF_nADV1_ALE_DF_nADV1   MFP_CFG(DF_nADV1_ALE, AF2)
+#define DF_nADV2_ALE_DF_nADV2   MFP_CFG(DF_nADV2_ALE, AF2)
+#define DF_nCS0_DF_nCS0         MFP_CFG(DF_nCS0, AF2)
+#define DF_nCS1_DF_nCS1         MFP_CFG(DF_nCS1, AF2)
+#define DF_nRE_nOE_DF_nOE       MFP_CFG(DF_nRE_nOE, AF2)
+#define DF_nWE_DF_nWE           MFP_CFG(DF_nWE, AF2)
+
+/* DFI - NAND */
+#define DF_CLE_nOE_ND_CLE       MFP_CFG_LPM(DF_CLE_nOE, AF1, PULL_HIGH)
+#define DF_INT_RnB_ND_INT_RnB   MFP_CFG_LPM(DF_INT_RnB, AF1, PULL_LOW)
+#define DF_IO0_ND_IO0           MFP_CFG_LPM(DF_IO0, AF1, PULL_LOW)
+#define DF_IO1_ND_IO1           MFP_CFG_LPM(DF_IO1, AF1, PULL_LOW)
+#define DF_IO2_ND_IO2           MFP_CFG_LPM(DF_IO2, AF1, PULL_LOW)
+#define DF_IO3_ND_IO3           MFP_CFG_LPM(DF_IO3, AF1, PULL_LOW)
+#define DF_IO4_ND_IO4           MFP_CFG_LPM(DF_IO4, AF1, PULL_LOW)
+#define DF_IO5_ND_IO5           MFP_CFG_LPM(DF_IO5, AF1, PULL_LOW)
+#define DF_IO6_ND_IO6           MFP_CFG_LPM(DF_IO6, AF1, PULL_LOW)
+#define DF_IO7_ND_IO7           MFP_CFG_LPM(DF_IO7, AF1, PULL_LOW)
+#define DF_IO8_ND_IO8           MFP_CFG_LPM(DF_IO8, AF1, PULL_LOW)
+#define DF_IO9_ND_IO9           MFP_CFG_LPM(DF_IO9, AF1, PULL_LOW)
+#define DF_IO10_ND_IO10         MFP_CFG_LPM(DF_IO10, AF1, PULL_LOW)
+#define DF_IO11_ND_IO11         MFP_CFG_LPM(DF_IO11, AF1, PULL_LOW)
+#define DF_IO12_ND_IO12         MFP_CFG_LPM(DF_IO12, AF1, PULL_LOW)
+#define DF_IO13_ND_IO13         MFP_CFG_LPM(DF_IO13, AF1, PULL_LOW)
+#define DF_IO14_ND_IO14         MFP_CFG_LPM(DF_IO14, AF1, PULL_LOW)
+#define DF_IO15_ND_IO15         MFP_CFG_LPM(DF_IO15, AF1, PULL_LOW)
+#define DF_nADV1_ALE_ND_ALE     MFP_CFG_LPM(DF_nADV1_ALE, AF1, PULL_HIGH)
+#define DF_nADV2_ALE_ND_ALE     MFP_CFG_LPM(DF_nADV2_ALE, AF1, PULL_HIGH)
+#define DF_nADV2_ALE_nCS3       MFP_CFG_LPM(DF_nADV2_ALE, AF3, PULL_HIGH)
+#define DF_nCS0_ND_nCS0         MFP_CFG_LPM(DF_nCS0, AF1, PULL_HIGH)
+#define DF_nCS1_ND_nCS1         MFP_CFG_LPM(DF_nCS1, AF1, PULL_HIGH)
+#define DF_nRE_nOE_ND_nRE       MFP_CFG_LPM(DF_nRE_nOE, AF1, PULL_HIGH)
+#define DF_nWE_ND_nWE           MFP_CFG_LPM(DF_nWE, AF1, PULL_HIGH)
+
+/* PWM */
+#define GPIO41_PWM0             MFP_CFG_LPM(GPIO41, AF1, PULL_LOW)
+#define GPIO42_PWM1             MFP_CFG_LPM(GPIO42, AF1, PULL_LOW)
+#define GPIO43_PWM3             MFP_CFG_LPM(GPIO43, AF1, PULL_LOW)
+#define GPIO20_PWM0             MFP_CFG_LPM(GPIO20, AF2, PULL_LOW)
+#define GPIO21_PWM2             MFP_CFG_LPM(GPIO21, AF3, PULL_LOW)
+#define GPIO22_PWM3             MFP_CFG_LPM(GPIO22, AF3, PULL_LOW)
+
+/* CIR */
+#define GPIO46_CIR_OUT          MFP_CFG(GPIO46, AF1)
+#define GPIO77_CIR_OUT          MFP_CFG(GPIO77, AF3)
+
+/* USB P2 */
+#define GPIO0_USB_P2_7          MFP_CFG(GPIO0, AF3)
+#define GPIO15_USB_P2_7         MFP_CFG(GPIO15, AF5)
+#define GPIO16_USB_P2_7         MFP_CFG(GPIO16, AF2)
+#define GPIO48_USB_P2_7         MFP_CFG(GPIO48, AF7)
+#define GPIO49_USB_P2_7         MFP_CFG(GPIO49, AF6)
+#define DF_IO9_USB_P2_7         MFP_CFG(DF_IO9, AF3)
+
+#define GPIO48_USB_P2_8         MFP_CFG(GPIO48, AF2)
+#define GPIO50_USB_P2_7         MFP_CFG_X(GPIO50, AF2, DS02X, FLOAT)
+#define GPIO51_USB_P2_5         MFP_CFG(GPIO51, AF2)
+#define GPIO47_USB_P2_4         MFP_CFG(GPIO47, AF2)
+#define GPIO53_USB_P2_3         MFP_CFG(GPIO53, AF2)
+#define GPIO54_USB_P2_6         MFP_CFG(GPIO54, AF2)
+#define GPIO49_USB_P2_2         MFP_CFG(GPIO49, AF2)
+#define GPIO52_USB_P2_1         MFP_CFG(GPIO52, AF2)
+
+#define GPIO63_USB_P2_8         MFP_CFG(GPIO63, AF3)
+#define GPIO64_USB_P2_7         MFP_CFG(GPIO64, AF3)
+#define GPIO65_USB_P2_6         MFP_CFG(GPIO65, AF3)
+#define GPIO66_USG_P2_5         MFP_CFG(GPIO66, AF3)
+#define GPIO67_USB_P2_4         MFP_CFG(GPIO67, AF3)
+#define GPIO68_USB_P2_3         MFP_CFG(GPIO68, AF3)
+#define GPIO69_USB_P2_2         MFP_CFG(GPIO69, AF3)
+#define GPIO70_USB_P2_1         MFP_CFG(GPIO70, AF3)
+
+/* ULPI */
+#define GPIO31_USB_ULPI_D0      MFP_CFG(GPIO31, AF4)
+#define GPIO30_USB_ULPI_D1      MFP_CFG(GPIO30, AF7)
+#define GPIO33_USB_ULPI_D2      MFP_CFG(GPIO33, AF5)
+#define GPIO34_USB_ULPI_D3      MFP_CFG(GPIO34, AF5)
+#define GPIO35_USB_ULPI_D4      MFP_CFG(GPIO35, AF5)
+#define GPIO36_USB_ULPI_D5      MFP_CFG(GPIO36, AF5)
+#define GPIO41_USB_ULPI_D6      MFP_CFG(GPIO41, AF5)
+#define GPIO42_USB_ULPI_D7      MFP_CFG(GPIO42, AF5)
+#define GPIO37_USB_ULPI_DIR     MFP_CFG(GPIO37, AF4)
+#define GPIO38_USB_ULPI_CLK     MFP_CFG(GPIO38, AF4)
+#define GPIO39_USB_ULPI_STP     MFP_CFG(GPIO39, AF4)
+#define GPIO40_USB_ULPI_NXT     MFP_CFG(GPIO40, AF4)
+
+#define GPIO3_CLK26MOUTDMD      MFP_CFG(GPIO3, AF3)
+#define GPIO40_CLK26MOUTDMD     MFP_CFG(GPIO40, AF7)
+#define GPIO94_CLK26MOUTDMD     MFP_CFG(GPIO94, AF5)
+#define GPIO104_CLK26MOUTDMD    MFP_CFG(GPIO104, AF4)
+#define DF_ADDR1_CLK26MOUTDMD   MFP_CFG(DF_ADDR2, AF3)
+#define DF_ADDR3_CLK26MOUTDMD   MFP_CFG(DF_ADDR3, AF3)
+
+#define GPIO14_CLK26MOUT        MFP_CFG(GPIO14, AF5)
+#define GPIO38_CLK26MOUT        MFP_CFG(GPIO38, AF7)
+#define GPIO92_CLK26MOUT        MFP_CFG(GPIO92, AF5)
+#define GPIO105_CLK26MOUT       MFP_CFG(GPIO105, AF4)
+
+#define GPIO2_CLK13MOUTDMD      MFP_CFG(GPIO2, AF3)
+#define GPIO39_CLK13MOUTDMD     MFP_CFG(GPIO39, AF7)
+#define GPIO50_CLK13MOUTDMD     MFP_CFG(GPIO50, AF3)
+#define GPIO93_CLK13MOUTDMD     MFP_CFG(GPIO93, AF5)
+#define GPIO103_CLK13MOUTDMD    MFP_CFG(GPIO103, AF4)
+#define DF_ADDR2_CLK13MOUTDMD   MFP_CFG(DF_ADDR2, AF3)
+
+/* 1 wire */
+#define GPIO95_OW_DQ_IN         MFP_CFG(GPIO95, AF5)
+
+#endif /* __ASM_ARCH_MFP_PXA9xx_H */
diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h
index 02f6157396d3..e7d58798da67 100644
--- a/include/asm-arm/arch-pxa/mfp.h
+++ b/include/asm-arm/arch-pxa/mfp.h
@@ -210,6 +210,14 @@ enum {
         MFP_PIN_DF_IO14,
         MFP_PIN_DF_IO15,
 
+        /* additional pins on PXA930 */
+        MFP_PIN_GSIM_UIO,
+        MFP_PIN_GSIM_UCLK,
+        MFP_PIN_GSIM_UDET,
+        MFP_PIN_GSIM_nURST,
+        MFP_PIN_PMIC_INT,
+        MFP_PIN_RDY,
+
         MFP_PIN_MAX,
 };
 
diff --git a/include/asm-arm/arch-pxa/palmtx.h b/include/asm-arm/arch-pxa/palmtx.h
new file mode 100644
index 000000000000..1e8bccbda510
--- /dev/null
+++ b/include/asm-arm/arch-pxa/palmtx.h
@@ -0,0 +1,106 @@
+/*
+ * GPIOs and interrupts for Palm T|X Handheld Computer
+ *
+ * Based on palmld-gpio.h by Alex Osborne
+ *
+ * Authors:     Marek Vasut <marek.vasut@gmail.com>
+ *              Cristiano P. <cristianop@users.sourceforge.net>
+ *              Jan Herman <2hp@seznam.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _INCLUDE_PALMTX_H_
+#define _INCLUDE_PALMTX_H_
+
+/** HERE ARE GPIOs **/
+
+/* GPIOs */
+#define GPIO_NR_PALMTX_GPIO_RESET               1
+
+#define GPIO_NR_PALMTX_POWER_DETECT             12 /* 90 */
+#define GPIO_NR_PALMTX_HOTSYNC_BUTTON_N         10
+#define GPIO_NR_PALMTX_EARPHONE_DETECT          107
+
+/* SD/MMC */
+#define GPIO_NR_PALMTX_SD_DETECT_N              14
+#define GPIO_NR_PALMTX_SD_POWER                 114 /* probably */
+#define GPIO_NR_PALMTX_SD_READONLY              115 /* probably */
+
+/* TOUCHSCREEN */
+#define GPIO_NR_PALMTX_WM9712_IRQ               27
+
+/* IRDA -  disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
+#define GPIO_NR_PALMTX_IR_DISABLE               40
+
+/* USB */
+#define GPIO_NR_PALMTX_USB_DETECT_N             13
+#define GPIO_NR_PALMTX_USB_POWER                95
+#define GPIO_NR_PALMTX_USB_PULLUP               93
+
+/* LCD/BACKLIGHT */
+#define GPIO_NR_PALMTX_BL_POWER                 84
+#define GPIO_NR_PALMTX_LCD_POWER                96
+
+/* LCD BORDER */
+#define GPIO_NR_PALMTX_BORDER_SWITCH            98
+#define GPIO_NR_PALMTX_BORDER_SELECT            22
+
+/* BLUETOOTH */
+#define GPIO_NR_PALMTX_BT_POWER                 17
+#define GPIO_NR_PALMTX_BT_RESET                 83
+
+/* PCMCIA (WiFi) */
+#define GPIO_NR_PALMTX_PCMCIA_POWER1            94
+#define GPIO_NR_PALMTX_PCMCIA_POWER2            108
+#define GPIO_NR_PALMTX_PCMCIA_RESET             79
+#define GPIO_NR_PALMTX_PCMCIA_READY             116
+
+/* NAND Flash ... this GPIO may be incorrect! */
+#define GPIO_NR_PALMTX_NAND_BUFFER_DIR          79
+
+/* INTERRUPTS */
+#define IRQ_GPIO_PALMTX_SD_DETECT_N     IRQ_GPIO(GPIO_NR_PALMTX_SD_DETECT_N)
+#define IRQ_GPIO_PALMTX_WM9712_IRQ      IRQ_GPIO(GPIO_NR_PALMTX_WM9712_IRQ)
+#define IRQ_GPIO_PALMTX_USB_DETECT      IRQ_GPIO(GPIO_NR_PALMTX_USB_DETECT)
+#define IRQ_GPIO_PALMTX_GPIO_RESET      IRQ_GPIO(GPIO_NR_PALMTX_GPIO_RESET)
+
+/** HERE ARE INIT VALUES **/
+
+/* Various addresses  */
+#define PALMTX_PCMCIA_PHYS      0x28000000
+#define PALMTX_PCMCIA_VIRT      0xf0000000
+#define PALMTX_PCMCIA_SIZE      0x100000
+
+#define PALMTX_PHYS_RAM_START   0xa0000000
+#define PALMTX_PHYS_IO_START    0x40000000
+
+#define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS    /* ChipSelect 0 */
+#define PALMTX_PHYS_NAND_START  PXA_CS1_PHYS    /* ChipSelect 1 */
+
+/* TOUCHSCREEN */
+#define AC97_LINK_FRAME                 21
+
+
+/* BATTERY */
+#define PALMTX_BAT_MAX_VOLTAGE          4000    /* 4.00v current voltage */
+#define PALMTX_BAT_MIN_VOLTAGE          3550    /* 3.55v critical voltage */
+#define PALMTX_BAT_MAX_CURRENT          0       /* unknokn */
+#define PALMTX_BAT_MIN_CURRENT          0       /* unknown */
+#define PALMTX_BAT_MAX_CHARGE           1       /* unknown */
+#define PALMTX_BAT_MIN_CHARGE           1       /* unknown */
+#define PALMTX_MAX_LIFE_MINS            360     /* on-life in minutes */
+
+#define PALMTX_BAT_MEASURE_DELAY        (HZ * 1)
+
+/* BACKLIGHT */
+#define PALMTX_MAX_INTENSITY            0xFE
+#define PALMTX_DEFAULT_INTENSITY        0x7E
+#define PALMTX_LIMIT_MASK               0x7F
+#define PALMTX_PRESCALER                0x3F
+#define PALMTX_PERIOD_NS                3500
+
+#endif
diff --git a/include/asm-arm/arch-pxa/pxa27x-udc.h b/include/asm-arm/arch-pxa/pxa27x-udc.h
index bc1cf7d0773a..ab1443f8bd89 100644
--- a/include/asm-arm/arch-pxa/pxa27x-udc.h
+++ b/include/asm-arm/arch-pxa/pxa27x-udc.h
@@ -97,7 +97,7 @@
 #define UP2OCR_IDON             (1 << 10)       /* OTG ID Read Enable */
 #define UP2OCR_HXS              (1 << 16)       /* Host Port 2 Transceiver Output Select */
 #define UP2OCR_HXOE             (1 << 17)       /* Host Port 2 Transceiver Output Enable */
-#define UP2OCR_SEOS             (1 << 24)       /* Single-Ended Output Select */
+#define UP2OCR_SEOS(x)          ((x & 7) << 24) /* Single-Ended Output Select */
 
 #define UDCCSN(x)       __REG2(0x40600100, (x) << 2)
 #define UDCCSR0         __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
diff --git a/include/asm-arm/arch-pxa/pxa2xx_spi.h b/include/asm-arm/arch-pxa/pxa2xx_spi.h
index 3459fb26ce97..2206cb61a9f9 100644
--- a/include/asm-arm/arch-pxa/pxa2xx_spi.h
+++ b/include/asm-arm/arch-pxa/pxa2xx_spi.h
@@ -41,4 +41,6 @@ struct pxa2xx_spi_chip {
         void (*cs_control)(u32 command);
 };
 
+extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info);
+
 #endif /*PXA2XX_SPI_H_*/
diff --git a/include/asm-arm/arch-pxa/pxa3xx_nand.h b/include/asm-arm/arch-pxa/pxa3xx_nand.h
index 81a8937486cb..eb4b190b6657 100644
--- a/include/asm-arm/arch-pxa/pxa3xx_nand.h
+++ b/include/asm-arm/arch-pxa/pxa3xx_nand.h
@@ -15,4 +15,6 @@ struct pxa3xx_nand_platform_data {
         struct mtd_partition *parts;
         unsigned int    nr_parts;
 };
+
+extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
 #endif /* __ASM_ARCH_PXA3XX_NAND_H */
diff --git a/include/asm-arm/arch-pxa/pxafb.h b/include/asm-arm/arch-pxa/pxafb.h
index bbd22396841a..daf018d0c604 100644
--- a/include/asm-arm/arch-pxa/pxafb.h
+++ b/include/asm-arm/arch-pxa/pxafb.h
@@ -71,7 +71,8 @@ struct pxafb_mode_info {
 
         u_char          bpp;
         u_int           cmap_greyscale:1,
-                        unused:31;
+                        depth:8,
+                        unused:23;
 
         /* Parallel Mode Timing */
         u_char          hsync_len;
diff --git a/include/asm-arm/arch-pxa/regs-lcd.h b/include/asm-arm/arch-pxa/regs-lcd.h
index 3ba464c913a5..820a189684a9 100644
--- a/include/asm-arm/arch-pxa/regs-lcd.h
+++ b/include/asm-arm/arch-pxa/regs-lcd.h
@@ -27,6 +27,12 @@
 #define LCCR3_4BPP      (2 << 24)
 #define LCCR3_8BPP      (3 << 24)
 #define LCCR3_16BPP     (4 << 24)
+#define LCCR3_18BPP     (5 << 24)
+#define LCCR3_18BPP_P   (6 << 24)
+#define LCCR3_19BPP     (7 << 24)
+#define LCCR3_19BPP_P   (1 << 29)
+#define LCCR3_24BPP     ((1 << 29) | (1 << 24))
+#define LCCR3_25BPP     ((1 << 29) | (2 << 24))
 
 #define LCCR3_PDFOR_0   (0 << 30)
 #define LCCR3_PDFOR_1   (1 << 30)
diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h
index 0255328c3c18..3c04cde2cf1f 100644
--- a/include/asm-arm/arch-pxa/regs-ssp.h
+++ b/include/asm-arm/arch-pxa/regs-ssp.h
@@ -20,6 +20,10 @@
 #define SSTSS           (0x38)  /* SSP Timeslot Status */
 #define SSACD           (0x3C)  /* SSP Audio Clock Divider */
 
+#if defined(CONFIG_PXA3xx)
+#define SSACDD          (0x40)  /* SSP Audio Clock Dither Divider */
+#endif
+
 /* Common PXA2xx bits first */
 #define SSCR0_DSS       (0x0000000f)    /* Data Size Select (mask) */
 #define SSCR0_DataSize(x)  ((x) - 1)    /* Data Size Select [4..16] */
@@ -29,10 +33,12 @@
 #define SSCR0_National  (0x2 << 4)      /* National Microwire */
 #define SSCR0_ECS       (1 << 6)        /* External clock select */
 #define SSCR0_SSE       (1 << 7)        /* Synchronous Serial Port Enable */
+
 #if defined(CONFIG_PXA25x)
 #define SSCR0_SCR       (0x0000ff00)    /* Serial Clock Rate (mask) */
 #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
-#elif defined(CONFIG_PXA27x)
+
+#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 #define SSCR0_SCR       (0x000fff00)    /* Serial Clock Rate (mask) */
 #define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
 #define SSCR0_EDSS      (1 << 20)       /* Extended data size select */
@@ -45,6 +51,10 @@
 #define SSCR0_MOD       (1 << 31)       /* Mode (normal or network) */
 #endif
 
+#if defined(CONFIG_PXA3xx)
+#define SSCR0_FPCKE     (1 << 29)       /* FIFO packing enable */
+#endif
+
 #define SSCR1_RIE       (1 << 0)        /* Receive FIFO Interrupt Enable */
 #define SSCR1_TIE       (1 << 1)        /* Transmit FIFO Interrupt Enable */
 #define SSCR1_LBM       (1 << 2)        /* Loop-Back Mode */
@@ -109,5 +119,9 @@
 #define SSACD_SCDB              (1 << 3)        /* SSPSYSCLK Divider Bypass */
 #define SSACD_ACPS(x)           ((x) << 4)      /* Audio clock PLL select */
 #define SSACD_ACDS(x)           ((x) << 0)      /* Audio clock divider select */
+#if defined(CONFIG_PXA3xx)
+#define SSACD_SCDX8             (1 << 7)        /* SYSCLK division ratio select */
+#endif
+
 
 #endif /* __ASM_ARCH_REGS_SSP_H */
diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h
index ba7e132de1b3..6956fc5235f8 100644
--- a/include/asm-arm/arch-pxa/system.h
+++ b/include/asm-arm/arch-pxa/system.h
@@ -21,19 +21,4 @@ static inline void arch_idle(void)
 }
 
 
-static inline void arch_reset(char mode)
-{
-        if (cpu_is_pxa2xx())
-                RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
-
-        if (mode == 's') {
-                /* Jump into ROM at address 0 */
-                cpu_reset(0);
-        } else {
-                /* Initialize the watchdog and let it fire */
-                OWER = OWER_WME;
-                OSSR = OSSR_M3;
-                OSMR3 = OSCR + 368640;  /* ... in 100 ms */
-        }
-}
-
+void arch_reset(char mode);
diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h
index c5b6fde6907c..a72803f0461b 100644
--- a/include/asm-arm/arch-pxa/tosa.h
+++ b/include/asm-arm/arch-pxa/tosa.h
@@ -25,21 +25,18 @@
  */
 #define TOSA_SCOOP_GPIO_BASE            NR_BUILTIN_GPIO
 #define TOSA_SCOOP_PXA_VCORE1           SCOOP_GPCR_PA11
-#define TOSA_SCOOP_TC6393_REST_IN       SCOOP_GPCR_PA12
+#define TOSA_GPIO_TC6393XB_REST_IN      (TOSA_SCOOP_GPIO_BASE + 1)
 #define TOSA_GPIO_IR_POWERDWN           (TOSA_SCOOP_GPIO_BASE + 2)
 #define TOSA_GPIO_SD_WP                 (TOSA_SCOOP_GPIO_BASE + 3)
 #define TOSA_GPIO_PWR_ON                (TOSA_SCOOP_GPIO_BASE + 4)
 #define TOSA_SCOOP_AUD_PWR_ON           SCOOP_GPCR_PA16
-#define TOSA_SCOOP_BT_RESET             SCOOP_GPCR_PA17
-#define TOSA_SCOOP_BT_PWR_EN            SCOOP_GPCR_PA18
+#define TOSA_GPIO_BT_RESET              (TOSA_SCOOP_GPIO_BASE + 6)
+#define TOSA_GPIO_BT_PWR_EN             (TOSA_SCOOP_GPIO_BASE + 7)
 #define TOSA_SCOOP_AC_IN_OL             SCOOP_GPCR_PA19
 
 /* GPIO Direction   1 : output mode / 0:input mode */
-#define TOSA_SCOOP_IO_DIR     ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \
-                TOSA_SCOOP_AUD_PWR_ON |\
-                TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN )
-/* GPIO out put level when init   1: Hi */
-#define TOSA_SCOOP_IO_OUT     ( TOSA_SCOOP_TC6393_REST_IN )
+#define TOSA_SCOOP_IO_DIR     (TOSA_SCOOP_PXA_VCORE1 | \
+                TOSA_SCOOP_AUD_PWR_ON)
 
 /*
  * SCOOP2 jacket GPIOs
@@ -49,16 +46,34 @@
 #define TOSA_GPIO_NOTE_LED              (TOSA_SCOOP_JC_GPIO_BASE + 1)
 #define TOSA_GPIO_CHRG_ERR_LED          (TOSA_SCOOP_JC_GPIO_BASE + 2)
 #define TOSA_GPIO_USB_PULLUP            (TOSA_SCOOP_JC_GPIO_BASE + 3)
-#define TOSA_SCOOP_JC_TC6393_SUSPEND    SCOOP_GPCR_PA15
-#define TOSA_SCOOP_JC_TC3693_L3V_ON     SCOOP_GPCR_PA16
+#define TOSA_GPIO_TC6393XB_SUSPEND      (TOSA_SCOOP_JC_GPIO_BASE + 4)
+#define TOSA_GPIO_TC6393XB_L3V_ON       (TOSA_SCOOP_JC_GPIO_BASE + 5)
 #define TOSA_SCOOP_JC_WLAN_DETECT       SCOOP_GPCR_PA17
 #define TOSA_GPIO_WLAN_LED              (TOSA_SCOOP_JC_GPIO_BASE + 7)
 #define TOSA_SCOOP_JC_CARD_LIMIT_SEL    SCOOP_GPCR_PA19
 
 /* GPIO Direction   1 : output mode / 0:input mode */
-#define TOSA_SCOOP_JC_IO_DIR ( \
-                TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \
-                TOSA_SCOOP_JC_CARD_LIMIT_SEL )
+#define TOSA_SCOOP_JC_IO_DIR (TOSA_SCOOP_JC_CARD_LIMIT_SEL)
+
+/*
+ * TC6393XB GPIOs
+ */
+#define TOSA_TC6393XB_GPIO_BASE         (NR_BUILTIN_GPIO + 2 * 12)
+#define TOSA_TC6393XB_GPIO(i)           (TOSA_TC6393XB_GPIO_BASE + (i))
+#define TOSA_TC6393XB_GPIO_BIT(gpio)    (1 << (gpio - TOSA_TC6393XB_GPIO_BASE))
+
+#define TOSA_GPIO_TG_ON                 (TOSA_TC6393XB_GPIO_BASE + 0)
+#define TOSA_GPIO_L_MUTE                (TOSA_TC6393XB_GPIO_BASE + 1)
+#define TOSA_GPIO_BL_C20MA              (TOSA_TC6393XB_GPIO_BASE + 3)
+#define TOSA_GPIO_CARD_VCC_ON           (TOSA_TC6393XB_GPIO_BASE + 4)
+#define TOSA_GPIO_CHARGE_OFF            (TOSA_TC6393XB_GPIO_BASE + 6)
+#define TOSA_GPIO_CHARGE_OFF_JC         (TOSA_TC6393XB_GPIO_BASE + 7)
+#define TOSA_GPIO_BAT0_V_ON             (TOSA_TC6393XB_GPIO_BASE + 9)
+#define TOSA_GPIO_BAT1_V_ON             (TOSA_TC6393XB_GPIO_BASE + 10)
+#define TOSA_GPIO_BU_CHRG_ON            (TOSA_TC6393XB_GPIO_BASE + 11)
+#define TOSA_GPIO_BAT_SW_ON             (TOSA_TC6393XB_GPIO_BASE + 12)
+#define TOSA_GPIO_BAT0_TH_ON            (TOSA_TC6393XB_GPIO_BASE + 14)
+#define TOSA_GPIO_BAT1_TH_ON            (TOSA_TC6393XB_GPIO_BASE + 15)
 
 /*
  * Timing Generator
@@ -84,13 +99,13 @@
 #define TOSA_GPIO_JACKET_DETECT         (7)
 #define TOSA_GPIO_nSD_DETECT            (9)
 #define TOSA_GPIO_nSD_INT               (10)
-#define TOSA_GPIO_TC6393_CLK            (11)
+#define TOSA_GPIO_TC6393XB_CLK          (11)
 #define TOSA_GPIO_BAT1_CRG              (12)
 #define TOSA_GPIO_CF_CD                 (13)
 #define TOSA_GPIO_BAT0_CRG              (14)
-#define TOSA_GPIO_TC6393_INT            (15)
+#define TOSA_GPIO_TC6393XB_INT          (15)
 #define TOSA_GPIO_BAT0_LOW              (17)
-#define TOSA_GPIO_TC6393_RDY            (18)
+#define TOSA_GPIO_TC6393XB_RDY          (18)
 #define TOSA_GPIO_ON_RESET              (19)
 #define TOSA_GPIO_EAR_IN                (20)
 #define TOSA_GPIO_CF_IRQ                (21)    /* CF slot0 Ready */
@@ -99,6 +114,7 @@
 #define TOSA_GPIO_TP_INT                (32)    /* Touch Panel pen down interrupt */
 #define TOSA_GPIO_JC_CF_IRQ             (36)    /* CF slot1 Ready */
 #define TOSA_GPIO_BAT_LOCKED            (38)    /* Battery locked */
+#define TOSA_GPIO_IRDA_TX               (47)
 #define TOSA_GPIO_TG_SPI_SCLK           (81)
 #define TOSA_GPIO_TG_SPI_CS             (82)
 #define TOSA_GPIO_TG_SPI_MOSI           (83)
@@ -137,7 +153,7 @@
 #define TOSA_IRQ_GPIO_BAT1_CRG          IRQ_GPIO(TOSA_GPIO_BAT1_CRG)
 #define TOSA_IRQ_GPIO_CF_CD             IRQ_GPIO(TOSA_GPIO_CF_CD)
 #define TOSA_IRQ_GPIO_BAT0_CRG          IRQ_GPIO(TOSA_GPIO_BAT0_CRG)
-#define TOSA_IRQ_GPIO_TC6393_INT        IRQ_GPIO(TOSA_GPIO_TC6393_INT)
+#define TOSA_IRQ_GPIO_TC6393XB_INT      IRQ_GPIO(TOSA_GPIO_TC6393XB_INT)
 #define TOSA_IRQ_GPIO_BAT0_LOW          IRQ_GPIO(TOSA_GPIO_BAT0_LOW)
 #define TOSA_IRQ_GPIO_EAR_IN            IRQ_GPIO(TOSA_GPIO_EAR_IN)
 #define TOSA_IRQ_GPIO_CF_IRQ            IRQ_GPIO(TOSA_GPIO_CF_IRQ)
diff --git a/include/asm-arm/arch-pxa/tosa_bt.h b/include/asm-arm/arch-pxa/tosa_bt.h
new file mode 100644
index 000000000000..efc3c3d3b75d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/tosa_bt.h
@@ -0,0 +1,22 @@
+/*
+ * Tosa bluetooth built-in chip control.
+ *
+ * Later it may be shared with some other platforms.
+ *
+ * Copyright (c) 2008 Dmitry Baryshkov
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef TOSA_BT_H
+#define TOSA_BT_H
+
+struct tosa_bt_data {
+        int gpio_pwr;
+        int gpio_reset;
+};
+
+#endif
+
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h
index dadf4c20b622..f4551269aaf2 100644
--- a/include/asm-arm/arch-pxa/uncompress.h
+++ b/include/asm-arm/arch-pxa/uncompress.h
@@ -11,11 +11,11 @@
 
 #include <linux/serial_reg.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/mach-types.h>
 
-#define __REG(x)        ((volatile unsigned long *)x)
-
-#define UART            FFUART
+#define __REG(x)       ((volatile unsigned long *)x)
 
+static volatile unsigned long *UART = FFUART;
 
 static inline void putc(char c)
 {
@@ -33,8 +33,13 @@ static inline void flush(void)
 {
 }
 
+static inline void arch_decomp_setup(void)
+{
+        if (machine_is_littleton())
+                UART = STUART;
+}
+
 /*
  * nothing to do
  */
-#define arch_decomp_setup()
 #define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
index de577de8d18c..0d35ca04731e 100644
--- a/include/asm-arm/arch-pxa/zylonite.h
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -16,6 +16,8 @@ struct platform_mmc_slot {
 extern struct platform_mmc_slot zylonite_mmc_slot[];
 
 extern int gpio_eth_irq;
+extern int gpio_debug_led1;
+extern int gpio_debug_led2;
 
 extern int wm9713_irq;
 
diff --git a/include/asm-arm/hardware/iop3xx-adma.h b/include/asm-arm/hardware/iop3xx-adma.h
index a32b86ac62aa..af64676650a2 100644
--- a/include/asm-arm/hardware/iop3xx-adma.h
+++ b/include/asm-arm/hardware/iop3xx-adma.h
@@ -260,7 +260,7 @@ static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op)
 static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt,
                                         int *slots_per_op)
 {
-        static const int slot_count_table[] = { 0,
+        static const char slot_count_table[] = {
                                                 1, 1, 1, 1, /* 01 - 04 */
                                                 2, 2, 2, 2, /* 05 - 08 */
                                                 4, 4, 4, 4, /* 09 - 12 */
@@ -270,7 +270,7 @@ static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt,
                                                 8, 8, 8, 8, /* 25 - 28 */
                                                 8, 8, 8, 8, /* 29 - 32 */
                                               };
-        *slots_per_op = slot_count_table[src_cnt];
+        *slots_per_op = slot_count_table[src_cnt - 1];
         return *slots_per_op;
 }
 
diff --git a/include/asm-arm/kgdb.h b/include/asm-arm/kgdb.h
new file mode 100644
index 000000000000..67af4b841984
--- /dev/null
+++ b/include/asm-arm/kgdb.h
@@ -0,0 +1,104 @@
+/*
+ * ARM KGDB support
+ *
+ * Author: Deepak Saxena <dsaxena@mvista.com>
+ *
+ * Copyright (C) 2002 MontaVista Software Inc.
+ *
+ */
+
+#ifndef __ARM_KGDB_H__
+#define __ARM_KGDB_H__
+
+#include <linux/ptrace.h>
+
+/*
+ * GDB assumes that we're a user process being debugged, so
+ * it will send us an SWI command to write into memory as the
+ * debug trap. When an SWI occurs, the next instruction addr is
+ * placed into R14_svc before jumping to the vector trap.
+ * This doesn't work for kernel debugging as we are already in SVC
+ * we would loose the kernel's LR, which is a bad thing. This
+ * is  bad thing.
+ *
+ * By doing this as an undefined instruction trap, we force a mode
+ * switch from SVC to UND mode, allowing us to save full kernel state.
+ *
+ * We also define a KGDB_COMPILED_BREAK which can be used to compile
+ * in breakpoints. This is important for things like sysrq-G and for
+ * the initial breakpoint from trap_init().
+ *
+ * Note to ARM HW designers: Add real trap support like SH && PPC to
+ * make our lives much much simpler. :)
+ */
+#define BREAK_INSTR_SIZE        4
+#define GDB_BREAKINST           0xef9f0001
+#define KGDB_BREAKINST          0xe7ffdefe
+#define KGDB_COMPILED_BREAK     0xe7ffdeff
+#define CACHE_FLUSH_IS_SAFE     1
+
+#ifndef __ASSEMBLY__
+
+static inline void arch_kgdb_breakpoint(void)
+{
+        asm(".word 0xe7ffdeff");
+}
+
+extern void kgdb_handle_bus_error(void);
+extern int kgdb_fault_expected;
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * From Kevin Hilman:
+ *
+ * gdb is expecting the following registers layout.
+ *
+ * r0-r15: 1 long word each
+ * f0-f7:  unused, 3 long words each !!
+ * fps:    unused, 1 long word
+ * cpsr:   1 long word
+ *
+ * Even though f0-f7 and fps are not used, they need to be
+ * present in the registers sent for correct processing in
+ * the host-side gdb.
+ *
+ * In particular, it is crucial that CPSR is in the right place,
+ * otherwise gdb will not be able to correctly interpret stepping over
+ * conditional branches.
+ */
+#define _GP_REGS                16
+#define _FP_REGS                8
+#define _EXTRA_REGS             2
+#define GDB_MAX_REGS            (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS)
+
+#define KGDB_MAX_NO_CPUS        1
+#define BUFMAX                  400
+#define NUMREGBYTES             (GDB_MAX_REGS << 2)
+#define NUMCRITREGBYTES         (32 << 2)
+
+#define _R0                     0
+#define _R1                     1
+#define _R2                     2
+#define _R3                     3
+#define _R4                     4
+#define _R5                     5
+#define _R6                     6
+#define _R7                     7
+#define _R8                     8
+#define _R9                     9
+#define _R10                    10
+#define _FP                     11
+#define _IP                     12
+#define _SPT                    13
+#define _LR                     14
+#define _PC                     15
+#define _CPSR                   (GDB_MAX_REGS - 1)
+
+/*
+ * So that we can denote the end of a frame for tracing,
+ * in the simple case:
+ */
+#define CFI_END_FRAME(func)     __CFI_END_FRAME(_PC, _SPT, func)
+
+#endif /* __ASM_KGDB_H__ */
diff --git a/include/asm-arm/mach/udc_pxa2xx.h b/include/asm-arm/mach/udc_pxa2xx.h
index f9f3606986c2..9e5ed7c0f27f 100644
--- a/include/asm-arm/mach/udc_pxa2xx.h
+++ b/include/asm-arm/mach/udc_pxa2xx.h
@@ -23,6 +23,7 @@ struct pxa2xx_udc_mach_info {
          */
         bool    gpio_vbus_inverted;
         u16     gpio_vbus;                      /* high == vbus present */
+        bool    gpio_pullup_inverted;
         u16     gpio_pullup;                    /* high == pullup activated */
 };
 
diff --git a/include/asm-arm/plat-orion/mv_xor.h b/include/asm-arm/plat-orion/mv_xor.h
new file mode 100644
index 000000000000..c349e8ff5cc0
--- /dev/null
+++ b/include/asm-arm/plat-orion/mv_xor.h
@@ -0,0 +1,28 @@
+/*
+ * Marvell XOR platform device data definition file.
+ */
+
+#ifndef __ASM_PLAT_ORION_MV_XOR_H
+#define __ASM_PLAT_ORION_MV_XOR_H
+
+#include <linux/dmaengine.h>
+#include <linux/mbus.h>
+
+#define MV_XOR_SHARED_NAME      "mv_xor_shared"
+#define MV_XOR_NAME             "mv_xor"
+
+struct mbus_dram_target_info;
+
+struct mv_xor_platform_shared_data {
+        struct mbus_dram_target_info    *dram;
+};
+
+struct mv_xor_platform_data {
+        struct platform_device          *shared;
+        int                             hw_id;
+        dma_cap_mask_t                  cap_mask;
+        size_t                          pool_size;
+};
+
+
+#endif
diff --git a/include/asm-arm/traps.h b/include/asm-arm/traps.h
index f1541afcf85c..aa399aec568e 100644
--- a/include/asm-arm/traps.h
+++ b/include/asm-arm/traps.h
@@ -24,4 +24,6 @@ static inline int in_exception_text(unsigned long ptr)
                ptr < (unsigned long)&__exception_text_end;
 }
 
+extern void __init early_trap_init(void);
+
 #endif
diff --git a/include/asm-avr32/arch-at32ap/at32ap700x.h b/include/asm-avr32/arch-at32ap/at32ap700x.h
index 31e48b0e7324..d18a3053be0d 100644
--- a/include/asm-avr32/arch-at32ap/at32ap700x.h
+++ b/include/asm-avr32/arch-at32ap/at32ap700x.h
@@ -30,4 +30,20 @@
 #define GPIO_PIN_PD(N)  (GPIO_PIOD_BASE + (N))
 #define GPIO_PIN_PE(N)  (GPIO_PIOE_BASE + (N))
 
+
+/*
+ * DMAC peripheral hardware handshaking interfaces, used with dw_dmac
+ */
+#define DMAC_MCI_RX             0
+#define DMAC_MCI_TX             1
+#define DMAC_DAC_TX             2
+#define DMAC_AC97_A_RX          3
+#define DMAC_AC97_A_TX          4
+#define DMAC_AC97_B_RX          5
+#define DMAC_AC97_B_TX          6
+#define DMAC_DMAREQ_0           7
+#define DMAC_DMAREQ_1           8
+#define DMAC_DMAREQ_2           9
+#define DMAC_DMAREQ_3           10
+
 #endif /* __ASM_ARCH_AT32AP700X_H__ */
diff --git a/include/asm-powerpc/kgdb.h b/include/asm-powerpc/kgdb.h
index b617dac82969..1399caf719ae 100644
--- a/include/asm-powerpc/kgdb.h
+++ b/include/asm-powerpc/kgdb.h
@@ -1,57 +1,65 @@
 /*
- * kgdb.h: Defines and declarations for serial line source level
- *         remote debugging of the Linux kernel using gdb.
+ * include/asm-powerpc/kgdb.h
  *
+ * The PowerPC (32/64) specific defines / externs for KGDB.  Based on
+ * the previous 32bit and 64bit specific files, which had the following
+ * copyrights:
+ *
+ * PPC64 Mods (C) 2005 Frank Rowand (frowand@mvista.com)
+ * PPC Mods (C) 2004 Tom Rini (trini@mvista.com)
+ * PPC Mods (C) 2003 John Whitney (john.whitney@timesys.com)
  * PPC Mods (C) 1998 Michael Tesch (tesch@cs.wisc.edu)
  *
+ *
  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ * Author: Tom Rini <trini@kernel.crashing.org>
+ *
+ * 2006 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
  */
 #ifdef __KERNEL__
-#ifndef _PPC_KGDB_H
-#define _PPC_KGDB_H
+#ifndef __POWERPC_KGDB_H__
+#define __POWERPC_KGDB_H__
 
 #ifndef __ASSEMBLY__
 
-/* Things specific to the gen550 backend. */
-struct uart_port;
-
-extern void gen550_progress(char *, unsigned short);
-extern void gen550_kgdb_map_scc(void);
-extern void gen550_init(int, struct uart_port *);
-
-/* Things specific to the pmac backend. */
-extern void zs_kgdb_hook(int tty_num);
-
-/* To init the kgdb engine. (called by serial hook)*/
-extern void set_debug_traps(void);
-
-/* To enter the debugger explicitly. */
-extern void breakpoint(void);
-
-/* For taking exceptions
- * these are defined in traps.c
- */
-extern int (*debugger)(struct pt_regs *regs);
-extern int (*debugger_bpt)(struct pt_regs *regs);
-extern int (*debugger_sstep)(struct pt_regs *regs);
-extern int (*debugger_iabr_match)(struct pt_regs *regs);
-extern int (*debugger_dabr_match)(struct pt_regs *regs);
-extern void (*debugger_fault_handler)(struct pt_regs *regs);
-
-/* What we bring to the party */
-int kgdb_bpt(struct pt_regs *regs);
-int kgdb_sstep(struct pt_regs *regs);
-void kgdb(struct pt_regs *regs);
-int kgdb_iabr_match(struct pt_regs *regs);
-int kgdb_dabr_match(struct pt_regs *regs);
+#define BREAK_INSTR_SIZE        4
+#define BUFMAX                  ((NUMREGBYTES * 2) + 512)
+#define OUTBUFMAX               ((NUMREGBYTES * 2) + 512)
+static inline void arch_kgdb_breakpoint(void)
+{
+        asm(".long 0x7d821008"); /* twge r2, r2 */
+}
+#define CACHE_FLUSH_IS_SAFE     1
 
+/* The number bytes of registers we have to save depends on a few
+ * things.  For 64bit we default to not including vector registers and
+ * vector state registers. */
+#ifdef CONFIG_PPC64
 /*
- * external low-level support routines (ie macserial.c)
+ * 64 bit (8 byte) registers:
+ *   32 gpr, 32 fpr, nip, msr, link, ctr
+ * 32 bit (4 byte) registers:
+ *   ccr, xer, fpscr
  */
-extern void kgdb_interruptible(int); /* control interrupts from serial */
-extern void putDebugChar(char);   /* write a single character      */
-extern char getDebugChar(void);   /* read and return a single char */
-
+#define NUMREGBYTES             ((68 * 8) + (3 * 4))
+#define NUMCRITREGBYTES         184
+#else /* CONFIG_PPC32 */
+/* On non-E500 family PPC32 we determine the size by picking the last
+ * register we need, but on E500 we skip sections so we list what we
+ * need to store, and add it up. */
+#ifndef CONFIG_E500
+#define MAXREG                  (PT_FPSCR+1)
+#else
+/* 32 GPRs (8 bytes), nip, msr, ccr, link, ctr, xer, acc (8 bytes), spefscr*/
+#define MAXREG                 ((32*2)+6+2+1)
+#endif
+#define NUMREGBYTES             (MAXREG * sizeof(int))
+/* CR/LR, R1, R2, R13-R31 inclusive. */
+#define NUMCRITREGBYTES         (23 * sizeof(int))
+#endif /* 32/64 */
 #endif /* !(__ASSEMBLY__) */
-#endif /* !(_PPC_KGDB_H) */
+#endif /* !__POWERPC_KGDB_H__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-x86/ipi.h b/include/asm-x86/ipi.h
index 196d63c28aa4..bb1c09f7a76c 100644
--- a/include/asm-x86/ipi.h
+++ b/include/asm-x86/ipi.h
@@ -122,7 +122,7 @@ static inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
          * - mbligh
          */
         local_irq_save(flags);
-        for_each_cpu_mask(query_cpu, mask) {
+        for_each_cpu_mask_nr(query_cpu, mask) {
                 __send_IPI_dest_field(per_cpu(x86_cpu_to_apicid, query_cpu),
                                       vector, APIC_DEST_PHYSICAL);
         }
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
index 15cb82a44e89..5f58da401b43 100644
--- a/include/asm-x86/processor.h
+++ b/include/asm-x86/processor.h
@@ -134,7 +134,7 @@ extern __u32			cleared_cpu_caps[NCAPINTS];
 #ifdef CONFIG_SMP
 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
-#define current_cpu_data        cpu_data(smp_processor_id())
+#define current_cpu_data        __get_cpu_var(cpu_info)
 #else
 #define cpu_data(cpu)           boot_cpu_data
 #define current_cpu_data        boot_cpu_data
diff --git a/include/asm-x86/thread_info.h b/include/asm-x86/thread_info.h
index 0a8f27d31d0d..3f2de1050988 100644
--- a/include/asm-x86/thread_info.h
+++ b/include/asm-x86/thread_info.h
@@ -79,7 +79,6 @@ struct thread_info {
 #define TIF_SYSCALL_AUDIT       7       /* syscall auditing active */
 #define TIF_SECCOMP             8       /* secure computing */
 #define TIF_MCE_NOTIFY          10      /* notify userspace of an MCE */
-#define TIF_HRTICK_RESCHED      11      /* reprogram hrtick timer */
 #define TIF_NOTSC               16      /* TSC is not accessible in userland */
 #define TIF_IA32                17      /* 32bit process */
 #define TIF_FORK                18      /* ret_from_fork */
@@ -102,7 +101,6 @@ struct thread_info {
 #define _TIF_SYSCALL_AUDIT      (1 << TIF_SYSCALL_AUDIT)
 #define _TIF_SECCOMP            (1 << TIF_SECCOMP)
 #define _TIF_MCE_NOTIFY         (1 << TIF_MCE_NOTIFY)
-#define _TIF_HRTICK_RESCHED     (1 << TIF_HRTICK_RESCHED)
 #define _TIF_NOTSC              (1 << TIF_NOTSC)
 #define _TIF_IA32               (1 << TIF_IA32)
 #define _TIF_FORK               (1 << TIF_FORK)
@@ -135,7 +133,7 @@ struct thread_info {
 
 /* Only used for 64 bit */
 #define _TIF_DO_NOTIFY_MASK                                             \
-        (_TIF_SIGPENDING|_TIF_MCE_NOTIFY|_TIF_HRTICK_RESCHED)
+        (_TIF_SIGPENDING|_TIF_MCE_NOTIFY)
 
 /* flags to check in __switch_to() */
 #define _TIF_WORK_CTXSW                                                 \
diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h
index eb640f0acfac..0f50d4cc4360 100644
--- a/include/linux/async_tx.h
+++ b/include/linux/async_tx.h
@@ -101,21 +101,14 @@ async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx,
 
 /**
  * async_tx_sync_epilog - actions to take if an operation is run synchronously
- * @flags: async_tx flags
- * @depend_tx: transaction depends on depend_tx
  * @cb_fn: function to call when the transaction completes
  * @cb_fn_param: parameter to pass to the callback routine
  */
 static inline void
-async_tx_sync_epilog(unsigned long flags,
-        struct dma_async_tx_descriptor *depend_tx,
-        dma_async_tx_callback cb_fn, void *cb_fn_param)
+async_tx_sync_epilog(dma_async_tx_callback cb_fn, void *cb_fn_param)
 {
         if (cb_fn)
                 cb_fn(cb_fn_param);
-
-        if (depend_tx && (flags & ASYNC_TX_DEP_ACK))
-                async_tx_ack(depend_tx);
 }
 
 void
@@ -152,4 +145,6 @@ struct dma_async_tx_descriptor *
 async_trigger_callback(enum async_tx_flags flags,
         struct dma_async_tx_descriptor *depend_tx,
         dma_async_tx_callback cb_fn, void *cb_fn_param);
+
+void async_tx_quiesce(struct dma_async_tx_descriptor **tx);
 #endif /* _ASYNC_TX_H_ */
diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h
index c24875bd9c5b..1b5c98e7fef7 100644
--- a/include/linux/cpumask.h
+++ b/include/linux/cpumask.h
@@ -17,6 +17,20 @@
  * For details of cpus_onto(), see bitmap_onto in lib/bitmap.c.
  * For details of cpus_fold(), see bitmap_fold in lib/bitmap.c.
  *
+ * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ * Note: The alternate operations with the suffix "_nr" are used
+ *       to limit the range of the loop to nr_cpu_ids instead of
+ *       NR_CPUS when NR_CPUS > 64 for performance reasons.
+ *       If NR_CPUS is <= 64 then most assembler bitmask
+ *       operators execute faster with a constant range, so
+ *       the operator will continue to use NR_CPUS.
+ *
+ *       Another consideration is that nr_cpu_ids is initialized
+ *       to NR_CPUS and isn't lowered until the possible cpus are
+ *       discovered (including any disabled cpus).  So early uses
+ *       will span the entire range of NR_CPUS.
+ * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ *
  * The available cpumask operations are:
  *
  * void cpu_set(cpu, mask)              turn on bit 'cpu' in mask
@@ -38,18 +52,60 @@
  * int cpus_empty(mask)                 Is mask empty (no bits sets)?
  * int cpus_full(mask)                  Is mask full (all bits sets)?
  * int cpus_weight(mask)                Hamming weigh - number of set bits
+ * int cpus_weight_nr(mask)             Same using nr_cpu_ids instead of NR_CPUS
  *
  * void cpus_shift_right(dst, src, n)   Shift right
  * void cpus_shift_left(dst, src, n)    Shift left
  *
  * int first_cpu(mask)                  Number lowest set bit, or NR_CPUS
  * int next_cpu(cpu, mask)              Next cpu past 'cpu', or NR_CPUS
+ * int next_cpu_nr(cpu, mask)           Next cpu past 'cpu', or nr_cpu_ids
  *
  * cpumask_t cpumask_of_cpu(cpu)        Return cpumask with bit 'cpu' set
+ *ifdef CONFIG_HAS_CPUMASK_OF_CPU
+ * cpumask_of_cpu_ptr_declare(v)        Declares cpumask_t *v
+ * cpumask_of_cpu_ptr_next(v, cpu)      Sets v = &cpumask_of_cpu_map[cpu]
+ * cpumask_of_cpu_ptr(v, cpu)           Combines above two operations
+ *else
+ * cpumask_of_cpu_ptr_declare(v)        Declares cpumask_t _v and *v = &_v
+ * cpumask_of_cpu_ptr_next(v, cpu)      Sets _v = cpumask_of_cpu(cpu)
+ * cpumask_of_cpu_ptr(v, cpu)           Combines above two operations
+ *endif
  * CPU_MASK_ALL                         Initializer - all bits set
  * CPU_MASK_NONE                        Initializer - no bits set
  * unsigned long *cpus_addr(mask)       Array of unsigned long's in mask
  *
+ * CPUMASK_ALLOC kmalloc's a structure that is a composite of many cpumask_t
+ * variables, and CPUMASK_PTR provides pointers to each field.
+ *
+ * The structure should be defined something like this:
+ * struct my_cpumasks {
+ *      cpumask_t mask1;
+ *      cpumask_t mask2;
+ * };
+ *
+ * Usage is then:
+ *      CPUMASK_ALLOC(my_cpumasks);
+ *      CPUMASK_PTR(mask1, my_cpumasks);
+ *      CPUMASK_PTR(mask2, my_cpumasks);
+ *
+ *      --- DO NOT reference cpumask_t pointers until this check ---
+ *      if (my_cpumasks == NULL)
+ *              "kmalloc failed"...
+ *
+ * References are now pointers to the cpumask_t variables (*mask1, ...)
+ *
+ *if NR_CPUS > BITS_PER_LONG
+ *   CPUMASK_ALLOC(m)                   Declares and allocates struct m *m =
+ *                                              kmalloc(sizeof(*m), GFP_KERNEL)
+ *   CPUMASK_FREE(m)                    Macro for kfree(m)
+ *else
+ *   CPUMASK_ALLOC(m)                   Declares struct m _m, *m = &_m
+ *   CPUMASK_FREE(m)                    Nop
+ *endif
+ *   CPUMASK_PTR(v, m)                  Declares cpumask_t *v = &(m->v)
+ * ------------------------------------------------------------------------
+ *
  * int cpumask_scnprintf(buf, len, mask) Format cpumask for printing
  * int cpumask_parse_user(ubuf, ulen, mask)     Parse ascii string as cpumask
  * int cpulist_scnprintf(buf, len, mask) Format cpumask as list for printing
@@ -59,7 +115,8 @@
  * void cpus_onto(dst, orig, relmap)    *dst = orig relative to relmap
  * void cpus_fold(dst, orig, sz)        dst bits = orig bits mod sz
  *
- * for_each_cpu_mask(cpu, mask)         for-loop cpu over mask
+ * for_each_cpu_mask(cpu, mask)         for-loop cpu over mask using NR_CPUS
+ * for_each_cpu_mask_nr(cpu, mask)      for-loop cpu over mask using nr_cpu_ids
  *
  * int num_online_cpus()                Number of online CPUs
  * int num_possible_cpus()              Number of all possible CPUs
@@ -216,23 +273,19 @@ static inline void __cpus_shift_left(cpumask_t *dstp,
         bitmap_shift_left(dstp->bits, srcp->bits, n, nbits);
 }
 
-#ifdef CONFIG_SMP
-int __first_cpu(const cpumask_t *srcp);
-#define first_cpu(src) __first_cpu(&(src))
-int __next_cpu(int n, const cpumask_t *srcp);
-#define next_cpu(n, src) __next_cpu((n), &(src))
-#else
-#define first_cpu(src)          ({ (void)(src); 0; })
-#define next_cpu(n, src)        ({ (void)(src); 1; })
-#endif
 
 #ifdef CONFIG_HAVE_CPUMASK_OF_CPU_MAP
 extern cpumask_t *cpumask_of_cpu_map;
-#define cpumask_of_cpu(cpu)    (cpumask_of_cpu_map[cpu])
-
+#define cpumask_of_cpu(cpu)     (cpumask_of_cpu_map[cpu])
+#define cpumask_of_cpu_ptr(v, cpu)                                      \
+                const cpumask_t *v = &cpumask_of_cpu(cpu)
+#define cpumask_of_cpu_ptr_declare(v)                                   \
+                const cpumask_t *v
+#define cpumask_of_cpu_ptr_next(v, cpu)                                 \
+                                        v = &cpumask_of_cpu(cpu)
 #else
 #define cpumask_of_cpu(cpu)                                             \
-(*({                                                                    \
+({                                                                      \
         typeof(_unused_cpumask_arg_) m;                                 \
         if (sizeof(m) == sizeof(unsigned long)) {                       \
                 m.bits[0] = 1UL<<(cpu);                                 \
@@ -240,8 +293,16 @@ extern cpumask_t *cpumask_of_cpu_map;
                 cpus_clear(m);                                          \
                 cpu_set((cpu), m);                                      \
         }                                                               \
-        &m;                                                             \
-}))
+        m;                                                              \
+})
+#define cpumask_of_cpu_ptr(v, cpu)                                      \
+                cpumask_t _##v = cpumask_of_cpu(cpu);                   \
+                const cpumask_t *v = &_##v
+#define cpumask_of_cpu_ptr_declare(v)                                   \
+                cpumask_t _##v;                                         \
+                const cpumask_t *v = &_##v
+#define cpumask_of_cpu_ptr_next(v, cpu)                                 \
+                                        _##v = cpumask_of_cpu(cpu)
 #endif
 
 #define CPU_MASK_LAST_WORD BITMAP_LAST_WORD_MASK(NR_CPUS)
@@ -281,6 +342,15 @@ extern cpumask_t cpu_mask_all;
 
 #define cpus_addr(src) ((src).bits)
 
+#if NR_CPUS > BITS_PER_LONG
+#define CPUMASK_ALLOC(m)        struct m *m = kmalloc(sizeof(*m), GFP_KERNEL)
+#define CPUMASK_FREE(m)         kfree(m)
+#else
+#define CPUMASK_ALLOC(m)        struct m _m, *m = &_m
+#define CPUMASK_FREE(m)
+#endif
+#define CPUMASK_PTR(v, m)       cpumask_t *v = &(m->v)
+
 #define cpumask_scnprintf(buf, len, src) \
                         __cpumask_scnprintf((buf), (len), &(src), NR_CPUS)
 static inline int __cpumask_scnprintf(char *buf, int len,
@@ -343,29 +413,59 @@ static inline void __cpus_fold(cpumask_t *dstp, const cpumask_t *origp,
         bitmap_fold(dstp->bits, origp->bits, sz, nbits);
 }
 
-#if NR_CPUS > 1
-#define for_each_cpu_mask(cpu, mask)            \
-        for ((cpu) = first_cpu(mask);           \
-                (cpu) < NR_CPUS;                \
-                (cpu) = next_cpu((cpu), (mask)))
-#else /* NR_CPUS == 1 */
-#define for_each_cpu_mask(cpu, mask)            \
+#if NR_CPUS == 1
+
+#define nr_cpu_ids              1
+#define first_cpu(src)          ({ (void)(src); 0; })
+#define next_cpu(n, src)        ({ (void)(src); 1; })
+#define any_online_cpu(mask)    0
+#define for_each_cpu_mask(cpu, mask)    \
         for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask)
-#endif /* NR_CPUS */
+
+#else /* NR_CPUS > 1 */
+
+extern int nr_cpu_ids;
+int __first_cpu(const cpumask_t *srcp);
+int __next_cpu(int n, const cpumask_t *srcp);
+int __any_online_cpu(const cpumask_t *mask);
+
+#define first_cpu(src)          __first_cpu(&(src))
+#define next_cpu(n, src)        __next_cpu((n), &(src))
+#define any_online_cpu(mask) __any_online_cpu(&(mask))
+#define for_each_cpu_mask(cpu, mask)                    \
+        for ((cpu) = -1;                                \
+                (cpu) = next_cpu((cpu), (mask)),        \
+                (cpu) < NR_CPUS; )
+#endif
+
+#if NR_CPUS <= 64
 
 #define next_cpu_nr(n, src)             next_cpu(n, src)
 #define cpus_weight_nr(cpumask)         cpus_weight(cpumask)
 #define for_each_cpu_mask_nr(cpu, mask) for_each_cpu_mask(cpu, mask)
 
+#else /* NR_CPUS > 64 */
+
+int __next_cpu_nr(int n, const cpumask_t *srcp);
+#define next_cpu_nr(n, src)     __next_cpu_nr((n), &(src))
+#define cpus_weight_nr(cpumask) __cpus_weight(&(cpumask), nr_cpu_ids)
+#define for_each_cpu_mask_nr(cpu, mask)                 \
+        for ((cpu) = -1;                                \
+                (cpu) = next_cpu_nr((cpu), (mask)),     \
+                (cpu) < nr_cpu_ids; )
+
+#endif /* NR_CPUS > 64 */
+
 /*
  * The following particular system cpumasks and operations manage
- * possible, present and online cpus.  Each of them is a fixed size
+ * possible, present, active and online cpus.  Each of them is a fixed size
  * bitmap of size NR_CPUS.
  *
  *  #ifdef CONFIG_HOTPLUG_CPU
  *     cpu_possible_map - has bit 'cpu' set iff cpu is populatable
  *     cpu_present_map  - has bit 'cpu' set iff cpu is populated
  *     cpu_online_map   - has bit 'cpu' set iff cpu available to scheduler
+ *     cpu_active_map   - has bit 'cpu' set iff cpu available to migration
  *  #else
  *     cpu_possible_map - has bit 'cpu' set iff cpu is populated
  *     cpu_present_map  - copy of cpu_possible_map
@@ -416,14 +516,16 @@ static inline void __cpus_fold(cpumask_t *dstp, const cpumask_t *origp,
 extern cpumask_t cpu_possible_map;
 extern cpumask_t cpu_online_map;
 extern cpumask_t cpu_present_map;
+extern cpumask_t cpu_active_map;
 
 #if NR_CPUS > 1
-#define num_online_cpus()       cpus_weight(cpu_online_map)
-#define num_possible_cpus()     cpus_weight(cpu_possible_map)
-#define num_present_cpus()      cpus_weight(cpu_present_map)
+#define num_online_cpus()       cpus_weight_nr(cpu_online_map)
+#define num_possible_cpus()     cpus_weight_nr(cpu_possible_map)
+#define num_present_cpus()      cpus_weight_nr(cpu_present_map)
 #define cpu_online(cpu)         cpu_isset((cpu), cpu_online_map)
 #define cpu_possible(cpu)       cpu_isset((cpu), cpu_possible_map)
 #define cpu_present(cpu)        cpu_isset((cpu), cpu_present_map)
+#define cpu_active(cpu)         cpu_isset((cpu), cpu_active_map)
 #else
 #define num_online_cpus()       1
 #define num_possible_cpus()     1
@@ -431,21 +533,13 @@ extern cpumask_t cpu_present_map;
 #define cpu_online(cpu)         ((cpu) == 0)
 #define cpu_possible(cpu)       ((cpu) == 0)
 #define cpu_present(cpu)        ((cpu) == 0)
+#define cpu_active(cpu)         ((cpu) == 0)
 #endif
 
 #define cpu_is_offline(cpu)     unlikely(!cpu_online(cpu))
 
-#ifdef CONFIG_SMP
-extern int nr_cpu_ids;
-#define any_online_cpu(mask) __any_online_cpu(&(mask))
-int __any_online_cpu(const cpumask_t *mask);
-#else
-#define nr_cpu_ids                      1
-#define any_online_cpu(mask)            0
-#endif
-
-#define for_each_possible_cpu(cpu)  for_each_cpu_mask((cpu), cpu_possible_map)
-#define for_each_online_cpu(cpu)  for_each_cpu_mask((cpu), cpu_online_map)
-#define for_each_present_cpu(cpu) for_each_cpu_mask((cpu), cpu_present_map)
+#define for_each_possible_cpu(cpu) for_each_cpu_mask_nr((cpu), cpu_possible_map)
+#define for_each_online_cpu(cpu)   for_each_cpu_mask_nr((cpu), cpu_online_map)
+#define for_each_present_cpu(cpu)  for_each_cpu_mask_nr((cpu), cpu_present_map)
 
 #endif /* __LINUX_CPUMASK_H */
diff --git a/include/linux/cpuset.h b/include/linux/cpuset.h
index 038578362b47..e8f450c499b0 100644
--- a/include/linux/cpuset.h
+++ b/include/linux/cpuset.h
@@ -78,6 +78,8 @@ extern void cpuset_track_online_nodes(void);
 
 extern int current_cpuset_is_being_rebound(void);
 
+extern void rebuild_sched_domains(void);
+
 #else /* !CONFIG_CPUSETS */
 
 static inline int cpuset_init_early(void) { return 0; }
@@ -156,6 +158,11 @@ static inline int current_cpuset_is_being_rebound(void)
         return 0;
 }
 
+static inline void rebuild_sched_domains(void)
+{
+        partition_sched_domains(0, NULL, NULL);
+}
+
 #endif /* !CONFIG_CPUSETS */
 
 #endif /* _LINUX_CPUSET_H */
diff --git a/include/linux/dca.h b/include/linux/dca.h
index af61cd1f37e9..b00a753eda53 100644
--- a/include/linux/dca.h
+++ b/include/linux/dca.h
@@ -10,6 +10,7 @@ void dca_unregister_notify(struct notifier_block *nb);
 #define DCA_PROVIDER_REMOVE  0x0002
 
 struct dca_provider {
+        struct list_head        node;
         struct dca_ops          *ops;
         struct device           *cd;
         int                      id;
@@ -18,7 +19,9 @@ struct dca_provider {
 struct dca_ops {
         int     (*add_requester)    (struct dca_provider *, struct device *);
         int     (*remove_requester) (struct dca_provider *, struct device *);
-        u8      (*get_tag)          (struct dca_provider *, int cpu);
+        u8      (*get_tag)          (struct dca_provider *, struct device *,
+                                     int cpu);
+        int     (*dev_managed)      (struct dca_provider *, struct device *);
 };
 
 struct dca_provider *alloc_dca_provider(struct dca_ops *ops, int priv_size);
@@ -32,9 +35,11 @@ static inline void *dca_priv(struct dca_provider *dca)
 }
 
 /* Requester API */
+#define DCA_GET_TAG_TWO_ARGS
 int dca_add_requester(struct device *dev);
 int dca_remove_requester(struct device *dev);
 u8 dca_get_tag(int cpu);
+u8 dca3_get_tag(struct device *dev, int cpu);
 
 /* internal stuff */
 int __init dca_sysfs_init(void);
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index d08a5c5eb928..adb0b084eb5a 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -89,10 +89,23 @@ enum dma_transaction_type {
         DMA_MEMSET,
         DMA_MEMCPY_CRC32C,
         DMA_INTERRUPT,
+        DMA_SLAVE,
 };
 
 /* last transaction type for creation of the capabilities mask */
-#define DMA_TX_TYPE_END (DMA_INTERRUPT + 1)
+#define DMA_TX_TYPE_END (DMA_SLAVE + 1)
+
+/**
+ * enum dma_slave_width - DMA slave register access width.
+ * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
+ * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
+ * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
+ */
+enum dma_slave_width {
+        DMA_SLAVE_WIDTH_8BIT,
+        DMA_SLAVE_WIDTH_16BIT,
+        DMA_SLAVE_WIDTH_32BIT,
+};
 
 /**
  * enum dma_ctrl_flags - DMA flags to augment operation preparation,
@@ -102,10 +115,14 @@ enum dma_transaction_type {
  * @DMA_CTRL_ACK - the descriptor cannot be reused until the client
  *      acknowledges receipt, i.e. has has a chance to establish any
  *      dependency chains
+ * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
+ * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
  */
 enum dma_ctrl_flags {
         DMA_PREP_INTERRUPT = (1 << 0),
         DMA_CTRL_ACK = (1 << 1),
+        DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
+        DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
 };
 
 /**
@@ -115,6 +132,32 @@ enum dma_ctrl_flags {
 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
 
 /**
+ * struct dma_slave - Information about a DMA slave
+ * @dev: device acting as DMA slave
+ * @dma_dev: required DMA master device. If non-NULL, the client can not be
+ *      bound to other masters than this.
+ * @tx_reg: physical address of data register used for
+ *      memory-to-peripheral transfers
+ * @rx_reg: physical address of data register used for
+ *      peripheral-to-memory transfers
+ * @reg_width: peripheral register width
+ *
+ * If dma_dev is non-NULL, the client can not be bound to other DMA
+ * masters than the one corresponding to this device. The DMA master
+ * driver may use this to determine if there is controller-specific
+ * data wrapped around this struct. Drivers of platform code that sets
+ * the dma_dev field must therefore make sure to use an appropriate
+ * controller-specific dma slave structure wrapping this struct.
+ */
+struct dma_slave {
+        struct device           *dev;
+        struct device           *dma_dev;
+        dma_addr_t              tx_reg;
+        dma_addr_t              rx_reg;
+        enum dma_slave_width    reg_width;
+};
+
+/**
  * struct dma_chan_percpu - the per-CPU part of struct dma_chan
  * @refcount: local_t used for open-coded "bigref" counting
  * @memcpy_count: transaction counter
@@ -139,6 +182,7 @@ struct dma_chan_percpu {
  * @rcu: the DMA channel's RCU head
  * @device_node: used to add this to the device chan list
  * @local: per-cpu pointer to a struct dma_chan_percpu
+ * @client-count: how many clients are using this channel
  */
 struct dma_chan {
         struct dma_device *device;
@@ -154,6 +198,7 @@ struct dma_chan {
 
         struct list_head device_node;
         struct dma_chan_percpu *local;
+        int client_count;
 };
 
 #define to_dma_chan(p) container_of(p, struct dma_chan, dev)
@@ -202,11 +247,14 @@ typedef enum dma_state_client (*dma_event_callback) (struct dma_client *client,
  * @event_callback: func ptr to call when something happens
  * @cap_mask: only return channels that satisfy the requested capabilities
  *  a value of zero corresponds to any capability
+ * @slave: data for preparing slave transfer. Must be non-NULL iff the
+ *  DMA_SLAVE capability is requested.
  * @global_node: list_head for global dma_client_list
  */
 struct dma_client {
         dma_event_callback      event_callback;
         dma_cap_mask_t          cap_mask;
+        struct dma_slave        *slave;
         struct list_head        global_node;
 };
 
@@ -263,6 +311,8 @@ struct dma_async_tx_descriptor {
  * @device_prep_dma_zero_sum: prepares a zero_sum operation
  * @device_prep_dma_memset: prepares a memset operation
  * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
+ * @device_prep_slave_sg: prepares a slave dma operation
+ * @device_terminate_all: terminate all pending operations
  * @device_issue_pending: push pending transactions to hardware
  */
 struct dma_device {
@@ -279,7 +329,8 @@ struct dma_device {
         int dev_id;
         struct device *dev;
 
-        int (*device_alloc_chan_resources)(struct dma_chan *chan);
+        int (*device_alloc_chan_resources)(struct dma_chan *chan,
+                        struct dma_client *client);
         void (*device_free_chan_resources)(struct dma_chan *chan);
 
         struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
@@ -297,6 +348,12 @@ struct dma_device {
         struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
                 struct dma_chan *chan, unsigned long flags);
 
+        struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
+                struct dma_chan *chan, struct scatterlist *sgl,
+                unsigned int sg_len, enum dma_data_direction direction,
+                unsigned long flags);
+        void (*device_terminate_all)(struct dma_chan *chan);
+
         enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
                         dma_cookie_t cookie, dma_cookie_t *last,
                         dma_cookie_t *used);
@@ -318,16 +375,14 @@ dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
         struct dma_chan *chan);
 
-static inline void
-async_tx_ack(struct dma_async_tx_descriptor *tx)
+static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
 {
         tx->flags |= DMA_CTRL_ACK;
 }
 
-static inline int
-async_tx_test_ack(struct dma_async_tx_descriptor *tx)
+static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
 {
-        return tx->flags & DMA_CTRL_ACK;
+        return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
 }
 
 #define first_dma_cap(mask) __first_dma_cap(&(mask))
diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h
new file mode 100644
index 000000000000..04d217b442bf
--- /dev/null
+++ b/include/linux/dw_dmac.h
@@ -0,0 +1,62 @@
+/*
+ * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
+ * AVR32 systems.)
+ *
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef DW_DMAC_H
+#define DW_DMAC_H
+
+#include <linux/dmaengine.h>
+
+/**
+ * struct dw_dma_platform_data - Controller configuration parameters
+ * @nr_channels: Number of channels supported by hardware (max 8)
+ */
+struct dw_dma_platform_data {
+        unsigned int    nr_channels;
+};
+
+/**
+ * struct dw_dma_slave - Controller-specific information about a slave
+ * @slave: Generic information about the slave
+ * @ctl_lo: Platform-specific initializer for the CTL_LO register
+ * @cfg_hi: Platform-specific initializer for the CFG_HI register
+ * @cfg_lo: Platform-specific initializer for the CFG_LO register
+ */
+struct dw_dma_slave {
+        struct dma_slave        slave;
+        u32                     cfg_hi;
+        u32                     cfg_lo;
+};
+
+/* Platform-configurable bits in CFG_HI */
+#define DWC_CFGH_FCMODE         (1 << 0)
+#define DWC_CFGH_FIFO_MODE      (1 << 1)
+#define DWC_CFGH_PROTCTL(x)     ((x) << 2)
+#define DWC_CFGH_SRC_PER(x)     ((x) << 7)
+#define DWC_CFGH_DST_PER(x)     ((x) << 11)
+
+/* Platform-configurable bits in CFG_LO */
+#define DWC_CFGL_PRIO(x)        ((x) << 5)      /* priority */
+#define DWC_CFGL_LOCK_CH_XFER   (0 << 12)       /* scope of LOCK_CH */
+#define DWC_CFGL_LOCK_CH_BLOCK  (1 << 12)
+#define DWC_CFGL_LOCK_CH_XACT   (2 << 12)
+#define DWC_CFGL_LOCK_BUS_XFER  (0 << 14)       /* scope of LOCK_BUS */
+#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
+#define DWC_CFGL_LOCK_BUS_XACT  (2 << 14)
+#define DWC_CFGL_LOCK_CH        (1 << 15)       /* channel lockout */
+#define DWC_CFGL_LOCK_BUS       (1 << 16)       /* busmaster lockout */
+#define DWC_CFGL_HS_DST_POL     (1 << 18)       /* dst handshake active low */
+#define DWC_CFGL_HS_SRC_POL     (1 << 19)       /* src handshake active low */
+
+static inline struct dw_dma_slave *to_dw_dma_slave(struct dma_slave *slave)
+{
+        return container_of(slave, struct dw_dma_slave, slave);
+}
+
+#endif /* DW_DMAC_H */
diff --git a/include/linux/hid.h b/include/linux/hid.h
index fe56b86f2c67..ac4e678a04ed 100644
--- a/include/linux/hid.h
+++ b/include/linux/hid.h
@@ -512,7 +512,7 @@ struct hid_descriptor {
 
 /* Applications from HID Usage Tables 4/8/99 Version 1.1 */
 /* We ignore a few input applications that are not widely used */
-#define IS_INPUT_APPLICATION(a) (((a >= 0x00010000) && (a <= 0x00010008)) || (a == 0x00010080) || (a == 0x000c0001))
+#define IS_INPUT_APPLICATION(a) (((a >= 0x00010000) && (a <= 0x00010008)) || (a == 0x00010080) || (a == 0x000c0001) || (a == 0x000d0002))
 
 /* HID core API */
 
diff --git a/include/linux/ide.h b/include/linux/ide.h
index 4726126f5a59..d67ccca2b964 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -178,6 +178,7 @@ typedef struct hw_regs_s {
         ide_ack_intr_t  *ack_intr;              /* acknowledge interrupt */
         hwif_chipset_t  chipset;
         struct device   *dev, *parent;
+        unsigned long   config;
 } hw_regs_t;
 
 void ide_init_port_data(struct hwif_s *, unsigned int);
@@ -307,7 +308,65 @@ struct ide_acpi_drive_link;
 struct ide_acpi_hwif_link;
 #endif
 
-typedef struct ide_drive_s {
+/* ATAPI device flags */
+enum {
+        IDE_AFLAG_DRQ_INTERRUPT         = (1 << 0),
+        IDE_AFLAG_MEDIA_CHANGED         = (1 << 1),
+
+        /* ide-cd */
+        /* Drive cannot lock the door. */
+        IDE_AFLAG_NO_DOORLOCK           = (1 << 2),
+        /* Drive cannot eject the disc. */
+        IDE_AFLAG_NO_EJECT              = (1 << 3),
+        /* Drive is a pre ATAPI 1.2 drive. */
+        IDE_AFLAG_PRE_ATAPI12           = (1 << 4),
+        /* TOC addresses are in BCD. */
+        IDE_AFLAG_TOCADDR_AS_BCD        = (1 << 5),
+        /* TOC track numbers are in BCD. */
+        IDE_AFLAG_TOCTRACKS_AS_BCD      = (1 << 6),
+        /*
+         * Drive does not provide data in multiples of SECTOR_SIZE
+         * when more than one interrupt is needed.
+         */
+        IDE_AFLAG_LIMIT_NFRAMES         = (1 << 7),
+        /* Seeking in progress. */
+        IDE_AFLAG_SEEKING               = (1 << 8),
+        /* Saved TOC information is current. */
+        IDE_AFLAG_TOC_VALID             = (1 << 9),
+        /* We think that the drive door is locked. */
+        IDE_AFLAG_DOOR_LOCKED           = (1 << 10),
+        /* SET_CD_SPEED command is unsupported. */
+        IDE_AFLAG_NO_SPEED_SELECT       = (1 << 11),
+        IDE_AFLAG_VERTOS_300_SSD        = (1 << 12),
+        IDE_AFLAG_VERTOS_600_ESD        = (1 << 13),
+        IDE_AFLAG_SANYO_3CD             = (1 << 14),
+        IDE_AFLAG_FULL_CAPS_PAGE        = (1 << 15),
+        IDE_AFLAG_PLAY_AUDIO_OK         = (1 << 16),
+        IDE_AFLAG_LE_SPEED_FIELDS       = (1 << 17),
+
+        /* ide-floppy */
+        /* Format in progress */
+        IDE_AFLAG_FORMAT_IN_PROGRESS    = (1 << 18),
+        /* Avoid commands not supported in Clik drive */
+        IDE_AFLAG_CLIK_DRIVE            = (1 << 19),
+        /* Requires BH algorithm for packets */
+        IDE_AFLAG_ZIP_DRIVE             = (1 << 20),
+
+        /* ide-tape */
+        IDE_AFLAG_IGNORE_DSC            = (1 << 21),
+        /* 0 When the tape position is unknown */
+        IDE_AFLAG_ADDRESS_VALID         = (1 << 22),
+        /* Device already opened */
+        IDE_AFLAG_BUSY                  = (1 << 23),
+        /* Attempt to auto-detect the current user block size */
+        IDE_AFLAG_DETECT_BS             = (1 << 24),
+        /* Currently on a filemark */
+        IDE_AFLAG_FILEMARK              = (1 << 25),
+        /* 0 = no tape is loaded, so we don't rewind after ejecting */
+        IDE_AFLAG_MEDIUM_PRESENT        = (1 << 26)
+};
+
+struct ide_drive_s {
         char            name[4];        /* drive name, such as "hda" */
         char            driver_req[10]; /* requests specific driver */
 
@@ -355,7 +414,6 @@ typedef struct ide_drive_s {
         unsigned nodma          : 1;    /* disallow DMA */
         unsigned remap_0_to_1   : 1;    /* 0=noremap, 1=remap 0->1 (for EZDrive) */
         unsigned blocked        : 1;    /* 1=powermanagment told us not to do anything, so sleep nicely */
-        unsigned vdma           : 1;    /* 1=doing PIO over DMA 0=doing normal DMA */
         unsigned scsi           : 1;    /* 0=default, 1=ide-scsi emulation */
         unsigned sleeping       : 1;    /* 1=sleeping & sleep field valid */
         unsigned post_reset     : 1;
@@ -400,7 +458,14 @@ typedef struct ide_drive_s {
         struct list_head list;
         struct device   gendev;
         struct completion gendev_rel_comp;      /* to deal with device release() */
-} ide_drive_t;
+
+        /* callback for packet commands */
+        void (*pc_callback)(struct ide_drive_s *);
+
+        unsigned long atapi_flags;
+};
+
+typedef struct ide_drive_s ide_drive_t;
 
 #define to_ide_device(dev)container_of(dev, ide_drive_t, gendev)
 
@@ -408,8 +473,28 @@ typedef struct ide_drive_s {
     ((1<<ide_pci)|(1<<ide_cmd646)|(1<<ide_ali14xx))
 #define IDE_CHIPSET_IS_PCI(c)   ((IDE_CHIPSET_PCI_MASK >> (c)) & 1)
 
+struct ide_task_s;
 struct ide_port_info;
 
+struct ide_tp_ops {
+        void    (*exec_command)(struct hwif_s *, u8);
+        u8      (*read_status)(struct hwif_s *);
+        u8      (*read_altstatus)(struct hwif_s *);
+        u8      (*read_sff_dma_status)(struct hwif_s *);
+
+        void    (*set_irq)(struct hwif_s *, int);
+
+        void    (*tf_load)(ide_drive_t *, struct ide_task_s *);
+        void    (*tf_read)(ide_drive_t *, struct ide_task_s *);
+
+        void    (*input_data)(ide_drive_t *, struct request *, void *,
+                              unsigned int);
+        void    (*output_data)(ide_drive_t *, struct request *, void *,
+                               unsigned int);
+};
+
+extern const struct ide_tp_ops default_tp_ops;
+
 struct ide_port_ops {
         /* host specific initialization of a device */
         void    (*init_dev)(ide_drive_t *);
@@ -447,8 +532,6 @@ struct ide_dma_ops {
         void    (*dma_timeout)(struct ide_drive_s *);
 };
 
-struct ide_task_s;
-
 typedef struct hwif_s {
         struct hwif_s *next;            /* for linked-list in ide_hwgroup_t */
         struct hwif_s *mate;            /* other hwif from same PCI chip */
@@ -486,22 +569,12 @@ typedef struct hwif_s {
 
         void (*rw_disk)(ide_drive_t *, struct request *);
 
+        const struct ide_tp_ops         *tp_ops;
         const struct ide_port_ops       *port_ops;
         const struct ide_dma_ops        *dma_ops;
 
-        void (*tf_load)(ide_drive_t *, struct ide_task_s *);
-        void (*tf_read)(ide_drive_t *, struct ide_task_s *);
-
-        void (*input_data)(ide_drive_t *, struct request *, void *, unsigned);
-        void (*output_data)(ide_drive_t *, struct request *, void *, unsigned);
-
         void (*ide_dma_clear_irq)(ide_drive_t *drive);
 
-        void (*OUTB)(u8 addr, unsigned long port);
-        void (*OUTBSYNC)(struct hwif_s *hwif, u8 addr, unsigned long port);
-
-        u8  (*INB)(unsigned long port);
-
         /* dma physical region descriptor table (cpu view) */
         unsigned int    *dmatable_cpu;
         /* dma physical region descriptor table (dma view) */
@@ -524,8 +597,6 @@ typedef struct hwif_s {
         int             irq;            /* our irq number */
 
         unsigned long   dma_base;       /* base addr for dma ports */
-        unsigned long   dma_command;    /* dma command register */
-        unsigned long   dma_status;     /* dma status register */
 
         unsigned long   config_data;    /* for use by chipset-specific code */
         unsigned long   select_data;    /* for use by chipset-specific code */
@@ -552,6 +623,11 @@ typedef struct hwif_s {
 #endif
 } ____cacheline_internodealigned_in_smp ide_hwif_t;
 
+struct ide_host {
+        ide_hwif_t      *ports[MAX_HWIFS];
+        unsigned int    n_ports;
+};
+
 /*
  *  internal ide interrupt handler type
  */
@@ -611,8 +687,6 @@ enum {
         PC_FLAG_WRITING                 = (1 << 6),
         /* command timed out */
         PC_FLAG_TIMEDOUT                = (1 << 7),
-        PC_FLAG_ZIP_DRIVE               = (1 << 8),
-        PC_FLAG_DRQ_INTERRUPT           = (1 << 9),
 };
 
 struct ide_atapi_pc {
@@ -646,8 +720,6 @@ struct ide_atapi_pc {
          */
         u8 pc_buf[256];
 
-        void (*callback)(ide_drive_t *);
-
         /* idetape only */
         struct idetape_bh *bh;
         char *b_data;
@@ -807,13 +879,6 @@ int generic_ide_ioctl(ide_drive_t *, struct file *, struct block_device *, unsig
 extern int ide_vlb_clk;
 extern int ide_pci_clk;
 
-ide_hwif_t *ide_find_port_slot(const struct ide_port_info *);
-
-static inline ide_hwif_t *ide_find_port(void)
-{
-        return ide_find_port_slot(NULL);
-}
-
 extern int ide_end_request (ide_drive_t *drive, int uptodate, int nrsecs);
 int ide_end_dequeued_request(ide_drive_t *drive, struct request *rq,
                              int uptodate, int nr_sectors);
@@ -884,6 +949,7 @@ enum {
         IDE_TFLAG_IN_HOB                = IDE_TFLAG_IN_HOB_FEATURE |
                                           IDE_TFLAG_IN_HOB_NSECT |
                                           IDE_TFLAG_IN_HOB_LBA,
+        IDE_TFLAG_IN_FEATURE            = (1 << 1),
         IDE_TFLAG_IN_NSECT              = (1 << 25),
         IDE_TFLAG_IN_LBAL               = (1 << 26),
         IDE_TFLAG_IN_LBAM               = (1 << 27),
@@ -948,9 +1014,25 @@ typedef struct ide_task_s {
 
 void ide_tf_dump(const char *, struct ide_taskfile *);
 
+void ide_exec_command(ide_hwif_t *, u8);
+u8 ide_read_status(ide_hwif_t *);
+u8 ide_read_altstatus(ide_hwif_t *);
+u8 ide_read_sff_dma_status(ide_hwif_t *);
+
+void ide_set_irq(ide_hwif_t *, int);
+
+void ide_tf_load(ide_drive_t *, ide_task_t *);
+void ide_tf_read(ide_drive_t *, ide_task_t *);
+
+void ide_input_data(ide_drive_t *, struct request *, void *, unsigned int);
+void ide_output_data(ide_drive_t *, struct request *, void *, unsigned int);
+
 extern void SELECT_DRIVE(ide_drive_t *);
 void SELECT_MASK(ide_drive_t *, int);
 
+u8 ide_read_error(ide_drive_t *);
+void ide_read_bcount_and_ireason(ide_drive_t *, u16 *, u8 *);
+
 extern int drive_is_ready(ide_drive_t *);
 
 void ide_pktcmd_tf_load(ide_drive_t *, u32, u16, u8);
@@ -1000,12 +1082,15 @@ extern int __ide_pci_register_driver(struct pci_driver *driver, struct module *o
 #define ide_pci_register_driver(d) pci_register_driver(d)
 #endif
 
-void ide_pci_setup_ports(struct pci_dev *, const struct ide_port_info *, int, u8 *);
+void ide_pci_setup_ports(struct pci_dev *, const struct ide_port_info *, int,
+                         hw_regs_t *, hw_regs_t **);
 void ide_setup_pci_noise(struct pci_dev *, const struct ide_port_info *);
 
 #ifdef CONFIG_BLK_DEV_IDEDMA_PCI
 int ide_pci_set_master(struct pci_dev *, const char *);
 unsigned long ide_pci_dma_base(ide_hwif_t *, const struct ide_port_info *);
+extern const struct ide_dma_ops sff_dma_ops;
+int ide_pci_check_simplex(ide_hwif_t *, const struct ide_port_info *);
 int ide_hwif_setup_dma(ide_hwif_t *, const struct ide_port_info *);
 #else
 static inline int ide_hwif_setup_dma(ide_hwif_t *hwif,
@@ -1015,10 +1100,6 @@ static inline int ide_hwif_setup_dma(ide_hwif_t *hwif,
 }
 #endif
 
-extern void default_hwif_iops(ide_hwif_t *);
-extern void default_hwif_mmiops(ide_hwif_t *);
-extern void default_hwif_transport(ide_hwif_t *);
-
 typedef struct ide_pci_enablebit_s {
         u8      reg;    /* byte pci reg holding the enable-bit */
         u8      mask;   /* mask to isolate the enable-bit */
@@ -1081,7 +1162,6 @@ enum {
         IDE_HFLAG_IO_32BIT              = (1 << 24),
         /* unmask IRQs */
         IDE_HFLAG_UNMASK_IRQS           = (1 << 25),
-        IDE_HFLAG_ABUSE_SET_DMA_MODE    = (1 << 26),
         /* serialize ports if DMA is possible (for sl82c105) */
         IDE_HFLAG_SERIALIZE_DMA         = (1 << 27),
         /* force host out of "simplex" mode */
@@ -1092,8 +1172,6 @@ enum {
         IDE_HFLAG_NO_IO_32BIT           = (1 << 30),
         /* never unmask IRQs */
         IDE_HFLAG_NO_UNMASK_IRQS        = (1 << 31),
-        /* host uses VDMA (disabled for now) */
-        IDE_HFLAG_VDMA                  = 0,
 };
 
 #ifdef CONFIG_BLK_DEV_OFFBOARD
@@ -1110,6 +1188,7 @@ struct ide_port_info {
         int                     (*init_dma)(ide_hwif_t *,
                                             const struct ide_port_info *);
 
+        const struct ide_tp_ops         *tp_ops;
         const struct ide_port_ops       *port_ops;
         const struct ide_dma_ops        *dma_ops;
 
@@ -1163,7 +1242,6 @@ void ide_destroy_dmatable(ide_drive_t *);
 extern int ide_build_dmatable(ide_drive_t *, struct request *);
 int ide_allocate_dma_engine(ide_hwif_t *);
 void ide_release_dma_engine(ide_hwif_t *);
-void ide_setup_dma(ide_hwif_t *, unsigned long);
 
 void ide_dma_host_set(ide_drive_t *, int);
 extern int ide_dma_setup(ide_drive_t *);
@@ -1217,8 +1295,14 @@ void ide_undecoded_slave(ide_drive_t *);
 
 void ide_port_apply_params(ide_hwif_t *);
 
-int ide_device_add_all(u8 *idx, const struct ide_port_info *);
-int ide_device_add(u8 idx[4], const struct ide_port_info *);
+struct ide_host *ide_host_alloc_all(const struct ide_port_info *, hw_regs_t **);
+struct ide_host *ide_host_alloc(const struct ide_port_info *, hw_regs_t **);
+void ide_host_free(struct ide_host *);
+int ide_host_register(struct ide_host *, const struct ide_port_info *,
+                      hw_regs_t **);
+int ide_host_add(const struct ide_port_info *, hw_regs_t **,
+                 struct ide_host **);
+void ide_host_remove(struct ide_host *);
 int ide_legacy_device_add(const struct ide_port_info *, unsigned long);
 void ide_port_unregister_devices(ide_hwif_t *);
 void ide_port_scan(ide_hwif_t *);
@@ -1350,33 +1434,4 @@ static inline ide_drive_t *ide_get_paired_drive(ide_drive_t *drive)
 
         return &hwif->drives[(drive->dn ^ 1) & 1];
 }
-
-static inline void ide_set_irq(ide_drive_t *drive, int on)
-{
-        ide_hwif_t *hwif = drive->hwif;
-
-        hwif->OUTBSYNC(hwif, ATA_DEVCTL_OBS | (on ? 0 : 2),
-                       hwif->io_ports.ctl_addr);
-}
-
-static inline u8 ide_read_status(ide_drive_t *drive)
-{
-        ide_hwif_t *hwif = drive->hwif;
-
-        return hwif->INB(hwif->io_ports.status_addr);
-}
-
-static inline u8 ide_read_altstatus(ide_drive_t *drive)
-{
-        ide_hwif_t *hwif = drive->hwif;
-
-        return hwif->INB(hwif->io_ports.ctl_addr);
-}
-
-static inline u8 ide_read_error(ide_drive_t *drive)
-{
-        ide_hwif_t *hwif = drive->hwif;
-
-        return hwif->INB(hwif->io_ports.error_addr);
-}
 #endif /* _IDE_H */
diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h
new file mode 100644
index 000000000000..bb3dd0545928
--- /dev/null
+++ b/include/linux/mfd/core.h
@@ -0,0 +1,55 @@
+#ifndef MFD_CORE_H
+#define MFD_CORE_H
+/*
+ * drivers/mfd/mfd-core.h
+ *
+ * core MFD support
+ * Copyright (c) 2006 Ian Molton
+ * Copyright (c) 2007 Dmitry Baryshkov
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/platform_device.h>
+
+/*
+ * This struct describes the MFD part ("cell").
+ * After registration the copy of this structure will become the platform data
+ * of the resulting platform_device
+ */
+struct mfd_cell {
+        const char              *name;
+
+        int                     (*enable)(struct platform_device *dev);
+        int                     (*disable)(struct platform_device *dev);
+        int                     (*suspend)(struct platform_device *dev);
+        int                     (*resume)(struct platform_device *dev);
+
+        void                    *driver_data; /* driver-specific data */
+
+        /*
+         * This resources can be specified relatievly to the parent device.
+         * For accessing device you should use resources from device
+         */
+        int                     num_resources;
+        const struct resource   *resources;
+};
+
+static inline struct mfd_cell *
+mfd_get_cell(struct platform_device *pdev)
+{
+        return (struct mfd_cell *)pdev->dev.platform_data;
+}
+
+extern int mfd_add_devices(
+                struct platform_device *parent,
+                const struct mfd_cell *cells, int n_devs,
+                struct resource *mem_base,
+                int irq_base);
+
+extern void mfd_remove_devices(struct platform_device *parent);
+
+#endif
diff --git a/include/linux/mfd/tc6393xb.h b/include/linux/mfd/tc6393xb.h
new file mode 100644
index 000000000000..7cc824a58f7c
--- /dev/null
+++ b/include/linux/mfd/tc6393xb.h
@@ -0,0 +1,49 @@
+/*
+ * Toshiba TC6393XB SoC support
+ *
+ * Copyright(c) 2005-2006 Chris Humbert
+ * Copyright(c) 2005 Dirk Opfer
+ * Copyright(c) 2005 Ian Molton <spyro@f2s.com>
+ * Copyright(c) 2007 Dmitry Baryshkov
+ *
+ * Based on code written by Sharp/Lineo for 2.4 kernels
+ * Based on locomo.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef TC6393XB_H
+#define TC6393XB_H
+
+/* Also one should provide the CK3P6MI clock */
+struct tc6393xb_platform_data {
+        u16     scr_pll2cr;     /* PLL2 Control */
+        u16     scr_gper;       /* GP Enable */
+        u32     scr_gpo_doecr;  /* GPO Data OE Control */
+        u32     scr_gpo_dsr;    /* GPO Data Set */
+
+        int     (*enable)(struct platform_device *dev);
+        int     (*disable)(struct platform_device *dev);
+        int     (*suspend)(struct platform_device *dev);
+        int     (*resume)(struct platform_device *dev);
+
+        int     irq_base;       /* a base for cascaded irq */
+        int     gpio_base;
+
+        struct tmio_nand_data   *nand_data;
+};
+
+/*
+ * Relative to irq_base
+ */
+#define IRQ_TC6393_NAND         0
+#define IRQ_TC6393_MMC          1
+#define IRQ_TC6393_OHCI         2
+#define IRQ_TC6393_SERIAL       3
+#define IRQ_TC6393_FB           4
+
+#define TC6393XB_NR_IRQS        8
+
+#endif
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
new file mode 100644
index 000000000000..9438d8c9ac1c
--- /dev/null
+++ b/include/linux/mfd/tmio.h
@@ -0,0 +1,17 @@
+#ifndef MFD_TMIO_H
+#define MFD_TMIO_H
+
+/*
+ * data for the NAND controller
+ */
+struct tmio_nand_data {
+        struct nand_bbt_descr   *badblock_pattern;
+        struct mtd_partition    *partition;
+        unsigned int            num_partitions;
+};
+
+#define TMIO_NAND_CONFIG        "tmio-nand-config"
+#define TMIO_NAND_CONTROL       "tmio-nand-control"
+#define TMIO_NAND_IRQ           "tmio-nand"
+
+#endif
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index d8507eb394cf..119ae7b8f028 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2371,6 +2371,14 @@
 #define PCI_DEVICE_ID_INTEL_ICH9_7      0x2916
 #define PCI_DEVICE_ID_INTEL_ICH9_8      0x2918
 #define PCI_DEVICE_ID_INTEL_82855PM_HB  0x3340
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG4   0x3429
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG5   0x342a
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG6   0x342b
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG7   0x342c
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG0   0x3430
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG1   0x3431
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG2   0x3432
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG3   0x3433
 #define PCI_DEVICE_ID_INTEL_82830_HB    0x3575
 #define PCI_DEVICE_ID_INTEL_82830_CGC   0x3577
 #define PCI_DEVICE_ID_INTEL_82855GM_HB  0x3580
diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h
index 71fc81360048..e5996984ddd0 100644
--- a/include/linux/scatterlist.h
+++ b/include/linux/scatterlist.h
@@ -224,4 +224,42 @@ size_t sg_copy_to_buffer(struct scatterlist *sgl, unsigned int nents,
  */
 #define SG_MAX_SINGLE_ALLOC             (PAGE_SIZE / sizeof(struct scatterlist))
 
+
+/*
+ * Mapping sg iterator
+ *
+ * Iterates over sg entries mapping page-by-page.  On each successful
+ * iteration, @miter->page points to the mapped page and
+ * @miter->length bytes of data can be accessed at @miter->addr.  As
+ * long as an interation is enclosed between start and stop, the user
+ * is free to choose control structure and when to stop.
+ *
+ * @miter->consumed is set to @miter->length on each iteration.  It
+ * can be adjusted if the user can't consume all the bytes in one go.
+ * Also, a stopped iteration can be resumed by calling next on it.
+ * This is useful when iteration needs to release all resources and
+ * continue later (e.g. at the next interrupt).
+ */
+
+#define SG_MITER_ATOMIC         (1 << 0)         /* use kmap_atomic */
+
+struct sg_mapping_iter {
+        /* the following three fields can be accessed directly */
+        struct page             *page;          /* currently mapped page */
+        void                    *addr;          /* pointer to the mapped area */
+        size_t                  length;         /* length of the mapped area */
+        size_t                  consumed;       /* number of consumed bytes */
+
+        /* these are internal states, keep away */
+        struct scatterlist      *__sg;          /* current entry */
+        unsigned int            __nents;        /* nr of remaining entries */
+        unsigned int            __offset;       /* offset within sg */
+        unsigned int            __flags;
+};
+
+void sg_miter_start(struct sg_mapping_iter *miter, struct scatterlist *sgl,
+                    unsigned int nents, unsigned int flags);
+bool sg_miter_next(struct sg_mapping_iter *miter);
+void sg_miter_stop(struct sg_mapping_iter *miter);
+
 #endif /* _LINUX_SCATTERLIST_H */
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 1941d8b5cf11..dc7e592c473a 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -295,10 +295,11 @@ extern void softlockup_tick(void);
 extern void spawn_softlockup_task(void);
 extern void touch_softlockup_watchdog(void);
 extern void touch_all_softlockup_watchdogs(void);
-extern unsigned long  softlockup_thresh;
+extern unsigned int  softlockup_panic;
 extern unsigned long sysctl_hung_task_check_count;
 extern unsigned long sysctl_hung_task_timeout_secs;
 extern unsigned long sysctl_hung_task_warnings;
+extern int softlockup_thresh;
 #else
 static inline void softlockup_tick(void)
 {
@@ -824,7 +825,16 @@ extern void partition_sched_domains(int ndoms_new, cpumask_t *doms_new,
                                     struct sched_domain_attr *dattr_new);
 extern int arch_reinit_sched_domains(void);
 
-#endif  /* CONFIG_SMP */
+#else /* CONFIG_SMP */
+
+struct sched_domain_attr;
+
+static inline void
+partition_sched_domains(int ndoms_new, cpumask_t *doms_new,
+                        struct sched_domain_attr *dattr_new)
+{
+}
+#endif  /* !CONFIG_SMP */
 
 struct io_context;                      /* See blkdev.h */
 #define NGROUPS_SMALL           32
diff --git a/include/linux/smc91x.h b/include/linux/smc91x.h
index 8e0556b8781c..3827b922ba1f 100644
--- a/include/linux/smc91x.h
+++ b/include/linux/smc91x.h
@@ -5,9 +5,19 @@
 #define SMC91X_USE_16BIT (1 << 1)
 #define SMC91X_USE_32BIT (1 << 2)
 
+#define SMC91X_NOWAIT           (1 << 3)
+
+/* two bits for IO_SHIFT, let's hope later designs will keep this sane */
+#define SMC91X_IO_SHIFT_0       (0 << 4)
+#define SMC91X_IO_SHIFT_1       (1 << 4)
+#define SMC91X_IO_SHIFT_2       (2 << 4)
+#define SMC91X_IO_SHIFT_3       (3 << 4)
+#define SMC91X_IO_SHIFT(x)      (((x) >> 4) & 0x3)
+
+#define SMC91X_USE_DMA          (1 << 6)
+
 struct smc91x_platdata {
         unsigned long flags;
-        unsigned long irq_flags; /* IRQF_... */
 };
 
 #endif /* __SMC91X_H__ */